芯
洲
科
SCT2401
技
Silicon Content Technology
Rev.1.2
4.5V-40V Vin, 600mA Synchronous Step-down DCDC Converter
FEATURES
DESCRIPTION
The SCT2401 is a high frequency, up to 600mA
continuous output synchronous buck converter. It has
wide input voltage rating from 4.5V to 40V, which
integrates a 600mΩ high-side MOSFET and a 300mΩ
low-side MOSFET. The SCT2401, adopts the peak
current mode control with built-in loop compensation to
make the chip easy to use.
Wide Input Range: 4.5V-40V
Up to 600mA Continuous Output Current
0.81V ± 2.5% Feedback Reference Voltage
Integrated 600mΩ High-Side and 300mΩ LowSide Power MOSFETs
Fixed Frequency 1.2MHz
Pulse Skipping Mode (PSM) at Light Load
90uA Quiescent Current in Sleep Mode
80ns Minimum On-time
1ms Internal Soft-start Time
Over-Temperature Protection
Available in an TSOT23-6 Package
The SCT2401 features fixed 1.2MHz switching
frequency, which minimizes the external off chip
passive components size and reduces the output ripple
to be lower than 0.1% of output when the output is 12V.
With a minimum 80ns on-time of high-side MOSFET,
the SCT2401 allows power conversion from high input
voltage to low output voltage.
APPLICATIONS
The SCT2401 supports the Pulse Skipping Modulation
(PSM) with typical 90uA low quiescent current. It
achieves 85% power efficiency at 10mA light load
condition.
Industrial 24V Distributed Power Bus
Power meter
Elevator, PLC, Servo
Automatic Control
Automotive
The SCT2401 offers cycle-by-cycle current limit,
thermal shutdown protection and input voltage undervoltage protection. The device is available in a 6-pin
small profile TSOT23-6 package.
TYPICAL APPLICATION
100
90
C2
L1
SW
BST
VIN
VIN
GND
FB
EN
ON
C1
C3
Efficiency(%)
80
VOUT
70
60
50
40
30
VIN=24V, VOUT=5V
20
OFF
10
R1
0
0.001
R2
VIN=24V, VOUT=12V
0.01
0.1
1
IOUT(A)
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1
SCT2401
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Revision 1.0: Production
Revision 1.1: Correct EN pin function description in page 2
Revision 1.2: Update efficiency curve and application waveform
DEVICE ORDER INFORMATION
PART NUMBER
PACKAGE MARKING
PACKAGE DISCRIPTION
2401
6-Lead Plastic TSOT23-6
SCT2401TVB
1）For Tape & Reel, Add Suffix R (e.g. SCT2401TVBR).
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature unless otherwise
PIN CONFIGURATION
noted (1)
DESCRIPTION
MIN
MAX
UNIT
VIN, EN
-0.3
42
V
BST
-0.3
49
V
SW
-1
42
V
BST-SW
-0.3
7
V
FB
-0.3
6
V
Operating junction temperature (2)
-40
150
C
Storage temperature TSTG
-65
150
C
BST
1
6
SW
GND
2
5
VIN
FB
3
4
EN
6-Lead Plastic TSOT23-6
(1)
(2)
Stresses beyond those listed under Absolute Maximum Rating may cause device permanent damage. The device is not guaranteed to
function outside of its Recommended Operation Conditions.
The IC includes over temperature protection to protect the device during overload conditions. Junction temperature will exceed 150°C
when over temperature protection is active. Continuous operation above the specified maximum operating junction temperature will
reduce lifetime.
PIN FUNCTIONS
NAME
NO.
BST
1
Power supply for the high-side power MOSFET gate driver. Must connect a 0.1uF
or greater ceramic capacitor between BST pin and SW node.
GND
2
GND
FB
3
Buck converter output feedback sensing voltage. Connect a resistor divider from
VOUT to FB to set up output voltage. The device regulates FB to the internal
reference of 0.81V typically.
2
PIN FUNCTION
EN
4
VIN
5
Enable logic input. This pin supports high voltage input up to VIN supply to be
connected VIN directly to enable the device automatically. The device has
precision enable thresholds 1.21V rising / 1.1V falling for programmable UVLO
threshold and hysteresis.
Power supply input. Must be locally bypassed.
SW
6
Switching node of the buck converter.
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SCT2401
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range unless otherwise noted
PARAMETER
DEFINITION
VIN
TJ
Input voltage range
Operating junction temperature
MIN
MAX
UNIT
4.5
-40
40
125
V
°C
MIN
MAX
UNIT
-2
+2
kV
-0.5
+0.5
kV
ESD RATINGS
PARAMETER
DEFINITION
Human Body Model (HBM), per ANSI-JEDEC-JS-0012014 specification, all pins(1)
Charged Device Model (CDM), per ANSI-JEDEC-JS-0022014specification, all pins(1)
VESD
(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.
THERMAL INFORMATION
PARAMETER
RθJA
THERMAL METRIC
TSOT23-6
Junction to ambient thermal resistance(1)
RθJC
Junction to case thermal
UNIT
89
resistance(1)
°C/W
39
(1) SCT provides RθJA and RθJC numbers only as reference to estimate junction temperatures of the devices. RθJA and RθJC are not a
characteristic of package itself, but of many other system level characteristics such as the design and layout of the printed circuit
board (PCB) on which the SCT2401 is mounted, thermal pad size, and external environmental factors. The PCB board is a heat sink
that is soldered to the leads and thermal pad of the SCT2401. Changing the design or configuration of the PCB board changes the
efficiency of the heat sink and therefore the actual RθJA and RθJC.
ELECTRICAL CHARACTERISTICS
VIN=12V, TJ=-40°C~125°C, typical value is tested under 25°C.
SYMBOL
PARAMETER
TEST CONDITION
Power Supply and Output
VIN
Operating input voltage
ISD
Input UVLO
Hysteresis
Shutdown current
IQ
Quiescent current
VIN_UVLO
MIN
4.5
VIN rising
4.3
440
1
EN=0, No load, VIN=12V
EN=floating, No load, No
switching. VIN=12V. BSTSW=5V
1.21
Enable low threshold
MAX
0.9
UNIT
40
V
5
V
mV
uA
90
Enable, Soft Start and Working Modes
VEN_H
Enable high threshold
VEN_L
TYP
uA
1.4
V
1.1
V
Power MOSFETs
RDSON_H
High side FET on-resistance
600
mΩ
RDSON_L
300
mΩ
Low side FET on-resistance
Feedback and Error Amplifier
VFB
Feedback Voltage
0.79
0.81
0.83
V
Current Limit
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3
SCT2401
SYMBOL
PARAMETER
ILIM_HSD
HSD peak current limit
ILIM_LSD
LSD valley current limit
TEST CONDITION
TYP
MAX
0.7
0.9
1.1
0.8
Switching Frequency
FSW
Switching frequency
tON_MIN
MIN
VIN=12V, VOUT=5V
Minimum on-time
960
1200
UNIT
A
A
1440
kHz
80
ns
1
ms
Soft Start Time
tSS
Internal soft-start time
Protection
VOVP
TSD*
Feedback overvoltage with respect to
VFB/VREF rising
110
%
reference voltage
VFB/VREF falling
105
%
Thermal shutdown threshold
Hysteresis
TJ rising
170
25
°C
*Derived from bench characterization
4
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SCT2401
100
100
90
90
80
80
70
70
Efficiency(%)
Efficiency(%)
TYPICAL CHARACTERISTICS
60
50
40
30
20
40
30
VIN=24V
10
VIN=24V
0
0.001
50
20
VIN=12V
10
60
VIN=36V
0
0.01
0.1
1
0.001
0.01
IOUT(A)
Figure 1. Efficiency vs Load Current, Vout=5V
1
Figure 2. Efficiency vs Load Current, Vout=12V
12.40
5.10
12.35
5.09
5.08
12.30
Output Voltage (V)
Output Voltage (V)
0.1
IOUT(A)
12.25
12.20
12.15
12.10
5.07
5.06
5.05
5.04
5.03
5.02
12.05
5.01
12.00
0.001
0.01
0.1
5.00
0.001
1
0.01
IOUT (A)
0.1
1
IOUT (A)
Figure 3. Load Regulation (Vout=12V), Vin=24V
Figure 4. Load Regulation (Vout=5V), Vin=24V
0.95
0.815
0.814
0.813
0.90
HS OC Limit (A)
VREF (V)
0.812
0.811
0.81
0.809
0.808
0.807
0.85
0.80
0.75
0.806
0.805
-50
-25
0
25
50
75
100
125
Temperature (°C)
0.70
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 5. Reference VS Temperature
Figure 6. HS Current Limit VS Temperature
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5
SCT2401
TYPICAL CHARACTERISTICS
0.95
110
105
100
0.85
Iq (uA)
LS OC Limit (A)
0.90
0.80
95
90
85
80
0.75
75
0.70
70
-50
-25
0
25
50
75
100
125
-50
-25
0
25
Temperature (°C)
50
75
100
125
Temperature (°C)
Figure 7. LS Current Limit VS Temperature
Figure 8. Quiescent Current vs Temperature VIN=12V
1.30
5.0
4.5
1.25
1.20
3.5
EN (V)
Isd (uA)
4.0
3.0
2.5
1.15
1.10
2.0
1.05
1.5
1.0
-50
-25
0
25
50
75
100
EN_RISING
EN_FALLING
1.00
125
-50
-25
0
Temperature (°C)
25
50
75
100
Temperature (°C)
Figure 9. Shutdown Current vs Temperature, Vin=24V
Figure 10. EN Threshold vs Temperature
4.40
130
128
126
4.20
VOVP_R(%)
UVLO (V)
4.30
4.10
UVLO_RISING
UVLO_FALLING
4.00
124
122
120
118
116
OVP_RISING
114
3.90
OVP_FALLING
112
110
3.80
-50
-25
0
25
50
75
100
125
Figure 11. VIN UVLO VS Temperature
6
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-50
0
50
Temperature (°C)
Temperature (°C)
Figure 12. OVP VS Temperature
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100
125
SCT2401
FUNCTIONAL BLOCK DIAGRAM
VIN
5
UVLO
EN
4
+
VIN UVLO
and LDO
EN
VCC
1.21V
480K
VCC
HS MOSFET
Current Limit
BOOT
UVLO
Ramp
SS
0.81V
FB
+
+ GM
COMP
BOOT
Strap
PWM
+
1 BST
Q1
3
PWM and Dead
Time Control
Logic
+
6 SW
OVP
0.88V
Q2
Oscillator
with PLL
CLK
Thermal
Protection
LS MOSFET
Current Limit
2 GND
Figure 13. Functional Block Diagram
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7
SCT2401
OPERATION
Overview
The SCT2401 device is 4.5V-40V input, 600mA output, fully integrated synchronous buck converters. The device
employs fixed frequency peak current mode control. An internal clock with 1.2MHz frequency initiates turning on
the integrated high-side power MOSFET Q1 in each cycle, then inductor current rises linearly and the converter
charges output cap. When sensed voltage on high-side MOSFET peak current rising above the voltage of internal
COMP (see functional block diagram), the device turns off high-side MOSFET Q1 and turns on low-side MOSFET
Q2. The inductor current decreases when MOSFET Q2 is ON. In the next rising edge of clock cycle, the low-side
MOSFET Q2 turns off. This repeats on cycle-by-cycle based.
The peak current mode control with the internal loop compensation network and the built-in 1ms soft-start simplify
the SCT2401 footprints and minimize the off-chip component counts. Meanwhile, it reduces the external passive
components size as well.
The quiescent current of SCT2401 is 90uA typical under no-load and without switching condition. When disabling
the device, the supply shut down current is only 1μA. The SCT2401 works at Pulse Skipping Mode PSM to further
increase the power efficiency in light load condition.
Peak Current Mode Control and Pulse Skipping Mode
The SCT2401 employs fixed frequency peak current mode control. An internal clock initiates turning on the
integrated high-side power MOSFET Q1 in each cycle, then inductor current rises linearly. When the current through
high-side MOSFET reaches the threshold level set by the COMP voltage of the internal error amplifier, the highside MOSFET turns off. The synchronous low-side MOSFET Q2 turns on till the next clock cycle begins or the
inductor current falls to zero.
The error amplifier serves the COMP node by comparing the voltage of the FB pin with an internal 0.81V reference
voltage. When the load current increases, a reduction in the feedback voltage relative to the reference raises COMP
voltage till the average inductor current matches the increased load current. This feedback loop well regulates the
output voltage to the reference. The device also integrates an internal slope compensation circuitry to prevent subharmonic oscillation when duty cycle is greater than 50% for a fixed frequency peak current mode control.
The SCT2401 operates in Pulse Skipping Mode (PSM) with light load current to improve efficiency. When the load
current decreases, an increment in the feedback voltage leads COMP voltage drop. When COMP falls to a low
clamp threshold (400mV typically), device enters PSM. The output voltage decays due to output capacitor
discharging during skipping period. Once FB voltage drops lower than the reference voltage, and the COMP voltage
rises above low clamp threshold. Then high-side power MOSFET turns on in next clock pulse. After several
switching cycles with typical 100mA peak inductor current, COMP voltage drops and is clamped again and pulse
skipping mode repeats if the output continues light loaded.
This control scheme helps achieving higher efficiency by skipping cycles to reduce switching power loss and gate
drive charging loss.
VIN Power
The SCT2401 is designed to operate from an input voltage supply range between 4.5V to 40V, at least 0.1uF
decoupling ceramic cap is recommended to bypass the supply noise. If the input supply locates more than a few
inches from the converter, an additional electrolytic or tantalum bulk capacitor or with recommended 10uF may be
required in addition to the local ceramic bypass capacitors.
8
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SCT2401
Enable and Under Voltage Lockout UVLO
The SCT2401 Under Voltage Lock Out (UVLO) default startup threshold is typical 4.3V with VIN rising and shutdown
threshold is 3.8V with VIN falling. The more accurate UVLO threshold can be programmed through the precision
enable threshold of EN pin.
When applying a voltage higher than the EN high threshold (typical 1.21V/rising), the SCT2401 enables all functions
and the device starts soft-start phase. The SCT2401 has the built in 1ms soft-start time to prevent the output
overshoot and inrush current. When EN pin is pulled low, the internal SS net will be discharged to ground. Buck
operation is disabled when EN voltage falls below its lower threshold (typically 1.1V/falling).
An internal 480k pull down resistor make EN pin floating shut down the SCT2401. For the application requiring
higher VIN UVLO voltage than the default setup, connecting an external R3 to VIN to program the new VIN UVLO.
The resistor divider R3 is calculated by equation (1). If there is no requirement for the VIN UVLO program, connect
the EN to VIN to simplify the external circuitry.
EN pin is a high voltage pin and can be directly connected to VIN to automatically start up the device with VIN rising
to its internal UVLO threshold.
VIN
R3
EN
4
+
EN
1.21V
480K
Figure 14. Adjustable VIN UVLO
𝑅3 =
(𝑉𝑟𝑖𝑠𝑒 − 1.21) ∗ 480𝑘
1.21
(1)
Where:
Vrise: Vin rise threshold to enable the device
Output Voltage
The SCT2401 regulates the internal reference voltage at 0.81V with 2.5% tolerance over the operating
temperature and voltage range. The output voltage is set by a resistor divider from the output node to the FB pin. It
is recommended to use 1% tolerance or better resistors. Use Equation 2 to calculate resistance of resistor dividers.
To improve efficiency at light loads, larger value resistors are recommended. However, if the values are too high,
the regulator will be more susceptible to noise affecting output voltage accuracy.
𝑉𝑂𝑈𝑇
𝑅𝐹𝐵_𝑇𝑂𝑃 = (
− 1) ∗ 𝑅𝐹𝐵_𝐵𝑂𝑇
𝑉𝑅𝐸𝐹
(2)
where
RFB_TOP is the resistor connecting the output to the FB pin.
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SCT2401
RFB_BOT is the resistor connecting the FB pin to the ground.
Peak Current Limit
The SCT2401 has cycle-by-cycle peak current limit with sensing the internal high side MOSFET Q1 current during
overcurrent condition. While the Q1 turns on, its conduction current is monitored by the internal sensing circuitry.
Once the high-side MOSFET Q1 current exceeds the limit, it turns off immediately. The maximum current passing
through the power MOSFET is limited cycle-by-cycle. The switching frequency folds back to prevent an inductor
current run-away during start-up or short circuit.
Bootstrap Voltage Regulator
An external bootstrap capacitor between BST and SW pin powers floating high-side power MOSFET gate driver.
The bootstrap capacitor voltage is charged from an integrated voltage regulator when high-side power MOSFET is
off and low-side power MOSFET is on.
The floating supply (BST to SW) UVLO threshold is 2.7V rising and hysteresis of 350mV. When the converter
operates with high duty cycle or prolongs in sleep mode for certain long time, the required time interval to recharging
bootstrap capacitor is too long to keep the voltage at bootstrap capacitor sufficient. When the voltage across
bootstrap capacitor drops below 2.35V, BST UVLO occurs. The SCT2401 intervenes to turn on low side MOSFET
periodically to refresh the voltage of bootstrap capacitor to guarantee operation over a wide duty range.
Internal Soft-Start
The SCT2401 integrates an internal soft-start circuit that ramps the reference voltage from zero volts to 0.81V
reference voltage in 1ms. If the EN pin is pulled below 1.1V, switching stops and the internal soft-start resets.
The soft-start also resets during shutdown due to thermal overloading.
Over Current Protection
The SCT2401 implements over current protection with cycle-by-cycle limiting high-side MOSFET peak current and
low-side MOSFET valley current to avoid inductor current running away during unexpected overload or output hard
short condition. The inductor current IL is monitored during high-side MOSFET Q1 and low-side MOSFET Q2 on.
As shown in Figure 15, when overload or hard short happens, once the high-side MOSFET Q1 current exceeds the
HS limit, Q1 is turned off immediately and Q2 is turned on. If the low-side MOSFET Q2 current is higher than the
LS current limit during Q2 ON time and next switching cycle will be skipped until Q2 current is lower than LS current
limit. Then, Q1 is turned on and Q2 is turned off in another Over protection cycle until the overload or hard short is
released.
Q1
HS limit
LS limit
IL
Overload/ Hard short
Happens
VOUT
Figure 15. Over Current Protection
10
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SCT2401
Over voltage Protection
The SCT2401 implements the Over-voltage Protection OVP circuitry to minimize output voltage overshoot during
load transient, recovering from output fault condition or light load transient. The overvoltage comparator in OVP
circuit compares the FB pin voltage to the internal reference voltage. When FB voltage exceeds 110% of internal
0.81V reference voltage, the high-side MOSFET turns off to avoid output voltage continue to increase. When the
FB pin voltage falls below 105% of the 0.81V reference voltage, the high-side MOSFET can turn on again.
Thermal Shutdown
Once the junction temperature in the SCT2401 exceeds 170°C, the thermal sensing circuit stops converter
switching and restarts with the junction temperature falling below 145°C. Thermal shutdown prevents the damage
on device during excessive heat and power dissipation condition.
.
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11
SCT2401
APPLICATION INFORMATION
Typical Application
C4
0.1uF
L1
22uH
1
2
BST
SW
GND
VIN
FB
EN
3
6
VOUT=5V
5
4
VIN=24V
C5
22uF
R3
100K
C1
0.1uF
C2
4.7uF
C6
100uF
(Optional)
C3
47uF
R1
105K
C7
100pF
(Optional)
(Optional)
R2
20K
Figure 16. 24V Input, 5V/0.6A Output
C4
0.1uF
L1
33uH
1
2
BST
SW
GND
VIN
FB
EN
3
6
VOUT=12V
5
4
VIN=24V
C5
22uF
R3
100K
C1
0.1uF
C2
4.7uF
C6
100uF
(Optional)
C3
47uF
R1
280K
C7
100pF
(Optional)
(Optional)
R2
20K
Figure 17. 24V Input, 12V/0.6A Output
Design Parameters
12
Design Parameters
Example Value
Input Voltage
24V
Output Current
0.6A
Switching Frequency
1.2MHz
Start Input Voltage (rising VIN)
20V
Stop Input Voltage (falling VIN)
16V
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SCT2401
Output Voltage
The output voltage is set by an external resistor divider
R1 and R2 in typical application schematic.
Recommended R2 resistance is 20KΩ. Use equation 3
to calculate R1.
𝑉𝑂𝑈𝑇
𝑅1 = (
− 1) ∗ 𝑅2
𝑉𝑅𝐸𝐹
where:
(3)
VREF is the feedback reference voltage, typical
0.81V
Table 1. R1, R2Value for Common Output Voltage
(Room Temperature)
VOUT
R1
R2
1.8 V
24.9 KΩ
20 KΩ
2.5 V
42.2 KΩ
20 KΩ
3.3 V
62 KΩ
20 KΩ
5 V
105 KΩ
20 KΩ
12 V
280 KΩ
20 KΩ
Under Voltage Lock-Out
An external resistor R3 from the input to EN pin can set the input voltage’s Under Voltage Lock-Out (UVLO) threshold
higher than the default 4.3V, like shown in Figure 14. The UVLO has two thresholds, one for power up when the
input voltage is rising and the other for power down or brown outs when the input voltage is falling. Use Equation 4
to calculate the values of R3. The power off voltage of UVLO can be derived by Equation 5.
Vrise = 1.21 ∗ (1 +
Vfall = 1.1 ∗ (1 +
𝑅3
)
480k
(4)
𝑅3
)
480k
(5)
Inductor Selection
There are several factors should be considered in selecting inductor such as inductance, saturation current, the
RMS current and DC resistance (DCR). Larger inductance results in less inductor current ripple and therefore leads
to lower output voltage ripple. However, the larger value inductor always corresponds to a bigger physical size,
higher series resistance, and lower saturation current. A good rule for determining the inductance to use is to allow
the inductor peak-to-peak ripple current to be approximately 20%~30% of the maximum output current.
The peak-to-peak ripple current in the inductor ILPP can be calculated as in Equation 6.
𝐼𝐿𝑃𝑃 =
Where
𝑉𝑂𝑈𝑇 ∗ (𝑉𝐼𝑁 − 𝑉𝑂𝑈𝑇 )
𝑉𝐼𝑁 ∗ 𝐿 ∗ 𝑓𝑆𝑊
(6)
ILPP is the inductor peak-to-peak current
L is the inductance of inductor
fSW is the switching frequency
VOUT is the output voltage
VIN is the input voltage
Since the inductor-current ripple increases with the input voltage, so the maximum input voltage in application is
always used to calculate the minimum inductance required. Use Equation 7 to calculate the inductance value.
𝐿𝑀𝐼𝑁 =
𝑉𝑂𝑈𝑇
𝑉𝑂𝑈𝑇
∗ (1 −
)
𝑓𝑆𝑊 ∗ 𝐿𝐼𝑅 ∗ 𝐼𝑂𝑈𝑇(𝑚𝑎𝑥)
𝑉𝐼𝑁(𝑚𝑎𝑥)
(7)
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SCT2401
Where
LMIN is the minimum inductance required
fsw is the switching frequency
VOUT is the output voltage
VIN(max) is the maximum input voltage
IOUT(max) is the maximum DC load current
LIR is coefficient of ILPP to IOUT
The total current flowing through the inductor is the inductor ripple current plus the output current. When selecting
an inductor, choose its rated current especially the saturation current larger than its peak operation current and
RMS current also not be exceeded. Therefore, the peak switching current of inductor, ILPEAK and ILRMS can be
calculated as in equation 8 and equation 9.
𝐼𝐿𝑃𝐸𝐴𝐾 = 𝐼𝑂𝑈𝑇 +
𝐼𝐿𝑃𝑃
2
𝐼𝐿𝑅𝑀𝑆 = √(𝐼𝑂𝑈𝑇 )2 +
Where
(8)
1
∗ (𝐼𝐿𝑃𝑃 )2
12
(9)
ILPEAK is the inductor peak current
IOUT is the DC load current
ILPP is the inductor peak-to-peak current
ILRMS is the inductor RMS current
In overloading or load transient conditions, the inductor peak current can increase up to the switch current limit of
the device which is typically 0.8A. The most conservative approach is to choose an inductor with a saturation current
rating greater than 0.8A. Because of the maximum ILPEAK limited by device, the maximum output current that the
SCT2401 can deliver also depends on the inductor current ripple. Thus, the maximum desired output current also
affects the selection of inductance. The smaller inductor results in larger inductor current ripple leading to a higher
maximum output current.
33uH inductor value is recommended for 12V output voltage and 22uH inductor is recommended for 5V output
voltage.
Input Capacitor Selection
The input current to the step-down DCDC converter is discontinuous, therefore it requires a capacitor to supply the
AC current to the step-down DCDC converter while maintaining the DC input voltage. Use capacitors with low ESR
for better performance. Ceramic capacitors with X5R or X7R dielectrics are usually suggested because of their low
ESR and small temperature coefficients, and it is strongly recommended to use another lower value capacitor (e.g.
0.1uF) with small package size (0603) to filter high frequency switching noise. Place the small size capacitor as
close to VIN and GND pins as possible.
The voltage rating of the input capacitor must be greater than the maximum input voltage. And the capacitor must
also have a ripple current rating greater than the maximum input current ripple. The RMS current in the input
capacitor can be calculated using Equation 10.
ICINRMS = IOUT ∗ √
VOUT
VOUT
∗ (1 −
)
VIN
VIN
(10)
The worst case condition occurs at VIN=2*VOUT, where:
ICINRMS = 0.5 ∗ IOUT
14
(11)
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SCT2401
For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load
current.
When selecting ceramic capacitors, it needs to consider the effective value of a capacitor decreasing as the DC
bias voltage across a capacitor increases.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 12 and the maximum input voltage ripple occurs at 50% duty cycle.
∆VIN =
IOUT
VOUT
VOUT
∗
∗ (1 −
)
fSW ∗ CIN VIN
VIN
(12)
For this example, a 4.7μF, X7R ceramic capacitors rated of 50 V in parallel are used. And a 0.1 μF for high-frequency
filtering capacitor is placed as close as possible to the device pins.
Bootstrap Capacitor Selection
A 0.1μF ceramic capacitor must be connected between BOOT pin and SW pin for proper operation. A ceramic
capacitor with X5R or better grade dielectric is recommended. The capacitor should have a 10V or higher voltage
rating.
Output Capacitor Selection
The selection of output capacitor will affect output voltage ripple in steady state and load transient performance.
The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going through
the Equivalent Series Resistance ESR of the output capacitors and the other is caused by the inductor current ripple
charging and discharging the output capacitors. To achieve small output voltage ripple, choose a low-ESR output
capacitor like ceramic capacitor. For ceramic capacitors, the capacitance dominates the output ripple. For
simplification, the output voltage ripple can be estimated by Equation 13 desired.
∆VOUT =
Where
𝑉𝑂𝑈𝑇 ∗ (𝑉𝐼𝑁 − 𝑉𝑂𝑈𝑇 )
(13)
8 ∗ 𝑓𝑆𝑊 2 ∗ 𝐿 ∗ 𝐶𝑂𝑈𝑇 ∗ 𝑉𝐼𝑁
ΔVOUT is the output voltage ripple
fSW is the switching frequency
L is the inductance of inductor
COUT is the output capacitance
VOUT is the output voltage
VIN is the input voltage
Due to capacitor’s degrading under DC bias, the bias voltage can significantly reduce capacitance. Ceramic
capacitors can lose most of their capacitance at rated voltage. Therefore, leave margin on the voltage rating to
ensure adequate effective capacitance. Typically, one 22μF ceramic output capacitors work for most applications.
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SCT2401
Application Waveforms
Unless otherwise noted the following conditions apply: Vin=24V, VOUT=5V, FSW=1200kHz.
16
Figure 18. Power up
Figure 19. Power down
Figure 20.Load Transient (0.06A-0.54A, 250mA/us)
Figure 21. SW and Vout Ripple (Iout=0.6A)
Figure 22. SW and Vout Ripple (Iout=0A)
Figure 23. Thermal, 24VIN, 5Vout, 0.6A
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SCT2401
Layout Guideline
The regulator could suffer from instability and noise problems without carefully layout of PCB. Radiation of highfrequency noise induces EMI, so proper layout of the high-frequency switching path is essential.
1. Minimize the length and area of all traces connected to the SW pin, and always use a ground plane under the
switching regulator to minimize coupling.
2. The input capacitor needs to be very close to the VIN pin and GND pin to reduce the input supply ripple. Place
a low ESR ceramic capacitor as close to VIN pin and the ground as possible to reduce parasitic effect.
3. Output inductor should be placed close to the SW pin. The area of the PCB conductor minimized to prevent
excessive capacitive coupling.
4. The layout needs be done with well consideration of the thermal. A large top layer ground plate using multiple
thermal vias is used to improve the thermal dissipation. The bottom layer is a large ground plane connected to
the top layer ground by vias.
VOUT
Inductor
Output capacitors
BST
SW
GND
VIN
FB
EN
VIN
VIN
Input
Capacitor
Feedback
Resistors
GND
Figure 23. PCB Layout Example
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SCT2401
PACKAGE INFORMATION
TOP VIEW
BOTTOM VIEW
SYMBOL
SIDE VIEW
NOTE:
1.
2.
3.
4.
5.
6.
Drawing proposed to be made a JEDEC package outline MO220 variation.
Drawing not to scale.
All linear dimensions are in millimeters.
Thermal pad shall be soldered on the board.
Dimensions of exposed pad on bottom of package do not
include mold flash.
Contact PCB board fabrication for minimum solder mask web
tolerances between the pins.
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A
A1
A2
D
E
E1
b
c
e
L
ɵ
Unit: Millimeter
MIN
TYP
MAX
------1.10
0.000
0.10
0.70
1.00
2.85
2.95
2.65
2.95
1.55
1.65
0.30
0.50
0.08
0.20
0.95(BSC)
0.30
0.60
0º
8º
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SCT2401
TAPE AND REEL INFORMATION
Feeding Direction
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