芯
洲
科
SCT2360
技
Silicon Content Technology
Rev. 1.0
4V-28V Vin, 6A Synchronous Step-down DCDC Converter
FEATURES
DESCRIPTION
The SCT2360 is a high efficiency synchronous stepdown 6A DC-DC converter with 4V-28V input voltage
range and adjustable output voltage down to 0.6V. The
device fully integrates high-side and low-side power
MOSFETs with 36mΩ/16mΩ on-resistance to minimize
the conduction loss.
Wide 4V-28V Input Voltage Range
0.6V-14V Output Voltage Range
6A Continuous Output Current
Integrated 36mΩ/16mΩ Rdson of HS/LS Power
MOSFETs
Fixed 1ms Soft-start Time
Selectable 400KHz, 800KHz, 1.2MHz Switching
Frequencies
Selectable PWM, PFM and USM Operation
Modes
Cycle-by-Cycle Current Limiting
Output Over-Voltage Protection
Over-Temperature Protection
Available in a QFN 12-leads 3mmx3mm Package
APPLICATIONS
Auto
DTV, Monitor/LCD Display
Printer, Charging Station
Industry PC
The SCT2360 adopts a Constant On-Time (COT)
control to provide fast transient response and easy loop
stabilization. The switching clock frequency can be
selected from 400KHz, 800KHz and 1.2MHz for
optimization of the filter size and output voltage ripple.
The device offers fixed 1ms soft start to prevent inrush
current during the startup of output voltage ramping.
Power Good with open drain output signals that the
output voltage is within regulation.
The SCT2360 has the MODE pin to select Pulse
Frequency Modulation (PFM) operation mode to
achieve the light load power save, or Ultrasonic Mode
(USM) to keep the switching frequency above audible
frequency areas during light-load or no-load conditions,
or the PWM mode to achieve the small output ripple.
Full protection includes over current protection, undervoltage protection, and thermal shutdown.
The converter requires a minimum number of external
components and is available in a QFN- 12 (3mmx3mm)
package.
TYPICAL APPLICATION
100.0
VIN
C3
C1
ON/OFF
PG
R3
90.0
BST
EN
MODE
FSEL
PG
L1
80.0
VOUT
SW
C4
Efficiency (%)
VIN
R1
VOUT
FB
VCC
C2
R2
AGND
PGND
70.0
60.0
50.0
40.0
30.0
PFM
20.0
FCCM
10.0
USM
0.0
0.001
0.01
0.1
1
10
Iout (A)
4V-28V, Synchronous Buck Converter
VIN=12V, Vout=5V, fsw = 400kHz
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1
SCT2360
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Revision 1.0: Production
DEVICE ORDER INFORMATION
PART NUMBER
PACKAGE MARKING
PACKAGE DISCRIPTION
SCT2360FPB
2360
12-Lead 3mm×3mm Plastic QFN
1)
For Tape & Reel, Add Suffix R (e.g. SCT2360FPBR)
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature unless otherwise
PIN CONFIGURATION
noted(1)
DESCRIPTION
MIN
MAX
UNIT
VIN, EN
-0.3
32
V
SW
-1
32
V
BST
-0.3
38
V
BST-SW
-0.3
6
V
VOUT
-0.3
16
V
PG, FSEL, MODE,VCC, FB
-0.3
6
V
Operating junction temperature(2)
-40
125
C
Storage temperature TSTG
-65
150
C
EN
FB AGND VCC
12
11
VIN
(2)
9
1
8
7
BST
SW
2
PGND
3
(1)
10
PG
4
FSEL
5
6
VOUT MODE
Top View: QFN-12L 3mm x 3mm, Plastic
Stresses beyond those listed under Absolute Maximum Rating may cause device permanent damage. The device is not guaranteed to
function outside of its Recommended Operation Conditions.
The IC includes over temperature protection to protect the device during overload conditions. Junction temperature will exceed 150°C
when over temperature protection is active. Continuous operation above the specified maximum operating junction temperature will
reduce lifetime.
PIN FUNCTIONS
NAME
NO.
PIN FUNCTION
VIN
1
Input voltage. Decouple the input rail with at least 0.1uF input ceramic capacitor. Place
the capacitor as close to VIN and PGND pins as possible. Use wide PCB traces and
multiple vias to make the connection.
PGND
2
PG
3
FSEL
4
VOUT
5
2
Power ground. Using wide PCB traces and multiple vias large enough to handle the
load current.
Power good open-drain output. PG is high if the output voltage is higher than 95% and
lower than 105% of the nominal voltage.
Switching frequency selection. Connecting to ground sets clock frequency to 400KHz.
Floating sets clock frequency to 800KHz. Connecting to VCC sets clock frequency to
1.2MHz.
VOUT is used to sense the output voltage of the buck regulator. Connect VOUT to the
output capacitor of the regulator directly. Keep the VOUT sensing trace far away from
the SW node. VIAs should also be avoided on the VOUT sensing trace. A trace larger
than 25mil is required.
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SCT2360
PFM, USM or FCCM mode selection. Connect the pin to VCC to force the device in
Forced Continuous Current Modulation (FCCM) operation mode. Ground the pin to
operate the device in Pulse Frequency Modulation (PFM) mode without Ultrasonic
Mode (USM). Floating the pin to operate the device in PFM with USM.
Switch output. SW is driven up to VIN through the high-side power MOSFET during ontime. The inductor current drives SW to negative voltage through low-side power
MOSFET during off-time. Use wide and short PCB traces to make the connection. Keep
the SW pattern area minimized.
Bootstrap. Must connect a 0.1uF capacitor or greater between SW and BST to form a
floating supply across the gate driver of high-side power MOSFET.
MODE
6
SW
7
BST
8
VCC
9
Internal VCC LDO output. Decouple with 1µF ceramic capacitor placed as close to VCC
as possible.
AGND
10
Signal logic ground. AGND is the Kelvin connection to PGND.
FB
11
EN
12
Feedback voltage Input. Connect FB to the tap of a resistor divider from output voltage
to AGND to set up output voltage. The device regulates FB to the internal reference
value of 0.6V typical.
Enable logic input. EN is a digital input that controls the converter on or off. EN high
turns on the device and EN low turns off the device. Connecting to VIN with a 100kΩ
pull-up resistor can enable the device. Floating EN pin automatically starts up the
converter.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range unless otherwise noted
PARAMETER
DEFINITION
VIN
TJ
Input voltage range
Operating junction temperature
MIN
MAX
UNIT
4
-40
28
125
V
°C
MIN
MAX
UNIT
-2
+2
kV
-0.5
+0.5
kV
ESD RATINGS
PARAMETER
VESD
DEFINITION
Human Body Model(HBM), per ANSI-JEDEC-JS-0012014 specification, all pins(1)
Charged Device Model(CDM), per ANSI-JEDEC-JS-0022014specification, all pins(1)
(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.
THERMAL INFORMATION
PARAMETER
THERMAL METRIC
QFN-12L
RθJA
Junction to ambient thermal resistance(1)
50
RθJC
Junction to case thermal resistance(1)
12
UNIT
°C/W
(1) SCT provides RθJA and RθJC numbers only as reference to estimate junction temperatures of the devices. RθJA and RθJC are not a
characteristic of package itself, but of many other system level characteristics such as the design and layout of the printed circuit
board (PCB) on which the SCT2360 is mounted. The PCB board is a heat sink that is soldered to the leads and thermal pad of the
SCT2360. Changing the design or configuration of the PCB board changes the efficiency of the heat sink and therefore the actual RθJA
and RθJC.
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3
SCT2360
ELECTRICAL CHARACTERISTICS
VIN=12V, TJ=-40°C~125°C, typical value is tested under 25°C.
SYMBOL
PARAMETER
TEST CONDITION
Power Supply and Output
VIN
Operating input voltage
MIN
TYP
4
28
V
5
V
mV
uA
ISD
IQ
Quiescent current
VCC
VCC internal LDO regulator voltage
EN=0, No load, VIN=12V
EN=floating, No load, No
switching. VIN=12V. BSTSW=5V
IVCC=0mA
VCC_LR
VCC internal LDO load regulation
IVCC=5mA
1
%
IVCC_LIM
VCC internal LDO current limit
VCC short to ground
30
mA
Buck Reference
VREF
Reference voltage of FB
TJ=25OC
IFB
VFB=1.2V
FB pin leakage current
3.8
300
1
UNIT
Input UVLO
Hysteresis
Shutdown current
VIN_UVLO
VIN rising
MAX
130
4.75
0.594
5
0.6
uA
5.25
V
0.606
V
100
nA
Power MOSFETs
RDSON_H
High side FET on-resistance
VCC=5V
36
mΩ
RDSON_L
VCC=5V
16
mΩ
Low side FET on-resistance
Enable
VEN_H
Enable high threshold
1.2
V
VEN_L
Enable low threshold
1.09
V
IEN
Enable pin input current
1.4
uA
IEN_HYS
Enable pin hysteresis current
3.6
uA
Operation Mode
VMD_PWM
PWM mode input logic high threshold
VMD_USM
PFM mode with USM logic threshold
VMD_PFM
PFM mode input logic low threshold
VCC=5V
4.2
V
1.5
3.5
V
0.9
V
Switching Frequency
FSEL=0V
400
kHz
FSEL=open
800
kHz
FSEL=5V
FSW
Switching frequency
1200
kHz
TON_TIME
Minimum On-time
100
ns
TOFF_TIME
Minimum Off-time
200
ns
Internal soft-start time
1
ms
PGRising(in)
VFB rising, percentage of VREF (Good)
95
%
PGFalling(in)
VFB falling, percentage of VREF
85
%
PGRising(out)
VFB rising, percentage of VREF
115
%
PGFallng(out)
VFB falling, percentage of VREF (Good)
105
%
PGTD
PG low to high delay
0.5
ms
VPG
Power Good PG pull-down strength
0.4
V
Soft Start Time
tSS
Power Good
4
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IPG =4mA
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SCT2360
SYMBOL
PARAMETER
TEST CONDITION
MIN
TYP
MAX
IPG_LEAK
Power Good PG leakage current
VPG=5V
Output OVP threshold
Hysteresis
OCP hiccup wait time
VOUT rising
120
5
7
%
%
Cycles
Output UVP threshold
VOUT falling
75
%
ILIM_P
LS MOSFET positive current limit
7.5
A
ILIM_N
LS MOSFET negative current limit
From source to drain
From drain to source, MODE
connects to VCC
2.5
A
RDischarge
SW to ground resistance
100
Ω
TSD
Thermal shutdown threshold
Hysteresis
160
25
°C
5
UNIT
uA
Protection
VOVP
THIC_W
VUVP
TJ rising
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5
SCT2360
100.0
100.0
90.0
90.0
80.0
80.0
70.0
70.0
Efficiency (%)
Efficiency (%)
TYPICAL CHARACTERISTICS
60.0
50.0
40.0
PFM
FCCM
USM
30.0
20.0
10.0
60.0
50.0
40.0
30.0
PFM
20.0
FCCM
10.0
USM
0.0
0.0
0.001
0.01
0.1
1
0.001
10
0.01
1
10
Figure 2. Efficiency, Vin=12V, Vout=5V, Fsw=800kHz
Figure 1. Efficiency, Vin=12V, Vout=5V, Fsw=400kHz
100.0
100.0
90.0
90.0
80.0
80.0
70.0
70.0
Efficiency (%)
Efficiency (%)
0.1
Iout (A)
Iout (A)
60.0
50.0
40.0
60.0
50.0
40.0
30.0
PFM
30.0
PFM
20.0
FCCM
20.0
USM
FCCM
10.0
10.0
USM
0.0
0.0
0.001
0.01
0.1
1
0.001
10
0.01
Iout (A)
0.1
1
10
Iout (A)
Figure 4. Efficiency, Vin=24V, Vout=5V, Fsw=400kHz
Figure 3. Efficiency, Vin=12V, Vout=5V, Fsw=1200kHz
4.945
415
PFM
4.94
FPWM
USM
Fsw(KHz)
Vout(V)
4.935
4.93
4.925
410
4.92
4.915
405
4.91
0
1
2
3
4
5
6
Figure 5. Load Regulation, Vin=12V, Fsw=400kHz
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10
13
16
19
Vin(V)
Iout(A)
6
7
Figure 6. Buck Fsw VS Vin
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22
25
28
SCT2360
FUNCTIONAL BLOCK DIAGRAM
VIN
1
12
EN
VCC
Ibias current
VCC
regu lator
8
BST
Boo tstr ap
Regula tor
9
HS
MOSFET
6
MODE
FSEL
Vref Voltage
Bias and
Reference
Mode
Sele ction
On-time
Gen erator
and Freq.
Sele ction
4
Soft Start
DC Err or
Correction
0.6V
Control Logic
and Pro tection
7
SW
Gate
Driver
PWM
Compara tor
11
FB
LS
MOSFET
3
PG
0.57V 0.63V
Curren t Sensing
2
PGND
OCP Comparator
PG
Comparators
Ramp
Compensation
Switching Sensing
5
VOUT
10
AGND
OVP
Disable
Output
Discharge
Figure 7. Functional Block Diagram
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7
SCT2360
OPERATION
Overview
The SCT2360 is a 4V-28V input, 6A continuous output synchronous buck converter with built-in 36mΩ Rdson highside and 16mΩ Rdson low-side power MOSFETs. It implements the Constant on-time (COT) mode control to
regulate output voltage, providing excellent line and load transient response and simplifying the external frequency
compensation design.
The switching frequency is selectable, 400kHz, 800kHz and 1.2MHz, by setting different FSEL status, to optimizes
either the power efficiency or the external components’ sizes. The SCT2360 features an internal 1ms soft-start time
to avoid large inrush current and output voltage overshoot during startup. The device features three different
operation modes at light loading: Pulse Frequency Modulation (PFM) mode, and Ultra-Sonic Modulation (USM)
mode, and PWM mode. The quiescent current is typically 130uA under no load and sleep mode condition to achieve
high efficiency at light load.
The SCT2360 has a default input start-up voltage of 3.8V with 300mV hysteresis. The EN function features with a
precision threshold that can be used to adjust the input voltage lockout thresholds with two external resistors to
meet accurate higher UVLO system requirements. Floating EN pin enables the device with the internal pull-up
current to the pin.
The SCT2360 full protection features include the input under-voltage lockout, the output over-voltage protection,
over current protection with cycle-by-cycle current limiting and hiccup mode, output hard short protection and
thermal shutdown protection.
Constant on-time (COT) Mode Control
The SCT2360 employs constant on-time (COT) Mode control providing fast transient with pseudo fixed switching
frequency. At the beginning of each switching cycle, since the feedback voltage (VFB) is lower than the internal
reference voltage (VREF), the high-side MOSFET (Q1) is turned on during one on-time and the inductor current
rises to charge up the output voltage. The on-time is determined by the input voltage and output voltage. After the
on-time, the Q1 turns off and the low-side MOSFET (Q2) turns on after dead time duration. The inductor current
drops and the output capacitors are discharged. When the output voltage decreases and the VFB decreased below
the VREF, the Q1 turns during one on-time after another dead time duration. This repeats on cycle-by-cycle based.
The SCT2360 works with an internal compensation for optimizing the loop stability and transient response.
Pulse Frequency Modulation (PFM) and Ultra-sonic Modulation (USM) Modes
Grounding the MODE pin makes the SCT2360 works at Pulse Frequency Modulation (PFM) mode to improve the
power efficiency in light load. As the output current decreases from heavy load condition, the inductor current is also
reduced. If the output current is reduced, the valley of the inductor current reaches the zero level, which is the
boundary between continuous conduction and discontinuous conduction modes. The low-side MOSFET is turned
off when a zero inductor current is detected. As the load current further decreases the converter runs into
discontinuous conduction mode. The on-time is kept the same as it is in continuous conduction mode. The off-time
increases as it takes more time to discharge the output with a smaller load current.
Floating the MODE pin makes the device works at PFM with Ultra-Sonic Modulation (USM) mode to keep the
switching frequency out of the acoustic audible frequency. The USM mode block monitors the state of both highside and low-side MOSFETs. When both high-side and low-side MOSFETs are off for 33us, the low-side MOSFET
forces to turn on until the negative current limit is triggered or the feedback voltage (VFB) drops below the internal
reference voltage (VREF).
Forced Pulse Width Modulation (FPWM) mode
Connecting MODE pin to VCC, the SCT2360 forces the device operating at forced Pulse Width Modulation (PWM)
mode with pseudo-fixed switching frequency regardless loading current. Operating in PWM mode can achieve
smaller output voltage ripple compared with PFM or USM at light load. When the load current approaches zero, the
low-side MOSFET current crosses zero and sinks current from output to maintain the constant output. Hence power
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SCT2360
efficiency in light load is much lower than heavy load.
Enable and Under Voltage Lockout Threshold
The SCT2360 is enabled when the VIN pin voltage rises above 3.8V and the EN pin voltage exceeds the enable
threshold of 1.18V. The device is disabled when the VIN pin voltage falls below 3.5V or when the EN pin voltage is
below 1.1V. An internal 1.4uA pull up current source to EN pin allows the device enable when EN pin floats.
EN pin is a high voltage pin that can be connected to VIN directly to start up the device.
For a higher system UVLO threshold, connect an external resistor divider (R1 and R2) shown in Figure 8 from VIN
to EN. The UVLO rising and falling threshold can be calculated by Equation 1 and Equation 2 respectively.
Vrise = 1.18 ∗ (1 +
Vfall = 1.1 ∗ (1 +
VIN
R1
) − 1.4uA ∗ R1
R2
(1)
1.4uA
3.6uA
R1
R1
) − 5uA ∗ R1
R2
EN
(2)
R2
where
Vrise is rising threshold of Vin UVLO
Vfall is falling threshold of Vin UVLO
20K
+
1.18V
Figure 8. System UVLO by enable divide
Output Voltage
The SCT2360 regulates the internal reference voltage at 0.6V with 1% tolerance over the operating temperature
and voltage range. The output voltage is set by a resistor divider from the output node to the FB pin. It is
recommended to use 1% tolerance or better resistors. Use Equation 3 to calculate resistance of resistor dividers.
To improve efficiency at light loads, larger value resistors are recommended. However, if the values are too high,
the regulator will be more susceptible to noise affecting output voltage accuracy.
𝑉𝑂𝑈𝑇
𝑅𝐹𝐵_𝑇𝑂𝑃 = (
− 1) ∗ 𝑅𝐹𝐵_𝐵𝑂𝑇
𝑉𝑅𝐸𝐹
(3)
where
RFB_TOP is the resistor connecting the output to the FB pin.
RFB_BOT is the resistor connecting the FB pin to the ground.
Internal Soft-Start
The SCT2360 integrates an internal soft-start circuit that ramps the reference voltage from zero volts to 0.6V
reference voltage in 1ms. If the EN pin is pulled below 1.1V, switching stops and the internal soft-start resets. The
soft-start also resets during shutdown due to thermal overloading.
Switching Frequency Selection
The switching frequency of the SCT2360 is selectable to be one of three options: 400KHz, 800KHz and 1200KHz.
The switching frequency selection is programmed by FSEL pin. The selection information is shown in following table.
The frequency setting is latched in at each power up and is not be able to be modified during operation. Cycling the
input power or the EN pin can reselect the switching frequency.
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9
SCT2360
Table 1. FSEL Pin Set-up for Switching Frequency Selection
FSEL Set-up
Connect to GND
Floating
Connect to VCC
Switching Frequency
400KHz
800KHz
1200KHz
Mode Selection
The SCT2360 features three different operation modes at light load by easily programming the MODE pin. The
programming information is listed in following table. The mode setting is latched in at each power up and is not be
able to be modified during operation. Cycling the input power or the EN pin can reselect the switching frequency.
Table 2. MODE Pin Set-up for Mode Selection
MODE Set-up
Floating
Connect to GND
Connect to VCC
Switching Frequency
PFM with USM
PFM
FPWM
Power Good (PG)
The Power Good (PG) pin is the output of an open drain output. When the FB pin is typically between 95% and
105% of VREF the PG is de-asserted and floats after a 500μs de-glitch time. A pull-up resistor of 10 kΩ to 100 kΩ is
recommended to pull it up to VCC. The PGOOD pin is pulled low when the FB pin voltage falls under 85% or rises
over 115% of VREF, including UVP and OVP; or, in an event of thermal shutdown or during the soft-start period.
Bootstrap Voltage Regulator
An external bootstrap capacitor between BOOT pin and SW pin powers the floating gate driver to high-side power
MOSFET. The bootstrap capacitor voltage is charged from 5V VCC power or when high-side power MOSFET is off
and low-side power MOSFET is on.
Over Current Limit and Hiccup Mode
The output over-current limit (OCL) is implemented in SCT2360 by using a cycle-by-cycle valley detect control
circuit. The switch current is monitored during the OFF state of the high-side FET (Q1) by measuring the low-side
FET(Q2) drain to source voltage. This voltage is proportional to the switch current. During the on time of the highside FET switch, the switch current increases at a linear rate determined by input voltage, output voltage, the ontime and the output inductor value. During the on time of the low-side FET switch, this current decrease linearly.
The average value of the switch current is the load current IOUT.
If the measured drain to source voltage of the low-side FET is above the voltage proportional to current limit, the
low side FET stays on until the current level becomes lower than the OCL level which reduces the output current
available. When the current is limited, the output voltage tends to drop because the load demand is higher than
what the converter can support. When the output voltage falls below 75% of the target voltage, the UVP comparator
detects it and shuts down the device immediately, the device re-starts after a hiccup time of 7ms. In this type of
valley detect control the load current is higher than the OCL threshold by one half of the peak to peak inductor ripple
current. When the overcurrent condition is removed, the output voltage returns to the regulated value. If an OCL
condition happens during start-up then the device enters hiccup-mode immediately without a wait time of 1ms.
The hiccup protection mode above makes the average short circuit current to alleviate thermal issues and protect
the regulator.
Under-voltage Protection
The SCT2360 features the Under-voltage Protection (UVP) by monitoring the output voltage to detect the undervoltage voltage. When the feedback voltage falls below 75% of VREF, the SCT2360 enters hiccup mode until the
under-voltage scenario released.
10
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SCT2360
Over voltage Protection
The SCT2360 implements the Over-voltage Protection (OVP) circuitry to minimize output voltage overshoot during
load transient, recovering from output fault condition or light load transient. The overvoltage comparator in OVP
circuit compares the FB pin voltage to the internal reference voltage. When the feedback voltage rises higher than
120% of the feedback voltage, the OVP comparator output goes high and the circuit turns off the HS-FET driver.
The LS-FET driver turns on until trigger negative current limit or FB below reference voltage. Then HS-FET turns
on with normal ON-time and turn off, following with a LS-FET on until negative current limited triggered or FB lower
than reference voltage. The device exits this regulation period when the feedback voltage falls below 115% of the
reference voltage.
Thermal Shutdown
The SCT2360 protects the device from the damage during excessive heat and power dissipation conditions. Once
the junction temperature exceeds 160C, the internal thermal sensor stops power MOSFETs switching. When the
junction temperature falls below 135C, the device restarts with internal soft start phase.
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11
SCT2360
APPLICATION INFORMATION
Typical Application
R4
0
VIN
C1
22uF
VIN
C2
22uF
C3
0.1uF
BST
SCT2360
SW
EN
R1
100K
MODE
FSEL
PG
R2
NC
R3
100K
VCC
C4
1uF
AGND
C5
0.1uF
L1
3.3uH
VOUT
5V
R7
75k
FB
Cf
NC
C7
22uF
VOUT
R8
10.2k
PGND
Figure 9. 12V Input, 5V/6A Output
Design Parameters
12
Design Parameters
Example Value
Input Voltage
12V
Output Voltage
5V
Output Current
6A
Output voltage ripple (peak to peak)
50mV
Switching Frequency
400kHz
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C8
22uF
C9
22uF
SCT2360
Input Capacitor Selection
For good input voltage filtering, choose low-ESR ceramic capacitors. A ceramic capacitor 22μF is recommended for
the decoupling capacitor and a 0.1μF ceramic bypass capacitor is recommended to be placed as close as possible
to the VIN pin of the SCT2360.
Use Equation 4 to calculate the input voltage ripple:
∆𝑉𝐼𝑁 =
𝐼𝑂𝑈𝑇
VOUT
𝑉𝑂𝑈𝑇
×
× (1 −
)
𝐶𝐼𝑁 × 𝑓𝑆𝑊
VIN
𝑉𝐼𝑁
(4)
Where:
CIN is the input capacitor value
fsw is the converter switching frequency
IOUT is the maximum load current
Due to the inductor current ripple, the input voltage changes if there is parasitic inductance and resistance between
the power supply and the VIN pin. It is recommended to have enough input capacitance to make the input voltage
ripple less than 100mV. Generally, two 22uF input ceramic capacitor is recommended for most of applications.
Choose the right capacitor value carefully with considering high-capacitance ceramic capacitors DC bias effect,
which has a strong influence on the final effective capacitance.
Inductor Selection
The performance of inductor affects the power supply’s steady state operation, transient behavior, loop stability, and
buck converter efficiency. The inductor value, DC resistance (DCR), and saturation current influences both efficiency
and the magnitude of the output voltage ripple. Larger inductance value reduces inductor current ripple and
therefore leads to lower output voltage ripple. For a fixed DCR, a larger value inductor yields higher efficiency via
reduced RMS and core losses. However, a larger inductor within a given inductor family will generally have a greater
series resistance, thereby counteracting this efficiency advantage.
Inductor values can have ±20% or even ±30% tolerance with no current bias. When the inductor current approaches
saturation level, its inductance can decrease 20% to 35% from the value at 0-A current depending on how the
inductor vendor defines saturation. When selecting an inductor, choose its rated current especially the saturation
current larger than its peak current during the operation.
To calculate the current in the worst case, use the maximum input voltage, minimum output voltage, maxim load
current and minimum switching frequency of the application, while considering the inductance with -30% tolerance
and low-power conversion efficiency.
For a buck converter, calculate the inductor minimum value as shown in equation 5.
𝐿𝐼𝑁𝐷𝑀𝐼𝑁 =
(5)
𝑉𝑂𝑈𝑇 × (𝑉𝐼𝑁𝑀𝐴𝑋 − 𝑉𝑂𝑈𝑇 )
𝑉𝐼𝑁𝑀𝐴𝑋 × 𝐾𝐼𝑁𝐷 × 𝐼𝑂𝑈𝑇 × 𝑓𝑆𝑊
Where:
KIND is the coefficient of inductor ripple current relative to the maximum output current.
Therefore, the peak switching current of inductor, ILPEAK, is calculated as in equation 6.
𝐼𝐿𝑃𝐸𝐴𝐾 = 𝐼𝑂𝑈𝑇 + 𝐾𝐼𝑁𝐷 ×
𝐼𝑂𝑈𝑇
2
(6)
Set the current limit of the SCT2360 higher than the peak current ILPEAK and select the inductor with the saturation
current higher than the current limit. The inductor’s DC resistance (DCR) and the core loss significantly affect the
efficiency of power conversion. Core loss is related to the core material and different inductors have different core
loss. For a certain inductor, larger current ripple generates higher DCR and ESR conduction losses and higher core
loss.
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13
SCT2360
Output Capacitor Selection
The selection of output capacitor will affect output voltage ripple in steady state and load transient performance.
The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going through
the Equivalent Series Resistance ESR of the output capacitors and the other is caused by the inductor current ripple
charging and discharging the output capacitors. To achieve small output voltage ripple, choose a low-ESR output
capacitor like ceramic capacitor. For ceramic capacitors, the capacitance dominates the output ripple. For
simplification, the output voltage ripple can be estimated by Equation 7 desired.
∆VOUT =
Where
𝑉𝑂𝑈𝑇 ∗ (𝑉𝐼𝑁 − 𝑉𝑂𝑈𝑇 )
(7)
8 ∗ 𝑓𝑆𝑊 2 ∗ 𝐿 ∗ 𝐶𝑂𝑈𝑇 ∗ 𝑉𝐼𝑁
ΔVOUT is the output voltage ripple
fSW is the switching frequency
L is the inductance of inductor
COUT is the output capacitance
VOUT is the output voltage
VIN is the input voltage
Due to capacitor’s degrading under DC bias, the bias voltage can significantly reduce capacitance. Ceramic
capacitors can lose most of their capacitance at rated voltage. Therefore, leave margin on the voltage rating to
ensure adequate effective capacitance. Typically, three 22μF ceramic output capacitors work for most applications.
Output Feedback Resistor Divider Selection
The SCT2360 features external programmable output voltage by using a resistor divider network R7 and R8 as
shown in the typical application circuit Figure 9. Use equation 8 to calculate the resistor divider values.
𝑅7 =
(𝑉𝑂𝑈𝑇 − 𝑉𝑟𝑒𝑓 ) × 𝑅8
𝑉𝑟𝑒𝑓
(8)
Table 3. Recommended Component Values for Typical Output Voltage (Vin=12V)
Fsw (kHz)
400
800
1200
Vout (V)
L (uH)
R7 (kΩ)
R8 (kΩ)
Cout(uF)
1.0
3.3
5.0
1.0
3.3
5.0
1.0
3.3
5.0
1.0
3.3
3.3
0.56
1.5
1.5
0.33
1.0
1.0
6.8
46.4
75.0
6.8
46.4
75.0
6.8
46.4
75.0
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
100
88
66
100
88
66
100
88
66
Table 4. Recommended Component Values for Typical Output Voltage (Vin=24V)
Fsw (kHz)
400
800
1200
14
Vout (V)
L (uH)
R7 (kΩ)
R8 (kΩ)
Cout(uF)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
3.3
1.5
1.5
1.0
1.0
46.4
75.0
46.4
75.0
46.4
75.0
10.2
10.2
10.2
10.2
10.2
10.2
88
66
88
66
88
66
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SCT2360
Application Waveforms(continued)
Vin=12V, Vout=5V, unless otherwise noted
Figure 10. Power up
Figure 11. Power down
Figure 12. EN toggle (Iload=6A)
Figure 13. EN toggle (Iload=10mA)
Figure 14. Over Current Protection(1A to hard short)
Figure 15. Over Current Release (hard short to 1A)
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15
SCT2360
Application Waveforms
Vin=12V, Vout=5V, unless otherwise noted
16
Figure 16. Load Transient (1.5A-4.5A, 1.6A/us)
Figure 17. Output Ripple (Iload=0A, PFM)
Figure 18. Output Ripple (Iload=0A, USM)
Figure 19. Output Ripple (Iload=0A, FPWM)
Figure 20. Output Ripple (Iload=6A)
Figure 21. Thermal, 12VIN, 5Vout, 6A
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SCT2360
Layout Guideline
Proper PCB layout is a critical for SCT2360 stable and efficient operation. The traces conducting fast switching
currents or voltages are easy to interact with stray inductance and parasitic capacitance to generate noise and
degrade performance. For better results, follow these guidelines as below:
0402
1. Place a low ESR ceramic capacitor as close to VIN pin and the ground as possible to reduce parasitic effect.
2. For operation at full rated load, the top side ground area must provide adequate heat dissipating area. Make
sure top switching loop with power have lower impendence of grounding.
3. The bottom layer is a large ground plane connected to the ground plane on top layer by vias. it is recommended
8mil diameter drill holes of thermal vias, but a smaller via offers less risk of solder volume loss. On applications
where solder volume loss thru the vias is of concern, plugging or tenting can be used to achieve a repeatable
process.
4. Output inductor should be placed close to the SW pin. The area of the PCB conductor minimized to prevent
excessive capacitive coupling.
5. UVLO adjust and loop compensation and feedback components should connect to small signal ground which
must return to the GND pin without any interleaving with power ground.
6. Route BST resistor and capacitor with a minimized length between the BST PIN and SW PIN.
VOUT
EN
FB
AGND
VCC
12
11
10
9
11
VIN
8
7
PG
BST
0603
SW
22
PGND
3
PG
4
FSEL
5
6
VOUT MODE
L1
0805
VOUT
Figure 22. PCB Layout Example
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17
SCT2360
PACKAGE INFORMATION
SYMBOL
MIN
0.7
0
A
A1
A2
A3
b
b1
D
E
e
e1
L
L1
L2
aaa
ccc
eee
bbb
0.2
0.25
0.3
1.725
1.95
MILLIMETER
NOM
0.75
0.02
0.55
0.203REF
0.25
0.3
3 BSC
3 BSC
0.5 BSC
1.1 BSC
0.4
1.825
2.05
0.1
0.1
0.08
0.1
MAX
0.8
0.05
0.3
0.35
0.5
1.925
2.15
NOTE:
1.
2.
3.
4.
5.
Drawing proposed to be made a JEDEC package outline MO-220 variation.
Drawing not to scale.
Thermal pad shall be soldered on the board.
Dimensions of exposed pad on bottom of package do not include mold flash.
Contact PCB board fabrication for minimum solder mask web tolerances between the pins.
18
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SCT2360
TAPE AND REEL INFORMATION
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19
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