AU5329B00-QMR

Au5329: Dual Frequency Translation and Jitter Clean Synthesizer General Description Features The Au5329 is a programmable Dual Fractional Frequency translation based jitter attenuating clock synthesizer with flexible input to output frequency translation options. It supports up to 2 input clocks that are common for all the 2 fractional translations and provides 10 clock outputs. The clock outputs can be derived from the 2 PLLs in a highly flexible manner. It is fully programmable with the I2C / SPI interface or an on chip two time programmable non-volatile memory for factory pre-programmed devices. Using advanced design technology, it provides excellent integrated jitter performance as well as low frequency offset noise performance while working reliably for ambient temperatures from -40 °C to 85 °C. The chip has best in class transient performance features in terms of clock switching transients and repeatable input to output delays • Nomenclature: • • Au5329: 2 input, 10 output, 64-QFN 9 mm X 9 mm Au5329: VDDIN = VDD = 3.3 V or 2.5 V • • o o o o o o • • • o o o Applications: • • • • • • • • • • • Carrier Ethernet, OTN Equipment, Microwave Backhaul, Gigabit Ethernet, Wireless Infrastructure, Network Line Cards, Small Cells, Data Center/Storage, SONET/SDH, Test / Instrumentation, Broadcast Video o • • • • • • Flexible dual PLL frequency translation from a common input: fractional output domains from single input Fully Integrated Fractional N PLLs with integrated VCO and programmable loop filter (1 mHz to 4 kHz) Wide frequency support Differential Output from 8 KHz to 2.1 GHz Single Ended Output from 8 KHz to 250 MHz Support for 1 Hz frequency on one output Differential Input from 8 KHz to 2.1 GHz Single Ended Input from 8 KHz to 250 MHz Multiple Crystals / XO / TCXO / OCXO support LVPECL, CML, HCSL, LVDS and LVCMOS Outputs 150 fs typical rms integrated jitter performance Synchronized, holdover or free run operation modes Meets G.8262 EEC Option 1,2(Sync E) Hitless input clock switching: Auto or manual Sub 50 ps phase build out mode transients Phase Propagation with programmable slopes Frequency ramp for plesiochronous clocks with programmable slopes Robust and fast cycle slip and frequency step detection for input frequency steps (Clean frequency tracking for large frequency steps) Excellent Close-in Phase noise performance with no external discrete VCXOs or passive external filters Digitally Controlled Oscillator mode: to 0.005 ppb Programmable Output Delay Control Programmable Frequency Ramp Slopes for Switching Pleisochronous Clocks Indicators: Lock Loss, Clock Loss, Frequency Drift Repeatable Input to Output delays for each power up of chip Figure 1 Functional Overview Au5329 Short Datasheet Table of Contents General Description ................................................................................................................................................1 Features ..................................................................................................................................................................1 Table of Contents ...................................................................................................................................................2 List of Tables ..........................................................................................................................................................3 List of Figures .........................................................................................................................................................4 Detailed Pin Description .............................................................................................................................5 Electrical Characteristics ............................................................................................................................8 Functional Description ............................................................................................................................. 19 Master and Slaves: Architecture Description and Programming Procedures ......................................... 23 Input Slave Description ............................................................................................................................ 27 Clock Monitor Slave Description .............................................................................................................. 28 6.1 Fault Monitoring ................................................................................................................................... 28 6.1.1 Clock Loss Monitors..................................................................................................................... 29 6.1.2 Frequency Drift Monitors ............................................................................................................. 29 6.1.3 Lock Loss Monitors ...................................................................................................................... 30 6.1.4 XO Clock Loss Monitors .............................................................................................................. 30 Output Slave Description ......................................................................................................................... 31 PLL Slave Description ............................................................................................................................. 32 PLL Input Selection: Manual and Hitless Switching ................................................................................ 33 PLL Bandwidth Control ............................................................................................................................ 34 PLL Crystal Clock Reference................................................................................................................... 35 PLL Lock Loss Defect Monitoring ............................................................................................................ 36 PLL DCO Mode operation ....................................................................................................................... 37 Package Information ................................................................................................................................ 38 Output Termination Information ............................................................................................................... 39 Input Termination Information .................................................................................................................. 44 Crystal Pathway Connectivity Options ..................................................................................................... 47 Ordering Information ................................................................................................................................ 50 Revision History ....................................................................................................................................... 51 Trademarks .............................................................................................................................................. 52 Contact Information ................................................................................................................................. 53 Aura Semiconductor Confidential Rev 1.0 Page 2 of 53 Au5329 Short Datasheet List of Tables Table 1 Detailed Pin Description ............................................................................................................................5 Table 2 Absolute Maximum Ratings .......................................................................................................................8 Table 3 Operating Temperatures and Thermal Characteristics .............................................................................8 Table 4 DC Electrical Characteristics .....................................................................................................................9 Table 5 Input Clock Characteristics ..................................................................................................................... 10 Table 6 Serial and Control Input .......................................................................................................................... 11 Table 7 Output Serial and Status Pin .................................................................................................................. 11 Table 8 Output Clock Characteristics .................................................................................................................. 11 Table 9 Fault Monitoring Indicators ..................................................................................................................... 13 Table 10 Crystal Requirements ........................................................................................................................... 13 Table 11 Output RMS Jitter in Frequency Translation Modes ............................................................................ 14 Table 12 Close In Offset Phase Noise ................................................................................................................ 15 Table 13 Power Supply Rejection ....................................................................................................................... 16 Table 14 Adjacent Output Cross Talk .................................................................................................................. 17 Table 15 Output Clock Specifications .................................................................................................................. 17 Table 16 PIF Description ..................................................................................................................................... 22 Table 33 Ordering Information for Au5329 .......................................................................................................... 50 Table 34 Revision History .................................................................................................................................... 51 Aura Semiconductor Confidential Rev 1.0 Page 3 of 53 Au5329 Short Datasheet List of Figures Figure 1 Functional Overview .................................................................................................................................1 Figure 2 Au5329 Top View .....................................................................................................................................5 Figure 3 Representative Phase Noise Measurement .......................................................................................... 15 Figure 4 Representative Close In Phase Noise Measurement ........................................................................... 16 Figure 5 Au5329 Overall Architecture ................................................................................................................. 19 Figure 6 Au5329 Overall Hierarchy of Clocks .................................................................................................... 20 Figure 7 Au5329 Input Clock Distribution ............................................................................................................ 20 Figure 8 Au5329 PLL Divider............................................................................................................................... 21 Figure 9 Output Clock Distribution ....................................................................................................................... 21 Figure 10 Master Memory Structure .................................................................................................................... 23 Figure 11 Slave Memory Structure ...................................................................................................................... 24 Figure 12 Master Wake-up Finite State Machine ................................................................................................ 25 Figure 13 Slave Wake-up Finite State Machine .................................................................................................. 26 Figure 14 PLL Architecture .................................................................................................................................. 32 Figure 15 Au5329 – 64 QFN Package Description ............................................................................................. 38 Figure 16 LVPECL DC Termination to VDDO – 2V ............................................................................................ 39 Figure 17 LVPECL Alternate DC Termination: Thevenin Equivalent .................................................................. 39 Figure 18 DC Coupled LVDS Termination .......................................................................................................... 40 Figure 19 DC Coupled CML ................................................................................................................................ 40 Figure 20 AC Coupled Receiver side resistive Termination options ................................................................... 41 Figure 21 Alternate AC Coupled LVPECL with DC coupled resistors on Chip side ............................................ 42 Figure 22 DC Coupled LVCMOS ......................................................................................................................... 42 Figure 23 HCSL AC Coupled Termination. Source Terminated 50 Ohm ............................................................ 43 Figure 24 HCSL DC Coupled Termination. Source Terminated 50 Ohm ........................................................... 43 Figure 25 AC Coupled Differential LVDS Input / Other AC Coupled Driver without DC Terminations ............... 44 Figure 26 AC Coupled Differential LVPECL or CML ........................................................................................... 44 Figure 27 DC Coupled Single Ended Driver ........................................................................................................ 45 Figure 28 AC Coupled Single Ended Driver with 50 Ohm Termination on receiver (chip) side .......................... 45 Figure 29 AC Coupled Single Ended LVCMOS input without 50 Ohm Termination ........................................... 46 Figure 30 Crystal Connection .............................................................................................................................. 47 Figure 31 CMOS XO Connection ........................................................................................................................ 48 Figure 32 Differential XO Connection .................................................................................................................. 49 Aura Semiconductor Confidential Rev 1.0 Page 4 of 53 Au5329 Short Datasheet Detailed Pin Description Figure 2 Au5329 Top View Table 1 Detailed Pin Description Pin Name I/O Type Au5329 IN1P Input 1 IN1N Input 2 IN2P Input 14 IN2N Input 15 GND Power EPAD OUT0P Output 28 OUT0N Output 27 OUT1P Output 31 OUT1N Output 30 OUT2P Output 35 OUT2N Output 34 OUT3P Output 38 Aura Semiconductor Confidential Function Comments True input for IN1 differential pair. Input for LVCMOS IN1 input. Need series external capacitor for differential input. Complement input for IN1 differential pair. Ground with capacitor for LVCMOS IN1 input. Need series external capacitor for differential input. True input for IN2 differential pair. Input for LVCMOS IN2 input. Need series external capacitor for differential input. Complement input for IN2 differential pair. Ground with capacitor for LVCMOS IN2 input. Need series external capacitor for differential input. IN1 / IN2 inputs can be used for output clock synchronization. An active clock and three spare clocks are chosen such that the same choice holds for all PLLs. Electrical and Package Ground Exposed Ground on the bottom E-PAD Output 0 True Output or Output 0 LVCMOS. Output 0 Complement Output or Output 0 LVCMOS. Output 1 True Output or Output 1 LVCMOS. Output 1 Complement Output or Output 1 LVCMOS. Output 2 True Output or Output 2 LVCMOS. Output 2 Complement Output or Output 2 LVCMOS. Output 3 True Output or Output 3 LVCMOS. LVPECL, LVDS, HCSL, CML and LVCMOS support. Rev 1.0 Page 5 of 53 Au5329 Short Datasheet Pin Name I/O Type Au5329 Function Output 3 Complement Output or Output 3 LVCMOS. Output 4 True Output or Output 4 LVCMOS. Output 4 Complement Output or Output 4 LVCMOS. Output 5 True Output or Output 5 LVCMOS. Output 5 Complement Output or Output 5 LVCMOS. Output 6 True Output or Output 6 LVCMOS. Output 6 Complement Output or Output 6 LVCMOS. Output 7 True Output or Output 7 LVCMOS. Output 7 Complement Output or Output 7 LVCMOS. Output 0B True Output or Output 0B LVCMOS. Output 0B Complement Output or Output 0B LVCMOS. Output 1B True Output or Output 1B LVCMOS. Output 1B Complement Output or Output 1B LVCMOS. OUT3N Output 37 OUT4P Output 42 OUT4N Output 41 OUT5P Output 45 OUT5N Output 44 OUT6P Output 51 OUT6N Output 50 OUT7P Output 54 OUT7N Output 53 OUT0BP Output 21 OUT0BN Output 20 OUT1BP Output 24 OUT1BN Output 23 VDDIN Power 13 Power Supply Voltage pin VDD Power 46,60 Power Supply Voltage pin IN_SEL0 Input 3 IN_SEL1 Input 4 FLEXIO3 Output 5 RSTB Input 6 OEb Input 11 INTRb Output 12 SCLK Input 16 SDO Output 17 SDAIO Input/Output 18 CSB Input 19 I2C1_SPI0 Input 39 Aura Semiconductor Confidential Input Clock Selection for Manual selection of active clock. Can be left floating or pulled down to GND if not used. Flexible Status GPIO. Can be left floating or pulled down to GND if not used. Active low reset internally pulled up to VDDIO; Pull Up Resistor to VDDIO of fixed value (25 KΩ). Can be left floating or pulled up to VDD if not used. Used to disable (when 1) all the output clocks. Can be left floating or pulled down to GND if not used Active low indicator of programmable sticky notifies. Can be left floating if not used. I2C Serial Interface Clock or SPI Clock Input. Pull Up Resistor to VDDIO of fixed value (25 KΩ) Serial Data Output (SPI Interface). In I2C mode this is the A1 address pin (see I2C section) I2C Serial Interface Data (SDA) / SPI Input data (SDI) Chip Select for the SPI Interface. In I2C mode this is the A0 address pin (see I2C section) Choose between SPI (0) and I2C(1) interface being used Rev 1.0 Comments Decoupling capacitor close to supply pin required. Multiple Supply Pins, Decoupling capacitor close to each supply pin required. Active low signal performs a complete reset of the part Page 6 of 53 Au5329 Short Datasheet Pin Name I/O Type Au5329 LOLb Input/Output 47 FDEC Input/Output 25 FINC Input/Output 48 FLEXIO14 Input/Output 55 FLEXIO15 Input/Output 56 {X1, X1G} Input/Output 8,7 {X2, X2G} Input/Output 9,10 VDDO0 Power 26 VDDO1 Power 29 VDDO2 Power 33 VDDO3 Power 36 VDDO4 Power 40 VDDO5 Power 43 VDDO6 Power 49 VDDO7 Power 52 VDDO1B Power 22 NC No Connect 32, 57, 58, 59, 61, 62, 63, 64 Function Loss of Lock Indicator (NOR value of all PLLs’ LOL active high indicators comes out on the LOLb pin). Can be left floating if not used. DCO Decrement. Can be left floating or pulled down to GND if not used. DCO Increment. Can be left floating or pulled down to GND if not used. Can also be used as SYSREF Trigger to start the SYSREF clock. Please refer AN53006. Flexible Outputs can be used for programmable status monitoring (Refer AN53001 for more information). Can be left floating or pulled down to GND if not used. Crystal X1 Pin and accompanying ground pin Crystal X2 Pin and accompanying ground pin Output Power Supply for Bank 0 outputs Output Power Supply for Bank 1 outputs Output Power Supply for Bank 2 outputs Output Power Supply for Bank 3 outputs Output Power Supply for Bank 4 outputs Output Power Supply for Bank 5 outputs Output Power Supply for Bank 6 outputs Output Power Supply for Bank 7 outputs Output Power Supply for Bank 0B and 1B outputs Comments {X1G, X2G} land on a floating island on the PCB Decoupling capacitor close to each supply pin required. No connect. This pin is not connected to the die. Notes: 1. VDDIO is the voltage used for all the status GPIOs and the serial interface. The default voltage for VDDIO can be chosen as either VDDIN or VDD through the programmable GUI. 2. All digital input/output GPIOs (FLEXIOs) have an on-chip 25 kΩ pull down resistor to ePAD ground (unless mentioned otherwise) and can be left unconnected if not used. 3. The I2C1_SPI0 pad has a an on-chip 25 kΩ pull up resistor to indicate default mode of communication as I2C unless this pin is pulled down on the board to indicate the SPI mode. 4. In I2C mode, the serial data and clock have an on-chip 25 kΩ pull up resistor to VDDIO. 5. The RSTB pin has an on-chip 25 kΩ pull up resistor to VDDIO. Writing 0xFE[0] to 1 with delay addition of 10ms has the same effect as the pulling RSTB pin to GND for chip reset. 6. SDO and CSB pins are used to set the I2C default address as 0x69 when floating since SDO and CSB has 25k pull down and pull up to GND and VDDIN respectively. Otherwise the I2C address can be changed as 11010{SDO},{CSB} by forcing the SDO and CSB externally to VDDIN or GND accordingly. a. The chip can be reset from the register map by writing address 0xFE as 0x01 using the current I2C address. b. To disable reset from register map by writing 0xFE register as 0x00, Address needs to be 0b11010{SDO}{CSB}, 5 MSB address bits are 11010, LSB 2 bits are the state of SDO and CSB pins. If these pins are floating, use 0x69 as the address. At all other times default slave address chosen for the part can be used. Aura Semiconductor Confidential Rev 1.0 Page 7 of 53 Au5329 Short Datasheet Electrical Characteristics Table 2 Absolute Maximum Ratings Description Conditions Symbol Min VDDIN Typ Max Units -0.5 +3.63 V VDD -0.5 +3.63 VDDO -0.5 +3.63 V +3.63 V Core supply voltage, Analog Input Core supply voltage, PLL Output bank supply voltage Input voltage, All Inputs Relative to GND VIN -0.5 XO Inputs Relative to GND VXO -0.5 +1.4 V I2C Bus input voltage SCLK, SDAT pins VINI2C -0.5 +3.63 V VINSPI -0.5 +3.63 V TS -55 +150 °C TPROG +25 +85 °C +125 °C 2.625 V SPI Bus input voltage Storage temperature Programming Temperature Maximum Junction Temperature in Operation Programming Voltage (for Programming the OTP Fuse Memory). ESD (human body model) Latchup Notes: • • Non-functional, NonCondensing TJCT VPROG 2.375 2.5 JESD22A-114 ESDHBM 2000 V JEDEC JESD78D LU 100 mA Exceeding maximum ratings may shorten the useful life of the device. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or at any other conditions beyond those indicated under the DC Electrical Characteristics is not implied. Exposure to Absolute-Maximum-Rated conditions for extended periods may affect device reliability or cause permanent device damage. Table 3 Operating Temperatures and Thermal Characteristics Description Conditions Symbol Min Typ Max Units Ambient temperature TA –40 – +85 °C Junction temperature TJ +125 °C Au5329 64-QFN Package Still Air Thermal Resistance Junction to Ambient Air Flow 1m/s θJA Air Flow 2m/s 25.5 °C/W 20.8 °C/W 19.6 °C/W Thermal Resistance Junction to Case θJC 8.70 °C/W Thermal Resistance Junction to Board θJB 7.07 °C/W Thermal Resistance Junction to Top Center ψJT 0.2 °C/W Aura Semiconductor Confidential Rev 1.0 Page 8 of 53 Au5329 Short Datasheet Table 4 DC Electrical Characteristics Description Conditions Symbol Min Typ Max Units 2.97 3.3 3.63 V 2.375 2.5 2.625 V Au5329 Supply voltage, Analog Input Pathways and XTAL Pathways Supply voltage, PLL 3.3 V range: ±10% 2.5 V range: ±5% 3.3 V range: ±10% 2.5 V range: ±5% VDDIN[1] VDD[1] 1.8 V range: ±5% Supply Voltage, Output Drivers 2.5 V range: ±5% VDDO 3.3 V range: ±10% 2.97 3.3 3.63 V 2.375 2.5 2.625 V 1.71 1.80 1.89 V 2.375 2.50 2.625 V 2.97 3.3 3.63 V 1175 1410 mW 390 470 mW Au5329 (VDDIN = VDD = 3.3 V; VDDO = 1.8 V) Total Power Dissipation (2.5V LVDS Outputs @ 156.25M) 2 PLLs, 10 Outputs (2 Independent Fractional Translations) Pd 1 PLL, 2 Outputs Supply Current, VDDIN Both Inputs assumed to be enabled IDDIN[1] 10 12 mA Supply Current, VDD Both PLLs and All 10 Outputs enabled (Maximum current mode) IDD 220 264 mA LVPECL, output pair terminated 50  to VTT (VDDO – 2 V). IDDO[2,3,4,5,6] 40 48 mA 28 36 mA Power supply current, VDDO LVPECL2, output pair terminated 50  to VTT (VDDO – 2 V) or 0 V without common mode current. Power supply current, VDDO CML, output pair terminated 50  to VDDO IDDO[2,3,4,5,6,7 20 24 mA Power supply current, VDDO HCSL, output pair with HCSL termination IDDO[2,3,4,5,6,7 27 36 mA Power supply current, VDDO LVDS, output pair terminated with an AC or DC Coupled diff 100  IDDO[2,3,4,5,6,7 16 19.2 mA Power supply current, VDDO LVDS Boost, output pair terminated with an AC or DC Coupled diff 100  IDDO[2,3,4,5,6,7 20 24 mA Power supply current, VDDO LVCMOS, 250 MHz, 2.5 V output, 5 pF load IDDO[2,3,4,5,6,7 15 18 mA Notes: 1. 2. 3. 4. 5. 6. 7. VDD and VDDIN are independent supplies that are expected to be at the same voltage level (either 3.3 V or 2.5 V) for Au5329. Additional current consumption of 3 mA for a third overtone crystal instead of a fundamental mode crystal. LVPECL and LVDS Boost standards are supported for VDDO = {2.5 V, 3.3 V}. LVPECL2, HCSL, CML and LVDS standards are supported for VDDO = {1.8 V, 2.5 V, 3.3 V}. LVPECL mode provides 6mA of common mode current on each output. LVPECL2 mode does not provide this common mode current. A 50 Ω Termination resistor with a DC bias of VDDO – 2 V for LVPECL standards is supported for VDDO = {2.5 V, 3.3 V}. IDDOx Output driver supply current specified for one output driver in the table. This includes current in each of the output module that includes output dividers, drivers and clock distributions. The LVDS Boost Mode and the LVDS Mode can be used for AC Coupled output terminations. LVDS Boost provides an LVPECL like swing with an AC Coupled 100 Ω Differential termination. Refer to Output Termination Information in the data sheet for the descipription of the various terminations that are supported. For efuse programming in Au5329, VDD alongwith VDDIN can be set to 2.5 V and has no reliability concerns. Aura Semiconductor Confidential Rev 1.0 Page 9 of 53 Au5329 Short Datasheet Table 5 Input Clock Characteristics Parameter Test Condition Symbol Min Typ Max Unit Standard Input Buffer with Differential or Single-Ended — AC-coupled (IN1/IN1, IN2/IN2) 0.008 — 2100 MHz 0.008 — 250 MHz 100 — mV 400 MHz< AC-coupled fIN < 750 MHz 225 — mV 750 MHz < ACcoupled fIN < 2100 MHz 350 — mV AC-Coupled fIN < 250 MHz 500 _ 3600 mV Differential Input Frequency Range Voltage Swing (Differential Amplitude Peak or Single Ended Peak to Peak for the differential signal) [1] Single Ended AC Coupled Inputs (Single Ended Peak to Peak Input) [1][4] fIN All Single-ended signals (including LVCMOS) AC-coupled fIN < 400 MHz VIN Slew Rate [2,3] SR 400 — — V/µs Duty Cycle DC 40 — 60 % CIN — 0.3 — pF RIN — 15 — kΩ — 10 — kΩ 0.008 — 250 MHz VIL –0.2 — 0.4 V VIH 0.8 — — V SR 400 — — V/µs DC 40 — 60 % PW 1.6 — — ns RIN — 30 — kΩ 48 - 160 MHz 37.5 - 160 MHz Input Capacitance Input Resistance AC Coupled SE Differential Pulsed CMOS Input Buffer — DC-coupled (IN1, IN2) fIN_PULSED_ Input Frequency CMOS Input Voltage Slew Rate [2,3] Duty Cycle Minimum Pulse Width [3] Pulse Input Input Resistance Reference Clock (Applied to X1), Can be external XO, TCXO or OCXO Reference Clock Frequency Range for best jitter FIN_REF Overall supported range Single Ended peak to peak VIN_SE 365 - 2000 mVpp_se Differential peak to peak VIN_DIFF 365 - 2500 mVpp_diff Slew rate SR 400 - - V/us Duty Cycle DC 40 - 60 % Input Voltage Swing Notes: 1. 2. 3. 4. AC Coupled input assumed with series capacitance for differential inputs or single ended AC Coupled inputs. Swing requirement at device pins. Resistor termination for differential input followed by series capacitors for each of true and complement differential input connecting to the device pins. LVCMOS single ended is direct coupled on the true input. Connect complement input to ground with a 100 nF capacitor. Single Ended AC coupled Input Swing requirement (Single Ended Peak to Peak Input) [1][4] is for optimal noise performance. Aura Semiconductor Confidential Rev 1.0 Page 10 of 53 Au5329 Short Datasheet Table 6 Serial and Control Input Parameter Test Condition Symbol Min Typ Max Unit VIL — — 0.3 x VDDIO 1 V VIH 0.7 x VDDIO 1 — — V Input Capacitance CIN — 1 — pF Input Resistance RIN — 25 — kΩ PW 100 — — ns Input Voltage Minimum Pulse Width FINC, FDEC Update Rate FINC, FDEC FUR — — 1 µs Notes: 1. VDDIO is the voltage used for all the status GPIOs and the serial interface. The default voltage for VDDIO can be chosen as either VDDIN or VDD with a hard coded eFuse based selection. Table 7 Output Serial and Status Pin Parameter Test Condition Symbol Min Typ IOH = –2 mA IOL = 2 mA Max Unit VOH VDDIO x 0.75 VOL — — — V — VDDIO x 0.25 Typ Max Units All VDDIO Based GPIOs Output Voltage V Notes: 1. VDDIO is the voltage used for all the status GPIOs and the serial interface. The default voltage for VDDIO can be chosen as either VDDIN or VDD with a hard coded eFuse based selection. Table 8 Output Clock Characteristics Description Conditions Symbol Differential output frequency LVPECL, CML, LVDS outputs FOUT,DIFF [1] 1 2100M Hz Differential output frequency HCSL outputs FOUT,DIFFH [1] 1 700 M Hz Single ended output frequency LVCMOS outputs FOUN,SE [1] 1 250 M Hz PLL loop bandwidth Programmable FBW 0.001 4000 Hz Jitter peaking Meets SONET Jitter Peaking requirements in closed loop JPEAK 0.1 dB Time delay before the Historical average for output Frequency is considered. Programmable in register map HDELAY [2,3] 0.035 0.5 35 s Length of time for which the Average of the frequency is considered Programmable in register map HAVG [2,3] 0.07 1 70 s Power Supply to I2C or SPI interface ready No I2C transaction valid till 10ms after all power supplies are ramped to 90% of final value. TSTART 10 ms With Speed-Up mode enabled Speed-up mode is programmable. This is a Typical number. Actual wake up time depends on fast lock and normal BW settings TLOCK [4] Aura Semiconductor Confidential Rev 1.0 Min 300 ms Page 11 of 53 Au5329 Short Datasheet Description Conditions Symbol Min Typ Max Units DCO Mode Frequency Step Resolution Frequency Increment or Decrement resolution. This is controlled through the register map. FRES,DCO [5] Resolution for output delay Programmable per output clock with this resolution for a total delay of ±7.5 ns TRES [6] Maximum Phase Hit Default Hitless Switching Mode (no phase propagation) TMAX [7] -50 50 ps Uncertainty in Input to Output Delay Maximum variation in the static delay from input to output clock between repeated power ups of the chip ΔTDELAY -175 175 ps 0.005 ppb 35 ps Pull Range ωP POR to Serial Interface Ready TRDY 15 ms TSTART,Special 10 ms One free run PLL clock on fuse locked parts Notes: 1. 2. 3. 4. 5. 6. 7. Using a special mode for fuse locked parts to generate one free run output from one PLL 500 ppm 1 Hz Output Available only on output OUT0B (OUT0BP, OUT0BN). Range supported is 8 kHz to 2100 MHz for all the other outputs. Hitless Switching enables PLL to switch between input clocks when the current clock is lost, a. Clock Loss can be defined as 2 / 4 / 8 / 16 consecutive missing pulses. b. Priority list for the input clocks can be set in the register map independently for each PLL. c. Output is truly hitless (no phase transient and 0 ppb relative error in frequency) for exactly same frequency input clocks that are switched. d. Hitless switching support is both revertive and non-revertive e. Revertive / Non-revertive Support: Assume Clock Input 0 is lost and switch is made to Clock Input 1. Then, PLL reverts to Clock Input 0 when it becomes valid again in Revertive mode. It does not switch back to Clock Input 0 even when it becomes valid again in the non-Revertive mode. PLL enters holdover mode when the active input clock and all spare clocks in the clock priority list for hitless switching are lost, a. Clock Loss can be defined as 2 / 4 / 8 / 16 consecutive missing pulses b. Entering hold over mode is supported with the frequency frozen at a historical average determined from the HDELAY and HAVG settings. For low PLL Loop Bandwidths, wake up time can be very large unless the speed up feature is used. The speed up feature provides the user options to use a completely independent loop bandwidth for the wake up transitioning to the regular bandwidth after frequency and phase are locked. a. Fast Lock Bandwidth needs to be less than 100 times smaller than the input clock frequency (divided input at PLL phase detector) for stable and bounded (in time) lock trajectory of the PLL The 0.005 ppb specification is for the smallest frequency step resolution available. Larger frequency step resolutions up to 100 ppm can be used also. The frequency resolution for the DCO mode frequency step is independently programmable for each DCO step. All output clocks from one specific PLL are phase aligned. Relative delay adjustment is then possible on each clock individually as defined by the TRES parameter. This test is for 2 inputs at 8 M that are switched to get a 622.08 M output. Aura Semiconductor Confidential Rev 1.0 Page 12 of 53 Au5329 Short Datasheet Table 9 Fault Monitoring Indicators Description Conditions Symbol Min Typ Max Units Clock Loss Indicator Thresholds Clock Loss Indicators can be set on any of the two inputs. Loss of 2 / 4 / 8 / 16 consecutive pulses can be used to indicate a clock loss. Programmable in the register map. CLX [1,4] 2 4 16 Pulses Fine Frequency Drift Indicator Thresholds: Step Size Fine Frequency Drift Indicator Thresholds: Hysteresis Range Fine Frequency Drift Indicator Thresholds: Range Frequency drift threshold is programmable in the range with the step size resolution specified. Frequency drift hysteresis is programmable in the range with the step size resolution specified. Coarse Frequency Drift Indicator Thresholds Coarse Drift Indicators programmable from {Up to ±1600 ppm in steps of ±100 ppm} Lock Loss Indicator Threshold Lock Loss Indicator threshold is programmable in the range specified from the following choices for setting and clearing LL: {±0.2, ±0.4} ppm, {±2, ±4} ppm, {±20, ±40} ppm, {±200, ±400} ppm, {±2000, ±4000} ppm FDX [2,3,4] LL ±2 ppm ±2 ±500 ppm ±2 ±500 ppm ±100 ±1600 ppm ±0.2 ±4000 ppm Notes: 1. Clock Loss Indicators are used for: a. Hitless Switching Triggers b. Update in Status Registers in the register map 2. Frequency Drift Indicators can use any one of the two inputs or the Crystal / Reference input as the golden reference with respect to which FDx for all other clocks can be recorded in the Status Registers. FDx thresholds for each clock input for each clock can be set independently. 3. Coarse and Fine Frequency Drift indicators can be concurrently enabled. This enables the user to detect fast drifting frequencies since detecting fine drifts will take longer measurements. 4. Clock loss and Lock loss indicators are available as alerts on flexible IO pins as described in the functional description section of the data sheet. 5. Clock Loss can be combined with either of the frequency drift monitors (coarse and fine) to trigger the hitless switching event in the PLLs. The trigger for a hitless switching event in the PLL can therefore be either the Clock Loss event or either of Clock Loss or Frequency Drift. Table 10 Crystal Requirements Description Conditions Symbol Min Typ Max Units 160 MHz 2 pF High Fundamental Frequency Crystal Reference (HFF) Crystal Frequency Can be supported with a fundamental crystal of 100-160 MHz range. C0 cap for crystal CL cap for crystal XTALIN 100 XTALC0 Small range around CL only Aura Semiconductor Confidential XTALCL Rev 1.0 5 pF Page 13 of 53 Au5329 Short Datasheet Description Conditions Symbol ESR for crystal ESR defined at frequency of oscillation Rm1 for crystal Power delivered to crystal Drive Level to the crystal Min Max Units XTALESR 40 Ω XTALRm1 20 Ω XTALPWR Typ 100 µW Third Overtone Crystal Reference (OT3) Crystal Frequency Can be supported with an OT3 crystal of 100160 MHz range. C0 cap for crystal XTALIN 100 XTALC0 160 MHz 2 pF CL cap for crystal Small range around CL only XTALCL ESR for crystal ESR defined at frequency of oscillation XTALESR[1] 80 Ω XTALRm3 40 Ω Rm3 for crystal Power delivered to crystal Drive Level to the crystal 5 XTALPWR pF 100 µW Low Frequency Fundamental Crystal (LFF) Crystal Frequency Can be supported with a fundamental crystal > 37.5 MHz range. For Best Performance use an LFF crystal > 48 MHz C0 cap for crystal 48 XTALC0 CL cap for crystal Small range around CL only ESR for crystal ESR defined at frequency of oscillation Rm1 for crystal Power delivered to crystal XTALIN Drive Level to the crystal XTALCL 54 MHz 2 pF 8 XTALESR pF [1] 60 Ω XTALRm1 40 Ω XTALPWR 100 µW Notes: 1. ESR relates to the motional resistance Rm with the relationship 𝐸𝑆𝑅 = 𝑅𝑚 (1 + 𝐶0/𝐶𝐿)2 Table 11 Output RMS Jitter in Frequency Translation Modes Description Conditions RMS Jitter for 12 kHz-20 MHz Integration Bandwidth FIN = 38.88 MHz, PLL BW = 100 Hz, Single PLL Profile FOUT = 622.08 MHz, FOUT = 156.25 MHz, Symbol RMSJIT[1,2] Min Typ Max Units 140 fs rms 150 fs rms Notes: 1. For best noise performance in jitter attenuation mode, use lowest usable loop bandwidth for the PLL. 2. Does not include noise from the input clocks to the PLL Aura Semiconductor Confidential Rev 1.0 Page 14 of 53 Au5329 Short Datasheet Figure 3 Representative Phase Noise Measurement Note: FOUT = 622.08 MHz, FIN = 38.88 MHz, BW = 100 Hz, FREF = 54M XO Table 12 Close In Offset Phase Noise Description Phase Noise Skirt FOUT = 122.88 MHz, PLL BW = 100 Hz Notes: 1. Conditions Symbol Offset Frequency = 100 Hz Offset Frequency = 1 kHz Min Typ Max Units -113 PN[1] Offset Frequency = 10 kHz -130 dBc/Hz -138 This is the noise contribution of the chip only without including the input and reference self contributions Aura Semiconductor Confidential Rev 1.0 Page 15 of 53 Au5329 Short Datasheet Figure 4 Representative Close In Phase Noise Measurement Note: FOUT = 122.88M, BW = 100 Hz, FREF and FIN are provided from R&S SMA100 equipment to ensure a low close in phase noise for the reference and input to illustrate the chip contribution to close in phase noise. Table 13 Power Supply Rejection Description FOUT = 156.25 MHz, FSPUR = 100 kHz, BW = 100 Hz PSRR on VDD Supply FOUT = 156.25 MHz, FSPUR = 100 kHz, BW = 100 Hz PSRR on VDDIN Supply FOUT = 156.25 MHz, FSPUR = 100 kHz, BW = 100 Hz Conditions Symbol VDD = 3.3 V Min Typ Units -85 PSRRVDD dBc VDD = 2.5 V -85 VDDIN = 3.3 V -100 PSRRVDDIN VDDIN = 2.5 V VDDO = 3.3 V Max dBc -100 PSRRVDDO -80 dBc PSRR on VDDO Supply Notes: 1. The PSRR is measured with a 50 mVpp sinusoid in series with the supply and checking the spurious level relative to the carrier on the output in terms of phase disturbance impact. 2. Output PSRR measured with LVDS standard which (along with the LVDS boost) are the recommended standards for AC Coupled terminations Aura Semiconductor Confidential Rev 1.0 Page 16 of 53 Au5329 Short Datasheet Table 14 Adjacent Output Cross Talk Description Conditions Symbol 156.25 M and 155.52 M on adjacent outputs Notes: • • • Min XTALK Typ Max Units -75 dBc Measured across adjacent outputs- All adjacent outputs are covered and the typical value for the worst case output to output coupling is reported. The adjacent output pairs are chosen at 155.52 MHz and 156.25 MHz frequencies. This cross talk between outputs is mainly package dependent therefore terminated outputs are used for reporting these numbers ensuring that there is signal current in the bond wires. Table 15 Output Clock Specifications Description Conditions Symbol Min Typ Max Units DC Electrical Specifications - LVCMOS output (Complementary Out of Phase Outputs or One CMOS Output per Output Driver) Output High Voltage 4 mA load, VDDO = 3.3 V VOH VDDO - 0.3 - V Output High Voltage 4 mA load, VDDO = 1.8 V and 2.5 V VOH VDDO - 0.4 - V Output Low Voltage 4 mA load VOL 0.3 V DC Electrical Specifications - LVCMOS output (In Phase Outputs) Output High Voltage 4 mA load, VDDO = 3.3 V VOH VDDO - 0.35 - V Output High Voltage 4 mA load, VDDO = 2.5 V VOH VDDO - 0.45 - V Output High Voltage 4 mA load, VDDO = 1.8 V VOH VDDO - 0.5 - V 1.375 V 50 mV 20 µA V DC Electrical Specifications – LVDS Outputs (VDDO = 1.8 V, 2.5 V or 3.3 V range) Output Common-Mode Voltage VDDO = 2.5 V or 3.3 V range Change in VOCM between complementary output states Output Leakage Current VOCM 1.125 1.2 ΔVOCM Output Off, VOUT = 0.75 V to 1.75 V IOZ -20 DC Electrical Specifications - LVPECL Outputs (VDDO = 2.5 V or 3.3 V range) Output High Voltage Rterm = 50 Ω to VTT(VDDO – 2.0 V) VOH VDDO-1.165 VDDO – 0.800 Output Low Voltage Rterm = 50 Ω to VTT(VDDO – 2.0 V), w/o common mode current VOL VDDO-2.0 VDDO –1.45 AC Electrical Specifications - HCSL Outputs (VDDO = 1.8 V, 2.5 V or 3.3 V range) Output High Voltage Max Measurement on singleended signal VMAX Output Low Voltage Min Measurement on singleended signal VMIN -300 mV Differential Voltage Measurement taken from differential waveform VP 300 mV Absolute Crossing point voltage Measurement taken from single ended waveform VCROSS 250 Variation of VCROSS over all rising clock edges Measurement taken from single ended waveform VCROSS DELTA 1150 mV 600 mV 140 mV DC Electrical Specifications - CML Outputs (VDDO = 1.8 V, 2.5 V or 3.3 V range) Output High Voltage Rterm = 50 Ω to VDDO VOH VDDO-0.085 VDDO – 0.01 VDDO V Output Low Voltage Rterm = 50 Ω to VDDO VOL VDDO-0.6 VDDO –0.4 VDDO – 0.3 V AC Electrical Specifications LVCMOS Output Load: 10 pF < 100 MHz, 7.5 pF < 150 MHz, 5 pF > 150 MHz > 200 MHz Output Frequency Output Duty cycle Measured at 1/2 VDDO, loaded, fOUT < 100 MHz Aura Semiconductor Confidential fOUT 8k 250M Hz tDC 45 55 % Rev 1.0 Page 17 of 53 Au5329 Short Datasheet Description Conditions Symbol Output Duty cycle Measured at 1/2 VDDO, loaded, fOUT > 100 MHz tDC Rise/Fall time VDDO = 1.8 V, 20-80%, Highest Drive setting Rise/Fall time Rise/Fall time Min Typ Max Units 60 % tRFCMOS 2 ns VDDO = 2.5 V, 20-80%, Highest Drive setting tRFCMOS 1.5 ns VDDO = 3.3 V, 20-80%, Highest Drive setting tRFCMOS 1.2 ns 2100M Hz 40 AC Electrical Specifications (LVPECL, LVDS, CML) Clock Output Frequency fOUT 8k PECL Output Rise/Fall Time 20% to 80% of AC levels. Measured at 156.25 MHz for PECL outputs. tRF 350 ps CML Output Rise/Fall Time 20% to 80% of AC levels. Measured at 156.25 MHz for CML outputs tRF 350 ps LVDS Output Rise/Fall Time 20% to 80% of AC levels. Measured at 156.25 MHz for LVDS outputs. tRF 350 ps Output Duty Cycle Measured at differential 50% level, 156.25 MHz tODC 45 50 55 % LVDS Output differential peak Measured at 156.25 M Output VP 247 350 454 mV Boosted LVDS Output differential peak Measured at 156.25 M Output VP 500 700 mV LVPECL Output Differential peak Measured at 156.25 M Output VP 450 750 mV VP 250 CML Output Differential Measured at 156.25 M Peak Output Notes: Convention for Wave Forms Aura Semiconductor Confidential Rev 1.0 600 mV Page 18 of 53 Au5329 Short Datasheet Functional Description Figure 5 Au5329 Overall Architecture Au5329 is a jitter attenuating frequency translation device family that offers two PLLs for 2 frequency translation pathways from the same input. The two clock inputs map to the two PLLs such that clock priority is the same across the 2 PLLs. This creates an arrangement that provides up to 2 fractional translations from one input at any given time. The output high frequency voltage controlled oscillators (VCOs) associated with each PLL are mapped to the 10 outputs in a very flexible fashion. This offers a very flexible frequency translation arrangement with independent control of each PLL in terms of jitter attenuation, bandwidth control and input clock selection with redundancy. The hierarchy of the clocks, nomenclature of the various frequency dividers as well as the clock translation pathways available on the chip are shown in Figure 5 Aura Semiconductor Confidential Rev 1.0 Page 19 of 53 Au5329 Short Datasheet Figure 6 Au5329 Overall Hierarchy of Clocks The two input clocks with frequencies fin_extk translate to PLL input clocks fink following division by the respective input dividers with fractional or integer frequency division ratios DIVN1k where the index k ϵ {1, 2}. See Figure 6. All of the PLLs choose one of the two divided input clocks fink as its active input clock and set the priority for up to three spare clocks from the remaining three input clocks if required for hitless switching to a redundant input. Figure 7 Au5329 Input Clock Distribution The crystal oscillator reference input (called fref) is also routed to each PLL. A TCXO or OCXO based input reference clock can also be used directly in place of the crystal oscillator. Each PLLx (x ϵ {B, D}) has a high frequency VCO whose frequency is determined in the free run mode by fref with the relation fVCOx = DIVNx*fref. In the frequency translation synchronized mode, the VCO frequency is corrected from its free run frequency to satisfy the relation fVCOx = DIVN2x*finx where finx is chosen from one of fink input clocks per the desired input clock priority for PLLx. Nominally the fractional dividers DIVNx and DIVN2x are chosen such that the relation DIVNx*fref = DIVN2x*fin,x = fVCOx is satisfied. See Figure 8. Aura Semiconductor Confidential Rev 1.0 Page 20 of 53 Au5329 Short Datasheet Figure 8 Au5329 PLL Divider Each of the Output Drivers (ODRj, j ϵ {0, 1, 2, 3, 4, 5, 6, 7, 1B, 0B}) then chooses an appropriate VCO frequency and divides it using their respective integer divider DIVOj to get the output frequency foutj. See Figure 9. Figure 9 Output Clock Distribution Aura Semiconductor Confidential Rev 1.0 Page 21 of 53 Au5329 Short Datasheet The choice of the fractional dividers {DIVN1k, DIVNx, DIVN2x, DIVOj} as well as the placement of foutj frequencies at various outputs is facilitated by associated software tools. The digital architecture of the chip is partitioned into a master digital controller and five slave controllers. The master controller and each of the five controllers has an associated volatile programmable interface (PIF). The overall PIF structure is a register map that is divided into several pages according to function. Each controller (master and slaves) has an associated unique Page number. Each Page has an independent 8 bit addressable PIF memory. In all the pages, the last address, FF, holds the current page number and is reserved for changing the page. The current page to be communicated with can be set by writing the page number in hexadecimal form {0x00, 0x01, 0x02, 0x03, 0x0B, 0x0D} corresponding to pages {0, 1, 2, 3, B, D} in the address FF on any page. Table 16 shows a summary of the PIF contents residing on each page. Table 16 PIF Description Page Contents 0 Master 1 ClkMon Slave 2 Input Slave 3 Output Slave B D PLL B Slave PLL D Slave Summary of contents All Generic Information related to the chip Chip Configuration details Control for the master sequencer FSM Crystal Reference Related Information Fuse Pointer for each of the remaining pages Clock Loss related function Frequency Drift related function Input 2 / 1 related information (Input type, DIVN1 divider configuration) Flexible Outputs 7 / 6 / 5 / 4 / 3 / 2 / 1 / 0 (ODR Standards, DIVO, Programmable delay configurations for each) Fixed Outputs 0B (ODR Standards, DIVO, Programmable delay configurations for each) All PLL related functionality All PLL related functionality Aura Semiconductor Confidential Rev 1.0 Page 22 of 53 Au5329 Short Datasheet Master and Slaves: Architecture Description and Programming Procedures The Master controller is the first system to autonomously wake up on the application of power to the chip due to on-chip power on reset circuitry. All generic system information resides in the Master controller memory and it proceeds to wake up the Slaves as required based on this information. The relative wake up sequences of the Master and the various Slaves are described in more detail later in this section after a description of the memory structures. A complete power up of the chip is also emulated with the release of an active low hard reset (RSTB) from pin while selective Master and Slave sub-system resets are enacted from software using the serial interface (I2C/SPI). The Master memory structure is shown in Figure 10. It contains a one-time programmable non-volatile memory (NVM) that stores the settings for the chip associated with the master controller. The master controller also contains a volatile PIF bank (NVMCopy) that has an exact copy of the NVM at every chip power up. This NVMCopy is the memory that is addressable using the serial interface (I2C/SPI) on Page 0 and can be overwritten from the I2C/SPI interface. The “Chip Settings” is the memory space that is not addressable from the I2C/SPI control and is the actual control for the chip. The NVM contains a two bit “Lock Pattern” that can be set to “10” or “01” to ‘lock’ the chip configuration once the final configuration is determined and wake up of the entire chip is desired in this configuration. Additionally, there is a bit in the NVM that is an active low indicator of a manual wake up. This bit set to “1” along with the ‘lock’ for the configuration leads to an autonomous wake up of the chip using the ‘locked’ configuration. Any number of different configurations can alternatively be tried at all times using only the volatile NVMCopy PIF section. This is useful for evaluations as well as allowing real time programming of the chip in various configurations with complete flexibility. The Master Controller finite state machine (FSM) described later in this section controls the device behavior in accordance with the configuration in this memory structure and as per the wake up mode. Figure 10 Master Memory Structure The memory structure for each slave is shown in Figure 11 and is similar in construction to the master controller memory structure with some minor differences. The NVMCopy volatile PIF for the slave is addressable by the serial interface with the unique Page number associated with the slave. The “Slave Settings” is the memory space that is not addressable from the I2C/SPI control and is the actual control for the slave. Each Slave has a two time programmable NVM by virtue of two copies of the NVM memory. This makes the slave settings two time programmable with the fuse pointer from the master controller determining which of the two NVM banks is used. Aura Semiconductor Confidential Rev 1.0 Page 23 of 53 Au5329 Short Datasheet The presence of two NVM banks is transparent to the slave controller since the current pointer which determines which of the two NVM banks is used is set by the master controller independently. Figure 11 Slave Memory Structure The Master Wake-Up Finite State Machine (FSM) is shown in more detail in Figure 12. At every power up of the device (or release from hard reset), the power-on-reset circuitry resets all systems and then autonomously releases only the master controller from reset. The NVM contents are copied to the NVMCopy volatile space on Page 0 which is in turn copied to the “Chip Settings”. The master controller now decides if the chip configuration is locked and it is an autonomous wake up of the entire chip or if a manual wake up is desired through the PIF based on the contents in the “Chip Settings”. In case a “Lock” is detected and an autonomous wake up is desired, the Master controller proceeds to enable the Crystal oscillator and associated fref pathways followed by the Slave systems in a pre-determined sequence. This finally leads the chip to the “Active State” with all desired outputs available as a result of all slave systems released from reset by the master controller. This is according to the requested settings that are programmed in the Master and the Slave NVM banks. For the case where the final chip settings are not frozen hence the “Lock” pattern is not exercised, the master controller FSM reaches the Program Command Wait State (PRG_CMD). The desired chip settings can be written in the NVMCopy on Page 0 using the serial interface and desired slave sub-systems can be enabled. Several PRG_CMD state directives are available that are exercisable only in this state. Using these directives, the desired settings written in NVMCopy can now be copied to “Chip Settings” followed by issuing the directive for the FSM to proceed to the “Active” state where each slave can now be manually written with the desired settings and in turn asked to proceed to its “Active” state. Aura Semiconductor Confidential Rev 1.0 Page 24 of 53 Au5329 Short Datasheet A similar “Lock” pattern is available in the NVM bank of each slave. The currently used NVM bank for a slave (as determined by the current pointer from the master controller) can be locked for the autonomous wake up of each slave. The slave wake-up FSM is shown in Figure 13 and it similarly has a PRG_CMD state with associated directives. On Proceed to Active state directive on the slave, the slave controller wakes up the various blocks in its sub-system with the correct pre-determined sequence. The NVM bank for the master and each slave can be programmed with a PRG_CMD directive in that state to lock a configuration / setting specific to the respective sub-system. Figure 12 Master Wake-up Finite State Machine Aura Semiconductor Confidential Rev 1.0 Page 25 of 53 Au5329 Short Datasheet Figure 13 Slave Wake-up Finite State Machine Each FSM (Master and Slaves) allows an escape sequence to go back to PRG_CMD state from its Active State. This can be used to selectively change the settings for that particular sub-system. Such an escape to the PRG_CMD state in the master FSM can be used for example to change current NVM pointers for any of the slaves. Note that the NVM for the master controller and current NVM for all slaves should be locked after writing desired settings for a completely autonomous wake up of the entire chip. The NVM pointer can then be changed for any slave independently if alternate settings are desired for that slave. In that case, the new NVM is unlocked and can be written with new settings and locked. For evaluations of the chip as well as cases where flexible on-thefly programmable settings are desired, the chip can be used without engaging the NVM banks at all by using the NVMCopy space for the master and each slave in conjunction with the PRG_CMD directives. It is also possible to lock some of the slaves (to not re-write their settings for each wake up) while use programmable settings for other slaves. This provides complete flexibility in terms of programming and using the chip in all scenarios. Aura Semiconductor Confidential Rev 1.0 Page 26 of 53 Au5329 Short Datasheet Input Slave Description Two independent clock inputs are available on the chip that can be routed to any PLL with complete flexibility. Both single ended and AC coupled differential clock inputs are possible. The input clock receiver settings (to receive a single ended or differential clock) as well as the input clock divider settings are configurable on Page 2 that is assigned to the Input Slave. It is possible to bypass the input clock divider and use the input clock directly as an input to the PLL. Aura Semiconductor Confidential Rev 1.0 Page 27 of 53 Au5329 Short Datasheet Clock Monitor Slave Description Various fault monitoring indicators are available on the chip. The Clock Loss and the Frequency Drift indicators are configurable with the Clock Monitor Slave that is accessible on Page 1. The specifications of these fault monitors are indicated in the specifications section of the data sheet. Defect monitoring on any of the clock monitors can be accessed using multiple techniques. The current status of the defect is available as an Active High defect that can be read from the PIF. The “status” is a current indicator of the defect that is high only during the defect (for example during the time that a Clock Loss event is on-going). Additionally, a sticky indicator of the defect called “Notify” can be enabled in the PIF. In this case, the concerned “notify” bit is high the first time the respective defect occurs and stays high till cleared. There are multiple FLEXIOs (Flexible IOs) available in the system that can be programmed to monitor individual “notify” signals or a combination of them (as an OR logic). The choice of which fault defect is monitored as an output on the FLEXIO pin is flexible and can be programmed. Additionally there are selected GPIOs that are hard coded for the information for the clock defects. 6.1 Fault Monitoring The Au53xx parts provide an elaborate arrangement of fault monitoring indicators. There are 4 categories of clock monitoring that are necessary for the chip namely: Clock Loss Monitor (CL), Frequency Drift Monitor (FD), Lock Loss Monitor (LL) and XO Clock Loss Monitor (CL_XO). Clock Loss (CL) monitors loss of input clocks defined as a pre-determined number of consecutive edges missing. Frequency Drift (FD) monitors frequency drift of a particular clock against a pre-determined Golden Reference. Lock Loss (LL) monitors the loss of lock in any PLL by monitoring the difference in frequency between the feedback and input clocks. XO Clock Loss (CL_XO) monitors the loss of the XO reference that is generated from either an external oscillator (XO / TCXO / OCXO) or using the on chip XO amplifier that can work with a crystal blank on the PCB. Each of these categories monitors the health of a particular clock for a certain failure type as illustrated in the name of the clock monitoring category. For each clock failure observed by the clock monitor block there are two types of indicators provided to the user using the register map: 1. Live Failure Bit: There is a bit to indicate the live status of a particular failure. [Status] 2. Sticky Failure Bit: For each live failure bit there is a corresponding sticky bit that is set the first time that corresponding failure is encountered and stays set even if the failure has gone away. Only when the user clears the bit does it clear. [Notify] The status of these can be either read from the register map or from the pins as a dynamic alarm monitoring arrangement. Additionally, sticky notify registers are available which have sticky status read back from the register map for the various defects. These can be selectively chosen to create an INTRB de-assertion on the INTRB pin as well. An important point to note is that all of the fault monitoring indicators mentioned above that work with respect to the input clock work on the divided input clock post the DIVN1,k dividers (refer to the data sheet for the respective Au53xx part). This implies that the fault monitoring indicators use the frequency fink that is input to the PLL (kє {1, 2}) post the DIVN1,k divider translation rather than the external frequencies fin_extk (k є {1, 2}). Aura Semiconductor Confidential Rev 1.0 Page 28 of 53 Au5329 Short Datasheet Section 20 in the full Datasheet describes the read back of the alarms for the various fault monitoring arrangements using the chip register map. 6.1.1 Clock Loss Monitors Each of the 2 inputs (IN1, IN2) are monitored for Clock Loss in terms of missing edges to indicate a loss of input signal. The number of edges used to indicate a clock loss (or recovery from a clock loss) is programmable in the Au53xx GUI interface allowing for flexibility in choosing these thresholds. In addition there is a programmable “Wait Time” all of which are to be interpreted as follows: Assertion of Clock LossWe declare a CL if “Trigger Edge” number of consecutive edges are missing. The “Trigger Edge” parameter is programmable in the chip GUI. De-Assertion of Clock LossWe declare a ~CL if the clock is back and has less than “Clear Edge” consecutive edges missing. The “Clear Edge” parameter is programmable in the chip GUI. Wait Time: After the clock is established to have returned, it is ensured that no CL error as defined by the deassertion threshold occurs for “Val Time” seconds. This valid wait time is programmable using the chip GUI using the “Val Time” parameter which is programmable from the following options: {2 m, 100 m, 200 m, 1} sec. The use of the this valid wait time ensures that sporadic edges in the input clock (such as ones caused by noise on floating nodes or intermittent unstable clock edges) does not de-assert clock loss and it is established over a user determined period of time that the input clock is available and stable. 6.1.2 Frequency Drift Monitors Any one of the 2 input clocks or the XO clock can be used as the Golden Clock for calculating the frequency drifts of the other 2 clocks. The Golden Clock can be chosen in the GUI and is used as the “0 ppm” Reference Clock for all monitoring. Fine Frequency Drift has a step size of ±2 ppm. Fine Frequency Drift has a range of ±2 to ±510 ppm and an independent threshold is programmable for “Set” (for setting the FD monitor) and for “Clear” (for clearing the FD monitor). Fine Frequency Drift has an implicit hysteresis with resolution of ±2 ppm since the same range is available for the FD assertion and de-assertion. Use of hysteresis prevents unwanted oscillation of the FD monitor output at the decision threshold and is recommended for robust operation. The value of the FD threshold hysteresis is implicit in the choice of the set and clear thresholds. The Fine Frequency Drift monitors provide precise information for input clock frequency drift. However, since the resolution of the measurement determines time for the measurement- an alternate faster measurement mechanism for drift is needed. This is Coarse Frequency Drift which has coarser measurement but is fast. It is available for cases where the drift is very fast in the input frequency and is programmable from options as shown below. Coarse Frequency Drift has a step size of ±100 ppm. Coarse Frequency Drift has a range of ±100 to ±1600 ppm and an independent threshold is programmable for “Set” (for setting the FD monitor) and for “Clear” (for clearing the FD monitor). Coarse Frequency Drift has an implicit hysteresis with resolution of ±100 ppm since the same range is available for the FD assertion and de-assertion. Use of hysteresis prevents unwanted oscillation of the FD monitor output Aura Semiconductor Confidential Rev 1.0 Page 29 of 53 Au5329 Short Datasheet at the decision threshold and is recommended for robust operation. The value of the FD threshold hysteresis is implicit in the choice of the set and clear thresholds. Important Note regarding the above monitors with respect to clock switch in the PLL: Normally the CL monitor is used for ascertaining a clock is lost for the PLL to switch to a secondary reference or proceed to Holdover. However, the Fine and/or Coarse FD monitors can also be used in addition to the CL monitor to cause a PLL switch. This implements an “OR” logic for the FD Monitors to be used in addition to the CL monitors for triggering a PLL input clock switch or entry to Holdover. This is programmable as an option in the GUI. 6.1.3 Lock Loss Monitors Lock loss is programmable for each PLL with lock loss triggered if the frequency of the input reference to the PLL phase detection arrangement and the feedback clock to same PLL are different as per the programmed assertion and de-assertion thresholds. The Set threshold for asserting the LL monitor is programmable from {±0.2, ±0.4, ±2, ±4, ±20, ±40, ±200, ±400, ±2000, ±4000} ppm while the Clear threshold for de-asserting the LL monitor is programmable from {±0.2, ±0.4, ±2, ±200} ppm. A pre-determined level of hysteresis is implicit by choosing appropriately the set and clear thresholds for the LL monitor. Additionally from the point of view of LL de-assertion, there is a delay from the point in time that lower than the specified ppm value is achieved to the point where the actual LL is de-asserted to the user such that LL never asserts during this delay period. The choice of this delay is with a timer that ensures that the delay is in line with the BW of the PLL loop. It is fully programmable from the GUI and is useful to ensure complete settling of the PLL without un-necessary toggling before LL de-assertion. 6.1.4 XO Clock Loss Monitors The XO Clock Loss Monitor asserts the XO Clock Loss Alarm when the external reference input to the X1 pin (XO or TCXO or OCXO) or the internal XO clock generated with the crystal blank is not available. Aura Semiconductor Confidential Rev 1.0 Page 30 of 53 Au5329 Short Datasheet Output Slave Description The Output Slave accessible on Page 3 is used to configure the output divider (DIVO) and output standard for each output individually. The output load and terminations for each differential output standard are shown in the Output Terminations section of the data sheet. The LVDS and LVDS Boosted modes are recommended for AC coupled termination loads with the termination at the far end. Additionally, an internal termination mode for differential outputs is available where the resistive terminations are internally provided and a differential output is available that can be AC coupled to a clock receiver. The differential clock output pins are shared for LVCMOS outputs as well. LVCMOS outputs can be either enabled on both outputs individually or on any one of the two differential outputs {OUTjP, OUTjN}. The LVCMOS outputs can be used in-phase or out-of-phase on {OUTjP, OUTjN} in case both outputs are chosen. Out of phase LVCMOS toggling on the complementary outputs is recommended for best spur performance. Aura Semiconductor Confidential Rev 1.0 Page 31 of 53 Au5329 Short Datasheet PLL Slave Description All settings with respect to each PLLx slave (x ϵ {B, D}) are accessible on the respective Page {B, D}. The PLL architecture is shown in Figure 14. There are three distinct modes of operation of the PLL: free run mode, synchronized mode and holdover mode. The frequency of the high frequency VCO in the PLL is determined by the specific mode of operation. The VCO frequency is then divided down to get the output frequency on the ODR as described with relation to the overall hierarchy of clocks described earlier. The PLL in the free run mode can be described as a crystal based oscillator where the output frequency is determined by the relation fVCOx = DIVNx*fref. This is the mode of operation before the loop is locked to the selected input clock or the mode of operation for the case none of the input clocks is available. After locking to the chosen input clock, the PLL enters the synchronized mode of operation where the output is now locked to the input frequency with the relation fVCOx = DIVN2x*finx. The PLL Loop that synchronizes (locks) the output to the input clock has a programmable loop bandwidth between 1 mHz to 4 KHz and is not affected by static or dynamic drifts in the crystal oscillator based fref frequency. In case the input clock is lost, the PLL locks to the highest priority spare clock available. If all specified input clocks are lost, the PLL remembers the correction based on historical average of the input clock as specified to enter the Holdover mode of operation. In synchronized mode, the PLL is also able to lock to a Gapped Input clock with some edges missing producing a smooth output clock without any gaps with the requested frequency translation from input to output. Frequency translation ratios in this case should be specified with respect to the average input frequency of the gapped clock rather than the faster instantaneous frequency. Figure 14 PLL Architecture Aura Semiconductor Confidential Rev 1.0 Page 32 of 53 Au5329 Short Datasheet PLL Input Selection: Manual and Hitless Switching All PLL Slaves share the same clock priority in terms of the two input clocks. This is programmed in to the Clock Monitor slave memory. The PLL Slave then looks at Clock Loss status from the Clock Monitor slave to lock to the highest priority available clock to lock. One spare clocks with an order of priority can be specified in case the highest priority active clock is not available. Additionally, a forced manual selection of the active clock with no spares is possible. Phase Build Out Mode of hitless switching ensures that phase transients are not propagated to the output (the phase difference between redundant input clocks is absorbed by the PLL) and desired MTIE characteristics are seen in the output clock. This is the default mode of hitless switching for the PLL. The transition of input clock for a PLL from one clock to another is hitless in nature (with maximum phase hit limited to be less than 50 ps) for the case of the switched input clocks being same in frequency. Hitless switch is also supported for the switched clocks being fractionally related such that the same frequency can be obtained for both clocks at the input of the PLL using the input clock dividers (DIVN1k). For redundant input clocks to the PLL that are not exactly the same frequency (plesichronous clocks), the frequency ramp feature can be enabled that ramps the output frequency of the PLL at a slope that is programmable to one of the following 4 settings: {0.2, 2, 20, 40000} ppm/s. For redundant input clocks to the PLL that are exactly the same frequency, the frequency ramp feature should not be enabled. An alternate mode of hitless switching is the Phase Propagation mode where the phase difference between redundant input clocks is not absorbed by the PLL but is rather propagated to the output. The phase difference that is propagated to the output can either be allowed to propagate as per the PLL bandwidth or can be limited to a phase propagation slope that is programmable to one of the following 3 settings: {10, 40, 160} us/s. Aura Semiconductor Confidential Rev 1.0 Page 33 of 53 Au5329 Short Datasheet PLL Bandwidth Control Each PLL Slave independently chooses the Bandwidth for jitter attenuation from 1 mHz to 4 KHz. This is the bandwidth that is normally used for steady state operation. However, an independent choice for a fast bandwidth is also available that can be used for speeding up the initial lock. After the PLL lock is achieved and the system is in the synchronized mode, the bandwidth is automatically transitioned to the steady state jitter attenuation bandwidth. This feature avoids the abnormally large wake up times that may be needed for very low PLL bandwidths. For stability considerations of the PLL, the fast lock bandwidth or regular bandwidth for the PLL should be no larger than 1/100th of the input frequency at the input of the PLL (post the DIVN1k dividers). Aura Semiconductor Confidential Rev 1.0 Page 34 of 53 Au5329 Short Datasheet PLL Crystal Clock Reference An external crystal can be connected between the {X1, X2} pins on the die to work with the internal crystal oscillator circuitry to produce the fref clock for the system. Alternatively, a TCXO based external clock source can be directly connected on the X1 pin. The requirements for the crystal and the external clock source are presented in Section 2. It is recommended to place the crystal on a floating metal island on the PCB that is provided the ground connection by the chip with the X1G and X2G pins. This metal island should not be connected to the PCB ground to prevent extraneous fref related currents to distribute on the board. Aura Semiconductor Confidential Rev 1.0 Page 35 of 53 Au5329 Short Datasheet PLL Lock Loss Defect Monitoring PLL Lock Loss is another fault monitor whose specifications are available in the Electrical Specifications section of this data sheet. Various programmable thresholds are available that can be used to detect lock loss in the PLL. Lock loss is indicated by the programmable drift between the frequency of the input clock for the PLL and the divided VCO clock. Similar to the faults monitored by the Clock Monitor Slave, this defect can be tracked with status, notify and on the FLEXIOs. This defect monitoring is described in detail in the section on “Clock Monitor Slave Description”. Aura Semiconductor Confidential Rev 1.0 Page 36 of 53 Au5329 Short Datasheet PLL DCO Mode operation The Digitally Controlled Oscillator (DCO) mode of operation is used for changing the output frequency of a PLL using software control on the serial interface or pin control. A pre-defined change in frequency is programmed in the PIF of the respective PLL. After that an increase (FINC) or decrease (FDEC) command can be given on the PIF of the same PLL to make the change in output frequency effective. Alternatively, appropriate GPIOs are chosen for the trigger of the DCO function. A low to high transition (as an edge detect) is used for the trigger of the DCO increment or decrement. Any relative change in frequency from as fine as 5 ppt to as coarse as 100 ppm is available with the DCO mode. DCO mode is available in both free run and synchronized modes of operation. Aura Semiconductor Confidential Rev 1.0 Page 37 of 53 Au5329 Short Datasheet Package Information Figure 15 Au5329 – 64 QFN Package Description Notes: 1. 2. Coplanarity applies to LEADS, CORNER LEADS and DIE ATTACH PAD Total Thickness does not include SAW BURR Aura Semiconductor Confidential Rev 1.0 Page 38 of 53 Au5329 Short Datasheet Output Termination Information Traditional DC Coupled LVPECL Receiver: Use LVPECL Standard for the Au53xx Output Driver Spec Output Differential Peak Conditions Measured at 156.25M Output Min Typical 450 mV 750 mV Max Figure 16 LVPECL DC Termination to VDDO – 2V Alternate DC Coupled LVPECL Receiver: Use LVPECL Standard for the Au53xx Output Driver Spec Output Differential Peak Conditions Measured at 156.25M Output Min Typical 450 mV 750 mV Max Figure 17 LVPECL Alternate DC Termination: Thevenin Equivalent Aura Semiconductor Confidential Rev 1.0 Page 39 of 53 Au5329 Short Datasheet Traditional DC Coupled LVDS Receiver: Use LVDS Standard for the Au53xx Output Driver Spec Output Differential Peak Conditions Measured at 156.25M Output Min Typical Max 247 mV 350 mV 474 mV Figure 18 DC Coupled LVDS Termination Traditional DC Coupled CML Receiver: Use CML Standard for the Au53xx Output Driver Spec Output Differential Peak Conditions Measured at 156.25M Output Min Typical Max 250 mV 350 mV 600 mV Figure 19 DC Coupled CML Aura Semiconductor Confidential Rev 1.0 Page 40 of 53 Au5329 Short Datasheet AC Coupled Receiver side termination Option1: Use LVDS Standard for the Au53xx Output Driver LVDS Standard works for VDDO= 1.8 V/2.5 V/3.3 V Spec Output Differential Peak Conditions Measured at 156.25M Output Min Typical Max 247 mV 350 mV 474 mV AC Coupled Receiver side termination Option2: Use LVDS Boost Standard for the Au53xx Output Driver LVDS Boost Standard works for VDDO = 2.5 V/3.3 V Spec Output Differential Peak Conditions Measured at 156.25M Output Min Typical 500 mV 700 mV Max Figure 20 AC Coupled Receiver side resistive Termination options Aura Semiconductor Confidential Rev 1.0 Page 41 of 53 Au5329 Short Datasheet AC Coupled with termination on Chip side: Use LVPECL2 Standard for the Au53xx Output Driver Spec Output Differential Peak Conditions Measured at 156.25M Output Min Typical 335 mV 525 mV Max Figure 21 Alternate AC Coupled LVPECL with DC coupled resistors on Chip side Figure 22 DC Coupled LVCMOS Aura Semiconductor Confidential Rev 1.0 Page 42 of 53 Au5329 Short Datasheet Figure 23 HCSL AC Coupled Termination. Source Terminated 50 Ohm Note: Rs is sometimes used for limiting overshoot - Can be 0 Ohm Figure 24 HCSL DC Coupled Termination. Source Terminated 50 Ohm Note: Rs is sometimes used for limiting overshoot - Can be 0 Ohm Aura Semiconductor Confidential Rev 1.0 Page 43 of 53 Au5329 Short Datasheet Input Termination Information Figure 25 AC Coupled Differential LVDS Input / Other AC Coupled Driver without DC Terminations Note: Uses Differential Buffer Pathway Figure 26 AC Coupled Differential LVPECL or CML Note: Resistor and Voltage termination is as per the standard. Uses Differential Buffer Pathway. Please refer to the termination requirements of the driver. Aura Semiconductor Confidential Rev 1.0 Page 44 of 53 Au5329 Short Datasheet Drive Supply R1 (Ohms) R2 (Ohms) 1.8 V 140 665 2.5 V 325 475 3.3 V 445 365 Figure 27 DC Coupled Single Ended Driver Note: Uses Single Ended Buffer Pathway in DC Coupled Mode. Recommended for non-standard duty cycle applications. Please refer above table for the recommended resistor values for frequencies < 1 MHz. Figure 28 AC Coupled Single Ended Driver with 50 Ohm Termination on receiver (chip) side Note: Uses Single Ended Buffer pathway in AC coupled mode. Aura Semiconductor Confidential Rev 1.0 Page 45 of 53 Au5329 Short Datasheet Figure 29 AC Coupled Single Ended LVCMOS input without 50 Ohm Termination Note: Uses Single Ended Buffer pathway in AC Coupled Mode. The LVCMOS driver in this case needs to ensure source termination to match to the transmission line. Aura Semiconductor Confidential Rev 1.0 Page 46 of 53 Au5329 Short Datasheet Crystal Pathway Connectivity Options The CMOS XO/TCXO output and the termination components should be placed as close as possible to the X1/X2 pins Figure 30 Crystal Connection Aura Semiconductor Confidential Rev 1.0 Page 47 of 53 Au5329 Short Datasheet CMOS XO Driver Supply 1.8 V 2.5 V 3.3 V R1 (Ohms) 0 274 453 R2 (Ohms) DNP 732 549 Figure 31 CMOS XO Connection Aura Semiconductor Confidential Rev 1.0 Page 48 of 53 Au5329 Short Datasheet Figure 32 Differential XO Connection Aura Semiconductor Confidential Rev 1.0 Page 49 of 53 Au5329 Short Datasheet Ordering Information Table 17 Ordering Information for Au5329 Marking No. of Input/ Output Clocks Au5329B00-QMR[1][2] Au5329B 2/10 8KHz – 2.1GHz Au5329B00-QMT[1][2] Au5329B 2/10 8KHz – 2.1GHz Au5329A 2/10 8KHz – 2.1GHz Integer and Fractional 3.3,2.5 64-QFN 9x9 mm -40 to 85°C Au5329A 2/10 8KHz – 2.1GHz Integer and Fractional 3.3,2.5 64-QFN 9x9 mm -40 to 85°C Ordering Part Number (OPN) Output Clock Frequency Range (MHz) Supported Frequency Synthesis modes VDDIN (VDDA), VDD Package Temp Range Au5329 Au5329A00-QMR [1][2] [Not recommended for New Design] Au5329A00-QMT [1][2] [Not recommended for New Design] Au5329Cx-EVB Notes: 1. 2. 3. — — Integer and Fractional Integer and Fractional — 3.3,2.5 3.3,2.5 — 64-QFN 9x9 mm 64-QFN 9x9 mm -40 to 85°C -40 to 85°C Evaluation Board Add an R at the end of the OPN to denote tape and reel ordering option. Add a T at the end of the OPN to denote tray ordering option. Custom and factory preprogrammed devices are available. Ordering part numbers are assigned by Aura Semiconductor, please contact local sales to request the unique part number. Custom part number format is “Au5329BZZ-QM” where “ZZ” is a unique numerical sequence representing the preprogrammed configuration. Au5329B has exactly same performace and specifications as Au5329A except the revision ID which is the idenitifer for Aura Product platform. Au5329B is recommended for new designs with the changed revision ID. Aura Semiconductor Confidential Rev 1.0 Page 50 of 53 Au5329 Short Datasheet Revision History Table 18 Revision History Version Date Description Author 1.0 1st Au5329 Short Data Sheet Created Aurasemi June 2021 Aura Semiconductor Confidential Rev 1.0 Page 51 of 53 Au5329 Short Datasheet Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Aura Semiconductor Confidential Rev 1.0 Page 52 of 53 Au5329 Short Datasheet Contact Information For more information visit www.aurasemi.com For the full Datasheet and other sales related information please contact local Sales/FAE or send an email to sales@aurasemi.com Aura Semiconductor Private Limited The information contained herein is the exclusive and confidential property of Aura Semiconductor Private Limited and except as otherwise indicated, shall not be disclosed or reproduced in whole or in part. Aura Semiconductor Confidential Rev 1.0 Page 53 of 53