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KS81AAB0

KS81AAB0

  • 厂商:

    KONSEMI(康芯威)

  • 封装:

    FBGA153_11.5X13MM

  • 描述:

    FLASH存储器 FBGA153_11.5X13MM 32Gb -25℃~+85℃

  • 数据手册
  • 价格&库存
KS81AAB0 数据手册
Data Sheet KONSEMI eMMC Product eMMC 5.1 Specification compatibility KONSEMI RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. This document and all information discussed herein remain the sole and exclusive property of KONSEMI Co.. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other-wise. ⓒ 2019 KONSEMI Co., Ltd. All rights reserved Reversion History Revision No. History Draft Date Editor 0.1 Initial Feb. 10, 2020 David 0.2 Initial Feb. 15, 2020 David 0.3 User density May. 11, 2020 David 0.4 CSD Value May. 26, 2020 David 0.5 CSD Value update Jul. 14, 2020 David 1.0 Fix Ext CSD Nov.3, 2020 David 1.1 Cache size Dec.4, 2020 David 1.2 Timing setting Dec.22, 2020 David 1.3 CSD Value update Jul.20, 2021 Jordan 1.4 Package Dimension Aug.20, 2021 Daniel 1.5 Extend CSD Value update Schematic guideline added FFU user guideline added Dec.29, 2021 Pan Huimin /Jerry Yu 1.6 Ball map figuration modified Dec. 6, 2022 Jerry Contents 1. Basic Product List................................................................................................................................................................................4 2. Key Features.........................................................................................................................................................................................4 3. Package Configure ..............................................................................................................................................................................5 3.1 153 Ball Pin Configuration .............................................................................................................................................................5 3.1.1 Package Dimension ............................................................................................................................................................6 3.2 Product Architecture ......................................................................................................................................................................7 3.3 Reference Schematic......................................................................................................................................................................8 4. HS400 mode........................................................................................................................................................................................9 5. New eMMC5.1 Features ...................................................................................................................................................................10 5.1 Overview......................................................................................................................................................................................10 5.2 Command Queuing ....................................................................................................................................................................10 5.2.1 CMD Set Description...........................................................................................................................................................10 5.2.2 New Response: QSR (Queue Status Register) .................................................................................................................10 5.2.3 Send Status: CMD13 .........................................................................................................................................................10 5.2.4 Mechanism of CMD Queue operation.................................................................................................................................11 5.2.5 CMD Queue Register description ......................................................................................................................................11 5.3 Enhanced Strobe Mode.................................................................................................................................................................11 5.4 RPMB Throughput improve ..........................................................................................................................................................11 5.5 Secure Write Protection................................................................................................................................................................12 5.6 Field Firmware Update..................................................................................................................................................................13 6. Technical Notes ..................................................................................................................................................................................14 6.1 S/W Algorithm...............................................................................................................................................................................15 6.1.1 Partition Management ......................................................................................................................................................15 6.1.2 Boot operation...................................................................................................................................................................16 6.1.3 User Density......................................................................................................................................................................16 6.1.4 Auto Power Saving mode..................................................................................................................................................16 6.1.5 Performance......................................................................................................................................................................16 7. Register Value....................................................................................................................................................................................17 7.1 OCR Register .............................................................................................................................................................................17 7.2 CID Register ...............................................................................................................................................................................17 7.2.1 Product name table (In CID Register) ................................................................................................................................17 7.3 CSD Register........................................................................................................................................................................18 7.4 Extended CSD Register .......................................................................................................................................................18 8. AC Parameters ....................................................................................................................................................................................22 8.1 Timing Parameter .....................................................................................................................................................................23 8.2 Previous Bus Timing Parameters for DDR52 and HS200 mode are defined by JEDEC standard...........................................23 8.3 Bus Timing Specification in HS400 mode ................................................................................................................................24 8.3.1 HS400 Device Input Timing ...........................................................................................................................................24 8.3.2 HS400 Device Output Timing..........................................................................................................................................25 8.4 Bus signal levels.........................................................................................................................................................................26 8.4.1 Open-drain mode bus signal level....................................................................................................................................26 8.4.2 Push-pull mode bus signal level eMMC .................................................................................................................................26 9. DC Parameters ..................................................................................................................................................................................27 9.1 Active Power Consumption during operation ..................................................................................................................................27 9.2 Standby Power Consumption in auto power saving mode and standby state..................................................................................27 9.3 Sleep Power Consumption in Sleep State........................................................................................................................................27 9.4 Supply Voltage .................................................................................................................................................................................27 9.5 Bus Signal Line Load........................................................................................................................................................................28 -3- Introduction KONSEMI eMMC is an embedded MMC solution designed in a BGA package form. eMMC operation is identical to a MMC device and therefore is a simple read and write to memory using MMC protocol v5.1 which is a industry standard. eMMC consists of NAND flash and a MMC controller. 3V supply voltage is required for the NAND area (VDDF) whereas 1.8V supply voltage (VDD or VCCQ) is supported for the MMC controller. KONSEMI eMMC supports HS400 in order to improve sequential bandwidth, especially sequential read performance. There are several advantages of using eMMC. It is easy to use as the MMC interface allows easy integration with any microprocessor with MMC host. Any revision or amendment of NAND is invisible to the host as the embedded MMC controller insulates NAND technology from the host. This leads to faster product development as well as faster times to market. The embedded flash management software or FTL (Flash Transition Layer) of eMMC manages Wear Leveling, Bad Block Management and ECC. The FTL supports all features of the different kind of NAND flash and achieves optimal performance. 1.Basic Product List [Table 1] Product Information Part No. KS81AAB0 NAND Flash Type Capacity 256Gb*1 32GB Power System Package size(mm) Pin Configuration Interface power: VDD (1.70V ~ 1.95V or 2.7V ~ 3.6V) Memory power: VDDF (2.7V ~ 3.6V) 11.5*13*1 153 FBGA Density 91.7% 2.Key Features Key Features • eMMC5.1 compatible ( Backward compatible to eMMC4.5 & eMMC5.0) • Bus mode - Data bus width: 1bit(default), 4bits, 8bits - Data transfer rate: up to 400MB/s (HS400) - MMC I/F Clock frequency: 0~200MHz 1316 - MMC I/F Boot frequency: 0~52MHz • Operating Voltage Range - Vcc (NAND): 2.7V - 3.6V - Vccq (Controller): 1.7V - 1.95V / 2.7V ~ 3.6V • Temperature - Operation (-25℃ ~ +85℃) - Storage without operation (-40℃ ~ +85℃) • Others - This product is compliance with the RoHS directive Supported Features - HS400, HS200 - HPI, BKOPS, BKOP operation control - Packed CMD, CMD queuing - Cache, Cache barrier, Cache flushing report -Partitioning, RPMB, RPMB throughput improve - Discard, Trim, Erase, Sanitize - Write protect, Secure write protection - Lock/Unlock - PON, Sleep/Awake - Reliable Write - Boot feature, Boot partition - HW/SW Reset - Field Firmware Update - Configurable driver strength - Health(Smart) report - Production state awareness - Secure removal type - Data Strobe pin, Enhanced data strobe (Bold features are added in eMMC5.1) -4- 3.Package Configuration 3.1 153 Ball map [Table 2] 153 Ball Information Pin NO Name A3 DAT0 A4 DAT1 A5 DAT2 B2 DAT3 B3 DAT4 B4 DAT5 DAT6 B5           B6 DAT7 K5 RSTN C6 VDD M4 VDD N4 VDD P3 VDD P5 VDD E6 VDDF F5 VDDF J10 VDDF K9 VDDF C2 VDDi M5 CMD H5 Data Strobe M6 CLK J5 VSS A6 VSS C4 VSS E7 VSS G5 VSS H10 VSS K8 VSS N2 VSS N5 VSS P4 VSS P6 VSS TP5 VCCO-B G1 GPIO 1 G0 GPIO 0 TA2 URx TA3 UTx Figure 1 153-FBGA CLK: Clock input Data Strobe: Newly assigned pin for HS400 mode. Data Strobe is generated from eMMC to host. In HS400 mode, read data and CRC response are synchronized with Data Strobe. CMD: A bidirectional signal used for device initialization and command transfers. Command operates in two modes, open-drain for initialization and push-pull for fast command transfer. DAT0-7: Bidirectional data channels. It operates in push-pull mode. RSTN: H/W reset signal pin VDDF(VCC): Supply voltage for flash memory VDD(VCCQ): Supply voltage for memory controller VDDi: Internal power node to stabilize regulator output to controller core logics VSS: Ground connections RFU: Reserved for future use, do not use for any usage -5- 3.1.1 Package Dimension Figure 2 FPGA_153 Package -6- 3.2 Block Diagram eMMC consists of NAND Flash and Controller. VDD (VCCQ) is for Controller power and VDDF (VCC)is for flash power Figure 3. eMMC Block Diagram 3.3 Reference schematic Figure 4. eMMC reference schematic -7- [Table 3] Schematic design specification -8- 4.HS400 mode eMMC5.1 product supports high speed DDR interface timing mode up to 400MB/s at 200MHz with 1.8V I/O supply. HS400 mode supports the following features: DDR Data sampling method CLK frequency up to 200MHz DDR – up to 400Mbps Only 8-bits bus width available Signaling levels of 1.8V Five optional Drive Strength (refer to the table below) [Table 3] I/O driver strength types Driver Type HS200 & HS400 Support Nominal Impedance Approximated driving capability compared to Type-0 0 Default 50Ω x1 Default Driver Type. Supports up to 200MHz operation. 1 Optional 33Ω x1.5 Supports up to 200MHz Operation. 2 Optional 66Ω x0.75 The weakest driver that supports up to 200MHz operation. 3 Optional 100Ω x0.5 For low noise and low EMI systems. Maximal operating frequency is decided by Host design. 4 Optional 40Ω x1.2 Supports up to 200MHz DDR operation Remark NOTE:1) Support of Driver Type-0 is mandatory for HS200 & HS400 Device. NOTE:2) Nominal impedance is defined by I-V characteristics of output driver at 0.9V when VCCQ=1.8V NOTE:3) Nominal impedance is defined by I-V characteristics of output driver at 0.6V when VCCQ=1.2V [Table 4] Device type values (EXT_CSD register: DEVICE_TYPE [196]) Bit Device Type Support-ability 7 HS400 Dual Data Rate eMMC @ 200 MHz - 1.2V I/O Not support 6 HS400 Dual Data Rate eMMC @ 200 MHz - 1.8V I/O Support 5 HS200 Single Data Rate eMMC @ 200 MHz - 1.2V I/O Not support 4 HS200 Single Data Rate eMMC @ 200 MHz - 1.8V I/O Support 3 High-Speed Dual Data Rate eMMC @ 52MHz - 1.2V I/O Not support 2 High-Speed Dual Data Rate eMMC @ 52MHz - 1.8V or 3V I/O Support 1 High-Speed eMMC @ 52MHz - at rated device voltage(s) Support 0 High-Speed eMMC @ 26MHz - at rated device voltage(s) Support [Table 5] Extended CSD revisions (EXT_CSD register: EXT_CSD_REV [192]) Value Timing Interface EXT_CSD Register Value Reserved - Revision 1.8 (for MMC V5.1) 0x08 7 Revision 1.7 (for MMC V5.0) - 6 Revision 1.6 (for MMC V4.5, V4.51) - 5 Revision 1.5 (for MMC V4.41) - 4 Revision 1.4 (Obsolete) - 3 Revision 1.3 (for MMC V4.3) - 2 Revision 1.2 (for MMC V4.2) - 1 Revision 1.1 (for MMC V4.1) - 0 Revision 1.0 (for MMC V4.0) - 2558 8 [Table 6] High speed timing values (EXT_CSD register: HS_TIMING [185]) Value Timing Interface Support or not 0x0 Selecting backwards compatibility interface timing Supported 0x1 High Speed Supported 0x2 HS200 Supported 0x3 HS400 Supported -9- 5.New eMMC5.1 Features 5.1 Overview New Feature JEDEC Support Cache Flushing Report Mandatory Yes Background operation control Mandatory Yes Command Queuing Optional Yes Enhanced Strobe Optional Yes RPMB Throughput improve Optional Yes Secure Write Protection Optional No 5.2 Command Queuing To facilitate command queuing in eMMC, the device manages an internal task queue that the host can queue during data transfer tasks. Every task is issued by the host and initially queued as pending. The device works to prepare pending tasks for execution. When a task is ready for execution, its state changes to “ready for execution”. The host tracks the state of all queued tasks and may order the execution of any task, marked as “ready for execution”, by sending a command indicating its task ID. The device executes the data transfer transaction after receiving the execute command (CMD46/CMD47) 5.2.1 CMD Set Description [Table 7] CMD Set Description and Details CMD Type Argument Abbreviation Purpose CMD44 ac/R1 [31] Reliable Write Request [30] DAT_DIR - "0" write / "1" read [29] tag request [28:25] context ID [24] forced programming [23] Priority: “0” simple / “1” high [20:16] TASK ID [15:0] number of blocks QUEUED_TASK _PARAMS Define direction of operation (Read or Write) and set high priority CMD Queue with task ID CMD45 ac/R1 [31:0] Start block address QUEUED_TASK_ADDRES S Indicate data address for Queued CMD CMD46 adtc/R1 [20:16] TASK ID EXECUTE_READ_TASK (Read) Transmit the requested number of data blocks CMD47 adtc/R1 [20:16] TASK ID EXECUTE_WRITE_TASK (Write) Transmit the requested number of data blocks CMD48 ac/R1b [20:16] Task ID [3:0] TM op-code CMDQ_TASK _MGMT Reset a specific task or entire queue. [20:16] when TM op-code = 2h these bits represent Task ID When TM op-code = 1h these bits are reserved" 5.2.2 New Response: QSR (Queue Status Register) The 32-bit Queue Status Register (QSR) carries the state of tasks in the queue at a specific point in time. The host has read access to this register through device response to SEND_STATUS command (CMD13 with bit [15] =”1”), R1’s argument will be the 32- bit Queue Status Register (QSR). Every bit in the QSR represents the task whose ID corresponds to the bit index. If bit QSR[i] = “0”, then the queued task with a Task ID i is not ready for execution. The task may be queued and pending, or the Task ID is unused. If bit QSR[i] = “1”, then the queued task with Task ID i is ready for execution. 5.2.3 Send Status: CMD13 CMD13 for reading the Queue Status Register (QSR) by the host. If bit [15] in CMD13’s argument is set to 1, then the device shall send an R1 Response with the QSR instead of the Device Status. * There is still legacy CMD13 with R` response - 10 - 5.2.4 Mechanism of CMD Queue operation Host issues CMD44 with Task ID number, Sector, Count, Direction, Priority to the device followed by CMD45 and host checks the Queue Status check with CMD13 [15] bits to 1. After that host issues CMD46 for Read or CMD47 for write During CMD queue operation, CMD44/CMD45 is able to be issued at any time when the CMD line is not in use 5.2.5 CMD Queue Register description Configuration and capability structures shall be added to the EXT_CSD register, as described below [Table 8] CMD Queuing Support (EXT_CSD register: CMDQ_SUPPORT [308]) Bit7 Bit6 Bit5 Bit4 Reserved Bit3 Bit2 Bit1 Bit0 CMD Queue supported This field indicates whether the device supports command queuing or not 0x0: CMD Queue function is not supported 0x1: CMD Queue function is supported [Table 9] Command Queue Mode Enable (EXT_CSD register: CMDQ_MODE_EN [15]) Bit7 Bit6 Bit5 Bit4 Reserved Bit3 Bit2 Bit1 Bit0 - This field is used by the host enable command queuing 0x0: Queue function is not enabled 0x1: Queue function is enabled [Table 10] CMD Queuing Depth (EXT_CSD register: CMDQ_DEPTH [307]) Bit7 Bit6 Bit5 Bit4 Reserved This field is used to calculate the depth of the queue supported by the device Bit3 Bit2 Bit1 N Bit0 Bit encoding: [7:5]: Reserved [4:0]: N, a parameter used to calculate the Queue Depth of task queue in the device. Queue Depth = N+1. 5.3 Enhanced Strobe Mode This product supports Enhanced Strobe in HS400 mode and refer to the details as described in eMMC5.1 JEDEC standard 5.4 RPMB Throughput improve [Table 11] Related parameter register in EXT_CSD: WR_REL_PARAM [166] Name Field Enhanced RPMB Reliable Write EN_RPMB_REL_WR Bit [4]: EN_RPMB_REL_WR(R) 0x0: RPMB transfer size is either 256B (single 512B frame) or 512B (Two 512B frame). 0 x1: RPMB transfer size is either 256B (single 512B frame), 512B (Two 512B frame), or 8KB (Thirty-two 512B frames). - 11 - Bit 4 Type R 5.5 Secure Write Protection Configuration and capability structures shall be added to the EXT_CSD register and Authenticated Device Configuration Area as described below [Table 12] Parameter register in EXT_CSD: SECURE_WP_INFO [211] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Reserved Bit1 Bit0 SECURE_WP_EN_STATUS SECURE_WP_SUPPORT Bit [7:2]: Reserved Bit [1]: SECURE_WP_EN_STATUS(R) 0x0: Legacy Write Protection mode. 0x1: Secure Write Protection mode. Bit [0]: SECURE_WP_SUPPORT(R) 0x0: Secure Write Protection is NOT supported by this device 0x1: Secure Write Protection is supported by this device [Table 13] Authenticated Device Configuration Area [1]: SECURE_WP_MODE_ENABLE Bit7 Bit6 Bit5 Bit4 Reserved Bit3 Bit2 Bit1 Bit0 0x00 Bit1 Bit0 0x00 Bit [7:1]: Reserved Bit [0]: SECURE_WP_EN (R/W/E) The default value of this field is 0x0. x 0x0: Legacy Write Protection mode, i.e., TMP_WRITE_PROTECT [12], PERM_WRITE_PROTECT [13] is updated by CMD27. USER_WP [171], BOOT_WP [173] and BOOT_WP_STATUS [174] are updated by CMD6. x 0x1: Secure Write Protection mode. The access to the write protection related EXT_CSD and CSD fields depends on the value of SECURE_WP_MASK bit in SECURE_WP_MODE_CONFIG field. [Table 14] Authenticated Device Configuration Area [2]: SECURE_WP_MODE_CONFIG Bit7 Bit6 Bit5 Bit4 Reserved Bit3 Bit2 Bit [7:1]: Reserved Bit [0] : SECURE_WP_MASK (R/W/E_P) The default value of this field is 0x0. x 0x0: Disabling updating WP related EXT_CSD and CSD fields. CMD27 (Program CSD) will generate generic error for setting TMP_WRITE_PROTECT [12], PERM_WRITE_PROTECT [13]. CMD6 for updating USER_WP [171], BOOT_WP [173] and BOOT_WP_STATUS [174] generates SWITCH_ERROR. If a force erase command is issued, the command will fail (Device stays locked) and the LOCK_UNLOCK_FAILED error bit will be set in the status register. If CMD28 or CMD29 is issued, then generic error will be occurred. Power-on Write Protected boot partitions will keep protected mode after power failure, H/W reset assertion and any CMD0 reset. The device keeps the current value of BOOT_WP_STATUS in the EXT_CSD register to be same after power cycle, H/W reset assertion, and any CMD0 reset. x 0x1: Enabling updating WP related EXT_CSD and CSD fields. I.e., TMP_WRITE_PROTECT [12], PERM_WRITE_PROTECT [13], USER_WP [171], BOOT_WP [173] and BOOT_WP_STATUS [174] are accessed using CMD6, CMD8 and CMD27. If a force erase command is issued and accepted, then ALL THE DEVICE CONTENT WILL BE ERASED including the PWD and PWD_LEN register content and the locked Device will get unlocked. If a force erase command is issued and power-on protected or a permanently-writeprotected write protect groups exist on the device, the command will fail (Device stays locked) and the LOCK_UNLOCK_FAILED error bit will be set in the status register. An attempt to force erase on an unlocked Device will fail and LOCK_UNLOCK_FAILED error bit will be set in the status register. Write Protection is applied to the WPG indicated by CMD28 with the WP type indicated by the bit [2] and bit [0] of USER_WP [171]. All temporary WP Groups and power-on Write Protected boot partitions become writable/erasable temporarily which means write protect type is not changed. All power-on and permanent WP Groups in user area will not become writable/erasable temporarily. Those temporarily writable/erasable area will become write protected when this bit is cleared to 0x0 by the host or when there is power failure, H/W reset assertion and any CMD0 reset. The device keeps the current value of BOOT_WP_STATUS in the EXT_CSD register to be same after power cycle, H/W reset assertion, and any CMD0 reset. - 12- 5.6 Field Firmware Upgrade Field firmware upgrade (FFU) provide an effective way to do features modified in the field. By this way, host downloads new firmware to the eMMC device and enable the device to install the new downloaded firmware, the whole FFU process will not affect the user or OS data. During the FFU process, the host can replace firmware or single/all systems. Please refer to following FFU operation guideline: Step CMD Index CMD Argument Data Other Action & Note 1 Power Off *1 2 Delay 500ms *2 3 Power On *3 4 Delay 500ms 5 Set Host Clock 375KHz *4 6 Set Host Bus Width to 1-bit *5 7 Delay 100ms 8 CMD0 0x00000000 eMMC Vendor CMD Expect no response 9 CMD1 0x40FF8080 Check Response until ready (C0 FF 80 80) 10 CMD2 0x00000000 11 CMD3 0x00020000 12 CMD7 0x00020000 13 CMD13 0x00020000 Check Response until ready (00 00 09 00) 14 CMD6 0x031E0100 Enter FFU Mode 15 CMD13 0x00020000 Check Response until ready (00 00 09 00) 16 CMD25 0x1FCA0000 17 CMD12 0x00020000 18 CMD13 0x00020000 Check Response until ready (00 00 09 00) 19 CMD6 0x031D0100 Enter FFU Install ffu.bin Write “ffu.bin” into devices 20 Power Off 21 Delay 500ms 22 Power On 23 Delay 500ms Note: *1. Cutting off VCC, VCCQ supply *2. Delay 500mS *3. Resume VCC, VCCQ supply *4. Switch the CLK to 375KHz on the Host *5. Switch the Bus Width to 1-bit on the Host -13- 6. Technical Notes 6.1 S/W Algorithm 6.1.1 Partition Management The device initially consists of two Boot Partitions and RPMB Partition and User Data Area. The User Data Area can be divided into four General Purpose Area Partitions and User Data Area partition. Each of the General-purpose Area partitions and a section of User Data Area partition can be configured as enhanced partition. 6.1.1.1 Enhanced Partition (Area) KONSEMI eMMC adopts Enhanced User Data Area as SLC Mode. Therefore, when master adopts some portion as enhanced user data area in User Data Area, that area occupies double size of original set up size. ( if master set 1MB for enhanced mode, total 3MB user data area is needed to generate 1MB enhanced area) Max Enhanced User Data Area size is defined as (MAX_ENH_SIZE_MULT x HC_WP_GRP_SIZE x HC_ERASE_GRP_SIZE x 512kBytes) - 14 - 6.1.2 Boot operation Device supports not only boot mode but also alternative boot mode. Device supports high speed timing and dual data rate during boot. Figure 4. embedded Multi-Media Card state diagram (boot mode) Figure 5. embedded Multi-Media Card state diagram (alternative boot mode) [Table 15] Boot ack, boot data and initialization Time Timing Factor Value (1) Boot ACK Time < 50 mS (2) Boot Data Time < 150 mS (3) Initialization Time1) < 3 Sec NOTE: 1) This initialization time includes partition setting, please refer to INI_TIMEOUT_AP in 6.4 Extended CSD Register. Normal initialization time (without partition setting) is completed within 1sec - 15 - 6.1.3 User Density Total User Density depends on device type. For example, 32MB in the SLC Mode requires 64MB in MLC. This results in decreasing of user density [Table 16] Capacity according to partition Boot partition 1 Boot partition 2 RPMB Default. 4,096KB 4,096KB 4,096KB Max. 4,096KB 4,096KB 4,096KB [Table 17] Maximum Enhanced Partition Size Device 32GB 10,485,760,000 Bytes [Table 18] User Density Size Device User Density Size 32GB 31,474,057,216 Bytes 6.1.4 Auto Power Saving Mode If host does not issue any command during a certain duration (10ms), after previously issued command is completed, the device enters "Power Saving mode" to reduce power consumption. Mode Enter Condition Escape Condition When previous operation which came from Host is completed and no Auto Power Saving Mode command is issued during a certain time. At this time, commands arrive at the device while it is in power saving mode will be serviced in normal fashion If Host issues any command [Table 19] Auto Power Saving Mode enter and exit [Table 20] Auto Power Saving Mode and Sleep Mode Auto Power Saving Mode Sleeping Mode NAND Power ON OFF Go to Sleep Time > 100 mS < 55 mS 6.1.5 Performance [Table 21] Performance Density Sequential Read (MB/s) 32GB Up to 200 MB/S * Test Condition: Bus width x8, HS400, 512KB data transfer, test on card reader (Secondary drive) clean state. - 16 - Sequential Write (MB/s) Up to 110 MB/S 7. Register Value 7.1 OCR Register The 32-bit operation conditions register stores the VDD voltage profile of the eMMC. In addition, this register includes a status information bit. This status bit is set if the eMMC power up procedure has been finished. The OCR register shall be implemented by all eMMCs. [Table 22] OCR Register OCR bit [6:0] [7] [14:8] [23:15] [28:24] VDD voltage window2 Reserved 1.70 - 1.95 2.0-2.6 2.7-3.6 Reserved Register Value 00 00000b 0001b 000 0000b 1 1111 1111b 0 0000b [30:29] [31] Access Mode 00b (byte mode) 10b (sector mode) - [ *Higher than 2GB only] eMMC power up status bit (busy)1 NOTE: 1) This bit is set to LOW if the eMMC has not finished the power up routine 2) The voltage for internal flash memory (VDDF) should be 2.7-3.6v regardless of OCR Register value. 7.2 CID Register [Table 23] CID Register Name Manufacturer ID Reserved Card/BGA Field MID CBX Width 8 6 2 CID-slice [127:120] [119:114] [113:112] CID Value 0x2F --0x01 OEM/Application ID Product name OID PNM 8 48 [111:104] [103:56] 0x11 See Product name table Product revision PRV 8 [55:48] ---2 Product serial number PSN 32 [47:16] ---3 Manufacturing date MDT 8 [15:8] ---4 CRC7 checksum not used, always ’1’ CRC - 7 1 [7:1] [0:0] ---5 0x01 NOTE: 1),4),5) description are same as eMMC JEDEC standard 2) PRV is composed of the revision count of controller and the revision count of F/W patch 3) A 32 bits unsigned binary integer. (Random Number) 7.2.1 Product name table (In CID Register) [Table 24] Product name table Part Number Density KS81AAB0 32GB Product Name in CID Register (PNM) 0x303753303030 - 17 - 7.3 CSD Register The Card-Specific Data register provides information on how to access the eMMC contents. The CSD defines the data format, error correction type, maximum data access time, data transfer speed, whether the DSR register can be used etc. The programmable part of the register (entries marked by W or E, see below) can be changed by CMD27. The type of the entries in the table below is coded as follows: R: Read only W: One time programmable and not readable. R/W: One time programmable and readable. W/E: Multiple writable with value kept after power failure, H/W reset assertion and any CMD0 reset and not readable. R/W/E: Multiple writable with value kept after power failure, H/W reset assertion and any CMD0 reset and readable. R/W/C_P: Writable after value cleared by power failure and HW/ rest assertion (the value not cleared by CMD0 reset) and readable. R/W/E_P: Multiple writable with value reset after power failure, H/W reset assertion and any CMD0 reset and readable. W/E/_P: Multiple writable with value reset after power failure, H/W reset assertion and any CMD0 reset and not readable. [Table 25] CSD Register Name Field Width Cell Type CSD slice CSD Value CSD structure CSD_STRUCTURE 2 R [127:126] 0x03 System specification version SPEC_VERS 4 R [125:122] 0x04 Reserved - 2 R [121:120] - Data read access-time 1 TAAC 8 R [119:112] 0x4F Data read access-time 2 in CLK cycles (NSAC*100) NSAC 8 R [111:104] 0x00 Max. bus clock frequency TRAN_SPEED 8 R [103:96] 0x32 Device command classes CCC 12 R [95:84] 0x9F5 Max. read data block length READ_BL_LEN 4 R [83:80] 0x09 Partial blocks for read allowed READ_BL_PARTIAL 1 R [79:79] 0x00 Write block misalignment WRITE_BLK_MISALIGN 1 R [78:78] 0x00 Read block misalignment READ_BLK_MISALIGN 1 R [77:77] 0x00 DSR implemented DSR_IMP 1 R [76:76] 0x00 Reserved - 2 R [75:74] - Device size C_SIZE 12 R [73:62] 0xFFF Max. read current @ VDD min VDD_R_CURR_MIN 3 R [61:59] 0x07 Max. read current @ VDD max VDD_R_CURR_MAX 3 R [58:56] 0x07 Max. write current @ VDD min VDD_W_CURR_MIN 3 R [55:53] 0x07 Max. write current @ VDD max VDD_W_CURR_MAX 3 R [52:50] 0x07 Device size multiplier C_SIZE_MULT 3 R [49:47] 0x7 Erase group size ERASE_GRP_SIZE 5 R [46:42] 0x1F Erase group size multiplier ERASE_GRP_MULT 5 R [41:37] 0x1F Write protect group size WP_GRP_SIZE 5 R [36:32] 0xF Write protect group enable WP_GRP_ENABLE 1 R [31:31] 0x01 Manufacturer default ECC DEFAULT_ECC 2 R [30:29] 0x00 Write speed factor R2W_FACTOR 3 R [28:26] 0x04 Max. write data block length WRITE_BL_LEN 4 R [25:22] 0x09 Partial blocks for write allowed WRITE_BL_PARTIAL 1 R [21:21] 0x00 Reserved - 4 R [20:17] - Content protection application CONTENT_PROT_APP 1 R [16:16] 0x00 File format group FILE_FORMAT_GRP 1 R/W [15:15] 0x00 Copy flag (OTP) COPY 1 R/W [14:14] 0x00 Permanent write protection PERM_WRITE_PROTECT 1 R/W [13:13] 0x00 Temporary write protection TMP_WRITE_PROTECT 1 R/W/E [12:12] 0x00 File format FILE_FORMAT 2 R/W [11:10] 0x00 ECC code ECC 2 R/W/E [9:8] 0x00 CRC CRC 7 R/W/E [7:1] - Not used, always’1’ - 1 — [0:0] - - 18 - 7.4 Extended CSD Register The Extended CSD register defines the eMMC properties and selected modes. It is 512 bytes long. The most significant 320 bytes are the Properties segment, which defines the eMMC capabilities and cannot be modified by the host. The lower 192 bytes are the Modes segment, which defines the configuration the eMMC is working in. These modes can be changed by the host by means of the SWITCH command. R: Read only W: One time programmable and not readable. R/W: One time programmable and readable. W/E: Multiple writable with value kept after power failure, H/W reset assertion and any CMD0 reset and not readable. R/W/E: Multiple writable with value kept after power failure, H/W reset assertion and any CMD0 reset and readable. R/W/C_P: Writable after value cleared by power failure and HW/ rest assertion (the value not cleared by CMD0 reset) and readable. R/W/E_P: Multiple writable with value reset after power failure, H/W reset assertion and any CMD0 reset and readable. W/E/_P: Multiple writable with value reset after power failure, H/W reset assertion and any CMD0 reset and not readable [Table 26] Extended CSD Register Name Size Field Reserved1 Bytes Cell Type CSD slice CSD Value 6 - [511:506] - Extended Security Commands Error EXT_SECURITY_ERR 1 R [505] 0x00 Supported Command Sets S_CMD_SET 1 R [504] 0x01 HPI features HPI_FEATURES 1 R [503] 0x01 Background operations support BKOPS_SUPPORT 1 R [502] 0x01 Max packed read commands MAX_PACKED_READS 1 R [501] 0x20 Max packed write commands MAX_PACKED_WRITES 1 R [500] 0x20 Data Tag Support DATA_TAG_SUPPORT 1 R [499] 0x01 Tag Unit Size TAG_UNIT_SIZE 1 R [498] 0x3 Tag Resources Size TAG_RES_SIZE 1 R [497] 0x00 Context management capabilities CONTEXT_CAPABILITIES 1 R [496] 0x5 Large Unit size LARGE_UNIT_SIZE_M1 1 R [495] 0x7 Extended partitions attribute support EXT_SUPPORT 1 R [494] 0x03 Supported modes SUPPORTED_MODES 1 R [493] 0x01 FFU features FFU_FEATURES 1 R [492] 0x01 Operation codes timeout OPERATION_CODE_TIMEOUT 1 R [491] 0x11 FFU Argument FFU_ARG 4 R [490:487] 0x1FCA0000h Barrier support BARRIER_SUPPORT 1 R [486] 0x1 Reserved1 177 - [485:309] - CMD Queuing Support CMDQ_SUPPORT 1 R [308] 0x01 CMD Queuing Depth CMDQ_DEPTH 1 R [307] 0x1F 37 - [306] - Reserved1 Number of FW sectors correctly programmed NUMBER_OF_FW_SECTORS_CORRECTLY_PROGR AMMED 4 R [305:302] 0x00 Vendor proprietary health report VENDOR_PROPRIETARY_HEALTH_REPORT 32 R [301:270] 0x00 Device life time estimation type B DEVICE_LIFE_TIME_EST_TYP_B 1 R [269] 0x01 Device life time estimation type A DEVICE_LIFE_TIME_EST_TYP_A 1 R [268] 0x01 Pre EOL information PRE_EOL_INFO 1 R [267] 0x01 Optimal read size OPTIMAL_READ_SIZE 1 R [266] 0x00 Optimal write size OPTIMAL_WRITE_SIZE 1 R [265] 0x8 Optimal trim unit size OPTIMAL_TRIM_UNIT_SIZE 1 R [264] 0x1 Device version DEVICE_VERSION 2 R [263:262] 0x01 Firmware version FIRMWARE_VERSION 3 R [261:254] FW Patch Ver. Power class for 200MHz, DDR at VCC=3.6V PWR_CL_DDR_200_360 1 R [253] 0x00 Cache size CACHE_SIZE 4 R [252:249] 0x00001B10 Generic CMD6 timeout GENERIC_CMD6_TIME 1 R [248] 0x1E - 19 - Power off notification(long) timeout POWER_OFF_LONG_TIME 1 R [247] 0x64 Background operations status Number of correctly programmed sectors 1st initialization time after partitioning Cache Flushing Policy Power class for 52MHz, DDR at 3.6V Power class for 52MHz, DDR at 1.95V Power class for 200MHz at Vccq=1.95V, Vcc=3.6V Power class for 200MHz, at Vccq=1.3V, Vcc=3.6V Minimum Write Performance for 8bit at 52MHz in DDR mode Minimum Read Performance for 8bit at 52MHz in DDR mode BKOPS_STATUS 1 R [246] 0x00 CORRECTLY_PRG_SECTORS-NUM 4 R [245:242] 0x00 INI_TIMEOUT_AP 1 R [241] 0x1E CACHE_FLUSH_POLICY 1 R [240] 0x1 PWR_CL_DDR_52_360 1 R [239] 0x00 PWR_CL_DDR_52_195 1 R [238] 0x00 PWR_CL_200_360 1 R [237] 0x00 PWR_CL_200_195 1 R [236] 0x00 MIN_PERF_DDR_W_8_52 1 R [235] 0x00 MIN_PERF_DDR_R_8_52 1 R [234] 0x00 1 - [233] - Reserved1 TRIM Multiplier TRIM_MULT 1 R [232] 0x5 Secure Feature Support SEC_FEATURE_SUPPORT 1 R [231] 0x55 Secure Erase Multiplier SEC_ERASE_MULT 1 R [230] 0xA6 Secure TRIM Multiplier SEC_TRIM_MULT 1 R [229] 0xA6 Boot information BOOT_INFO 1 R [228] 0x07 1 - [227] - Reserved1 Boot partition size BOOT_SIZE_MULT 1 R [226] 0x20 Access size ACC_SIZE 1 R [225] 0x8 High-capacity erase unit size HC_ERASE_GRP_SIZE 1 R [224] 0x01 High-capacity erase timeout ERASE_TIMEOUT_MULT 1 R [223] 0x7 Reliable write sector count High-capacity write protect group size Sleep current (VCC) REL_WR_SEC_C 1 R [222] 0x01 HC_WP_GRP_SIZE 1 R [221] 0x10 S_C_VCC 1 R [220] 0x08 Sleep current (VCCQ) S_C_VCCQ 1 R [219] 0x8 Production state awareness timeout PRODUCTION_STATE_AWARENESS_TIMEOUT 1 R [218] 0x14 Sleep/awake timeout S_A_TIMEOUT 1 R [217] 0x16 Sleep Notification Timeout SLEEP_NOTIFICATION_TIME 1 R [216] 0x10 Sector Count SEC_COUNT 4 R [215:212] 0x03AA0000 Secure Write Protect Information Minimum Write Performance for 8bit at 52MHz Minimum Read Performance for 8bit at 52MHz Minimum Write Performance for 8bit at 26MHz, for 4bit at 52MHz Minimum Read Performance for 8bit at 26MHz, for 4bit at 52MHz Minimum Write Performance SECURE_WP_INFO 1 R [211] 0x00 MIN_PERF_W_8_52 1 R [210] 0x00 MIN_PERF_R_8_52 1 R [209] 0x00 MIN_PERF_W_8_26_4_52 1 R [208] 0x00 MIN_PERF_R_8_26_4_52 1 R [207] 0x00 MIN_PERF_W_4_26 1 R [206] 0x00 MIN_PERF_R_4_26 1 R [205] 0x00 1 - [204] - Minimum Read Performance for 4bit at 26MHz Reserved1 Power class for 26MHz at 3.6V 1 R PWR_CL_26_360 1 R [203] 0x00 Power class for 52MHz at 3.6V 1 R PWR_CL_52_360 1 R [202] 0x00 Power class for 26MHz at 1.95V 1 R PWR_CL_26_195 1 R [201] 0x00 - 20 - Power class for 52MHz at 1.95V 1R Partition switching timing Out-of-interrupt busy timing I/O Driver Strength Device type Reserved1 CSD structure Reserved1 Extended CSD revision Command set Reserved1 Command set revision Reserved1 Power class Reserved1 High-speed interface timing Strobe Support Bus width mode Reserved1 Erased memory content Reserved1 PWR_CL_52_195 1 R [200] 0x00 PARTITION_SWITCH_TIME OUT_OF_INTERRUPT_TIME DRIVER_STRENGTH DEVICE_TYPE 1 1 1 1 1 1 1 1 R R R R R R [199] [198] [197] [196] [195] [194] [193] [192] 0x1E 0x1E 0x1F 0x57 0x02 0x08 1 1 1 1 1 1 1 1 1 1 1 1 [191] [190] [189] [188] [187] [186] [185] [184] [183] [182] [181] [180] 0x00 0x00 0x00 0x00 0x01 0x00 0x00 - [179] 0x00 [178] 0x00 [177] [176] 0x00 - CSD_STRUCTURE EXT_CSD_REV Modes Segment CMD_SET Partition configuration PARTITION_CONFIG 1 Boot config protection BOOT_CONFIG_PROT 1 Boot bus Conditions Reserved1 BOOT_BUS_CONDITIONS 1 1 R/W/E_P R R/W/E_P R/W/E_P R W/E_P R R/W/E & R/W/E_P R/W & R/W/C_P R/W/E - High-density erase group definition ERASE_GROUP_DEF 1 R/W/E_P [175] 0x00 Boot write protection status registers BOOT_WP_STATUS 1 R [174] 0x00 Boot area write protection register BOOT_WP 1 [173] 0x00 [172] - [171] 0x00 [170] [169] [168] 0x00 0x20 CMD_SET_REV POWER_CLASS HS_TIMING STROBE_SUPPORT BUS_WIDTH ERASED_MEM_CONT USER_WP 1 Reserved1 FW configuration RPMB Size FW_CONFIG RPMB_SIZE_MULT 1 1 1 R/W & R/W/C_P R/W R/W/C_P R/W/E_P R/W R Write reliability setting register WR_REL_SET 1 R/W [167] 0x1F Write reliability parameter register WR_REL_PARAM 1 R [166] 0x15 Start Sanitize operation SANITIZE_START 1 W/E_P [165] 0x00 Manually start background operations BKOPS_START 1 W/E_P [164] 0x00 BKOPS_EN 1 [163] 0x00 RST_n_FUNCTION HPI_MGMT PARTITIONING_SUPPORT MAX_ENH_SIZE_MULT PARTITIONS_ATTRIBUTE 1 1 1 3 1 [162] [161] [160] [159:157] [156] 0x00 0x00 0x07 0x0004E2 0x00 Reserved1 User area write protection register Enable background operations handshake H/W reset function HPI management Partitioning Support Max Enhanced Area Size Partitions attribute 1 - 21 - R/W&R/W/ E R/W R/W/E_P R R R/W Partitioning Setting General Purpose Partition Size Enhanced User Data Area Size Enhanced User Data Start Address PARTITION_SETTING_COMPLETED 1 R/W [155] 0x00 GP_SIZE_MULT 12 R/W [154:143] 0x00 ENH_SIZE_MULT 3 R/W [142:140] 0x00 ENH_START_ADDR 4 R/W [139:136] 0x00 Reserved1 1 - [135] - Bad Block Management mode SEC_BAD_BLK_MGMNT 1 R/W [134] 0x00 Production state awareness PRODUCTION_STATE_AWARENESS 1 W/E_P [133] 0x00 TCASE_SUPPORT 1 W/E_P [132] 0x00 Periodic Wake-up PERIODIC_WAKEUP 1 R/W/E [131] 0x00 Program CID/CSD in DDR mode support PROGRAM_CID_CSD_DDR_SUPPORT 1 R [130] 0x1 - [129:128] - [127:64] - Package Case Temperature is controlled Reserved1 2 Vendor Specific Fields VENDOR_SPECIFIC_FIELD 64 Native sector size NATIVE_SECTOR_SIZE 1 R [63] 0x00 Sector size emulation USE_NATIVE_SECTOR 1 R/W [62] 0x00 Sector size DATA_SECTOR_SIZE 1 R [61] 0x00 1st initialization after disabling sector size emulation INI_TIMEOUT_EMU 1 R [60] 0x00 Class 6 commands control CLASS_6_CTRL 1 R/W/E_P [59] 0x00 Number of addressed groups to be Released DYNCAP_NEEDED 1 R [58] 0x00 Exception events control EXCEPTION_EVENTS_CTRL 2 R/W/E_P [57:56] 0x00 Exception events status EXCEPTION_EVENTS_STATUS 2 R [55:54] 0x00 Extended Partitions Attribute EXT_PARTITIONS_ATTRIBUTE 2 R/W [53:52] 0x00 Context configuration CONTEXT_CONF 15 R/W/E_P [51:37] 0x00 Packed command status PACKED_COMMAND_STATUS 1 R [36] 0x00 Packed command failure index PACKED_FAILURE_INDEX 1 R [35] 0x00 Power Off Notification POWER_OFF_NOTIFICATION 1 R/W/E_P [34] 0x00 Control to turn the Cache ON/OFF CACHE_CTRL 1 R/W/E_P [33] 0x00 Flushing of the cache FLUSH_CACHE 1 W/E_P [32] 0x00 Control to turn the Barrier ON/OFF BARRIER_CTRL 1 R [31] 0x00 Mode config MODE_CONFIG 1 R/W/E_P [30] 0x00 Mode operation codes MODE_OPERATION_CODES 1 W/E_P [29] 0x00 2 - [28:27] - Reserved 1 FFU status FFU_STATUS 1 R [26] 0x00 Pre-loading data size PRE_LOADING_DATA_SIZE 4 R/W/E_P [25:22] 0x00 Max pre-loading data size MAX_PRE_LOADING_DATA_SIZE 4 R [21:18] 0x01380000 Product state awareness enable PRODUCT_STATE_AWARENESS_ENABLEMENT 1 R/W/E & R [17] 0x03 SECURE_REMOVAL_TYPE 1 R/W & R [16] 0x01 CMDQ_MODE_EN 1 R/W/E_P [15] 0x00 15 - [14:0] - Secure Removal Type Command Queue Mode Enable Reserved1 NOTE: 1) Reserved bits should be read as “0.” - 22 - 8. AC Parameters 8.1 Timing Parameter [Table 27] Timing Parameter Timing Parameter Max. Value Unit 1 S 3 S Read Timeout 100 mS Write Timeout 350 mS Erase Timeout 600 mS Initialization Time (Tint) Normal 1) After partition setting 2) Force Erase Timeout 3 Min Secure Erase Timeout 6 S Secure Trim step1 Timeout 6 S Trim Timeout 600 mS Partition Switching Timeout (after Init) 60 mS Power Off Notification (Short) Timeout 50 mS Power Off Notification (Long) Timeout 1000 mS NOTE: 1) Normal Initialization Time without partition setting 2) Initialization Time after partition setting, refer to INI_TIMEOUT_AP in 6.4 EXT_CSD register 3) Be advised Timeout Values specified in Table above are for testing purposes under KONSEMI test pattern only and actual timeout situations may vary 4) EXCEPTION_EVENT may occur and the actual timeout values may vary due to user environment 8.2 Previous Bus Timing Parameters for DDR52 and HS200 mode are defined by JEDEC standard - 23 - 8.3 Bus Timing Specification in HS400 mode 8.3.1 HS400 Device Input Timing t PERIOD VCCQ V IH CLOCK INPUT VT VIL tTLH VSS tISUddrt VCCQ tTHL tISUddrt IHddr V V IH DAT [7-0] INPUT IHddr IH VALID WINDOW VIL VIL VALID WINDOW VSS Figure 6. HS400 Device Input Timing NOTE: 1) tISU and tIH are measured at VIL (max.) and VIH (min). 2) VIH denotes VIH (min.) and VIL denotes VIL (max.) [Table 28] HS400 Device input timing Parameter Symbol Min Max Unit Cycle time data transfer mode tPERIOD 5 nS Slew rate SR 1.125 V/nS Duty cycle distortion tCKDCD 0.0 Minimum pulse width tCKMPW 2.2 nS t ISUddr 0.4 nS Input hold time tIHddr 0.4 nS Slew rate SR 1.125 V/nS Input CLK 0.3 nS Input DAT (referenced to CLK) Input set-up time - 24 - 8.3.2 HS400 Device Output Timing Data Strobe is used to read data (data read and CRC status response read) in HS400 mode. The device output value of Data Strobe is “High-Z” when the device is not in outputting data (data read, CRC status response). Data Strobe is toggled only during data read period. t PERIOD VCCQ Data Strobe OUTPUT V OH VT V OL t VSS t TLH t VCCQ THL t RQH RQ V DAT[7-0] V OH VALID WINDOW OUTPUT V OL OH V OL VALID WINDOW VSS Figure 7. HS400 Device Output Timing NOTE: VOH denotes VOH (min.) and VOL denotes VOL (max.). [Table 29] HS400 Device Output timing Parameter Symbol Min Max Unit Data Strobe t Cycle time data transfer mode PERIOD 5 nS Slew rate SR 1.125 V/nS Duty cycle distortion tDSDCD 0.0 Minimum pulse width t 2.0 DSMPW Read preamble t Read post-amble t RPRE RPST 0.2 nS nS 0.4 - t 0.4 - t PERIOD PERIOD Output DAT (referenced to Data Strobe) tRQ 0.4 nS RQH 0.4 nS Output skew Output hold skew Slew rate t SR 1.125 - 25 - V/nS 8.4 Bus signal levels As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage. V V DD input high level V output high level OH V IH V undefined IL V input output low level OL low level VSS t 8.4.1 Open-drain mode bus signal level [Table 30] Open-drain bus signal level Parameter Output High Voltage Output Low Voltage Symbol V Min OH VOL Max. Unit Conditions VDD - 0.2 - V 1) - 0.3 V IOL = 2 mA NOTE: 1) Because VOH depends on external resistance value (including outside the package), this value does not apply as device specification. Host is responsible to choose the external pull-up and open drain resistance value to meet VOH Min value. 8.4.2 Push-pull mode bus signal level eMMC The device input and output voltages shall be within the following specified ranges for any VDD of the allowed voltage range [Table 31.1] Push-pull signal level— high-voltage Range Parameter Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Symbol V Min Max. Unit Conditions V IOH = -100uA@ VCCQ min V IOH = 100uA@ VCCQ min VDD + 0.3 V - 0.25*VDD V - Max. Unit Conditions V IOH = -2mA V IOL = 2mA V - V - OH 0.75*VDD OL - 0.125*VDD 0.625*VDD VSS - 0.3 V VIH VIL - [Table 31.2] Push-pull signal level—1.70 - 1.95 VCCQ voltage Range Parameter Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Symbol VOH VOL V IH V IL Min VCCQ - 0.45V - 0.65*VCCQ 0.45V 1) VCCQ + 0.3 VSS - 0.3 0.35*VCCQ NOTE: 1) 0.7*VCCQ for MMC4.3 and older revisions. 2) 0.3*VCCQ for MMC4.3 and older revisions. - 26 - 2) 9. DC Parameters 9.1 Active Power Consumption during operation [Table 32] Active Power Consumption during operation Density NAND Type ICCQ ICC Unit 32 GB 256 Gb *1 75 40 mA NOTE: * Power Measurement conditions: Bus configuration =x8 @HS400 * The measurement for max RMS current is the average RMS current consumption over a period of 100ms. 9.2 Standby Power Consumption in auto power saving mode and standby state. [Table 33] Standby Power Consumption in auto power saving mode and standby state Density NAND Type 32 GB 256 Gb *1 ICCQ ICC 25°C (Typ) 85°C 25°C (Typ) 85°C 150 500 15 20 Unit uA NOTE: *Power Measurement conditions: Bus configuration =x8, No CLK *Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested. 9.3 Sleep Power Consumption in Sleep State [Table 34] Sleep Power Consumption in Sleep State Density NAND Type 32 GB 256 Gb *1 ICCQ 25°C (Typ) 85°C 150 500 ICC Unit 1) uA NOTE: Power Measurement conditions: Bus configuration =x8, No CLK 1) In auto power saving mode, NAND power cannot be turned off. However, in sleep mode NAND power can be turned off. If NAND power is alive, NAND power is same with that of the Standby state. 9.4 Supply Voltage [Table 35] Supply voltage Item Min Max Unit DD (VCCQ) 1.8V/3.3V 1.70(2.70) 1.95(3.60) V DDF CC 2.7 3.6 V -0.5 0.5 V V V (V V ) SS - 27 - 9.5 Bus Signal Line Load The total capacitance CL of each line of the eMMC bus is the sum of the bus master capacitance CHOST, the bus capacitance CBUS itself and the capacitance CDEVICE of the eMMC connected to this line: The sum of the host and bus capacitance should be under 20pF. [Table 36] Bus Signal Line Load [Table 37] Capacitance and Resistance for HS400 mode Parameters Symbol Min Pull-up resistance for CMD RCMD Pull-up resistance for DAT0-DAT7 Typ. Max Unit Remark 4.7 100 KΩ to prevent bus floating RDAT 10 100 KΩ to prevent bus floating Internal pull up resistance DAT1-DAT7 Rint 10 150 KΩ to prevent unconnected lines floating Single Device capacitance CDEVICE 12 pF 16 nH fPP
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