Application Note: SY8370
High Efficiency Fast Response, 11A, 28V Input
Synchronous Step Down Regulator
General Description
Features
Low RDS(ON) for Internal Switches (Top/Bottom):
17/7.5 mΩ
Wide Input Voltage Range: 4~24V
Integrated Bypass Switch: 1.5Ω
Instant PWM Architecture to Achieve Fast
Transient Responses
Internal Soft-start Limits the Inrush Current
Pseudo-Constant Frequency: 500kHz
Adjustable Output Voltage Application
11A Output Current Capability
±1% Internal Reference Voltage
PFM/USM Selectable Light Load Operation
Mode
Power Good Indicator
Output Discharge Function
Cycle-by-cycle Valley and Peak Current Limit
Protection
Programmable Valley Current Limit Threshold
by ILMT Pin
Latch-off Mode Output Under Voltage Protection
Latch-off Mode Output Over Voltage Protection
Latch-off Mode Over Temperature Protection
Input UVLO
RoHS Compliant and Halogen Free
Compact Package: QFN3×4-13
The SY8370 develops a high efficiency synchronous
step-down DC/DC regulator capable of delivering 11A
current. The device integrates main switch and
synchronous switch with very low RDS(ON) to minimize
the conduction loss. In addition, it operates at pseudoconstant frequency of 500kHz under heavy load
conditions to minimize the size of inductor and
capacitor.
Silergy’s proprietary Instant-PWM™ fast-response,
constant-on-time (COT) PWM control method supports
high input/output voltage ratios (low duty cycles), and
fast transient response while maintaining a near
constant operating frequency over line, load and output
voltage ranges. This control method provides stable
operation without complex compensation and even
with low ESR ceramic capacitors.
The SY8370 operates over a wide input voltage range
from 4V to 24V. Cycle-by-cycle current limit, input
under voltage lock-out, internal soft-start, output under
voltage protection, over voltage protection and thermal
shutdown provide safe operation in all operating
conditions.
Ordering Information
SY8370 □(□□)□
Applications
Temperature Code
Package Code
Optional Spec Code
Ordering Number
SY8370TMC
Package type
QFN3×4-13
Note
--
LCD-TV/Net-TV/3DTV
Set Top Box
Notebook
High Power AP
Desk-top
Typical Applications
Efficiency vs. Output Current
(IOUT=0~11A, PFM, L=0.56μH/PCMB104T-R56MT)
100
CIN=10µF×2 CIN=0.1µF
VIN=4~24V
IN
PG
GND
BS
TEST
LX
PG (Open Drain Output)
90
TEST
(Floating or pull to GND)
EN
CFF=2.2nF
High/Floating/Low
3.3V External Voltage
(opt.)
COUT =22µF×4
RFF=1k
SY8370
ON/OFF
VOUT=1.2V
ILMT
FB
BYP
VCC
Efficiency (%)
80
CBS=0.1µF
L1=0.56µH
70
60
50
VIN =5V, VOUT=1.2V
VIN =12V, VOUT=1.2V
VIN =19V, VOUT=1.2V
VIN =24V, VOUT=1.2V
40
R1=100k
30
20
R2=100k
CVCC=2.2µF
CBYP=1.0µF
10
0.001
0.01
0.1
1
11
Output Current (A)
Figure1. Schematic Diagram
AN_SY8370 Rev. 0.9C
© 2020 Silergy Corp.
Figure2. Efficiency vs. Output Current
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SY8370
Pinout (top view)
BS
LX
GND
VCC
13
12
11
10
1
IN
Top Mark:
2
3
4
LX
GND
PG
9
BYP
8
FB
7
ILMT
6
TEST
5
EN
(QFN3×4-13)
CURxyz (Device code: CUR, x=year code, y=week code, z= lot number code)
Pin Name
Pin Number
IN
1
LX
GND
2, 12
3, 11
PG
4
EN
5
TEST
ILMT
FB
6
7
8
BYP
9
VCC
10
BS
13
AN_SY8370 Rev. 0.9C
© 2020 Silergy Corp.
Pin Description
Input pin. Decouple this pin to the GND pin with at least a 20µF ceramic capacitor.
A 0.1μF input ceramic capacitor is recommended to reduce the input noise.
Inductor pin. Connect this pin to the switching node of the inductor.
Ground pin.
Power good Indicator. Open drain output when the output voltage is within 90% to
120% of the regulation point.
Enable control of the DC/DC regulator. Pull this pin high to turn on the regulator. Do
not leave this pin floating.
The pin is also used for controlling operation mode of the regulator under light load
condition after the output of buck regulator is within the regulation range. When its
voltage is less than 1.6V, the Buck regulator works under ultra-sonic mode. When its
voltage is larger than 2.2V, the Buck regulator works under PFM mode.
For factory use only. Leave this pin floating or connect it to the GND in application.
Valley current limit threshold selection pin.
Output feedback pin. Connect to the center point of the resistor divider.
External 3.3V bypass power supply input. Decouple this pin to GND with a 1µF
ceramic capacitor. Leave this pin floating or connect it to GND if not used.
Internal 3.3V LDO output. Power supply for internal analog circuits and driving
circuit. This pin cannot support external power supply. Decouple this pin to GND
with a 2.2µF ceramic capacitor.
Boot-strap pin. Supply high side gate driver. Connect a 0.1μF ceramic capacitor
between the BS pin and the LX pin.
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SY8370
Block Diagram
IN
Input
UVLO
Current Sense
PG
VCC
Bootstrap
Charge
TEST
BS
EN
ILMT
Internal
SST
OTP
OVP
PWM
Control &
Protection
Logic
LX
Current Sense
VCC
UVP
0.6V
GND
FB
BYP
3.1V
IN
3.3V LDO
VCC
Figure3. Block Diagram
Absolute Maximum Ratings (Note 1)
Supply Input Voltage ------------------------------------------------------------------------------------------------- -0.3V to 28V
IN-LX, LX, PG, TEST, EN Voltage------------------------------------------------------------------------------- -0.3V to 26V
BS-LX, FB, VCC, BYP, ILMT Voltage---------------------------------------------------------------------------- -0.3V to 4V
Maximum Power Dissipation, PD,MAX, @ TA = 25°C QFN3×4-13 ------------------------------------------------------ 3.7W
Package Thermal Resistance (Note 2)
θ JA, QFN3×4-13 ------------------------------------------------------------------------------------------------ 27°C/W
θ JC, QFN3×4-13 ------------------------------------------------------------------------------------------------ 4.3°C/W
Junction Temperature Range ------------------------------------------------------------------------------------ -40°C to 150°C
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------------ 260°C
Storage Temperature Range ------------------------------------------------------------------------------------- -65°C to 150°C
Dynamic LX Voltage in 10ns Duration ---------------------------------------------------------------------------- -5V to 29V
Dynamic LX Voltage in 20ns Duration ---------------------------------------------------------------------------- -1V to 28V
Recommended Operating Conditions (Note 3)
Supply Input Voltage ---------------------------------------------------------------------------------------------------- 4V to 24V
Junction Temperature Range ------------------------------------------------------------------------------------ -40°C to 125°C
Ambient Temperature Range ------------------------------------------------------------------------------------- -40°C to 85°C
AN_SY8370 Rev. 0.9C
© 2020 Silergy Corp.
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SY8370
Electrical Characteristics
(VIN= 12V, COUT= 100µF, TA= 25°C, IOUT= 1A unless otherwise specified)
Parameter
Symbol
Test Conditions
Input Voltage Range
VIN
Input UVLO Threshold
VUVLO
VIN rising
UVLO Hysteresis
VHYS
IOUT=0A, VBYP=0V,
Quiescent Current
IQ
VOUT=VSET×105%
Shutdown Current
ISHDN
EN=0
Feedback Reference Voltage
VREF
FB Input Current
IFB
VFB=1V
Top FET RDS(ON)
RDS(ON)1
Bottom FET RDS(ON)
RDS(ON)2
Output Discharge Current
IDIS
VOUT=1.2V
Top FET Current Limit
ILMT,TOP
ILMT=Low
Bottom FET Current Limit
ILMT,BOT
ILMT=Floating
ILMT=High
Bottom FET Reverse Current Limit
ILMT,RVS
USM Mode
VOUT from 0% to
Soft-start Time
tSS
100%VSET
EN Input Voltage High
VEN,H
EN Input Voltage Low
VEN,L
EN Voltage for Ultra-sonic Mode
VEN,USM
EN Voltage for PFM Mode
VEN,PFM
ILMT Input Voltage High
VILMT,H
ILMT Input Voltage Low
VILMT,L
Switching Frequency
fSW
VOUT=1.2V, CCM
Ultra-sonic Mode Frequency
fUSM
USM mode, IOUT=0A
Min ON Time
tON,MIN
VIN=VIN,MAX
Min OFF Time
tOFF,MIN
VCC Output Voltage
VCC
VCC adds 1mA load
Output Over Voltage Threshold
VOVP
VFB rising
Output Over Voltage Hysteresis
VOVP,HYS
Output OVP Delay
tOVP,DLY
(Note 4)
Output Under Voltage Protection
VUVP
Threshold
Output UVP Delay
tUVP,DLY
(Note 4)
Power Good Threshold
VPG
VFB falling(not good)
Power Good Hysteresis
VPG,HYS
VFB rising (good)
tPG,R
Low to high (Note 4)
Power Good Delay
tPG,F
High to low (Note 4)
Power Good Low Voltage
VPG,LOW
VFB=0V, IPG=5mA
Bypass Switch RDS(ON)
RDS(ON),BYP
Bypass Switch Turn-on Voltage
VBYP
Bypass Switch Switchover Hysteresis VBYP,HYS
Bypass Switch OVP Threshold
VBYP,OVP
Thermal Shutdown Temperature
TOTP
TJ rising (Note 4)
Thermal Shutdown Hysteresis
TOTP,HYS
(Note 4)
AN_SY8370 Rev. 0.9C
© 2020 Silergy Corp.
Min
4
0.594
-50
Typ
0.5
Unit
V
V
V
140
µA
4
0.600
Max
24
3.9
9
0.606
50
6
µA
V
nA
mΩ
mΩ
mA
A
A
A
A
A
600
µs
17
7.5
40
24
12.5
15
18
4
1
0.4
1.6
VIN
1
2.2
2.5
425
3.1
117
55
80
500
27
50
200
3.3
120
5
30
60
200
83
7
200
20
0.5
575
3.5
123
65
86
0.45
2.97
1.5
3.1
0.2
120
150
15
V
V
V
V
V
V
kHz
kHz
ns
ns
V
%VREF
%VREF
µs
%VREF
µs
%VREF
%VREF
µs
µs
V
Ω
V
V
%VLDO
°C
°C
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SY8370
Note 1: Stresses beyond the “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2: Package thermal resistance is measured in the natural convection at T A = 25°C on a 8.5cm×8.5cm size,
four-layer Silergy Evaluation Board with 2-oz copper.
Note 3: The device is not guaranteed to function outside its operating conditions.
Note 4: Guaranteed by design.
AN_SY8370 Rev. 0.9C
© 2020 Silergy Corp.
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SY8370
Typical Performance Characteristics
Efficiency vs. Output Current
Efficiency vs. Output Current
(IOUT=0~11A, PFM, L=0.47μH/PCMB104T-R47MS)
(IOUT=0~11A, USM, L=0.47μH/PCMB104T-R47MS)
100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
(TA=25℃, VIN=12V, VOUT=1.2V, L=0.56μH, COUT=88μF, unless otherwise noted)
70
60
50
VIN =5V, VOUT=1.05V
VIN =12V, VOUT=1.05V
VIN =19V, VOUT=1.05V
VIN =24V, VOUT=1.05V
40
30
20
10
0.001
0.01
0.1
1
70
60
50
VIN =5V, VOUT=1.05V
VIN =12V, VOUT=1.05V
VIN =19V, VOUT=1.05V
VIN =24V, VOUT=1.05V
40
30
20
10
0.001
11
0.01
Efficiency vs. Output Current
Efficiency vs. Output Current
(IOUT=0~11A, USM, L=0.56μH/PCMB104T-R56MT)
100
90
90
80
80
70
60
50
VIN =5V, VOUT=1.2V
VIN =12V, VOUT=1.2V
VIN =19V, VOUT=1.2V
VIN =24V, VOUT=1.2V
40
30
20
0.01
0.1
1
60
50
VIN =5V, VOUT=1.2V
VIN =12V, VOUT=1.2V
VIN =19V, VOUT=1.2V
VIN =24V, VOUT=1.2V
40
30
20
10
0.001
11
0.01
1
Efficiency vs. Output Current
Efficiency vs. Output Current
(IOUT=0~11A, USM, L=0.68μH/PCMB104T-R68MT)
100
100
90
90
80
80
70
60
50
VIN =5V, VOUT=1.8V
VIN =12V, VOUT=1.8V
VIN =19V, VOUT=1.8V
VIN =24V, VOUT=1.8V
30
20
0.01
0.1
1
Output Current (A)
AN_SY8370 Rev. 0.9C
© 2020 Silergy Corp.
11
Output Current (A)
Efficiency (%)
Efficiency (%)
0.1
(IOUT=0~11A, PFM, L=0.68μH/PCMB104T-R68MT)
40
11
70
Output Current (A)
10
0.001
1
(IOUT=0~11A, PFM, L=0.56μH/PCMB104T-R56MT)
100
10
0.001
0.1
Output Current (A)
Efficiency (%)
Efficiency (%)
Output Current (A)
70
60
50
VIN =5V, VOUT=1.8V
VIN =12V, VOUT=1.8V
VIN =19V, VOUT=1.8V
VIN =24V, VOUT=1.8V
40
30
20
11
10
0.001
0.01
0.1
1
11
Output Current (A)
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Efficiency vs. Output Current
Efficiency vs. Output Current
(IOUT=0~11A, PFM, L=1.0μH/PCMB104T-1R0MT)
(IOUT=0~11A, USM, L=1.0μH/PCMB104T-1R0MT)
100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
SY8370
70
60
50
VIN =5V, VOUT=2.5V
VIN =12V, VOUT=2.5V
VIN =19V, VOUT=2.5V
VIN =24V, VOUT=2.5V
40
30
20
10
0.001
0.01
0.1
1
70
60
50
VIN =5V, VOUT=2.5V
VIN =12V, VOUT=2.5V
VIN =19V, VOUT=2.5V
VIN =24V, VOUT=2.5V
40
30
20
11
10
0.001
Output Current (A)
VOUT
0.1
1
Output Ripple
Output Ripple
(VIN =12V, VOUT=1.2V, IOUT=0A, USM)
VOUT
20mV/div
10V/div
IL
5A/div
Time (4μs/div)
20mV/div
VLX
10V/div
IL
5A/div
Time (20μs/div)
Output Ripple
Load Transient
(VIN =12V, VOUT=1.2V, IOUT=11A)
(VIN =12V, VOUT=1.2V, IOUT=1.1~11A)
VOUT
20mV/div
VLX
10V/div
IL
10A/div
IL
Time (4μs/div)
AN_SY8370 Rev. 0.9C
© 2020 Silergy Corp.
11
Output Current (A)
(VIN =12V, VOUT=1.2V, IOUT=0A, PFM)
VLX
VOUT
0.01
200mV/div
10A/div
Time (200µs/div)
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SY8370
VIN
Startup from VIN
Shutdown from VIN
(VIN =12V, VOUT=1.2V, IOUT=11A)
(VIN =12V, VOUT=1.2V, IOUT=11A)
VIN
10V/div
10V/div
VOUT
1V/div
VOUT
1V/div
VLX
10V/div
VLX
10V/div
IL
10A/div
IL
10A/div
Time (2ms/div)
Time (20ms/div)
Startup from EN
Shutdown from EN
(VIN =12V, VOUT=1.2V, IOUT=11A)
(VIN =12V, VOUT=1.2V, IOUT=11A)
EN
5V/div
EN
5V/div
VOUT
1V/div
VOUT
1V/div
VLX
10V/div
VLX
10V/div
IL
10A/div
IL
10A/div
Time (800µs/div)
Short Circuit Protection
Short Circuit Protection
(VIN =12V, VOUT=1.2V, IOUT=0A~Short, ILMT=Low)
(VIN =12V, VOUT=1.2V, IOUT=11A~Short, ILMT=Low)
VOUT
IL
Time (800µs/div)
1V/div
VOUT
1V/div
IL
10A/div
10A/div
Time (200µs/div)
AN_SY8370 Rev. 0.9C
© 2020 Silergy Corp.
Time (200µs/div)
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SY8370
Short Circuit Protection
Short Circuit Protection
(VIN =12V, VOUT=1.2V, IOUT=0A~Short, ILMT=Floating)
(VIN =12V, VOUT=1.2V, IOUT=11A~Short, ILMT=Floating)
VOUT
IL
1V/div
VOUT
1V/div
IL
10A/div
10A/div
Time (200µs/div)
Short Circuit Protection
Short Circuit Protection
(VIN =12V, VOUT=1.2V, IOUT=0A~Short, ILMT=High)
(VIN =12V, VOUT=1.2V, IOUT=11A~Short, ILMT=High)
VOUT
IL
Time (200µs/div)
1V/div
VOUT
1V/div
IL
10A/div
10A/div
Time (200µs/div)
AN_SY8370 Rev. 0.9C
© 2020 Silergy Corp.
Time (200µs/div)
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SY8370
Detailed Description
General Features
Constant-on-time Architecture
Fundamental to any constant-on-time (COT)
architecture is the one-shot circuit or on-time
generator, which determines how long to turn on the
high-side power switch. Each on-time (tON) is a
“fixed” period internally calculated to operate the
step down regulator at the desired switching
frequency considering the input and output voltage
ration,
t ON
1.2V
200ns
500kHz 12V
Each tON pulse is triggered by the feedback
comparator when the output voltage as measured at
FF drops below the target value. After one tON period,
a minimum off-time (tOFF,MIN) is imposed before any
further switching is initiated, even if the output
voltage is less than the target. This approach avoids
the making any switching decisions during the noisy
periods just after switching events and while the
switching node (LX) is rapidly rising or falling.
In a COT architecture, there is no fixed clock, so the
high-side power switch can turn on almost
immediately after a load transient and subsequent
switching pulses can be quickly initiated, ramping the
inductor current up to meet load requirements with
minimal delays. Traditional current mode or voltage
mode control methods must simultaneously monitor
the feedback voltage, current feedback and internal
ramps and compensation signals to determine when
to turn off the high-side power switch and turn on the
low-side synchronous rectifier. Considering these
small signals in a switching environment are difficult
to be noise-free after switching large currents,
making those architectures difficult to apply in noisy
environments and at low duty cycles.
Minimum Duty Cycle and Maximum Duty Cycle
In the COT architecture, there is no limitation for
small duty cycle, since at very low duty cycle
operation, once the on-time is close to the minimum
on time, the switching frequency can be reduced as
needed to always ensure a proper operation.
AN_SY8370 Rev. 0.9C
© 2020 Silergy Corp.
Instant-PWM Operation
L1
VIN
VOUT
R1
COUT
CIN
R2
VOUT
fSW VIN
For example, considering that a hypothetical
converter targets 1.2V output from a 12V input at
500kHz, the target on-time is
t ON
The device can support up to 2.5V maximum output
voltage operation with 60% maximum duty cycle
capability over full temperature range.
Ramp
Generator
VRAMP
VFB
S
Q
PWM
signal
R
VREF
tON
Generator
Silergy’s instant-PWM control method adds several
proprietary improvements to the traditional COT
architecture. Whereas most legacy based on COT
implementations require a dedicated connection to
the output voltage terminal to calculate the tON
duration, instant-PWM control method derives this
signal internally. Another improvement optimizes
operation with low ESR ceramic output capacitors. In
many applications it is desirable to utilize very low
ESR ceramic output capacitors, but legacy COT
regulators may become unstable in these cases
because the beneficial ramp signal that results from
the inductor current flowing into the output capacitor
maybe become too small to maintain smooth
operation. For this reason, instant-PWM synthesizes
a virtual replica of this signal internally. This internal
virtual ramp and the feedback voltage are combined
and compared to the reference voltage. When the sum
is lower than the reference voltage, the tON pulse is
triggered as long as the minimum tOFF has been
satisfied and the inductor current as measured in the
low-side synchronous rectifier is lower than the
bottom FET current limit. As the t ON pulse is
triggered, the low-side synchronous rectifier turns off
and the high-side power switch turns on. Then the
inductor current ramps up linearly during the tON
period. At the conclusion of the tON period, the highside power switch turns off, the low-side
synchronous rectifier turns on and the inductor
current ramps down linearly. This action also initiates
the minimum tOFF timer to ensure sufficient time for
stabilizing any transient conditions and settling the
feedback comparator
before the next cycle is
initiated. This minimum tOFF is relatively short so that
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SY8370
during high speed load transient tON can be
retriggered with minimal delay, allowing the inductor
current to ramp quickly to provide sufficient energy
to the load side.
flow and transients during startup. The startup and
shutdown sequence is shown below.
VUVLO
VIN
In order to avoid shoot-through, a dead time (tDEAD) is
generated internally between the high-side power
switch off and the low-side synchronous rectifier on
period or the low-side synchronous rectifier off and
the high-side power switch on period.
EN
tDLY1
VCC
50µs
tDLY2
120µs
VREF
VSS(internal signal)
Input Under Voltage Lock-out (UVLO)
To prevent operation before all internal circuitry is
ready and to ensure that the power and synchronous
rectifier switches can be sufficiently enhanced, the
instant-PWM incorporates one input under-voltage
lockout protections. The device remains in a low
current state and all switching actions are inhibited
until VIN exceeds their own UVLO (rising) threshold.
At that time, if EN is enabled, the device will start-up
by initiating a soft-start ramp. If VIN falls below
VUVLO less than the input UVLO hysteresis,
switching actions will again be suppressed.
If the input UVLO threshold is low for some high
input UVLO threshold requirement applications, use
EN to adjust the input UVLO by adopting two
external divided resistors.
VIN
IN
RH
EN
RL
GND
Enable Control
The EN input is a high-voltage capable input with
logic-compatible threshold. When EN is driven above
1V normal device operation will be enabled. When
driven < 0.4V the device will be shut down, reducing
input current to < 10µA.
It is not recommended to connect EN and IN directly.
A resistor in a range of 1kΩ to 1MΩ should be used
if EN is pulled high by IN.
Startup and Shutdown
The SY8370 incorporates an internal soft-start circuit
to smoothly ramp the output to the desired voltage
whenever the device is enabled. Internally, the softstart circuit clamps the output at a low voltage and
then allows the output to rise to the desired voltage
over approximately 0.4ms, which avoids high current
AN_SY8370 Rev. 0.9C
© 2020 Silergy Corp.
VPG+VPG,HYS
VPG
VUVP
VFB
tSS
VOUT
tPG,R
tPG,F
PG
After the input voltage exceeds its own UVLO
(rising) threshold, VCC is turned on after EN is
enabled for one delay time tDLY1, the buck regulator
is turned on after another delay time tDLY2 after VCC
voltage is set up. When the output voltage is 90% of
the regulation point, PG becomes high-impedance
after one delay time tPG,R.
If the output is pre-biased to a certain voltage before
start-up, the device disables the switching of both the
high-side power switch and the low-side synchronous
rectifier until the voltage on the internal soft start
circuit voltage VSS exceeds the sensed output voltage
at the FB node.
Light Load Operation Mode Selection
PFM or USM light load operation is selected by EN
pin. EN is not only Buck enable pin but also mode
selection pin to control operation mode of the
regulator under light load condition after the output
of Buck regulator is within the regulation range. If
the voltage on this pin is lower than 1.6V and higher
than its rising threshold, the Buck regulator works
under ultra-sonic mode (USM). If the voltage on this
pin is greater than 2.2V, the Buck regulator works
under pulse-frequency modulation mode (PFM).
If PFM light load operation is selected, under light
load conditions, typically IOUT < 1/2×ΔIL, the current
through the low-side synchronous rectifier will ramp
to near zero before the next tON time. When this
occurs, the low-side synchronous rectifier turns off,
preventing recirculation current that can seriously
reduce efficiency under these light load conditions.
As load current is further reduced, and the combined
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SY8370
feedback and ramp signals remain much greater than
the reference voltage, the instant-PWM control loop
will not trigger another tON until needed, so the
apparent operating switching frequency will
correspondingly drop, further enhancing efficiency.
The switching frequency can be lower than audible
frequency area under deep light load or null load
conditions. Continuous conduction mode (CCM)
resumes smoothly as soon as the load current
increases sufficiently for the inductor current to
remain above zero at the time of the next tON cycle.
The device enters CCM once the load current
exceeds the critical level. After that, the switching
frequency stays fairly constant over the output
current range. The critical level of the load current is
determined with
IOUT_CTL
IL VOUT (1 D)
2
2 fSW L1
PG should be connected to VIN or another voltage
source through a resistor (e.g. 100kΩ). After V IN
exceeds its own UVLO (rising) threshold, the PG
FET is turned on so that PG is pulled to GND before
output voltage is ready. After feedback voltage V FB
reaches VPG+VPG,HYS, PG is pulled high (after one
delay time typical 200µs). When VFB drops to VPG, or
rises to VOVP for one OVP delay time, PG is pulled
low (after one delay time typical 20µs).
External Bootstrap Capacitor Connection
This device integrates a floating power supply for the
gate driver that operates the high-side power switch.
Proper operation requires a 0.1µF low ESR ceramic
capacitor to be connected between BS and LX. This
bootstrap capacitor provides the gate driver supply
voltage for the high-side N-channel MOSFET power
switch.
BS
If USM light load operation is selected, it keeps the
switching frequency above an audible frequency area
even under deep light load or null load conditions.
Once the device detects that both the high-side power
switch and the low-side synchronous rectifier turn off
for more than one certain time, it forces the low-side
synchronous rectifier turn on in advance of one tON
cycle and discharge the output capacitor electric
quantity so that the switching frequency is out of
audio range. There is also one feedback loop to
match the low-side synchronous rectifier forced turn
on time with the error amplifier output voltage to
avoid output voltage becoming too high.
Output Discharge
SY8370 discharges the output voltage when the
converter shuts down from VIN or EN, or thermal
shutdown, so that output voltage can be discharged in
a minimal time, even load current is zero. The
discharge FET in parallel with the low-side
synchronous rectifier turns on after the low-side
synchronous rectifier turns off when shut down logic
is triggered. The output discharge current is typically
40mA. Note that the discharge FET is not active
beyond these shutdown conditions.
Buck Output Power Good Indicator
The Buck power good indicator is an open drain
output controlled by a window comparator connected
to the feedback signal. If VFB is greater than
VPG+VPG,HYS and less than VOVP for at least the power
good delay time (low to high), PG will be highimpedance.
AN_SY8370 Rev. 0.9C
© 2020 Silergy Corp.
CBS
0.1µF
LX
VCC Linear Regulator
SY8370 integrates one high performance, low dropout linear regulator 3.3V VCC, which can power the
internal gate drivers, PWM logic, analog circuitry
and other blocks. VCC is supplied by IN voltage.
Connect a 2.2µF low ESR ceramic capacitor from
VCC to GND. VCC can not support external power
supply because of its current limit.
VCC
CVCC
2.2µF
BYP Input
The control and drive circuit can also be powered by
external 3.3V power supply. When a 3.3V external
power supply is connected to the BYP pin, the VCC
LDO is turned off and the switch between BYP and
VCC is turned on. The overall efficiency may be
improved by connecting the BYP pin to external
3.3V switching power supply. Connect a 1.0µF low
ESR ceramic capacitor from BYP pin to GND when
BYP is supplied by 3.3V external power. Make one
good RC filter circuit between the supply source and
the BYP pin if the power supply is not one ideal DC
source. Leave this pin floating or connect it to GND
if not used.
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SY8370
Fault Protection Modes
Output Current Limit
Instant-PWM incorporates a cycle-by-cycle
“valley” current limit. Inductor current is measured
in the low-side synchronous rectifier when it turns
on and as the inductor current ramps down. If the
current exceeds the bottom FET current limit
threshold, tON is inhibited until the current returns
back to the limit threshold or lower.
Bottom FET current limit
IL
VFB
VREF
VLX
Output Under Voltage Protection (UVP)
If VFB < ~60% of the reference voltage for
approximately 200µs occurring when the output short
circuit or the load current is heavier than the
maximum current capacity, the output under voltage
protection (UVP) will be triggered, and the device
will latch off. Recycling EN input to re-enable the
device.
Output Short Circuit
VFB 500µF and minimum load
current is low, set feed-forward values as RFF = 1kΩ
and CFF = 4.7nF to provide sufficient ripple to FB for
small output ripple and good transient behavior.
L1
LX
0.56H (5.5A)2
80.21mV
2 88F 1.2V
Using the POS capacitor case, the above result is
AN_SY8370 Rev. 0.9C
© 2020 Silergy Corp.
VOUT
RFF
(opt.)
R1
COUT
Consider a 5.5A load increase using the ceramic
capacitor case when VIN = 12V. At VOUT = 1.2V, the
result is tON = 200ns, tOFF,MIN = 200ns, DMAX = 200 /
(200+ 200) = 0.5 and
VUNDERSHOOT,CAP
0.56H (5.5A)2
47.06mV
2 150F 1.2V
Combine the ESR and capacitive undershoot and
overshoot to calculate the total overshoot and
undershoot for a given application.
t ON
t ON +t OFF,MIN
Given this, the capacitive undershoot may be
calculated by
VUNDERSHOOT,CAP
VOVERSHOOT,CAP
FB
CFF
R2
Thermal Design Considerations
Maximum power dissipation depends on the thermal
resistance of the IC package, the PCB layout, the
surrounding airflow, and the difference between the
junction and ambient temperatures. The maximum
power dissipation may be calculated by:
PD,MAX = (TJ,MAX− TA) / θJA
Where, TJ,MAX is the maximum junction temperature,
TA is the ambient temperature, and θJA is the junction
to ambient thermal resistance.
To comply with the recommended operating conditions,
the maximum junction temperature is 125 ℃ . The
junction to ambient thermal resistance θJA is layout
dependent. For the QFN3×4-13 package the thermal
resistance θJA is 27 ℃ /W when measured on a
standard Silergy 8.5cm×8.5cm size four-layer
thermal test board. These standard thermal test
layouts have a very large area with long 2-oz. copper
traces connected to each IC pin and very large,
unbroken 1-oz. internal power and ground planes.
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SY8370
Meeting the performance of the standard thermal test
board in a typical tiny evaluation board area requires
wide copper traces well-connected to the IC's
backside pads leading to exposed copper areas on the
component side of the board as well as good thermal
via from the exposed pad connecting to a wide
middle-layer ground plane and, perhaps, to an
exposed copper area on the board's solder side.
The maximum power dissipation at T A=25℃ may be
calculated by the following formula:
PD,MAX = (125℃ − 25℃) / (27℃/W) = 3.7W
The maximum power dissipation depends on
operating ambient temperature for fixed T J,MAX and
thermal resistance θJA. Use the derating curve in
figure below to calculate the effect of rising ambient
temperature on the maximum power dissipation.
Maximum Power Dissipation (W)
Maximum Power Derating Curve
4
3.7
3.5
VCC Capacitor: Place the VCC capacitor close to
VCC using short, direct copper trace to one nearest
device GND pin (pin 11).
BYP Capacitor: Place the BYP capacitor close to
BYP using short, direct copper trace to one nearest
device GND pin (pin 11) if bypass function is used.
Feedback Network: Place the feedback components
(R1, R2, RFF and CFF) as close to FB pin as possible.
Avoid routing the feedback line near LX, BS or other
high frequency signal as it is noise sensitive. Make
the feedback sampling point Kelvin connect with
COUT rather than the inductor output terminal.
LX Connection: Keep LX area small to prevent
excessive EMI, while providing wide copper traces to
minimize parasitic resistance and inductance. Wide
LX copper trace between pin 2 and pin 12 should be
adopted to improve efficiency.
3
2.5
BS Capacitor: Place the BS capacitor on the same
layer as the device, keep the BS voltage path (BS, LX
and CBS) as short as possible.
2
1.5
1
0.5
0
0
25
50
75
100
125
Ambient Temperature (℃)
Layout Design
Follow these PCB layout guidelines for optimal
performance and thermal dissipation.
Input Capacitors: Place the input capacitor very
near IN and GND, minimizing the loop formed by
these connections. And the input capacitor should be
connected to the IN and GND by wide copper plane.
A 0.1μF input ceramic capacitor is recommended to
reduce the input noise.
Output Capacitors: Guarantee the COUT negative
sides are connected with GND pin by wide copper
traces instead of vias, in order to achieve better
accuracy and stability of output voltage.
AN_SY8370 Rev. 0.9C
© 2020 Silergy Corp.
Control Signals: It is not recommended to connect
control signals and IN directly. A resistor in a range
of 1kΩ to 1MΩ should be used if they are pulled high
by IN.
GND Vias: Place adequate number of vias on the
GND layer around the device for better thermal
performance. The exposed GND pad should be
connected by a larger copper area than its size, place
four GND vias on it for heat dissipation.
PCB Board: A four-layer layout with 2-oz copper is
strongly recommended to achieve better thermal
performance. The top layer and bottom layer should
place power IN and GND copper plane as wide as
possible. Middle1 layer should place all GND layer
for conducting heat and shielding middle2 layer
signal line from top layer crosstalk. Place signal lines
on middle2 layer instead of the other layers, so that
the other layers’ GND plane not be cut apart by these
signal lines.
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SY8370
VIN
CIN
L
IN Vias
CIN
CBS
CIN
IN
1
13
2
12
LX
GND
3
11
GND
PG
8
9
FB
BYP
EN
TEST
ILMT
5
7
GND
COUT
10 VCC
4
6
GND Vias
BS
LX
R2
COUT
CVCC
CBYP
R1
COUT
Output line
COUT
CFF
RFF
VBYP
GND
VOUT
Top Layer
Middle1 Layer
(GND Layer, not shown)
Middle2 Layer
Bottom Layer
Figure4. PCB Layout Suggestion
AN_SY8370 Rev. 0.9C
© 2020 Silergy Corp.
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SY8370
QFN3×4-13 Package Outline Drawing
Top View
Front View
Bottom View
Recommended PCB layout
(Reference only)
Notes: 1, All dimension in millimeter and exclude mold flash & metal burr;
2, center line on drawing refers to the chip body center
AN_SY8370 Rev. 0.9C
© 2020 Silergy Corp.
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SY8370
Taping & Reel Specification
1. QFN3×4-13 taping orientation
Feeding direction
2. Carrier Tape & Reel specification for packages
Reel
Size
Package
types
QFN3×4
Tape width
(mm)
Pocket
pitch(mm)
Reel size
(Inch)
Trailer
length(mm)
Leader length
(mm)
Qty per
reel
12
8
13"
400
400
5000
3. Others: NA
AN_SY8370 Rev. 0.9C
© 2020 Silergy Corp.
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SY8370
Revision History
The revision history provided is for informational purpose only and is believed to be accurate, however, not
warranted. Please make sure that you have the latest revision.
Date
Revision
Change
Feb.05, 2021
Revision 0.9C
Update Recommended PCB layout in POD (page 19)
Jan.22, 2021
Revision 0.9B
1.
2.
3.
Add (IN-LX) voltage in Absolute Maximum Ratings;
Add “A 0.1μF input ceramic capacitor is recommended to reduce the input
noise.” in the pin description and the layout design.
Add Table1: Programmable Valley Current Limit in page 13.
Oct.22, 2020
Revision 0.9A
ILMT voltage changes from 26V to 4V in Absolute Maximum Ratings (page3)
Jul.15, 2020
Revision 0.9
Initial Release
AN_SY8370 Rev. 0.9C
© 2020 Silergy Corp.
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SY8370
IMPORTANT NOTICE
1. Right to make changes. Silergy and its subsidiaries (hereafter Silergy) reserve the right to change any information
published in this document, including but not limited to circuitry, specification and/or product design, manufacturing or
descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the
publication hereof. Buyers should obtain the latest relevant information before placing orders and should verify that such
information is current and complete. All semiconductor products are sold subject to Silergy’s standard terms and conditions of
sale.
2. Applications. Application examples that are described herein for any of these products are for illustrative purposes only.
Silergy makes no representation or warranty that such applications will be suitable for the specified use without further testing or
modification. Buyers are responsible for the design and operation of their applications and products using Silergy products.
Silergy or its subsidiaries assume no liability for any application assistance or designs of customer products. It is customer’s sole
responsibility to determine whether the Silergy product is suitable and fit for the customer’s applications and products planned.
To minimize the risks associated with customer’s products and applications, customer should provide adequate design and
operating safeguards. Customer represents and agrees that it has all the necessary expertise to create and implement safeguards
which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures
that might cause harm and take appropriate remedial actions. Silergy assumes no liability related to any default, damage, costs or
problem in the customer’s applications or products, or the application or use by customer’s third-party buyers. Customer will
fully indemnify Silergy, its subsidiaries, and their representatives against any damages arising out of the use of any Silergy
components in safety-critical applications. It is also buyers’ sole responsibility to warrant and guarantee that any intellectual
property rights of a third party are not infringed upon when integrating Silergy products into any application. Silergy assumes no
responsibility for any said applications or for any use of any circuitry other than circuitry entirely embodied in a Silergy product.
3. Limited warranty and liability. Information furnished by Silergy in this document is believed to be accurate and reliable.
However, Silergy makes no representation or warranty, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such information. In no event shall Silergy be liable for
any indirect, incidental, punitive, special or consequential damages, including but not limited to lost profits, lost savings, business
interruption, costs related to the removal or replacement of any products or rework charges, whether or not such damages are
based on tort or negligence, warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer
might incur for any reason whatsoever, Silergy’ aggregate and cumulative liability towards customer for the products described
herein shall be limited in accordance with the Standard Terms and Conditions of Sale of Silergy.
4. Suitability for use. Customer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory
and safety-related requirements concerning its products, and any use of Silergy components in its applications, notwithstanding
any applications-related information or support that may be provided by Silergy. Silergy products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where
failure or malfunction of an Silergy product can reasonably be expected to result in personal injury, death or severe property or
environmental damage. Silergy assumes no liability for inclusion and/or use of Silergy products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own risk.
5. Terms and conditions of commercial sale. Silergy products are sold subject to the standard terms and conditions of
commercial sale, as published at http://www.silergy.com/stdterms, unless otherwise agreed in a valid written individual
agreement specifically agreed to in writing by an authorized officer of Silergy. In case an individual agreement is concluded only
the terms and conditions of the respective agreement shall apply. Silergy hereby expressly objects to and denies the application
of any customer’s general terms and conditions with regard to the purchase of Silergy products by the customer.
6. No offer to sell or license. Nothing in this document may be interpreted or construed as an offer to sell products that is
open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or
intellectual property rights. Silergy makes no representation or warranty that any license, either express or implied, is granted
under any patent right, copyright, mask work right, or other intellectual property right. Information published by Silergy
regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from Silergy under the patents or other intellectual property of Silergy.
For more information, please visit: www.silergy.com
© 2020 Silergy Corp.
AN_SY8370 Rev. 0.9C
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