XL224

Single Supply Quad Operational Amplifiers The 324 series are low−cost, quad operational amplifiers with true differential inputs. They have several distinct advantages overstandard operational amplifier types in single supply applications . Thequad amplifier can operate at supply voltages as low as 3.0 V or ashigh as 32 V with quiescent currents about one−fifth of thoseassociated with the MC1741 (on a per amplifier basis). The commonmode input range includes the negative supply, thereby eliminating thenecessity for external biasing components in many applications. Theoutput voltage range also includes the negative power supply voltage. Features • • • • • • • • • Short Circuited Protected Outputs True Differential Input Stage Single Supply Operation: 3.0 V to 32 V Low Input Bias Currents: 100 nA Maximum (324) Four Amplifiers Per Package Internally Compensated Common Mode Range Extends to Negative Supply Industry Standard Pinouts ESD Clamps on the Inputs Increase Ruggedness without Affecting Device Operation PIN CONNECTIONS Out 1 1 14 2 13 Inputs 1 3 VCC 4 * ) 5 6 Inputs 4 12 11 4 Inputs 2 Out 2 * 1 ) ) 2 * 3 ) * VEE, GND 10 Inputs 3 9 8 7 Out 4 Out 3 (Top View) 1/12 Rev.2.6-2018 224 324 2902 MAXIMUM RATINGS (TA = + 25°C, unless otherwise noted.) Symbol Value VCC VCC, VEE 32 ±16 Input Differential Voltage Range (Note 1) VIDR ±32 Vdc Input Common Mode Voltage Range (Note 2) VICR −0.3 to 32 Vdc Output Short Circuit Duration tSC Continuous Junction Temperature TJ 150 °C RJA 118 156 190 °C/W Storage Temperature Range Tstg −65 to +150 °C ESD Protection at any Pin Human Body Model Machine Model Vesd Rating Power Supply Voltages Single Supply Split Supplies Thermal Resistance, Junction−to−Air (Note 3) Unit Vdc Case 646 Case 751A Case 948G V 2000 200 Operating Ambient Temperature Range °C TA 224 324 −40 to +85 2902 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Split Power Supplies. 2. For supply voltages less than 32 V, the absolute maximum input voltage is equal to the supply voltage. 3. All RJA measurements made on evaluation board with 1 oz. copper traces of minimum pad size. All device outputs were active. 2/12 Rev.2.6-2018 224 324 2902 ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = GND, TA = 25°C, unless otherwise noted.) 224 Characteristics Input Offset Voltage Symbol Min Typ 2902 324 Max Min Typ Max Min Typ Max VIO Unit mV VCC = 5.0 V to 30 V VICR = 0 V to VCC −1.7 V, VO = 1.4 V, RS = 0  TA = 25°C − 2.0 5.0 − 2.0 7.0 − 2.0 7.0 TA = Thigh (Note 5) − − 7.0 − − 9.0 − − 10 TA = Tlow (Note 5) − − 7.0 − − 9.0 − − 10 VIO/T − 7.0 − − 7.0 − − 7.0 − V/°C Input Offset Current TA = Thigh to Tlow (Note 5) IIO − − 3.0 − 30 100 − − 5.0 − 50 150 − − 5.0 − 50 200 nA Average Temperature Coefficient of Input Offset Current IIO/T − 10 − − 10 − − 10 − pA/°C IIB − − −90 − −150 −300 − − −90 − −250 −500 − − −90 − −250 −500 nA Average Temperature Coefficient of Input Offset Voltage TA = Thigh to Tlow (Notes 5 and 7) TA = Thigh to Tlow (Notes 5 and 7) Input Bias Current TA = Thigh to Tlow (Note 5) Input Common Mode Voltage Range (Note 6) VICR V VCC = 30 V TA = +25°C 0 − 28.3 0 − 28.3 0 − 28.3 TA = Thigh to Tlow (Note 5) 0 − 28 0 − 28 0 − 28 − − VCC − − VCC − − VCC Differential Input Voltage Range VIDR Large Signal Open Loop Voltage Gain AVOL V V/mV RL = 2.0 k, VCC = 15 V, for Large VO Swing 50 100 − 25 100 − 25 100 − TA = Thigh to Tlow (Note 5) 25 − − 15 − − 15 − − CS − −120 − − −120 − − −120 − dB Common Mode Rejection, RS ≤ 10 k CMR 70 85 − 65 70 − 50 70 − dB Power Supply Rejection PSR 65 100 − 65 100 − 50 100 − dB Channel Separation 10 kHz ≤ f ≤ 20 kHz, Input Referenced 4. The input common mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common mode voltage range is VCC −1.7 V, but either or both inputs can go to +32 V without damage, independent of the magnitude of VCC. 5. Guaranteed by design. 3/12 Rev.2.6-2018 224 324 2902 ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = GND, TA = 25°C, unless otherwise noted.) 224 Characteristics Output Voltage − High Limit Symbol Min Typ 324 Max Min Typ 2902 Max Min Typ Max VOH V VCC = 5.0 V, RL = 2.0 k, TA = 25°C 3.3 3.5 − 3.3 3.5 − 3.3 3.5 − VCC = 30 V RL = 2.0 k (TA = Thigh to Tlow) (Note 8) 26 − − 26 − − 26 − − VCC = 30 V RL = 10 k (TA = Thigh to Tlow) (Note 8) 27 28 − 27 28 − 27 28 − − 5.0 20 − 5.0 20 − 5.0 100 Output Voltage − Low Limit, VCC = 5.0 V, RL = 10 k, TA = Thigh to Tlow (Note 8) VOL Output Source Current (VID = +1.0 V, VCC = 15 V) IO + Unit mV mA TA = 25°C 20 40 − 20 40 − 20 40 − TA = Thigh to Tlow (Note 8) 10 20 − 10 20 − 10 20 − 10 20 − 10 20 − 10 20 − TA = Thigh to Tlow (Note 8) 5.0 8.0 − 5.0 8.0 − 5.0 8.0 − (VID = −1.0 V, VO = 200 mV, TA = 25°C) 12 50 − 12 50 − − − − A − 40 60 − 40 60 − 40 60 mA Output Sink Current (VID = −1.0 V, VCC = 15 V) TA = 25°C IO − Output Short Circuit to Ground (Note 9) ISC Power Supply Current (TA = Thigh to Tlow) (Note 8) ICC mA mA VCC = 30 V VO = 0 V, RL = ∞ − − 3.0 − − 3.0 − − 3.0 VCC = 5.0 V, VO = 0 V, RL = ∞ − − 1.2 − − 1.2 − − 1.2 6. The input common mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common mode voltage range is VCC −1.7 V, but either or both inputs can go to +32 V without damage, independent of the magnitude of VCC. 4/12 Rev.2.6-2018 224 324 2902 Output Bias Circuitry Common to Four Amplifiers VCC Q15 Q16 Q22 Q14 Q13 40 k Q19 5.0 pF Q12 Q24 25 Q23 + Q20 Q18 Inputs Q11 Q9 - Q21 Q17 Q6 Q2 Q25 Q7 Q5 Q1 Q8 Q3 Q4 2.4 k Q10 Q26 2.0 k VEE/GND Figure 1. Representative Circuit Diagram (One−Fourth of Circuit Shown) 5/12 Rev.2.6-2018 224 324 2902 CIRCUIT DESCRIPTION 3.0 V to VCC(max) VCC = 15 Vdc RL = 2.0 k TA = 25°C 1.0 V/DIV The 324 series is made using four internally compensated, two−stage operational amplifiers. The first stage of each consists of differential input devices Q20 and Q18 with input buffer transistors Q21 and Q17 and the differential to single ended converter Q3 and Q4. The first stage performs not only the first stage gain function but also performs the level shifting and transconductance reduction functions. By reducing the transconductance, a smaller compensation capacitor (only 5.0 pF) can be employed, thus saving chip area. The transconductance reduction is accomplished by splitting the collectors of Q20 and Q18. Another feature of this input stage is that the input common mode range can include the negative supply or ground, in single supply operation, without saturating either the input devices or the differential to single−ended converter. The second stage consists of a standard current source load amplifier stage. 5.0 s/DIV Figure 2. Large Signal Voltage Follower Response Each amplifier is biased from an internal−voltage regulator which has a low temperature coefficient thus giving each amplifier good temperature characteristics as well as excellent power supply rejection. VCC VCC 1 1 1.5 V to VCC(max) 2 2 3 3 1.5 V to VEE(max) 4 4 VEE Single Supply Split Supplies VEE/GND Figure 3. 70 70 Phase Margin 60 50 50 40 40 30 30 Gain Margin 20 10 10 0 20 PHASE MARGIN (°) GAIN MARGIN (dB) 60 1.0 1000 10 100 LOAD CAPACITANCE (pF) 0 10000 Figure 4. Gain and Phase Margin 6/12 Rev.2.6-2018 224 324 2902 20 120 A VOL, LARGE-SIGNAL OPEN LOOP VOLTAGE GAIN (dB) ± V , INPUT VOLTAGE (V) I 18 16 14 12 10 Negative 8.0 Positive 6.0 4.0 2.0 0 80 60 40 20 0 -20 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 1.0 10 100 1.0 k 10 k 1.0 M 100 k ± VCC/VEE, POWER SUPPLY VOLTAGES (V) f, FREQUENCY (Hz) Figure 5. Input Voltage Range Figure 6. Open Loop Frequency 14 550 RL = 2.0 k VCC = 15 V VEE = GND Gain = -100 RI = 1.0 k RF = 100 k 12 10 8.0 VO , OUTPUT VOLTAGE (mV) VOR , OUTPUT VOLTAGE RANGE (V pp ) VCC = 15 V VEE = GND TA = 25°C 100 6. 04. 02. 500 Input 450 Output 400 350 300 250 VCC = 30 V VEE = GND TA = 25°C CL = 50 pF 200 0 1.0 10 100 0 1000 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 f, FREQUENCY (kHz) t, TIME (s) Figure 7. Large−Signal Frequency Response Figure 8. Small−Signal Voltage Follower Pulse Response (Noninverting) 0 8.0 TA = 25°C RL = R 42. I IB , INPUT BIAS CURRENT (nA) I CC , POWER SUPPLY CURRENT (mA) 2. 11. 81. 51. 20. 90. 60. 30 0 5.0 10 15 20 25 VCC, POWER SUPPLY VOLTAGE (V) 30 35 Figure 9. Power Supply Current versus Power Supply Voltage 90 80 70 0 2.0 4.0 6.0 8.0 10 12 14 16 VCC, POWER SUPPLY VOLTAGE (V) 18 20 Figure 10. Input Bias Current versus Power Supply Voltage 7/12 Rev.2.6-2018 224 324 2902 50 k R1 5.0 k VCC VCC R2 10 k 1/4 XL1403 2.5 V 1/4 R Hysteresis VOH R1 - a R1 1/4 eo 324 + b R1 1/4 VO Vref + Vin 324 - 1/4 1 CR e2 C VO 324 + VinH = R Figure 14. Comparator with Hysteresis R - 100 k C C R 1/4 - 324 + 100 k 1/4 1/4 324 + Vref Bandpass Output R2 R3 Vref R1 - R1 = QR R1 R2 = TBP Vref = 1 V 2 CC C1 = 10C For:fo=1.0 kHz For:Q= 10 For:TBP= 1 For:TN= 1 C1 1/4 Notch Output 324 + Vref 1 fo =2  RC R3 = TN R2 - 324 + Vref VinH Vref R1 (VOH - VOL) R1 + R2 R R2 VinL R1 (VOH - Vref) + Vref R1 + R2 H= Figure 13. High Impedance Differential Amplifier C1 VOL R1 (VOL - Vref) + Vref VinL = R1 + R2 eo = C (1 + a + b) (e2 - e1) Vin For: fo = 1.0 kHz R = 16 k C = 0.01 F Figure 12. Wien Bridge Oscillator 324 - R1 C R2 1 CR 1/4 R R R1 R2 Figure 11. Voltage Reference + 1 fo = 2  RC 1 Vref = VCC 2 VO = 2.5 V 1 + e1 VO 324 + VO 324 + VCC - Vref - Where:TBP=Center Frequency Gain Where:TN=Passband Notch Gain R = 160 k C = 0.001 F R1 = 1.6 MR 2 = 1.6 MR 3 = 1.6 M Figure 15. Bi−Quad Filter Rev.2.6-2018 224 Vref = Vref 1 V 2 CC Triangle Wave Output + R2 VCC + 1/4 75 k 324 - R1 100 k Vref C 2902 300 k R3 1/4 324 - 324 C Square Wave Output R1 R1 + RC 4 CRf R1 - Vin Vref R2 R1 R2 + R1 Figure 16. Function Generator VO 324 + R2 if R3 = CO 1/4 Rf f = C R3 CO = 10 C 1 Vref = 2 VCC Figure 17. Multiple Feedback Bandpass Filter Given:fo=center frequency A(fo)=gain at center frequency Choose value fo, C Then: R3 = Q  fo C R1 = R3 2 A(fo) R2 = R1 R3 4Q2 R1 - R3 For less than 10% error from operational amplifier, Qo fo BW < 0.1 where fo and BW are expressed in Hz. If source impedance varies, filter may be preceded with voltage follower buffer to stabilize filter parameters. 9/12 Rev.2.6-2018 TSSOP14 封装尺寸图 10/12 Rev.2.6-2018 SOP14 封装尺寸图 11/12 Rev.2.6-2018 DIP14 封装尺寸图 Xinluda reserves the right to change the above information without prior notice. 12/12 Rev.2.6-2018