GigaDevice Semiconductor Inc.
GD32F205xx
ARM® Cortex®-M3 32-bit MCU
Datasheet
GD32F205xx Datasheet
Table of Contents
Table of Contents ............................................................................................................... 1
List of Figures ..................................................................................................................... 3
List of Tables ....................................................................................................................... 4
1. General description ..................................................................................................... 5
2. Device overview ........................................................................................................... 6
2.1.
Device information ........................................................................................................... 6
2.2.
Block diagram .................................................................................................................. 8
2.3.
Pinouts and pin assignment ........................................................................................... 9
2.4.
Memory map ................................................................................................................... 12
2.5.
Clock tree ........................................................................................................................ 15
2.6.
Pin definitions ................................................................................................................ 16
2.6.1.
GD32F205Zx LQFP144 pin definitions .................................................................................. 16
2.6.2.
GD32F205Vx LQFP100 pin definitions ................................................................................. 25
2.6.3.
GD32F205Rx LQFP64 pin definitions ................................................................................... 31
3. Functional description .............................................................................................. 35
3.1.
ARM® Cortex®-M3 core .................................................................................................. 35
3.2.
On-chip memory............................................................................................................. 35
3.3.
Clock, reset and supply management ......................................................................... 36
3.4.
Boot modes..................................................................................................................... 36
3.5.
Power saving modes ..................................................................................................... 37
3.6.
Analog to digital converter (ADC) ................................................................................ 37
3.7.
Digital to analog converter (DAC) ................................................................................ 38
3.8.
DMA ................................................................................................................................. 38
3.9.
General-purpose inputs/outputs (GPIOs) ................................................................... 38
3.10.
Timers and PWM generation ..................................................................................... 39
3.11.
Real time clock (RTC) and backup registers........................................................... 40
3.12.
Inter-integrated circuit (I2C) ...................................................................................... 40
3.13.
Serial peripheral interface (SPI) ................................................................................ 41
3.14.
Universal synchronous/asynchronous receiver transmitter (USART/UART) ..... 41
3.15.
Inter-IC sound (I2S) .................................................................................................... 41
1
GD32F205xx Datasheet
3.16.
Universal serial bus full-speed interface (USBFS) ................................................. 42
3.17.
Controller area network (CAN) .................................................................................. 42
3.18.
External memory controller (EXMC) ........................................................................ 42
3.19.
Secure digital input and output card interface (SDIO) ........................................... 43
3.20.
TFT LCD interface (TLI) .............................................................................................. 43
3.21.
Debug mode ................................................................................................................ 43
3.22.
Package and operation temperature ........................................................................ 43
4. Electrical characteristics .......................................................................................... 44
4.1.
Absolute maximum ratings ........................................................................................... 44
4.2.
Recommended DC characteristics .............................................................................. 44
4.3.
Power consumption ....................................................................................................... 44
4.4.
EMC characteristics ....................................................................................................... 45
4.5.
Power supply supervisor characteristics ................................................................... 46
4.6.
Electrical sensitivity ...................................................................................................... 47
4.7.
External clock characteristics ...................................................................................... 48
4.8.
Internal clock characteristics ....................................................................................... 49
4.9.
PLL characteristics ........................................................................................................ 49
4.10.
Memory characteristics ............................................................................................. 50
4.11.
GPIO characteristics .................................................................................................. 50
4.12.
ADC characteristics ................................................................................................... 51
4.13.
DAC characteristics ................................................................................................... 51
4.14.
I2C characteristics...................................................................................................... 51
4.15.
SPI characteristics ..................................................................................................... 52
5. Package information ................................................................................................. 53
5.1.
LQFP package outline dimensions .............................................................................. 53
6. Ordering information ................................................................................................. 55
7. Revision history ......................................................................................................... 56
2
GD32F205xx Datasheet
List of Figures
Figure 2-1. GD32F205xx block diagram ......................................................................................................... 8
Figure 2-2. GD32F205Zx LQFP144 pinouts.................................................................................................... 9
Figure 2-3. GD32F205Vx LQFP100 pinouts ................................................................................................. 10
Figure 2-4. GD32F205Rx LQFP64 pinouts ................................................................................................... 11
Figure 2-5. GD32F205xx clock tree ............................................................................................................... 15
Figure 5-1. LQFP package outline ................................................................................................................. 53
3
GD32F205xx Datasheet
List of Tables
Table 2-1. GD32F205xx devices features and peripheral list ..................................................................... 6
Table 2-2 GD32F205xx memory map ............................................................................................................ 12
Table 2-3. GD32F205Zx LQFP144 pin definitions ....................................................................................... 16
Table 2-4. GD32F205Vx LQFP100 pin definitions ....................................................................................... 25
Table 2-5. GD32F205Rx LQFP64 pin definitions ......................................................................................... 31
Table 4-1. Absolute maximum ratings .......................................................................................................... 44
Table 4-2. DC operating conditions ............................................................................................................... 44
Table 4-3. Power consumption characteristics ........................................................................................... 44
Table 4-4. EMS characteristics ...................................................................................................................... 45
Table 4-5. EMI characteristics ........................................................................................................................ 46
Table 4-6. Power supply supervisor characteristics.................................................................................. 46
Table 4-7. ESD characteristics ....................................................................................................................... 47
Table 4-8. Static latch-up characteristics .................................................................................................... 47
Table 4-9. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics ... 48
Table 4-10. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics ... 48
Table 4-11. High speed internal clock (IRC8M) characteristics ................................................................ 49
Table 4-12. Low speed internal clock (IRC40K) characteristics ............................................................... 49
Table 4-13. PLL characteristics...................................................................................................................... 49
Table 4-14. Flash memory characteristics ................................................................................................... 50
Table 4-15. I/O port characteristics ............................................................................................................... 50
Table 4-16. ADC characteristics..................................................................................................................... 51
Table 4-17. DAC characteristics..................................................................................................................... 51
Table 4-18. I2C characteristics ....................................................................................................................... 51
Table 4-19. Standard SPI characteristics ..................................................................................................... 52
Table 5-1. LQFP package dimensions .......................................................................................................... 54
Table 6-1. Part ordering code for GD32F205xx devices ............................................................................ 55
Table 7-1. Revision history ............................................................................................................................. 56
4
GD32F205xx Datasheet
1.
General description
The GD32F205xx device belongs to the performance line of GD32 MCU Family. It is a new
32-bit general-purpose microcontroller based on the ARM® Cortex®-M3 RISC core with best
cost-performance ratio in terms of processing capacity, reduced power consumption and
peripheral set. The Cortex®-M3 is a next generation processor core which is tightly coupled
with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug
support.
The GD32F205xx device incorporates the ARM® Cortex®-M3 32-bit processor core operating
at 120 MHz frequency with flash accesses zero wait states to obtain maximum efficiency. It
provides up to 3072 KB on-chip flash memory and 256 KB SRAM memory. An extensive
range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up
to three 12-bit 2 MSPS ADCs, two 12-bit DACs, up to ten 16-bit general timers, two 16-bit
basic timers plus two 16-bit PWM advanced timers, as well as standard and advanced
communication interfaces: up to three SPIs, three I2Cs, four USARTs and four UARTs, two
I2Ss, two CANs, a SDIO, a USBFS. Additional peripherals as TFT-LCD Interface (TLI) and
EXMC interface with SDRAM extension support are included.
The device operates from a 2.6 to 3.6V power supply and available in –40 to +85 °C
temperature range. Several power saving modes provide the flexibility for maximum
optimization of power consumption, an especially important consideration in low power
applications.
The above features make GD32F205xx devices suitable for a wide range of interconnection
and advanced applications, especially in areas such as industrial control, consumer and
handheld equipment, embedded modules, human machine interface, security and alarm
systems, automotive navigation and so on.
5
GD32F205xx Datasheet
2.
Device overview
2.1.
Device information
Table 2-1. GD32F205xx devices features and peripheral list
GD32F205xx
Timers
Flash
Part Number
RC
RE
RG
RK
VC
VE
VG
VK
Fast area (KB)
256
512
384
384
256
512
384
384
Normal area (KB)
0
0
640
2688
0
0
640
2688
Total (KB)
256
512
1024
3072
256
512
1024
3072
SRAM (KB)
128
128
256
256
128
128
256
256
General timer
10
10
10
10
10
10
10
10
(16-bit)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
Advanced timer
2
2
2
2
2
2
2
2
(16-bit)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
SysTick
1
1
1
1
1
1
1
1
Basic timer (16-
2
2
2
2
2
2
2
2
bit)
(5,6)
(5,6)
(5,6)
(5,6)
(5,6)
(5,6)
(5,6)
(5,6)
Watchdog
2
2
2
2
2
2
2
2
RTC
1
1
1
1
1
1
1
1
USART
4
4
4
4
4
4
4
4
2
2
2
2
4
4
4
4
(3-4)
(3-4)
(3-4)
(3-4)
(3-4,6-7)
(3-4,6-7)
(3-4,6-7)
(3-4,6-7)
3
3
3
3
3
3
3
3
3/2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
SDIO
1
1
1
1
1
1
1
1
CAN
2
2
2
2
2
2
2
2
USBFS
1
1
1
1
1
1
1
1
TLI
0
0
0
0
1
1
1
1
GPIO
51
51
51
51
82
82
82
82
EXMC/SDRAM
0/0
0/0
0/0
0/0
1/0
1/0
1/0
1/0
ADC (CHs)
3(16)
3(16)
3(16)
3(16)
3(16)
3(16)
3(16)
3(16)
DAC
2
2
2
2
2
2
2
2
UART
Connectivity
I2C
SPI/I2S
6
GD32F205xx Datasheet
GD32F205xx
Part Number
RC
RE
RG
RK
VC
VE
LQFP64
Package
VG
VK
LQFP100
Table 2-1. GD32F205xx devices features and peripheral list (continued)
GD32F205xx
Flash
Part Number
ZC
ZE
ZG
ZK
Code area (KB)
256
512
384
384
Data area (KB)
0
0
640
2688
Total (KB)
256
512
1024
3072
128
128
256
256
General timer (16-
10
10
10
10
bit)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
Advanced timer
2
2
2
2
(16-bit)
(0,7)
(0,7)
(0,7)
(0,7)
SysTick
1
1
1
1
Connectivity
Timers
SRAM (KB)
Basic timer (16-
2
2
2
2
bit)
(5,6)
(5,6)
(5,6)
(5,6)
Watchdog(16-bit)
2
2
2
2
RTC
1
1
1
1
USART
4
4
4
4
UART
4
4
4
4
I2C
3
3
3
3
3/2
3/2
3/2
3/2
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
SDIO
1
1
1
1
CAN
2
2
2
2
USBFS
1
1
1
1
TLI
1
1
1
1
GPIO
114
114
114
114
EXMC/SDRAM
1/1
1/1
1/1
1/1
ADC (CHs)
3(24)
3(24)
3(24)
3(24)
DAC
2
2
2
2
SPI/I2S
Package
LQFP144
7
GD32F205xx Datasheet
2.2.
Block diagram
Figure 2-1. GD32F205xx block diagram
SW/JTAG
TPIU
ICode DCode System
ARM Cortex-M3
Processor
Fmax:120MHz
NVIC
POR/ PDR
Flash
Memory
PLL
F max : 120MHz
Dbus
Slave
Slave
Master
Slave
Master
Master
AHB Matrix
DMA0(7 chs)
DMA1(7 chs)
Flash
Memory
Controller
Ibus
Slave
LDO
1.2V
IRC
8MHz
AHB2 Peripherals
Slave
HXTAL
3-25MHz
SDIO USBFS CRC RCU
AHB1 Peripherals
Slave
TLI
EXMC
SRAM0
SRAM1
SRAM2
Master
AHB to AP B
Brid ge2
AHB to AP B
Brid ge1
LVD
Interrput request
WWDGT
USART0
Slave
SAR ADC
Slave
SPI0
FWDGT
ADC0~2
RTC
EXTI
DAC
GPIOA
CAN0
GPIOB
CAN1
Powered By V DDA
GPIOE
APB1: Fmax = 60MHz
GPIOD
APB2: Fmax = 120MHz
GPIOC
SPI1~2
TIMER1~3
TIMER4~6
GPIOF
TIMER
11~13
GPIOG
USART1~2
TIMER0
TIMER7
Powered By VDDA
UART3~4
UART6~7
TIMER8~10
I2C0
USART5
I2C1
GPIOH
I2C2
8
GD32F205xx Datasheet
2.3.
Pinouts and pin assignment
Figure 2-2. GD32F205Zx LQFP144 pinouts
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
VSS_10
VDD_10
PD6
PD7
PG9
PG10
PG11
PG12
PG13
PG14
VSS_11
VDD_11
PG15
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
144143142141140139138137136135134133 132131130129128127126125124123122121120 119118117116115114113112111110109
PE2
1
108
PE3
PE4
2
107
VSS_2
3
106
NC
PE5
PE6
4
105
PA13
5
104
PA12
VBAT
6
103
PA11
PC13-TAMPER-RTC
PC14-OSC32IN
7
102
PA10
8
101
PA9
PC15-OSC32OUT
9
100
PA8
PF0
10
99
PC9
PF1
11
98
PC8
PF2
12
97
PC7
PF3
PF4
13
96
PC6
14
95
VDD_9
VDD_2
PF5
15
94
VSS_9
VSS_5
16
93
PG8
VDD_5
17
92
PG7
91
PG6
90
PG5
89
PG4
GigaDevice GD32F205Zx
LQFP144
PF6
18
PF7
19
PF8
20
PF9
21
88
PG3
PF10
22
87
PG2
OSCIN
23
86
PD15
OSCOUT
24
85
PD14
NRST
25
84
VDD_8
PC0
26
83
VSS_8
PC1
27
82
PD13
PC2
28
81
PD12
PC3
VSSA
29
80
PD11
30
79
PD10
VREFVREF+
31
78
PD9
32
77
PD8
VDDA
33
76
PB15
PA0_WKUP
34
75
PB14
PA1
35
74
PB13
PA2
36
73
PB12
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
VDD_1
VSS_1
PB11
PB10
PE15
PE13
PE14
PE12
PE11
VDD_7
PE10
VSS_7
PE8
PE9
PE7
PG1
PG0
PF15
PF14
VDD_6
PF13
VSS_6
PF12
PB2
PF11
PB1
PC5
PB0
PA7
PC4
PA6
PA5
VDD_4
PA4
VSS_4
PA3
9
GD32F205xx Datasheet
Figure 2-3. GD32F205Vx LQFP100 pinouts
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
PE2
1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
PE3
PE4
2
74
VSS_2
3
73
NC
PE5
PE6
4
72
PA13
5
71
PA12
VBAT
6
PC13-TAMPER-RTC
PC14-OSC32IN
7
70
69
PA10
8
68
PA9
PC15-OSC32OUT
9
67
PA8
VSS_5
10
66
PC9
VDD_5
11
65
PC8
64
PC7
63
PC6
14
62
PD15
OSCIN
12
GigaDevice GD32F205Vx
LQFP100
VDD_2
PA11
OSCOUT
NRST
PC0
13
15
61
PD14
PC1
16
60
PD13
PC2
PC3
17
59
PD12
18
58
PD11
VSSA
19
57
PD10
VREFVREF+
20
56
PD9
21
55
PD8
VDDA
22
54
PB15
PA0-WKUP
23
53
PB14
PA1
24
52
PB13
PA2
25
51
PB12
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS_1
VDD_1
PB11
PB10
PE15
PE14
PE13
PE11
PE12
PE10
PE9
PE8
PE7
PB2
PB1
PC5
PB0
PA7
PC4
PA6
PA5
PA4
VDD_4
PA3
VSS_4
10
GD32F205xx Datasheet
Figure 2-4. GD32F205Rx LQFP64 pinouts
PA14
PA15
PC10
PC11
PC12
PD2
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
VSS_3
VDD_3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT
1
48
VDD_2
PC13-TAMPER-RTC
2
47
VSS_2
PA13
PC14-OSC32IN
3
46
PC15-OSC32OUT
PD0-OSCIN
4
45
PA12
5
44
PA11
PD1 OSCOUT
6
43
PA10
NRST
PC0
7
42
PA9
41
PA8
PC1
9
40
PC9
PC2
PC3
VSSA
10
39
PC8
11
38
PC7
12
37
PC6
VDDA
13
36
PB15
PA0-WKUP
14
35
PB14
PA1
15
34
PB13
PA2
16
33
PB12
GigaDevice GD32F205Rx
LQFP64
8
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS_1
VDD_1
PB11
PB10
PB2
PB1
PC5
PB0
PA7
PC4
PA6
PA5
PA4
VDD_4
PA3
VSS_4
11
GD32F205xx Datasheet
2.4.
Memory map
Table 2-2 GD32F205xx memory map
Pre-defined
Regions
Bus
External
Device
AHB
External
RAM
AHB2
AHB1
Peripheral
APB2
Address
Peripherals
0xC000 0000 - 0xDFFF FFFF
EXMC - SDRAM
0xA000 1000 - 0xBFFF FFFF
Reserved
0xA000 0000 - 0xA000 0FFF
EXMC - SWREG
0x9000 0000 - 0x9FFF FFFF
EXMC - PC CARD
0x7000 0000 - 0x8FFF FFFF
EXMC - NAND
0x6000 0000 - 0x6FFF FFFF
EXMC - NOR/PSRAM/SRAM
0x5004 0000 - 0x5FFF FFFF
Reserved
0x5000 0000 - 0x5003 FFFF
USBFS
0x4002 3400 - 0x4FFF FFFF
Reserved
0x4002 3000 - 0x4002 33FF
CRC
0x4002 2400 - 0x4002 2FFF
Reserved
0x4002 2000 - 0x4002 23FF
FMC
0x4002 1400 - 0x4002 1FFF
Reserved
0x4002 1000 - 0x4002 13FF
RCU
0x4002 0800 - 0x4002 0FFF
Reserved
0x4002 0400 - 0x4002 07FF
DMA0
0x4002 0000 - 0x4002 03FF
DMA1
0x4001 8400 - 0x4001 FFFF
Reserved
0x4001 8000 - 0x4001 83FF
SDIO
0x4001 7800 - 0x4001 7FFF
Reserved
0x4001 7400 - 0x4001 77FF
GPIOH
0x4001 7000 - 0x4001 73FF
USART5
0x4001 6C00 - 0x4001 6FFF
Reserved
0x4001 6800 - 0x4001 6BFF
TLI
0x4001 5800 - 0x4001 67FF
Reserved
0x4001 5400 - 0x4001 57FF
TIMER10
0x4001 5000 - 0x4001 53FF
TIMER9
0x4001 4C00 - 0x4001 4FFF
TIMER8
0x4001 4000 - 0x4001 4BFF
Reserved
0x4001 3C00 - 0x4001 3FFF
ADC2
0x4001 3800 - 0x4001 3BFF
USART0
0x4001 3400 - 0x4001 37FF
TIMER7
0x4001 3000 - 0x4001 33FF
SPI0
0x4001 2C00 - 0x4001 2FFF
TIMER0
0x4001 2800 - 0x4001 2BFF
ADC1
0x4001 2400 - 0x4001 27FF
ADC0
0x4001 2000 - 0x4001 23FF
GPIOG
12
GD32F205xx Datasheet
Pre-defined
Regions
Bus
APB1
Address
Peripherals
0x4001 1C00 - 0x4001 1FFF
GPIOF
0x4001 1800 - 0x4001 1BFF
GPIOE
0x4001 1400 - 0x4001 17FF
GPIOD
0x4001 1000 - 0x4001 13FF
GPIOC
0x4001 0C00 - 0x4001 0FFF
GPIOB
0x4001 0800 - 0x4001 0BFF
GPIOA
0x4001 0400 - 0x4001 07FF
EXTI
0x4001 0000 - 0x4001 03FF
AFIO
0x4000 C400 - 0x4000 FFFF
Reserved
0x4000 C000 - 0x4000 C3FF
I2C2
0x4000 8000 - 0x4000 BFFF
Reserved
0x4000 7C00 - 0x4000 7FFF
UART7
0x4000 7800 - 0x4000 7BFF
UART6
0x4000 7400 - 0x4000 77FF
DAC
0x4000 7000 - 0x4000 73FF
PMU
0x4000 6C00 - 0x4000 6FFF
BKP
0x4000 6800 - 0x4000 6BFF
CAN1
0x4000 6400 - 0x4000 67FF
CAN0
0x4000 5C00 - 0x4000 63FF
USBFS/CAN shared
0x4000 5800 - 0x4000 5BFF
I2C1
0x4000 5400 - 0x4000 57FF
I2C0
0x4000 5000 - 0x4000 53FF
UART4
0x4000 4C00 - 0x4000 4FFF
UART3
0x4000 4800 - 0x4000 4BFF
USART2
0x4000 4400 - 0x4000 47FF
USART1
0x4000 4000 - 0x4000 43FF
Reserved
0x4000 3C00 - 0x4000 3FFF
SPI2/I2S2
0x4000 3800 - 0x4000 3BFF
SPI1/I2S1
0x4000 3400 - 0x4000 37FF
Reserved
0x4000 3000 - 0x4000 33FF
FWDGT
0x4000 2C00 - 0x4000 2FFF
WWDGT
0x4000 2800 - 0x4000 2BFF
RTC
0x4000 2400 - 0x4000 27FF
Reserved
0x4000 2000 - 0x4000 23FF
TIMER13
0x4000 1C00 - 0x4000 1FFF
TIMER12
0x4000 1800 - 0x4000 1BFF
TIMER11
0x4000 1400 - 0x4000 17FF
TIMER6
0x4000 1000 - 0x4000 13FF
TIMER5
0x4000 0C00 - 0x4000 0FFF
TIMER4
0x4000 0800 - 0x4000 0BFF
TIMER3
13
GD32F205xx Datasheet
Pre-defined
Regions
SRAM
Code
Bus
AHB
AHB
Address
Peripherals
0x4000 0400 - 0x4000 07FF
TIMER2
0x4000 0000 - 0x4000 03FF
TIMER1
0x2004 0000 - 0x3FFF FFFF
Reserved
0x2002 0000 - 0x2003 FFFF
SRAM2(128KB)
0x2001 C000 - 0x2001 FFFF
SRAM1(16KB)
0x2000 0000 - 0x2001 BFFF
SRAM0(112KB)
0x1FFF F810 - 0x1FFF FFFF
Reserved
0x1FFF F800 - 0x1FFF F80F
Option Bytes
0x1FFF B000 - 0x1FFF F7FF
System memory
0x0830 0000 - 0x1FFF AFFF
Reserved
0x0800 0000 - 0x082F FFFF
Main flash(3072KB)
Aliased to flash or system
0x0000 0000 - 0x07FF FFFF
memory according to BOOT
pins configuration
14
GD32F205xx Datasheet
2.5.
Clock tree
Figure 2-5. GD32F205xx clock tree
CK_HXTAL
PLLT prescaler
(PLLTPSC )
÷2,3...63
1 PLLT input clock
0
CK_IRC8M
PLLTSEL
VCO input clock ×49,50,
…,432
CK_VCO
PLLTR prescaler
(PLLTRPSC )
÷2,3...7
CK_PLLTR
TLI prescaler
(TLIPSC )
÷2,4,8,16
CK_TLI
PLLTMF
(to FMC)
CK_USBFS(=48 MHz)
USBFS
Prescaler
÷1,1.5,2,2.5
1
SCS[1:0]
(to USBFS)
CK_FMC
CK_SDIO
CK_IRC8M
8 MHz
IRC8M
/2
×2,3,4
…,32
PLL
0
1
PLLSEL
PREDV0
0
4-32 MHz
HXTAL
1
Peripheral enable
00
CK_PLL
10
AHB
Prescaler
÷1,2...512
CK_SYS
120 MHz max
(to SDIO)
CK_AHB
120 MHz max
CK_EXMC
EXMC enable
(to EXMC)
AHB enable
(to AHB bus,Cortex-M3,SRAM,DMA)
HCLK
01
PLLMF
/1,2,3…
15,16
CK_CST
Clock
Monitor
÷8
(to Cortex-M3 SysTick)
FCLK
PREDV0SEL
EXT1 to
CK_OUT
(free running clock)
CK_HXTAL
APB1
Prescaler
÷1,2,4,8,16
CK_APB1
PCLK1
60 MHz max
to APB1 peripherals
Peripheral enable
×8,9,10…,
14,16,20
PLL1
TIMER1,2,3,4,5,6,
11,12,13 if(APB1
prescale =1)x1
else x 2
CK_PLL1
PLL1MF
/1,2,3…
15,16
×8,9,10…,
14,16,20
PLL2
PREDV1
0
CK_PLL2
x2
CK_I2S
1 (to I2S1,2)
APB2
Prescaler
÷1,2,4,8,16
/128
32.768 KHz
LXTAL
11
CK_RTC
01
(to RTC)
10
RTCSRC[1:0]
40 KHz
IRC40K
CK_OUT0
to TIMER1,2,3,4,5,
6,11,12,13
CK_APB2
PCLK2
120 MHz max
to APB2 peripherals
Peripheral enable
I2S1/2SEL
PLL2MF
CK_TIMERx
TIMERx
enable
TIMER0,7,8,9,10
if(APB2 prescale
=1)x1
else x 2
ADC
Prescaler
÷2,4,6,8,12,1
6
TIMERx
enable
CK_TIMERx
to TIMER0,7,8,9,10
CK_ADCX to ADC0,1,2
28 MHz max
CK_FWDGT
(to FWDGT)
CKOUT0DIV
÷1,2...64
00xx
0100
0101
0110
0111
NO CLK
CK_SYS
CK_IRC8M
CK_HXTAL
/2
CK_PLL
CK_PLL1
/2
CK_PLL2
1000
1001
1010
1011
EXT1
CK_PLL2
CKOUT0SEL[3:0]
CK_OUT1
CKOUT1DIV
÷1,2...64
00xx
0100
0101
0110
0111
NO CLK
CK_SYS
CK_IRC8M
CK_HXTAL
CK_PLL
/2
CK_PLL1
CK_PLL2
/2
1000
1001
1010
1011
EXT1
CK_PLL2
CKOUT1SEL[3:0]
0 CK_MACTX
1
Ethernet
PHY
/2,20
0 CK_MACRX
1
CK_MACRMII
Legend:
HXTAL: High speed crystal oscillator
LXTAL: Low speed crystal oscillator
IRC8M: Internal 8M RC oscillators
IRC40K: Internal 40K RC oscillator
15
GD32F205xx Datasheet
2.6.
Pin definitions
2.6.1.
GD32F205Zx LQFP144 pin definitions
Table 2-3. GD32F205Zx LQFP144 pin definitions
Pin Name Pins
Pin
I/O
Type(1)
Level(2)
PE2
1
I/O
5VT
PE3
2
I/O
5VT
Functions description
Default: PE2
Alternate: TRACECK, EXMC_A23
Default: PE3
Alternate: TRACED0, EXMC_A19
Default: PE4
PE4
3
I/O
5VT
Alternate:TRACED1, EXMC_A20
Remap: TLI_B0
Default: PE5
PE5
4
I/O
5VT
Alternate:TRACED2, EXMC_A21
Remap: TIMER8_CH0, TLI_G0
Default: PE6
PE6
5
I/O
5VT
Alternate:TRACED3, EXMC_A22
Remap: TIMER8_CH1, TLI_G1
VBAT
6
P
7
I/O
8
I/O
9
I/O
10
I/O
Default: VBAT
PC13TAMPER-
Default: PC13
Alternate: TAMPER-RTC
RTC
PC14OSC32IN
PC15OSC32OUT
Default: PC14
Alternate: OSC32IN
Default: PC15
Alternate: OSC32OUT
Default: PF0
PF0
5VT
Alternate: EXMC_A0
Remap: I2C1_SDA
Default: PF1
PF1
11
I/O
5VT
Alternate: EXMC_A1
Remap: I2C1_SCL
Default: PF2
PF2
12
I/O
5VT
Alternate: EXMC_A2
Remap: I2C1_SMBA
Default: PF3
PF3
13
I/O
5VT
PF4
14
I/O
5VT
PF5
15
I/O
5VT
VSS_5
16
P
Default: VSS_5
VDD_5
17
P
Default: VDD_5
Alternate: EXMC_A3, ADC2_IN9
Default: PF4
Alternate: EXMC_A4, ADC2_IN14
Default: PF5
Alternate: EXMC_A5, ADC2_IN15
16
GD32F205xx Datasheet
Pin Name Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Default: PF6
PF6
18
I/O
Alternate: ADC2_IN4, EXMC_NIORD
Remap: TIMER9_CH0, UART6_RX
Default: PF7
PF7
19
I/O
Alternate: ADC2_IN5, EXMC_NREG
Remap: TIMER10_CH0, UART6_TX
Default: PF8
PF8
20
I/O
Alternate: ADC2_IN6, EXMC_NIOWR
Remap: TIMER12_CH0
Default: PF9
PF9
21
I/O
Alternate: ADC2_IN7, EXMC_CD
Remap: TIMER13_CH0
Default: PF10
PF10
22
I/O
Alternate: ADC2_IN8, EXMC_INTR
Remap: TLI_DE
OSCIN
23
I
OSCOUT
24
O
NRST
25
I/O
PC0
26
I/O
Default: OSCIN
Remap: PH0
Default: OSCOUT
Remap: PH1
Default: NRST
Default: PC0
Alternate: ADC012_IN10
Remap: EXMC_SDNWE
PC1
27
I/O
PC2
28
I/O
Default: PC1
Alternate: ADC012_IN11
Default: PC2
Alternate: ADC012_IN12
Remap: EXMC_SDNE0, SPI1_MISO
Default: PC3
PC3
29
I/O
Alternate: ADC012_IN13
Remap: EXMC_SDCKE0, SPI1_MOSI, I2S1_SD
VSSA
30
P
Default: VSSA
VREF-
31
P
Default: VREF-
VREF+
32
P
Default: VREF+
VDDA
33
P
Default: VDDA
Default: PA0
PA0-WKUP
34
I/O
Alternate: WKUP, USART1_CTS, ADC012_IN0,
TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI
Remap: UART3_TX
Default: PA1
PA1
35
I/O
Alternate: USART1_RTS, ADC012_IN1, TIMER1_CH1,
TIMER4_CH1
Remap: UART3_RX
PA2
36
I/O
Default: PA2
Alternate: USART1_TX, ADC012_IN2, TIMER1_CH2,
17
GD32F205xx Datasheet
Pin Name Pins
Pin
I/O
Type(1)
Level(2)
Functions description
TIMER4_CH2, TIMER8_CH0, SPI0_IO3
Default: PA3
PA3
37
Alternate: USART1_RX, ADC012_IN3, TIMER1_CH3,
I/O
TIMER4_CH3, TIMER8_CH1, SPI0_IO4
Remap: TLI_B5
VSS_4
38
P
Default: VSS_4
VDD_4
39
P
Default: VDD_4
Default: PA4
PA4
40
Alternate: SPI0_NSS, USART1_CK, DAC_OUT0,
I/O
ADC01_IN4
Remap: SPI2_NSS, I2S2_WS, TLI_VSYNC
Default: PA5
PA5
41
Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
I/O
Remap: TIMER1_CH0, TIMER1_ETI, TIMER7_CH0_ON
Default: PA6
PA6
42
Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0,
I/O
TIMER7_BRKIN, TIMER12_CH0
Remap: TIMER0_BRKIN, TLI_G2
Default: PA7
PA7
43
Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1,
I/O
TIMER7_CH0_ON, TIMER13_CH0
Remap: TIMER0_CH0_ON
PC4
44
I/O
PC5
45
I/O
Default: PC4
Alternate: ADC01_IN14
Default: PC5
Alternate: ADC01_IN15
Default: PB0
PB0
46
Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON
I/O
Remap: TIMER0_CH1_ON, TLI_R3
Default: PB1
PB1
47
Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON
I/O
Remap: TIMER0_CH2_ON, TLI_R6
Default: PB2, BOOT1
PB2
48
I/O
5VT
PF11
49
I/O
5VT
PF12
50
I/O
5VT
VSS_6
51
P
Default: VSS_6
VDD_6
52
P
Default: VDD_6
PF13
53
I/O
5VT
PF14
54
I/O
5VT
PF15
55
I/O
5VT
Default: PF11
Alternate: EXMC_NIOS16, EXMC_SDNRAS
Default: PF12
Alternate: EXMC_A6
Default: PF13
Alternate: EXMC_A7
Default: PF14
Alternate: EXMC_A8
Default: PF15
Alternate: EXMC_A9
18
GD32F205xx Datasheet
Pin Name Pins
Pin
I/O
Type(1)
Level(2)
PG0
56
I/O
5VT
PG1
57
I/O
5VT
PE7
58
I/O
5VT
Functions description
Default: PG0
Alternate: EXMC_A10
Default: PG1
Alternate: EXMC_A11
Default: PE7
Alternate: EXMC_D4, UART6_RX
Remap: TIMER0_ETI
Default: PE8
PE8
59
I/O
5VT
Alternate: EXMC_D5, UART6_TX
Remap: TIMER0_CH0_ON
Default: PE9
PE9
60
I/O
5VT
Alternate: EXMC_D6
Remap: TIMER0_CH0
VSS_7
61
P
Default: VSS_7
VDD_7
62
P
Default: VDD_7
Default: PE10
PE10
63
I/O
5VT
Alternate: EXMC_D7
Remap: TIMER0_CH1_ON
Default: PE11
PE11
64
I/O
5VT
Alternate: EXMC_D8
Remap: TIMER0_CH1, TLI_G3
Default: PE12
PE12
65
I/O
5VT
Alternate: EXMC_D9
Remap: TIMER0_CH2_ON, TLI_B4
Default: PE13
PE13
66
I/O
5VT
Alternate: EXMC_D10
Remap: TIMER0_CH2, TLI_DE
Default: PE14
PE14
67
I/O
5VT
Alternate: EXMC_D11
Remap: TIMER0_CH3, TLI_PIXCLK
Default: PE15
PE15
68
I/O
5VT
Alternate: EXMC_D12
Remap: TIMER0_BRKIN, TLI_R7
Default: PB10
PB10
69
I/O
5VT
Alternate: I2C1_SCL, USART2_TX
Remap: TIMER1_CH2, TLI_G4, SPI1_SCK, I2S1_CK
Default: PB11
PB11
70
I/O
5VT
Alternate: I2C1_SDA, USART2_RX
Remap: TIMER1_CH3, TLI_G5
VSS_1
71
P
Default: VSS_1
VDD_1
72
P
Default: VDD_1
Default: PB12
PB12
73
I/O
5VT
Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK,
TIMER0_BRKIN, I2S1_WS, CAN1_RX
PB13
74
I/O
5VT
Default: PB13
19
GD32F205xx Datasheet
Pin Name Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON,
I2S1_CK, CAN1_TX
Default: PB14
PB14
75
I/O
5VT
Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON,
TIMER11_CH0
Default: PB15
PB15
76
I/O
5VT
Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD,
TIMER11_CH1
Default: PD8
PD8
77
I/O
5VT
Alternate: EXMC_D13
Remap: USART2_TX
Default: PD9
PD9
78
I/O
5VT
Alternate: EXMC_D14
Remap: USART2_RX
Default: PD10
PD10
79
I/O
5VT
Alternate: EXMC_D15
Remap: USART2_CK, TLI_B3
Default: PD11
PD11
80
I/O
5VT
Alternate: EXMC_A16
Remap: USART2_CTS
Default: PD12
PD12
81
I/O
5VT
Alternate: EXMC_A17
Remap: TIMER3_CH0, USART2_RTS
Default: PD13
PD13
82
I/O
5VT
Alternate: EXMC_A18
Remap: TIMER3_CH1
VSS_8
83
P
Default: VSS_8
VDD_8
84
P
Default: VDD_8
Default: PD14
PD14
85
I/O
5VT
Alternate: EXMC_D0
Remap: TIMER3_CH2
Default: PD15
PD15
86
I/O
5VT
Alternate: EXMC_D1
Remap: TIMER3_CH3
PG2
87
I/O
5VT
PG3
88
I/O
5VT
PG4
89
I/O
5VT
PG5
90
I/O
5VT
Default: PG2
Alternate: EXMC_A12
Default: PG3
Alternate: EXMC_A13
Default: PG4
Alternate: EXMC_A14, EXMC_BA0
Default: PG5
Alternate: EXMC_A15, EXMC_BA1
Default: PG6
PG6
91
I/O
5VT
Alternate: EXMC_INT1
Remap:TLI_R7
PG7
92
I/O
5VT
Default: PG7
20
GD32F205xx Datasheet
Pin Name Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Alternate: EXMC_INT2
Remap: USART5_CK, TLI_PIXCLK
5VT
Default: PG8
PG8
93
I/O
VSS_9
94
P
Default: VSS_9
VDD_9
95
P
Default: VDD_9
Alternate: EXMC_SDCLK, USART5_RTS
Default: PC6
PC6
96
I/O
5VT
Alternate: I2S1_MCK, TIMER7_CH0, SDIO_D6,
USART5_TX
Remap: TIMER2_CH0, TLI_HSYNC
Default: PC7
PC7
97
I/O
5VT
Alternate: I2S2_MCK, TIMER7_CH1, SDIO_D7,
USART5_RX
Remap: TIMER2_CH1, TLI_G6
Default: PC8
PC8
98
I/O
5VT
Alternate: TIMER7_CH2, SDIO_D0, USART5_CK
Remap: TIMER2_CH2
Default: PC9
PC9
99
I/O
5VT
Alternate: TIMER7_CH3, SDIO_D, CK_OUT1
Remap: TIMER2_CH3, I2C2_SDA
Default: PA8
PA8
100
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT0,
VCORE, USBFS_SOF
Remap: TLI_R6, I2C2_SCL
Default: PA9
PA9
101
I/O
5VT
Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS
Remap: I2C2_SMBAI
PA10
102
I/O
5VT
Default: PA10
Alternate: USART0_RX, TIMER0_CH2, USBFS_ID
Default: PA11
PA11
103
I/O
5VT
Alternate: USART0_CTS, CAN0_RX, USBFS_DM,
TIMER0_CH3
Remap: TLI_R4
Default: PA12
PA12
104
I/O
5VT
Alternate: USART0_RTS, USBFS_DP, CAN0_TX,
TIMER0_ETI
Remap: TLI_R5
I/O
5VT
Default: JTMS, SWDIO
PA13
105
NC
106
VSS_2
107
P
Default: VSS_2
VDD_2
108
P
Default: VDD_2
PA14
109
I/O
5VT
PA15
110
I/O
5VT
Remap: PA13
-
Default: JTCK, SWCLK
Remap: PA14
Default: JTDI
21
GD32F205xx Datasheet
Pin Name Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Alternate: SPI2_NSS, I2S2_WS
Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS
Default: PC10
PC10
111
I/O
5VT
Alternate: UART3_TX, SDIO_D2
Remap: USART2_TX, SPI2_SCK, I2S2_CK, TLI_R2
Default: PC11
PC11
112
I/O
5VT
Alternate: UART3_RX, SDIO_D3
Remap: USART2_RX, SPI2_MISO
Default: PC12
PC12
113
I/O
5VT
Alternate: UART4_TX, SDIO_CK
Remap: USART2_CK, SPI2_MOSI, I2S2_SD
Default: PD0
PD0
114
I/O
5VT
Alternate: EXMC_D2
Remap: CAN0_RX, OSCIN
Default: PD1
PD1
115
I/O
5VT
Alternate: EXMC_D3
Remap: CAN0_TX, OSCOUT
PD2
116
I/O
5VT
Default: PD2
Alternate: TIMER2_ETI, UART4_RX, SDIO_CMD
Default: PD3
PD3
117
I/O
5VT
Alternate: EXMC_CLK
Remap: USART1_CTS, TLI_G7, SPI1_SCK, I2S1_CK
Default: PD4
PD4
118
I/O
5VT
Alternate: EXMC_NOE
Remap: USART1_RTS
Default: PD5
PD5
119
I/O
5VT
Alternate: EXMC_NWE
Remap: USART1_TX
VSS_10
120
Default: VSS_10
VDD_10
121
Default: VDD_10
PD6
122
Default: PD6
I/O
5VT
Alternate: EXMC_NWAIT
Remap: USART1_RX, TLI_B2, SPI2_MOSI, I2S2_SD
Default: PD7
PD7
123
I/O
5VT
Alternate: EXMC_NE0, EXMC_NCE1
Remap: USART1_CK
Default: PG9
PG9
124
I/O
5VT
Alternate: EXMC_NE1, EXMC_NCE2
Remap: USART5_RX
Default: PG10
PG10
125
I/O
5VT
Alternate: EXMC_NCE3_0, EXMC_NE2
Remap: TLI_G3, TLI_B2
Default: PG11
PG11
126
I/O
5VT
Alternate: EXMC_NCE3_1
Remap: TLI_B3
PG12
127
I/O
5VT
Default: PG12
22
GD32F205xx Datasheet
Pin Name Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Alternate: EXMC_NE3
Remap: USART5_RTS, TLI_B4, TLI_B1
Default: PG13
PG13
128
I/O
5VT
Alternate: EXMC_A24
Remap: USART5_CTS
Default: PG14
PG14
129
I/O
5VT
Alternate: EXMC_A25
Remap: USART5_TX
VSS_11
130
P
Default: VSS_10
VDD_11
131
P
Default: VDD_10
PG15
132
I/O
5VT
PB3
133
I/O
5VT
Default: PG15
Alternate: EXMC_SDNCAS, USART5_CTS
Default: JTDO
Alternate:SPI2_SCK, I2S2_CK
Remap: PB3, TRACESWO, TIMER1_CH1, SPI0_SCK
Default: JNTRST
PB4
134
I/O
5VT
Alternate: SPI2_MISO
Remap: TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
135
Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD
I/O
Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX,
EXMC_SDCKE1
Default: PB6
PB6
136
I/O
5VT
Alternate: I2C0_SCL, TIMER3_CH0
Remap: USART0_TX, CAN1_TX, EXMC_SDNE1,
SPI0_IO3
Default: PB7
PB7
137
I/O
5VT
Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NL
Remap: USART0_RX, SPI0_IO4
BOOT0
138
I
PB8
139
I/O
Default: BOOT0
Default: PB8
5VT
Alternate: TIMER3_CH2, TIMER9_CH0, SDIO_D4
Remap: I2C0_SCL, CAN0_RX, TLI_B6
Default: PB9
PB9
140
I/O
5VT
Alternate: TIMER3_CH3, TIMER10_CH0, SDIO_D5
Remap: I2C0_SDA, CAN0_TX, TLI_B7, SPI1_NSS,
I2S1_WS
Default: PE0
PE0
141
I/O
5VT
PE1
142
I/O
5VT
VSS_3
143
P
Default: VSS_3
VDD_3
144
P
Default: VDD_3
Alternate: TIMER3_ETI, EXMC_NBL0, UART7_RX
Default: PE1
Alternate: EXMC_NBL1, UART7_TX
Notes:
(1) Type: I = input, O = output, P = power.
23
GD32F205xx Datasheet
(2) I/O Level: 5VT = 5 V tolerant.
24
GD32F205xx Datasheet
2.6.2.
GD32F205Vx LQFP100 pin definitions
Table 2-4. GD32F205Vx LQFP100 pin definitions
Pin
I/O(2)
Pin Name
Pins
PE2
1
I/O
5VT
PE3
2
I/O
5VT
Functions description
Type(1) Level
Default: PE2
Alternate: TRACECK, EXMC_A23
Default: PE3
Alternate: TRACED0, EXMC_A19
Default: PE4
PE4
3
I/O
5VT Alternate:TRACED1, EXMC_A20
Remap: TLI_B0
Default: PE5
PE5
4
I/O
5VT Alternate:TRACED2, EXMC_A21
Remap: TIMER8_CH0, TLI_G0
Default: PE6
5VT Alternate:TRACED3, EXMC_A22
PE6
5
I/O
VBAT
6
P
7
I/O
8
I/O
9
I/O
VSS_5
10
P
Default: VSS_5
VDD_5
11
P
Default: VDD_5
OSCIN
12
I
OSCOUT
13
O
NRST
14
I/O
PC0
15
I/O
Remap: TIMER8_CH1, TLI_G1
PC13TAMPERRTC
PC14OSC32IN
PC15OSC32OUT
Default: VBAT
Default: PC13
Alternate: TAMPER-RTC
Default: PC14
Alternate: OSC32IN
Default: PC15
Alternate: OSC32OUT
Default: OSCIN
Remap: PH0
Default: OSCOUT
Remap: PH1
Default: NRST
Default: PC0
Alternate: ADC012_IN10
Remap: EXMC_SDNWE
PC1
16
I/O
Default: PC1
Alternate: ADC012_IN11
Default: PC2
PC2
17
I/O
Alternate: ADC012_IN12
Remap: EXMC_SDNE0, SPI1_MISO
Default: PC3
PC3
18
I/O
Alternate: ADC012_IN13
Remap: EXMC_SDCKE0, SPI1_MOSI, I2S1_SD
VSSA
19
P
Default: VSSA
VREF-
20
P
Default: VREF25
GD32F205xx Datasheet
Pin
I/O(2)
Pin Name
Pins
Functions description
VREF+
21
P
Default: VREF+
VDDA
22
P
Default: VDDA
Type(1) Level
Default: PA0
PA0-WKUP
23
I/O
Alternate: WKUP, USART1_CTS, ADC012_IN0, TIMER1_CH0,
TIMER1_ETI, TIMER4_CH0, TIMER7_ETI
Remap: UART3_TX
Default: PA1
PA1
24
I/O
Alternate: USART1_RTS, ADC012_IN1, TIMER1_CH1,
TIMER4_CH1
Remap: UART3_RX
Default: PA2
PA2
25
I/O
Alternate: USART1_TX, ADC012_IN2, TIMER1_CH2,
TIMER4_CH2, TIMER8_CH0, SPI0_IO3
Default: PA3
PA3
26
I/O
Alternate: USART1_RX, ADC012_IN3, TIMER1_CH3,
TIMER4_CH3, TIMER8_CH1, SPI0_IO4
Remap: TLI_B5
VSS_4
27
P
Default: VSS_4
VDD_4
28
P
Default: VDD_4
Default: PA4
PA4
29
I/O
Alternate: SPI0_NSS, USART1_CK, DAC_OUT0, ADC01_IN4
Remap: SPI2_NSS, I2S2_WS, TLI_VSYNC
Default: PA5
PA5
30
I/O
Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
Remap: TIMER1_CH0, TIMER1_ETI, TIMER7_CH0_ON
Default: PA6
PA6
31
I/O
Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0,
TIMER7_BRKIN, TIMER12_CH0
Remap: TIMER0_BRKIN, TLI_G2
Default: PA7
PA7
32
I/O
Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1,
TIMER7_CH0_ON, TIMER13_CH0
Remap: TIMER0_CH0_ON
PC4
33
I/O
PC5
34
I/O
PB0
35
I/O
Default: PC4
Alternate: ADC01_IN14
Default: PC5
Alternate: ADC01_IN15
Default: PB0
Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON
Remap: TIMER0_CH1_ON, TLI_R3
Default: PB1
PB1
36
I/O
Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON
Remap: TIMER0_CH2_ON, TLI_R6
PB2
37
I/O
5VT Default: PB2, BOOT1
PE7
38
I/O
5VT Default: PE7
26
GD32F205xx Datasheet
Pin Name
Pins
Pin
I/O(2)
Functions description
Type(1) Level
Alternate: EXMC_D4, UART6_RX
Remap: TIMER0_ETI
Default: PE8
PE8
39
I/O
5VT Alternate: EXMC_D5, UART6_TX
Remap: TIMER0_CH0_ON
Default: PE9
PE9
40
I/O
5VT Alternate: EXMC_D6
Remap: TIMER0_CH0
Default: PE10
PE10
41
I/O
5VT Alternate: EXMC_D7
Remap: TIMER0_CH1_ON
Default: PE11
PE11
42
I/O
5VT Alternate: EXMC_D8
Remap: TIMER0_CH1, TLI_G3
Default: PE12
PE12
43
I/O
5VT Alternate: EXMC_D9
Remap: TIMER0_CH2_ON, TLI_B4
Default: PE13
PE13
44
I/O
5VT Alternate: EXMC_D10
Remap: TIMER0_CH2, TLI_DE
Default: PE14
PE14
45
I/O
5VT Alternate: EXMC_D11
Remap: TIMER0_CH3, TLI_PIXCLK
Default: PE15
PE15
46
I/O
5VT Alternate: EXMC_D12
Remap: TIMER0_BRKIN, TLI_R7
Default: PB10
PB10
47
I/O
5VT Alternate: I2C1_SCL, USART2_TX
Remap: TIMER1_CH2, TLI_G4, SPI1_SCK, I2S1_CK
Default: PB11
PB11
48
I/O
5VT Alternate: I2C1_SDA, USART2_RX
Remap: TIMER1_CH3, TLI_G5
VSS_1
49
P
Default: VSS_1
VDD_1
50
P
Default: VDD_1
PB12
51
I/O
Default: PB12
5VT Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK,
TIMER0_BRKIN, I2S1_WS, CAN1_RX
Default: PB13
PB13
52
I/O
5VT Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON,
I2S1_CK, CAN1_TX
Default: PB14
PB14
53
I/O
5VT Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON,
TIMER11_CH0
Default: PB15
PB15
54
I/O
5VT Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD,
TIMER11_CH1
27
GD32F205xx Datasheet
Pin Name
Pins
PD8
55
Pin
I/O(2)
Functions description
Type(1) Level
Default: PD8
I/O
5VT Alternate: EXMC_D13
Remap: USART2_TX
Default: PD9
PD9
56
I/O
5VT Alternate: EXMC_D14
Remap: USART2_RX
Default: PD10
PD10
57
I/O
5VT Alternate: EXMC_D15
Remap: USART2_CK, TLI_B3
Default: PD11
PD11
58
I/O
5VT Alternate: EXMC_A16
Remap: USART2_CTS
Default: PD12
PD12
59
I/O
5VT Alternate: EXMC_A17
Remap: TIMER3_CH0, USART2_RTS
Default: PD13
PD13
60
I/O
5VT Alternate: EXMC_A18
Remap: TIMER3_CH1
Default: PD14
PD14
61
I/O
5VT Alternate: EXMC_D0
Remap: TIMER3_CH2
Default: PD15
PD15
62
I/O
5VT Alternate: EXMC_D1
Remap: TIMER3_CH3
Default: PC6
PC6
63
I/O
5VT Alternate: I2S1_MCK, TIMER7_CH0, SDIO_D6, USART5_TX
Remap: TIMER2_CH0, TLI_HSYNC
Default: PC7
PC7
64
I/O
5VT Alternate: I2S2_MCK, TIMER7_CH1, SDIO_D7, USART5_RX
Remap: TIMER2_CH1, TLI_G6
Default: PC8
PC8
65
I/O
5VT Alternate: TIMER7_CH2, SDIO_D0, USART5_CK
Remap: TIMER2_CH2
Default: PC9
PC9
66
I/O
5VT Alternate: TIMER7_CH3, SDIO_D, CK_OUT1
Remap: TIMER2_CH3, I2C2_SDA
Default: PA8
PA8
67
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, VCORE,
USBFS_SOF
Remap: TLI_R6, I2C2_SCL
Default: PA9
PA9
68
I/O
5VT Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS
Remap: I2C2_SMBAI
Default: PA10
PA10
69
I/O
5VT
PA11
70
I/O
5VT Default: PA11
Alternate: USART0_RX, TIMER0_CH2, USBFS_ID
28
GD32F205xx Datasheet
Pin Name
Pins
Pin
I/O(2)
Functions description
Type(1) Level
Alternate: USART0_CTS, CAN0_RX, USBFS_DM,
TIMER0_CH3
Remap: TLI_R4
Default: PA12
PA12
71
I/O
5VT Alternate: USART0_RTS, USBFS_DP, CAN0_TX, TIMER0_ETI
Remap: TLI_R5
I/O
5VT
Default: JTMS, SWDIO
PA13
72
NC
73
VSS_2
74
P
Default: VSS_2
VDD_2
75
P
Default: VDD_2
PA14
76
I/O
5VT
PA15
77
I/O
5VT Alternate: SPI2_NSS, I2S2_WS
Remap: PA13
-
Default: JTCK, SWCLK
Remap: PA14
Default: JTDI
Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS
Default: PC10
PC10
78
I/O
5VT Alternate: UART3_TX, SDIO_D2
Remap: USART2_TX, SPI2_SCK, I2S2_CK, TLI_R2
Default: PC11
PC11
79
I/O
5VT Alternate: UART3_RX, SDIO_D3
Remap: USART2_RX, SPI2_MISO
Default: PC12
PC12
80
I/O
5VT Alternate: UART4_TX, SDIO_CK
Remap: USART2_CK, SPI2_MOSI, I2S2_SD
Default: PD0
PD0
81
I/O
5VT Alternate: EXMC_D2
Remap: CAN0_RX, OSCIN
Default: PD1
PD1
82
I/O
5VT Alternate: EXMC_D3
Remap: CAN0_TX, OSCOUT
Default: PD2
PD2
83
I/O
5VT
PD3
84
I/O
5VT Alternate: EXMC_CLK
Alternate: TIMER2_ETI, UART4_RX, SDIO_CMD
Default: PD3
Remap: USART1_CTS, TLI_G7, SPI1_SCK, I2S1_CK
Default: PD4
PD4
85
I/O
5VT Alternate: EXMC_NOE
Remap: USART1_RTS
Default: PD5
PD5
86
I/O
5VT Alternate: EXMC_NWE
Remap: USART1_TX
Default: PD6
PD6
87
I/O
5VT Alternate: EXMC_NWAIT
Remap: USART1_RX, TLI_B2, SPI2_MOSI, I2S2_SD
29
GD32F205xx Datasheet
Pin Name
Pins
PD7
88
Pin
I/O(2)
Functions description
Type(1) Level
Default: PD7
I/O
5VT Alternate: EXMC_NE0, EXMC_NCE1
Remap: USART1_CK
Default: JTDO
PB3
89
I/O
5VT Alternate:SPI2_SCK, I2S2_CK
Remap: PB3, TRACESWO, TIMER1_CH1, SPI0_SCK
Default: JNTRST
PB4
90
I/O
5VT Alternate: SPI2_MISO
Remap: TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
91
Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD
I/O
Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX,
EXMC_SDCKE1
Default: PB6
PB6
92
I/O
5VT Alternate: I2C0_SCL, TIMER3_CH0
Remap: USART0_TX, CAN1_TX, EXMC_SDNE1, SPI0_IO3
Default: PB7
PB7
93
I/O
5VT Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NL
Remap: USART0_RX, SPI0_IO4
BOOT0
94
I
PB8
95
I/O
Default: BOOT0
Default: PB8
5VT Alternate: TIMER3_CH2, TIMER9_CH0, SDIO_D4
Remap: I2C0_SCL, CAN0_RX, TLI_B6
Default: PB9
PB9
96
I/O
5VT Alternate: TIMER3_CH3, TIMER10_CH0, SDIO_D5
Remap: I2C0_SDA, CAN0_TX, TLI_B7, SPI1_NSS, I2S1_WS
Default: PE0
PE0
97
I/O
5VT
PE1
98
I/O
5VT
VSS_3
99
P
Default: VSS_3
VDD_3
100
P
Default: VDD_3
Alternate: TIMER3_ETI, EXMC_NBL0, UART7_RX
Default: PE1
Alternate: EXMC_NBL1, UART7_TX
Notes:
(1) Type: I = input, O = output, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
30
GD32F205xx Datasheet
2.6.3.
GD32F205Rx LQFP64 pin definitions
Table 2-5. GD32F205Rx LQFP64 pin definitions
Pin
I/O
Type(1)
Level(2)
Pin Name
Pins
VBAT
1
P
2
I/O
3
I/O
4
I/O
OSCIN
5
I
OSCOUT
6
O
NRST
7
I/O
PC0
8
I/O
PC13TAMPER-
Functions description
Default: VBAT
Default: PC13
Alternate: TAMPER-RTC
RTC
PC14OSC32IN
PC15OSC32OUT
Default: PC14
Alternate: OSC32IN
Default: PC15
Alternate: OSC32OUT
Default: OSCIN
Remap: PD0
Default: OSCOUT
Remap: PD1
Default: NRST
Default: PC0
Alternate: ADC012_IN10
Remap: EXMC_SDNWE
PC1
9
I/O
Default: PC1
Alternate: ADC012_IN11
Default: PC2
PC2
10
I/O
Alternate: ADC012_IN12
Remap: EXMC_SDNE0, SPI1_MISO
Default: PC3
PC3
11
I/O
Alternate: ADC012_IN13
Remap: EXMC_SDCKE0, SPI1_MOSI, I2S1_SD
VSSA
12
P
Default: VSSA
VDDA
13
P
Default: VDDA
Default: PA0
PA0-WKUP
14
I/O
Alternate: WKUP, USART1_CTS, ADC012_IN0,
TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI
Remap: UART3_TX
Default: PA1
PA1
15
I/O
Alternate: USART1_RTS, ADC012_IN1, TIMER1_CH1,
TIMER4_CH1
Remap: UART3_RX
Default: PA2
PA2
16
I/O
Alternate: USART1_TX, ADC012_IN2, TIMER1_CH2,
TIMER4_CH2, TIMER8_CH0, SPI0_IO3
Default: PA3
PA3
17
I/O
Alternate: USART1_RX, ADC012_IN3, TIMER1_CH3,
TIMER4_CH3, TIMER8_CH1, SPI0_IO4
Remap: TLI_B5
VSS_4
18
P
Default: VSS_4
31
GD32F205xx Datasheet
Pin Name
Pins
VDD_4
19
Pin
I/O
Type(1)
Level(2)
Functions description
Default: VDD_4
P
Default: PA4
PA4
20
Alternate: SPI0_NSS, USART1_CK, DAC_OUT0,
I/O
ADC01_IN4
Remap: SPI2_NSS, I2S2_WS, TLI_VSYNC
Default: PA5
PA5
21
Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
I/O
Remap: TIMER1_CH0, TIMER1_ETI, TIMER7_CH0_ON
Default: PA6
PA6
22
Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0,
I/O
TIMER7_BRKIN, TIMER12_CH0
Remap: TIMER0_BRKIN, TLI_G2
Default: PA7
PA7
23
Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1,
I/O
TIMER7_CH0_ON, TIMER13_CH0
Remap: TIMER0_CH0_ON
PC4
24
I/O
PC5
25
I/O
PB0
26
I/O
Default: PC4
Alternate: ADC01_IN14
Default: PC5
Alternate: ADC01_IN15
Default: PB0
Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON
Remap: TIMER0_CH1_ON, TLI_R3
Default: PB1
PB1
27
Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON
I/O
Remap: TIMER0_CH2_ON, TLI_R6
PB2
28
I/O
5VT
PB10
29
I/O
5VT
Default: PB2, BOOT1
Default: PB10
Alternate: I2C1_SCL, USART2_TX
Remap: TIMER1_CH2, TLI_G4, SPI1_SCK, I2S1_CK
Default: PB11
PB11
30
I/O
5VT
Alternate: I2C1_SDA, USART2_RX
Remap: TIMER1_CH3, TLI_G5
VSS_1
31
P
Default: VSS_1
VDD_1
32
P
Default: VDD_1
PB12
33
I/O
Default: PB12
5VT
Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK,
TIMER0_BRKIN, I2S1_WS, CAN1_RX
Default: PB13
PB13
34
I/O
5VT
Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON,
I2S1_CK, CAN1_TX
Default: PB14
PB14
35
I/O
5VT
Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON,
TIMER11_CH0
PB15
36
I/O
5VT
Default: PB15
32
GD32F205xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD,
TIMER11_CH1
Default: PC6
PC6
37
I/O
5VT
Alternate: I2S1_MCK, TIMER7_CH0, SDIO_D6, USART5_TX
Remap: TIMER2_CH0, TLI_HSYNC
Default: PC7
PC7
38
I/O
5VT
Alternate: I2S2_MCK, TIMER7_CH1, SDIO_D7,
USART5_RX
Remap: TIMER2_CH1, TLI_G6
Default: PC8
PC8
39
I/O
5VT
Alternate: TIMER7_CH2, SDIO_D0, USART5_CK
Remap: TIMER2_CH2
Default: PC9
PC9
40
I/O
5VT
Alternate: TIMER7_CH3, SDIO_D, CK_OUT1
Remap: TIMER2_CH3, I2C2_SDA
Default: PA8
PA8
41
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, VCORE,
USBFS_SOF
Remap: TLI_R6, I2C2_SCL
Default: PA9
PA9
42
I/O
5VT
Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS
Remap: I2C2_SMBAI
PA10
43
I/O
5VT
Default: PA10
Alternate: USART0_RX, TIMER0_CH2, USBFS_ID
Default: PA11
PA11
44
I/O
5VT
Alternate: USART0_CTS, CAN0_RX, USBFS_DM,
TIMER0_CH3
Remap: TLI_R4
Default: PA12
PA12
45
I/O
5VT
Alternate: USART0_RTS, USBFS_DP, CAN0_TX,
TIMER0_ETI
Remap: TLI_R5
5VT
Default: JTMS, SWDIO
PA13
46
I/O
VSS_2
47
P
Default: VSS_2
VDD_2
48
P
Default: VDD_2
PA14
49
I/O
5VT
PA15
50
I/O
5VT
Remap: PA13
Default: JTCK, SWCLK
Remap: PA14
Default: JTDI
Alternate: SPI2_NSS, I2S2_WS
Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS
Default: PC10
PC10
51
I/O
5VT
Alternate: UART3_TX, SDIO_D2
Remap: USART2_TX, SPI2_SCK, I2S2_CK, TLI_R2
PC11
52
I/O
5VT
Default: PC11
Alternate: UART3_RX, SDIO_D3
33
GD32F205xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Remap: USART2_RX, SPI2_MISO
Default: PC12
PC12
53
I/O
5VT
Alternate: UART4_TX, SDIO_CK
Remap: USART2_CK, SPI2_MOSI, I2S2_SD
PD2
54
I/O
5VT
Default: PD2
Alternate: TIMER2_ETI, UART4_RX, SDIO_CMD
Default: JTDO
PB3
55
I/O
5VT
Alternate:SPI2_SCK, I2S2_CK
Remap: PB3, TRACESWO, TIMER1_CH1, SPI0_SCK
Default: JNTRST
PB4
56
I/O
5VT
Alternate: SPI2_MISO
Remap: TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
57
Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD
I/O
Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX,
EXMC_SDCKE1
Default: PB6
PB6
58
I/O
5VT
Alternate: I2C0_SCL, TIMER3_CH0
Remap: USART0_TX, CAN1_TX, EXMC_SDNE1, SPI0_IO3
Default: PB7
PB7
59
I/O
5VT
Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NL
Remap: USART0_RX, SPI0_IO4
BOOT0
60
Default: BOOT0
I
Default: PB8
PB8
61
I/O
5VT
Alternate: TIMER3_CH2, TIMER9_CH0, SDIO_D4
Remap: I2C0_SCL, CAN0_RX, TLI_B6
Default: PB9
5VT
Alternate: TIMER3_CH3, TIMER10_CH0, SDIO_D5
PB9
62
I/O
VSS_3
63
P
Default: VSS_3
VDD_3
64
P
Default: VDD_3
Remap: I2C0_SDA, CAN0_TX, TLI_B7, SPI1_NSS,
I2S1_WS
Notes:
(1) Type: I = input, O = output, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
34
GD32F205xx Datasheet
3.
Functional description
3.1.
ARM® Cortex®-M3 core
The Cortex®-M3 processor is the latest generation of ARM® processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M3 processor core
Up to 120 MHz operation frequency
Single-cycle multiplication and hardware divider
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer
The Cortex®-M3 processor is based on the ARMv7 architecture and supports both Thumb
and Thumb-2 instruction sets. Some system peripherals listed below are also provided by
Cortex®-M3:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private
Peripheral Bus (PPB) and debug accesses (AHB-AP)
3.2.
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Memory Protection Unit (MPU)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)
On-chip memory
Up to 3072 Kbytes of flash memory, including code flash and data flash
Up to 256 Kbytes of SRAM
The ARM® Cortex®-M3 processor is structured in Harvard architecture which can use
separate buses to fetch instructions and load/store data. 3072 Kbytes of inner flash at most,
which includes code flash and data flash is available for storing programs and data, and
accessed (R/W) at CPU clock speed with zero wait states. Up to 256 Kbytes of inner SRAM
is composed of SRAM0, SRAM1, and SRAM2 that can be accessed at same time. Table 2-2
GD32F205xx memory map shows the memory map of the GD32F205xx series of devices,
including flash, SRAM, peripheral, and other pre-defined regions.
35
GD32F205xx Datasheet
3.3.
Clock, reset and supply management
Internal 8 MHz factory-trimmed RC and external 3 to 25 MHz crystal oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage
detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These
include speed internal RC oscillator and external crystal oscillator, high speed and low speed
two types. Several prescalers allow the frequency configuration of the AHB and two APB
domains. The maximum frequency of the AHB/APB2/APB1 domains is 120/120/60 MHz. See
Figure 2-5. GD32F205xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor
core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are
always active, and ensures proper operation starting from 2.6 V and down to 1.8V. The device
remains in reset mode when VDD is below a specified threshold. The embedded low voltage
detector (LVD) monitors the power supply, compares it to the voltage threshold and generates
an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks,
RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and
backup registers (through power switch) when VDD is not present.
3.4.
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from main flash memory (default)
Boot from system memory
Boot from on-chip SRAM
The boot loader is located in the internal boot ROM memory (system memory). It is used to
reprogram the flash memory by using USART0 (PA9 and PA10), USART1 (PD5 and PD6)
and USB (PA9, PA10, PA11 and PA12). It also can be used to transfer and update the flash
memory code, the data and the vector table sections. In default condition, boot from bank 0
of flash memory is selected. It also supports to boot from bank 1 of flash memory by setting
a bit in option bytes.
36
GD32F205xx Datasheet
3.5.
Power saving modes
The MCU supports three kinds of power saving modes to achieve even lower power
consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating
modes reduce the power consumption and allow the application to achieve the best balance
between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and
any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed
crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and
registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the
system from the deep-sleep mode including the 16 external lines, the RTC alarm, the
LVD output, and USB wakeup. When exiting the deep-sleep mode, the IRC8M is
selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of
IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except
backup registers) are lost. There are four wakeup sources for the standby mode,
including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the
rising edge on WKUP pin.
3.6.
Analog to digital converter (ADC)
12-bit SAR ADC engine with up to 2 MSPS conversion rate
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Conversion range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor
Up to three 12-bit 2 MSPS multi-channel ADC are integrated in the device. It is a total of up
to 16 multiplexed external channels with 2 internal channels for temperature sensor and
voltage reference measurement. The conversion range is between 2.6 V < VDDA < 3.6 V. An
on-chip 16-bit hardware oversample scheme improves performances while off-loading the
related computational burden from the MCU. An analog watchdog block can be used to detect
the channels, which are required to remain within a specific threshold window. A configurable
channel management block of analog inputs also can be used to perform conversions in
single, continuous, scan or discontinuous mode to support more advanced usages.
The ADC can be triggered from the events generated by the general level 0 timers (TIMERx)
and the advanced timers (TIMER0 and TIMER7) with internal connection. The temperature
sensor can be used to generate a voltage that varies linearly with temperature. It is internally
37
GD32F205xx Datasheet
connected to the ADC_IN16 input channel which is used to convert the sensor output voltage
into a digital value.
3.7.
Digital to analog converter (DAC)
12-bit DAC converter of independent output channel
8-bit or 12-bit mode in conjunction with the DMA controller
The 12-bit buffered DAC channel is used to generate variable analog outputs. The DAC is
designed with integrated resistor strings structure. The DAC channels can be triggered by the
timer update outputs or EXTI with DMA support. The maximum output value of the DAC is
VREF+.
3.8.
DMA
14 channels DMA controller and each channel are configurable (7 for DMA0 and 7 for
DMA1)
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S and SDIO
The flexible general-purpose DMA controllers provide a hardware method of transferring data
between peripherals and/or memory without intervention from the CPU, thereby freeing up
bandwidth for other system functions. Three types of access method are supported:
peripheral to memory, memory to peripheral, memory to memory.
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel
requests are determined by software configuration and hardware channel number. Transfer
size of source and destination are independent and configurable.
3.9.
General-purpose inputs/outputs (GPIOs)
Up to 114 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable
There are up to 114 general purpose I/O pins (GPIO) in GD32F205xx, named PA0 ~ PA15,
PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15, PG0 ~ PG15, PH0 ~
PH1 to implement logic input/output functions. Each of the GPIO ports has related control and
configuration registers to satisfy the requirements of specific applications. The external
interrupts on the GPIO pins of the device have related control and configuration registers in
the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative
functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can
be configured by software as output (push-pull or open-drain), as input (with or without pullup or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with
38
GD32F205xx Datasheet
digital or analog alternate functions. All GPIOs are high-current capable except for analog
inputs.
3.10.
Timers and PWM generation
Two 16-bit advanced timer (TIMER0 & TIMER7), ten 16-bit general timers (TIMER1 ~
TIMER4, TIMER8 ~ TIMER13), and two 16-bit basic timer (TIMER5 & TIMER6)
Up to 4 independent channels of PWM, output compare or input capture for each general
timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for
output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (free watchdog timer and window watchdog timer)
The advanced timer (TIMER0 & TIMER7) can be used as a three-phase PWM multiplexed
on 6 channels. It has complementary PWM outputs with programmable dead-time generation.
It can also be used as a complete general timer. The 4 independent channels can be used
for input capture, output compare, PWM generation (edge- or center-aligned counting modes)
and single pulse mode output. If configured as a 16-bit general timer, it has the same functions
as the TIMERx timer. It can be synchronized with external signals or to interconnect with other
general timers together which have the same architecture and features.
The general timer, known as TIMER1 ~ TIMER4, TIMER8 ~ TIMER13 can be used for a
variety of purposes including general time, input signal pulse width measurement or output
waveform generation such as a single pulse generation or PWM output, up to 4 independent
channels for input capture/output compare. The general timer is based on a 16-bit auto-reload
up/down counter and a 16-bit prescaler. TIMER1 ~ TIMER4 and TIMER8/TIMER11 also
supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5 & TIMER6, are mainly used for DAC trigger generation.
They can also be used as a simple 16-bit time base.
The GD32F205xx have two watchdog peripherals, free watchdog timer and window watchdog
timer. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler, it is
clocked from an independent 40 KHz internal RC and as it operates independently of the
main clock, it can operate in deep-sleep and standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free-running timer for application
timeout management.
The window watchdog timer is based on a 7-bit down counter that can be set as free-running.
It can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early wakeup interrupt capability and the counter can be frozen in
debug mode.
39
GD32F205xx Datasheet
The SysTick timer is dedicated for OS, but could also be used as a standard down counter.
The features are shown below:
3.11.
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source
Real time clock (RTC) and backup registers
32-bit up-counter with a programmable 20-bit prescaler
Alarm function
Interrupt and wake-up event
84 bytes backup registers for data protection
The real time clock is an independent timer which provides a set of continuously running
counters in backup registers to provide a real calendar function, and provides an alarm
interrupt or an expected interrupt. It is not reset by a system or power reset, or when the
device wakes up from standby mode. A 20-bit prescaler is used for the time base clock and
is by default configured to generate a time base of 1 second from a clock at 32.768 KHz from
external crystal oscillator.
The backup registers are located in the backup domain that remains powered-on by VBAT
even if VDD power is shut down, they are forty two 16-bit (84 bytes) registers for data protection
of user application data, and the wake-up action from standby mode or system reset do not
affect these registers.
In addition, the backup registers can be used to implement the tamper detection, RTC
calibration function and waveform detection.
3.12.
Inter-integrated circuit (I2C)
Up to three I2C bus interfaces can support both master and slave mode with a frequency
up to 400 KHz
Provide arbitration function, optional PEC (packet error checking) generation and
checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode
The I2C interface is an internal circuit allowing communication with an external I2C interface
which is an industry standard two line serial interface used for connection to external
hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line
(SCL). The I2C module provides transfer rate of up to 100 KHz in standard mode and up to
400 KHz in fast mode. The I2C module also has an arbitration detect function to prevent the
situation where more than one master attempts to transmit data to the I2C bus at the same
time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking
40
GD32F205xx Datasheet
for I2C data.
3.13.
Serial peripheral interface (SPI)
Up to three SPI interfaces with a frequency of up to 30 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking
Quad wire configuration available in master mode (only in SPI0)
The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO
& MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by
the DMA controller. The SPI interface may be used for a variety of purposes, including simplex
synchronous transfers on two lines with a possible bidirectional data line or reliable
communication using CRC checking. Quad-SPI master mode is also supported in SPI0.
3.14.
Universal synchronous/asynchronous receiver transmitter
(USART/UART)
Up to four USARTs and four UARTs with operating frequency up to 7.5 MHz
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
ISO 7816-3 compliant smart card interface
The USART (USART0, USART1, USART2, USART5) and UART (UART3, UART4, UART6,
UART7) are used to transmit data between parallel and serial interfaces, provides a flexible
full duplex data exchange using synchronous or asynchronous transfer. It is also commonly
used for RS-232 standard communication. The USART/UART includes a programmable baud
rate generator which is capable of dividing the system clock to produce a dedicated clock for
the USART/UART transmitter and receiver. The USART/UART also supports DMA function
for high speed data communication.
3.15.
Inter-IC sound (I2S)
Two I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz, multiplexed with
SPI1 and SPI2
Support either master or slave mode audio
Sampling frequencies from 8 KHz up to 192 KHz are supported.
The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio
applications by 3-wire serial lines. GD32F205xx contain an I2S-bus interface that can be
operated with 16/32-bit resolution in master or slave mode, pin multiplexed with SPI1 and
41
GD32F205xx Datasheet
SPI2. The audio sampling frequencies from 8 KHz to 192 KHz is supported with less than
0.5% accuracy error.
3.16.
Universal serial bus full-speed interface (USBFS)
One USB device/host full-speed Interface with frequency up to 12 Mbit/s
Internal main PLL for USB CLK compliantly
The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device
controller enables 12 Mbit/s data exchange with integrated transceivers in device/host mode.
Full-speed peripheral is compliant with the USB 2.0 specification. Transaction formatting is
performed by the hardware, including CRC generation and checking. The status of a
completed USB transfer or error condition is indicated by status registers. An interrupt is also
generated if enabled. The dedicated 48 MHz clock is generated from the internal main PLL
(the clock source must use a HXTAL crystal oscillator) and the operating frequency divided
from APB1 should be 12 MHz above.
3.17.
Controller area network (CAN)
Two CAN2.0B interface with communication frequency up to 1 Mbit/s
Internal main PLL for CAN CLK compliantly
Controller area network (CAN) is a method for enabling serial communication in field bus. The
CAN protocol has been used extensively in industrial automation and automotive applications.
It can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three
message deep for reception. It also provides 28 scalable/configurable identifier filter banks
for selecting the incoming messages needed and discarding the others.
3.18.
External memory controller (EXMC)
Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and
PC card, SDRAM with up to 32-bit data bus
Provide ECC calculating hardware module for NAND Flash memory block
Two SDRAM banks with independent configuration, up to 13-bits Row Address, 11-bits
Column Address, 2-bits internal banks address
SDRAM Memory size: 4x16Mx32bit(256 MB), 4x16Mx16bit (128 MB), 4x16Mx8bit (64
MB)
External memory controller (EXMC) is an abbreviation of external memory controller. It is
divided into several sub-banks for external device support, each sub-bank has its own chip
selection signal but at one time, only one bank can be accessed. The EXMC support code
execution from external memory except NAND Flash and PC card. The EXMC also can be
42
GD32F205xx Datasheet
configured to interface with the most common LCD module of Motorola 6800 and Intel 8080
series and reduce the system cost and complexity.
The EXMC of GD32F205xx in LQFP144 package also supports synchronous dynamic
random access memory (SDRAM). It translates AHB transactions into the appropriate
SDRAM protocol, and meanwhile, makes sure the access time requirements of the external
SDRAM devices are satisfied.
3.19.
Secure digital input and output card interface (SDIO)
Support SD2.0/SDIO2.0/MMC4.2 host interface
The Secure Digital Input and Output Card Interface (SDIO) provides access to external SD
memory cards specifications version 2.0, SDIO card specification version 2.0 and multi-media
card system specification version 4.2 with DMA supported. In addition, this interface is also
compliant with CE-ATA digital protocol rev1.1.
3.20.
TFT LCD interface (TLI)
24-bit RGB Parallel Pixel Output; 8 bits-per-pixel (RGB888)
Supports up to SVGA (800x600) resolution
The TFT LCD interface provides a parallel digital RGB (Red, Green, Blue) and signals for
horizontal, vertical synchronization, pixel clock and data enable as output to interface directly
to a variety of LCD (Liquid Crystal Display) and TFT (Thin Film Transistor) panels. A built-in
DMA engine continuously move data from system memory to TLI and then, output to an
external LCD display. Two separate layers are supported in TLI, as well as layer window and
blending function.
3.21.
Debug mode
Serial wire JTAG debug port (SWJ-DP)
The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
3.22.
Package and operation temperature
LQFP144 (GD32F205Zx), LQFP100 (GD32F205Vx), LQFP64 (GD32F205Rx)
Operation temperature range: -40°C to +85°C (industrial level)
43
GD32F205xx Datasheet
4.
Electrical characteristics
4.1.
Absolute maximum ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device. Note that the device is not guaranteed to operate properly at the
maximum ratings. Exposure to the absolute maximum rating conditions for extended periods
may affect device reliability.
Table 4-1. Absolute maximum ratings
Symbol
Parameter
Min
Max
Unit
VDD
External voltage range
VSS - 0.3
VSS + 3.6
V
VDDA
External analog supply voltage
VSSA - 0.3
VSSA + 3.6
V
VBAT
External battery supply voltage
VSS - 0.3
VSS + 3.6
V
Input voltage on 5V tolerant pin
VSS - 0.3
VDD + 4.0
V
Input voltage on other I/O
VSS - 0.3
4.0
V
Maximum current for GPIO pins
—
25
mA
Injected current on 5V tolerant pin
—
±5
mA
Injected current on other I/O
—
±5
mA
∑IINJ
Injected current on all I/O
—
±25
mA
TA
Operating temperature range
-40
+85
°C
TSTG
Storage temperature range
-55
+150
°C
TJ
Maximum junction temperature
—
125
°C
VIN
IIO
IINJ
4.2.
Recommended DC characteristics
Table 4-2. DC operating conditions
4.3.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
Supply voltage
—
2.6
3.3
3.6
V
VDDA
Analog supply voltage
Same as VDD
2.6
3.3
3.6
V
VBAT
Battery supply voltage
—
1.8
—
3.6
V
Power consumption
The power measurements specified in the tables represent that code with data executing from
on-chip Flash with the following specifications.
Table 4-3. Power consumption characteristics
Symbol Parameter
IDD
Conditions
Supply
VDD=VDDA=3.3V, HXTAL=25MHz, System clock=120
current
MHz, All peripherals enabled
Min Typ Max Unit
— 95.52 —
mA
44
GD32F205xx Datasheet
Symbol Parameter
Conditions
Min Typ Max Unit
(Run
VDD=VDDA=3.3V, HXTAL=25MHz, System clock =120
mode)
MHz, All peripherals disabled
VDD=VDDA=3.3V, HXTAL=25MHz, System clock=108
— 55.23 —
mA
— 86.22 —
mA
— 50.05 —
mA
-— 58.42 —
mA
— 34.32 —
mA
— 59.46 —
mA
— 12.22 —
mA
—
1.23
—
mA
—
1.18
—
mA
MHz, All peripherals enabled
VDD=VDDA=3.3V, HXTAL=25MHz, System clock =108
MHz, All peripherals disabled
VDD=VDDA=3.3V, HXTAL=25MHz, System clock =72MHz,
All peripherals enabled
VDD=VDDA=3.3V, HXTAL=25MHz, System Clock =72
MHz, All peripherals disabled
Supply
VDD=VDDA=3.3V, HXTAL=8MHz, CPU clock off, System
current
clock=120 MHz, All peripherals enabled
(Sleep
VDD=VDDA=3.3V, HXTAL=8MHz, CPU clock off, System
mode)
clock=120 MHz, All peripherals disabled
Supply
VDD=VDDA=3.3V, Regulator in Run mode, IRC40K on,
current
RTC on, All GPIOs analog mode
(DeepSleep
mode)
VDD=VDDA=3.3V, Regulator in Low Power mode, IRC40K
on, RTC on, All GPIOs analog mode
Supply
VDD=VDDA=3.3V, LXTAL off, IRC40K on, RTC on
—
7.47
—
μA
current
VDD=VDDA=3.3V, LXTAL off, IRC40K on, RTC off
—
7.35
—
μA
VDD=VDDA=3.3V, LXTAL off, IRC40K off, RTC off
—
6.13
—
μA
VBAT=3.6V, LXTAL on, RTC on, LXTAL High driving
—
2.69
—
μA
VBAT=3.3V, LXTAL on, RTC on, LXTAL High driving
—
2.41
—
μA
VBAT=2.6V, LXTAL on, RTC on, LXTAL High driving
—
1.81
—
μA
Battery
VBAT=3.6V, LXTAL on, RTC on, LXTAL Mid High driving
—
1.10
—
μA
supply
VBAT=3.3V, LXTAL on, RTC on, LXTAL Mid High driving
—
1.04
—
μA
current
VBAT=2.6V, LXTAL on, RTC on, LXTAL Mid High driving
—
0.92
—
μA
VBAT=3.6V, LXTAL on, RTC on, LXTAL Mid Low driving
—
0.83
—
μA
VBAT=3.3V, LXTAL on, RTC on, LXTAL Mid Low driving
—
0.76
—
μA
VBAT=2.6V, LXTAL on, RTC on, LXTAL Mid Low driving
—
0.63
—
μA
(Standby
mode)
IBAT
4.4.
EMC characteristics
EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and
negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is
given in the Table 4-4. EMS characteristics, based on the EMS levels and classes
compliant with IEC 61000 series standard.
Table 4-4. EMS characteristics
Symbol
Parameter
Conditions
Level/Class
VESD
Voltage applied to all device pins to
VDD = 3.3 V, TA = +25 °C
3B
45
GD32F205xx Datasheet
Symbol
Parameter
Conditions
induce a functional disturbance
conforms to IEC 61000-4-2
Fast transient voltage burst applied to
VFTB
induce a functional disturbance through
100 pF on VDD and VSS pins
Level/Class
VDD = 3.3 V, TA = +25 °C
4A
conforms to IEC 61000-4-4
EMI (Electromagnetic Interference) emission testing result is given in the Table 4-5. EMI
characteristics, compliant with IEC 61967-2 standard which specifies the test board and
the pin loading.
Table 4-5. EMI characteristics
Symbol
Parameter
Conditions
4.5.
Peak level
frequency band
Unit
56M
72M
120M
0.1 to 2 MHz
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