NCA9539-Q100
Low-voltage 16-bit I²C and SMBus low-power I/O expander
with interrupt output, reset pin and configuration registers
Rev. 1 — 31 March 2023
Product data sheet
1. General description
The NCA9539-Q100 provides 16 bits of General Purpose Input/Output (GPIO) expansion with
interrupt and reset for I²C-bus/SMBus applications. It is designed for a wide voltage range of
1.65 V to 5.5 V. Nexperia GPIO expanders provide an elegant solution when additional IOs are
needed while keeping the interconnections to a minimum, for example, in ACPI power switches,
sensors, push buttons, LEDs and fan control. The NCA9539-Q100 contains a set of 8 bit input,
output, configuration and polarity inversion registers. At power up all IOs default to inputs. Each IO
can be configured as either input or output by changing the corresponding bit in the configuration
register. The data for each input or output is stored in the corresponding input or output register.
The polarity inversion register can be programmed to invert the polarity of the read register. The
NCA9539-Q100 has an open-drain interrupt output which is activated when any one of the GPIO
changes from its corresponding input port register state. INT can be connected to the interrupt
input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the
microcontroller if there is incoming data on its ports without having to communicate via the I²Cbus. Thus, NCA9539-Q100 can remain a simple slave. The power on reset sets the registers to
default values and initializes the device state machine. The RESET pin can be used to achieve
same reset functionality without power down/up cycling by keeping active low. The state machine
and the registers are in their default state until the RESET input is once again HIGH. This input
requires pull up to VCC. The NCA9539-Q100 has two address pins A0 and A1 which can be used
to configure the I²C bus slave address of the device. It allows up-to four devices to share the same
I²C-bus/SMBus.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +125 °C
I²C-bus to parallel port expander
Operating power supply voltage range of 1.65 V to 5.5 V
Low standby current consumption:
• 4 µA (maximum)
Schmitt-trigger action allows slow input transition and better switching noise immunity at the
SCL and SDA inputs
• Vhys = 0.10 × VCC (typical)
• Noise filter on SCL and SDA inputs
5 V tolerant I/Os
16 I/O pins which power up configured in input state
Open-drain active LOW interrupt output (INT)
Reset input for resetting NCA9539-Q100 to default values (RESET)
400 kHz Fast-mode I²C-bus
Internal power-on reset
No glitch on power-up
Latched outputs with 25 mA drive maximum capability for directly driving LEDs
Latch-up performance exceeds 100 mA per JESD78, Class II
NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
•
•
ESD protection:
• HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2000 V
• CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 1000 V
Packages offered: TSSOP24
3. Ordering information
Table 1. Ordering information
Type number
Package
NCA9539PW-Q100
Temperature range
Name
Description
Version
-40 °C to +125 °C
TSSOP24
plastic thin shrink small outline package;
24 leads; body width 4.4 mm
SOT355-1
4. Block diagram
NCA9539
P1_0
P1_1
8-bit
A0
A1
write pulse
read pulse
P1_2
INPUT/
OUTPUT
PORTS
P1_3
P1_4
P1_5
P1_6
SCL
SDA
P1_7
INPUT
FILTER
I2C-BUS/SMBus
CONTROL
P0_0
P0_1
8-bit
VCC
RESET
POWER-ON
RESET
write pulse
P0_2
INPUT/
OUTPUT
PORTS
P0_3
P0_4
P0_5
read pulse
P0_6
P0_7
GND
VCC
INT
LP
FILTER
aaa-036334
Remark: All I/Os are set to inputs at reset.
Fig. 1.
Block diagram of NCA9539-Q100
NCA9539_Q100
Product data sheet
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2 / 31
NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
5. Pinning information
5.1. Pinning
PW package
SOT355-1 (TSSOP24)
INT
1
24 VCC
A1
2
23 SDA
RESET
3
22 SCL
P0_0
4
21 A0
P0_1
5
20 P1_7
P0_2
6
19 P1_6
P0_3
7
18 P1_5
P0_4
8
17 P1_4
P0_5
9
16 P1_3
P0_6 10
15 P1_2
P0_7 11
14 P1_1
GND 12
13 P1_0
aaa-036336
Fig. 2.
Pin configuration SOT355-1 (TSSOP24)
5.2. Pin description
Table 2. Pin description
Symbol Pin
Type
Description
INT
1
O
Interrupt output. Connect to VCC through a pull-up resistor
A1
2
I
Address input 1. Connect directly to VCC or GND
RESET
3
I
Active Low reset input. Connect to VCC through a pull-up resistor if no active connection is
used.
P0_0 [1]
4
I/O
Parallel port I/O. Push-pull driver. At power on, P0_0 is configured as input
P0_1 [1]
5
I/O
Parallel port I/O. Push-pull driver. At power on, P0_1 is configured as input
P0_2 [1]
6
I/O
Parallel port I/O. Push-pull driver. At power on, P0_2 is configured as input
P0_3 [1]
7
I/O
Parallel port I/O. Push-pull driver. At power on, P0_3 is configured as input
P0_4 [1]
8
I/O
Parallel port I/O. Push-pull driver. At power on, P0_4 is configured as input
P0_5 [1]
9
I/O
Parallel port I/O. Push-pull driver. At power on, P0_5 is configured as input
P0_6 [1]
10
I/O
Parallel port I/O. Push-pull driver. At power on, P0_6 is configured as input
P0_7 [1]
11
I/O
Parallel port I/O. Push-pull driver. At power on, P0_7 is configured as input
GND
12
power
Ground
P1_0 [2]
13
I/O
Parallel port I/O. Push-pull driver. At power on, P1_0 is configured as input
P1_1 [2]
14
I/O
Parallel port I/O. Push-pull driver. At power on, P1_1 is configured as input
P1_2 [2]
15
I/O
Parallel port I/O. Push-pull driver. At power on, P1_2 is configured as input
P1_3 [2]
16
I/O
Parallel port I/O. Push-pull driver. At power on, P1_3 is configured as input
P1_4 [2]
17
I/O
Parallel port I/O. Push-pull driver. At power on, P1_4 is configured as input
P1_5 [2]
18
I/O
Parallel port I/O. Push-pull driver. At power on, P1_5 is configured as input
P1_6 [2]
19
I/O
Parallel port I/O. Push-pull driver. At power on, P1_6 is configured as input
P1_7 [2]
20
I/O
Parallel port I/O. Push-pull driver. At power on, P1_7 is configured as input
NCA9539_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 31 March 2023
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Nexperia B.V. 2023. All rights reserved
3 / 31
NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
Symbol
Pin
Type
Description
A0
21
I
Address input 0. Connect directly to VCC or GND
SCL
22
I
Serial clock bus. Connect to VCC through a pull-up resistor
SDA
23
I/O
Serial data bus. Connect to VCC through a pull-up resistor.
VCC
24
power
Supply voltage.
[1]
[2]
Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-up, all I/O are configured as high-impedance inputs.
Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-up, all I/O are configured as high-impedance inputs.
6. Functional description
For the block diagram of the NCA9539-Q100 see Fig. 1.
6.1. Device address
slave address
1
1
1
0
fixed
1
A1
A0 R/W
hardware
selectable
aaa-036337
Fig. 3.
NCA9539-Q100 device address
A1 and A0 are the hardware address package pins and are held to either HIGH (logic 1) or LOW
(logic 0) to assign one of the four possible slave addresses. The last bit of the slave address (R/W)
defines the operation (read or write) to be performed. A HIGH (logic 1) selects a read operation,
while a LOW (logic 0) selects a write operation.
6.2. Registers
6.2.1. Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a command
byte, which is stored in the address pointer register of the NCA9539. The lower three bits of this
data byte state the operation (read or write) and the internal registers (Input, Output, Polarity
Inversion, or Configuration) that will be affected. This register is write only.
B7
B6
B5
B4
B3
B2
B1
B0
002aaf540
Fig. 4.
NCA9539_Q100
Product data sheet
Pointer register bits
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NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
Table 3. Command byte
Pointer register bits
Command byte Register
(hexadecimal)
Protocol
Power-up
default
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
0
0
00h
Input port 0
read byte
xxxx xxxx [1]
0
0
0
0
0
0
0
1
01h
Input port 1
read byte
xxxx xxxx
0
0
0
0
0
0
1
0
02h
Output port 0
read/write byte
1111 1111
0
0
0
0
0
0
1
1
03h
Output port 1
read/write byte
1111 1111
0
0
0
0
0
1
0
0
04h
Polarity Inversion port 0
read/write byte
0000 0000
0
0
0
0
0
1
0
1
05h
Polarity Inversion port 1
read/write byte
0000 0000
0
0
0
0
0
1
1
0
06h
Configuration port 0
read/write byte
1111 1111
0
0
0
0
0
1
1
1
07h
Configuration port 1
read/write byte
1111 1111
[1]
The default value ‘X’ is determined by the externally applied logic level.
6.2.2. Input port register pair (00h, 01h)
The Input port registers (registers 0 and 1) reflect the logic levels of the pins, regardless of whether
the pin is defined as an input or an output by the Configuration register. The Input port registers
are read only; writes to these registers have no effect. The default value ‘X’ is determined by the
externally applied logic level. An Input port register read operation is performed as described in
Section 7.2.
Table 4. Input port 0 register (address 00h)
Bit
7
6
5
4
3
2
1
0
Symbol
I0.7
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
Default
X
X
X
X
X
X
X
X
4
3
2
1
0
Table 5. Input port 1 register (address 01h)
Bit
7
6
5
Symbol
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
Default
X
X
X
X
X
X
X
X
6.2.3. Output port register pair (02h, 03h)
The Output port registers (registers 2 and 3) define the outgoing logic levels of the pins defined as
outputs by the Configuration register. Bit values in these registers have no effect on pins defined
as inputs. In turn, reads from these registers reflect the value that was written to these registers,
not the actual pin value. A register pair write is described in Section 7.1 and a register pair read is
described in Section 7.2.
Table 6. Output port 0 register (address 02h)
Bit
7
6
5
4
NCA9539_Q100
Product data sheet
3
2
1
0
Symbol
O0.7
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
O0.0
Default
1
1
1
1
1
1
1
1
Table 7. Output port 1 register (address 03h)
Bit
7
6
5
4
3
2
1
0
Symbol
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
Default
1
1
1
1
1
1
1
1
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NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
6.2.4. Polarity inversion register pair (04h, 05h)
The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs
by the Configuration register. If a bit in these registers is set (written with ‘1’), the corresponding
port pin’s polarity is inverted in the Input register. If a bit in this register is cleared (written with a ‘0’),
the corresponding port pin’s polarity is retained. A register pair write is described in Section 7.1 and
a register pair read is described in Section 7.2.
Table 8. Polarity inversion port 0 register (address 04h)
Bit
7
6
5
4
3
2
1
0
Symbol
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
Default
0
0
0
0
0
0
0
0
Table 9. Polarity inversion port 1 register (address 05h)
Bit
7
6
5
4
3
2
1
0
Symbol
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
Default
0
0
0
0
0
0
0
0
6.2.5. Configuration register pair (06h, 07h)
The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a bit in
these registers is set to 1, the corresponding port pin is enabled as a high-impedance input. If a bit
in these registers is cleared to 0, the corresponding port pin is enabled as an output. A register pair
write is described in Section 7.1 and a register pair read is described in Section 7.2.
Table 10. Configuration port 0 register (address 06h)
Bit
7
6
5
4
Product data sheet
2
1
0
Symbol
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
Default
1
1
1
1
1
1
1
1
3
2
1
0
Table 11. Configuration port 1 register (address 07h)
Bit
7
6
5
4
NCA9539_Q100
3
Symbol
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
Default
1
1
1
1
1
1
1
1
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NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
6.3. I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance
input. The input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output port
register. In this case, there are low-impedance paths between the I/O pin and either VCC or GND.
The external voltage applied to this I/O pin should not exceed the recommended levels for proper
operation.
data from
shift register
output port
register data
configuration
register
data from
shift register
D
VCC
Q1
Q
FF
write configuration
pulse
CK
D
Q
Q
FF
write pulse
P0_0 to P0_7
P1_0 to P1_7
CK
Q2
output port
register
GND
input port
register
D
Q
input port
register data
FF
read pulse
CK
to INT
polarity inversion
register
data from
shift register
D
polarity inversion
register data
Q
FF
write polarity
pulse
CK
aaa-036319
Reset using power-on reset or RESET, all registers return to default values.
Fig. 5.
Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)
6.4. Power-on reset
When power (from 0 V) is applied to VCC and starts rising, an internal power-on reset holds the
NCA9539-Q100 in a reset condition until VCC has reached VPORR. At that time, the reset condition
is released and the NCA9539-Q100 registers and I²C-bus/SMBus state machine initializes to
their default states. After that, VCC must be lowered to below VPORF and back up to the operating
voltage for a power-reset cycle. See Section 8.2.
6.5. RESET input
The RESET pin can be used to reset the registers, state machine and IOs to default values.
By sending active LOW on this pin, the device enters reset state irrespective of the state of the
system. A minimum active low time tw(rst) is required to guarantee the reset functionality. When
RESET is HIGH (1), the I/O levels at the ports can be changed externally or through master.
RESET input requires a pull up resistor to VCC if there is no active connection.
NCA9539_Q100
Product data sheet
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NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
6.6. Interrupt output
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode. After
time tv(INT), the signal INT is valid. The interrupt is reset when data on the port changes back
to the original value or when data is read form the port that generated the interrupt (see Fig. 9
and Fig. 10). Resetting occurs in the Read mode at the acknowledge (ACK) or not acknowledge
(NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK
clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Any
change of the I/Os after resetting is detected and is transmitted as INT.
A pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an
input may cause a false interrupt to occur, if the state of the pin does not match the contents of the
Input Port register.
7. Bus transactions
The NCA9539-Q100 is an I²C-bus slave device. Data is exchanged between the master and
NCA9539-Q100 through write and read commands using I²C-bus. The two communication lines
are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a
positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer
may be initiated only when the bus is not busy.
7.1. Writing to the port registers
Data is transmitted to the NCA9539-Q100 by sending the start condition, device address and
setting the read-write bit to a logic 0 (see Fig. 3). The command byte is sent after the address and
determines which register will receive the data following the command byte.
Eight registers within the NCA9539-Q100 are configured to operate as four register pairs. The four
pairs are input port, output port, polarity inversion, configuration registers. After sending data to
one register, the next data byte is sent to the other register in the pair (see Fig. 6 and Fig. 7). For
example, if the first byte is sent to Output Port 1 (register 3), the next byte is stored in Output Port 0
(register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this way, the
host can continuously update a register pair independently of the other registers, or the host can
simply update a single register.
NCA9539_Q100
Product data sheet
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NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and configuration registers
SCL
1
2
3
4
5
6
7
8
9
slave address
SDA S
1
1
1
0
data to port 0
command byte
1 A1 A0 0
START condition
A
R/W
0
0
0
0
0
0
1
0
acknowledge
from slave
A 0.7
data to port 1
DATA 0
0.0 A 1.7
acknowledge
from slave
DATA 1
1.0 A
acknowledge
from slave
P
STOP
condition
write to port
tv(Q)
data out
from port 0
tv(Q)
data out
from port 1
DATA VALID
aaa-036338
Fig. 6.
Write to output port registers
SCL
1
2
3
4
5
6
7
8
9
slave address
SDA S
1
1
1
0
START condition
command byte
1 A1 A0 0
R/W
A
0
0
0
acknowledge
from slave
0
data to register
0 0/1 0/1 0/1 A
DATA 0
MSB
acknowledge
from slave
STOP
condition
data to register
A
LSB
MSB
acknowledge
from slave
DATA 1
A
P
LSB
acknowledge
from slave
aaa-036339
Fig. 7.
Write to Control registers
NCA9539_Q100
Product data sheet
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NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
7.2. Reading the port registers
In order to read data from the NCA9539-Q100, the bus master must first send the start condition,
NCA9539-Q100 address with the read-write bit set to a logic 0 (see Fig. 3). The command byte
is sent after the address and determines which register will be accessed. After a start or restart,
the device address is sent again, but this time the least significant bit is set to a logic 1. Data from
the register defined by the command byte is sent by the NCA9539-Q100 (see Fig. 8, Fig. 9 and
Fig. 10). Data is clocked into the register on the rising edge of the acknowledge clock pulse. After
the first byte is read, additional bytes may be read but the data now reflects the information in the
other register in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0.
There is no limit on the number of data bytes received in one read transmission, but on the final
byte received the bus master must not acknowledge the data.
After a subsequent start or restart, the command byte contains the value of the next register to be
read in the pair. For example, if Input Port 1 was read last before the restart, the register that is
read after the restart is the Input Port 0.
command byte
slave address
SDA S
1
1
1
0
1 A1 A0 0
START condition
A
0
0
1
1
(cont.)
0 0/1 0/1 0/1 A
acknowledge
from slave
data from lower or
upper byte of register
slave address
1
0
R/W
acknowledge
from slave
(cont.) S
0
0
(repeated)
START condition
MSB
1 A1 A0 1
A
R/W
acknowledge
from slave
data from upper or
lower byte of register
LSB
DATA (first byte)
MSB
A
acknowledge
from master
LSB
DATA (last byte)
NA P
no acknowledge
from master
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
STOP
condition
aaa-036340
Remark: Transfer can be stopped at any time by a STOP condition.
Fig. 8.
Read from register
NCA9539_Q100
Product data sheet
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10 / 31
NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and configuration registers
data into port 0
data into port 1
INT
tv(INT)
SCL
1
2
3
4
trst(INT)
5
6
slave address
SDA S
1
1
1
0
7
8
9
R/W
1 A1 A0 1
START condition
I0.x
A
7
6
acknowledge
from slave
5
4
3
I1.x
2
1
0
A
7
6
5
4
3
I0.x
2
1
0
acknowledge
from master
A
7
6
acknowledge
from master
5
4
3
STOP condition
I1.x
2
1
0
A
7
6
acknowledge
from master
5
4
3
2
1
0
1
P
non acknowledge
from master
read from port 0
read from port 1
aaa-036335
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is
assumed that the command byte has previously been set to '00h' (read input port register).
This figure eliminates the command byte transfer and a restart between the initial slave address call and the actual data transfer from P port (see Fig. 8).
Fig. 9.
Read input port register, scenario 1
NCA9539_Q100
Product data sheet
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Rev. 1 — 31 March 2023
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Nexperia B.V. 2023. All rights reserved
11 / 31
NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and configuration registers
data into port 0
DATA 00
DATA 01
DATA 02
th(D)
data into port 1
DATA 03
tsu(D)
DATA 10
DATA 11
DATA 12
th(D)
tsu(D)
INT
tv(INT)
SCL
1
2
3
trst(INT)
4
5
6
slave address
SDA S
1
1
1
0
7
8
9
R/W
1 A1 A0 1
START condition
I0.x
A
acknowledge
from slave
DATA 00
I1.x
A
DATA 10
acknowledge
from master
I0.x
A
acknowledge
from master
DATA 03
I1.x
A
acknowledge
from master
STOP condition
DATA 12
1
P
non acknowledge
from master
read from port 0
read from port 1
aaa-036341
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is
assumed that the command byte has previously been set to '00h' (read input port register).
This figure eliminates the command byte transfer and a restart between the initial slave address call and the actual data transfer from P port (see Fig. 8).
Fig. 10. Read input port register, scenario 2
NCA9539_Q100
Product data sheet
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Rev. 1 — 31 March 2023
©
Nexperia B.V. 2023. All rights reserved
12 / 31
NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
8. Application design-in information
VCC
(3.3 V)
10 k
VCC
10 k
10 k
MASTER
CONTROLLER
2k
VCC
10 k
SCL
SCL
P0_0
SDA
P0_1
INT
INT
NCA9539
SDA
INT
RESET
SUB-SYSTEM 1(1)
(e.g., temp sensor)
100 k
(×3)
RESET
GND
SUB-SYSTEM 2
(e.g., counter)
P0_2
RESET
P0_3
A
P0_4
controlled
switch
(e.g., CBT device)
enable
P0_5
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
A1
A0
B
SUB-SYSTEM 3(1)
(e.g., alarm system)
10 DIGIT
NUMERIC
KEYPAD
ALARM
GND
GND
aaa-036343
Device address configured as 1110 100X for this example.
P0_0, P0_2, P0_3 configured as outputs.
P0_1, P0_4, P0_5 configured as inputs.
P0_6, P0_7 and (P1_0 to P1_7) configured as inputs.
(1) External pull-up and pull-down resistors are required for inputs IO P ports that may float. If a driver to an input
will never let the input float, a resistor is not needed. If an output in the P port is configured as a push-pull output
there is no need for external pull-up resistors. If an output in the P port is configured as an open-drain output,
external pull-up resistors are required.
Fig. 11. Typical application
8.1. Minimizing ICC when the I/Os are used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VCC through a resistor as
shown in Fig. 11. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less
than VCC. The supply current, ICC, increases as VI becomes lower than VCC.
Designs needing to minimize current consumption, such as battery power applications, should
consider maintaining the I/O pins greater than or equal to VCC when the LED is off. Fig. 12 shows a
high value resistor in parallel with the LED. Fig. 13 shows VCC less than the LED supply voltage by
at least 1.2 V. Both of these methods maintain the I/O VI at or above VCC and prevents additional
supply current consumption when the LED is off.
NCA9539_Q100
Product data sheet
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Rev. 1 — 31 March 2023
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Nexperia B.V. 2023. All rights reserved
13 / 31
NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
VCC
VCC
LED
3.3 V
5V
100 k
VCC
LED
Pn
Pn
aaa-035816
Fig. 12. High value resistor in parallel with
the LED
aaa-035817
Fig. 13. Device supplied by a lower voltage
8.2. Power-on reset requirements
In the event of a glitch or data corruption, NCA9539-Q100 can be reset to its default conditions by
using the power-on reset feature. Power-on reset requires that the device go through a power cycle
to be completely reset. This reset also happens when the device is powered on for the first time in
an application.
The two types of power-on reset are shown in Fig. 14 and Fig. 15.
VCC
ramp-up
ramp-down
re-ramp-up
td(rst)
trise(VCC)
tfall(VCC)
time to re-ramp
when VCC drops
below 0.2 V or to GND
time
trise(VCC)
aaa-035819
Fig. 14. VCC is lowered below 0.2 V or to 0 V and then ramped up to VCC
VCC
ramp-down
ramp-up
td(rst)
VI drops below POR levels
tfall(VCC)
time to re-ramp
when VCC drops
to VPORF(min) - 50 mV
time
trise(VCC)
aaa-035820
Fig. 15. VCC is lowered below the POR threshold, then ramped back up to VCC
Table 12 specifies the performance of the power-on reset feature for NCA9539-Q100 for both types
of power-on reset.
NCA9539_Q100
Product data sheet
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Rev. 1 — 31 March 2023
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Nexperia B.V. 2023. All rights reserved
14 / 31
NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
Table 12. Recommended supply sequencing and ramp rates
Tamb = 25 °C (unless otherwise noted). Not tested; specified by design.
Symbol
Parameter
Condition
Min
Typ
Max
trise(VCC)
supply ramp up time
see Fig. 14
0.1
-
2000
ms
tfall(VCC)
supply ramp down time
see Fig. 14
0.1
-
2000
ms
td(rst)
reset delay time
see Fig. 14; re-ramp time when VCC drops
below 0.2 V or to GND
1
-
-
µs
see Fig. 15; re-ramp time when VCC drops to
VPOR(min) - 50 mV
1
-
-
µs
-
-
1
V
1.5
-
-
V
-
-
10
μs
ΔVCC(gl)
Tamb = 25 °C
glitch supply voltage difference see Fig. 16
VCC_MIN(gl) minimum glitch supply voltage
minimum voltage that VCC can glitch down
to, but not cause functional disruption when
tw(gl)VCC ; see Fig. 16
tw(gl)VCC
see Fig. 16
supply voltage glitch pulse
width
Unit
Glitches in the power supply can also affect the power-on reset performance of this device. The
glitch width (tw(gl)VCC ) and glitch height (ΔVCC(gl)) are dependent on each other. The glitch on
power supply should never go below VCC_MIN(gl) in order to properly guarantee functionality. The
bypass capacitance, source impedance, and device impedance are factors that affect poweron reset performance. Fig. 16 and Table 12 provide more information on how to measure these
specification.
VCC
VCC(gl)
VCC_MIN(gl)
time
tw(gl)VCC
aaa-035821
Fig. 16. Glitch width and glitch height
VPORR and VPORF are critical to the power-on reset. VPORR is the voltage level of VCC at which the
reset condition is released and all the registers and the I²C-bus/SMBus state machine are initialized
to their default states. VPORF is the voltage level of VCC below which NCA9539-Q100 enters reset
state. Fig. 17 and Table 12 provide more details on this specification.
VCC
VPORR (rising VCC)
VPORF (falling VCC)
time
POR
time
aaa-035822
Fig. 17. Power-on reset voltage (VPOR)
NCA9539_Q100
Product data sheet
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Nexperia B.V. 2023. All rights reserved
15 / 31
NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
9. Limiting values
Table 13. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VCC
supply voltage
VI
input voltage
VO
output voltage
IIK
input clamping current
A0, A1, RESET, SCL; VI < 0 V
IOK
output clamping current
IIOK
input/output clamping current
IOL
Conditions
LOW-level output current
Min
Max
Unit
-0.5
6
V
[1]
-0.5
6
V
[1]
-0.5
6
V
-
-20
mA
INT; VO < 0 V
-
-20
mA
P port; VO < 0 V or VO > VCC
-
±20
mA
SDA; VO < 0 V
-
-20
mA
continuous; I/O port
-
50
mA
continuous; SDA, INT
-
25
mA
continuous; P port
-
25
mA
IOH
HIGH-level output current
ICC
supply current
-
160
mA
IGND
ground supply current
-
250
mA
Ptot
total power dissipation
Tstg
storage temperature
Tj(max)
maximum junction temperature
Tamb
ambient temperature
[1]
operating in free air
-
200
mW
-65
+150
°C
-
135
°C
-40
+125
°C
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
10. Recommended operating conditions
Table 14. Operating conditions
Symbol
Parameter
VCC
supply voltage
VIH
HIGH-level input voltage
VIL
Conditions
LOW-level input voltage
Min
Max
Unit
1.65
5.5
V
SCL, SDA
0.7 × VCC
5.5
V
P1_7 to P0_0
0.7 × VCC
5.5
V
A0, A1, RESET
0.7 × VCC
VCC
V
SCL, SDA
-0.5
0.3 × VCC
V
A0, A1, RESET, P1_7 to P0_0
-0.5
0.3 × VCC
V
IOH
HIGH-level output current
P1_7 to P0_0
-
10
mA
IOL
LOW-level output current
P1_7 to P0_0
-
25
mA
11. Thermal characteristics
Table 15. Thermal characteristics
Symbol
Parameter
Conditions
Zth(j-a)
TSSOP24 package
[1]
transient thermal impedance from junction to ambient
[1]
Max
Unit
100
K/W
The package thermal impedance is calculated in accordance with JESD 51-7.
NCA9539_Q100
Product data sheet
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16 / 31
NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
12. Static characteristics
Table 16. Static characteristics
VCC = 1.65 V to 5.5 V; unless otherwise specified.
Symbol
Parameter
Conditions
Tamb = -40 °C
to +125 °C
Unit
Min
Typ
[1]
Max
VIK
input clamping voltage
II = -18 mA
-1.2
-
-
V
VPORF
power-on reset trip voltage;
VCC falling
VI = VCC or GND; IO = 0 mA
0.8
1.1
-
V
VPORR
power-on reset trip voltage;
VCC rising
VI = VCC or GND; IO = 0 mA
-
1.25
1.6
V
IOL
LOW-level output current
VOL = 0.4 V; VCC = 1.65 V to 5.5 V
SDA
3
-
-
mA
INT
3
28 [2]
-
mA
P port
VOH
VOL
II
HIGH-level output voltage
LOW-level output voltage
input current
VOL = 0.5 V; VCC = 1.65 V
[3]
8
-
-
mA
VOL = 0.7 V; VCC = 1.65 V
[3]
9
-
-
mA
VOL = 0.5 V; VCC = 2.3 V
[3]
8
-
-
mA
VOL = 0.7 V; VCC = 2.3 V
[3]
10
-
-
mA
VOL = 0.5 V; VCC = 3.0 V
[3]
8
-
-
mA
VOL = 0.7 V; VCC = 3.0 V
[3]
10
-
-
mA
VOL = 0.5 V; VCC = 4.5 V
[3]
8
-
-
mA
VOL = 0.7 V; VCC = 4.5 V
[3]
10
-
-
mA
IOH = -8 mA; VCC = 1.65 V
[4]
1.2
-
-
V
IOH = -10 mA; VCC = 1.65 V
[4] 1.05
-
-
V
IOH = -8 mA; VCC = 2.3 V
[4]
2.0
-
-
V
IOH = -10 mA; VCC = 2.3 V
[4]
1.9
-
-
V
IOH = -8 mA; VCC = 3.0 V
[4]
2.6
-
-
V
IOH = -10 mA; VCC = 3.0 V
[4]
2.5
-
-
V
IOH = -8 mA; VCC = 4.5 V
[4]
4.1
-
-
V
IOH = -10 mA; VCC = 4.5 V
[4]
4.0
-
-
V
VCC = 1.65 V
-
-
0.45 V
VCC = 2.3 V
-
-
0.30 V
VCC = 3.0 V
-
-
0.25 V
VCC = 4.5 V
-
-
0.2
V
SCL, SDA; VI = VCC or GND
-
-
1
μA
A0, A1, RESET; VI = VCC or GND
-
-
±1
μA
P port
P port; IOL = 8 mA
VCC = 1.65 V to 5.5 V
IIH
HIGH-level input current
P port; VI = VCC; VCC = 1.65 V to 5.5 V
-
-
1
μA
IIL
LOW-level input current
P port; VI = GND; VCC = 1.65 V to 5.5 V
-
-
-1
μA
NCA9539_Q100
Product data sheet
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Nexperia B.V. 2023. All rights reserved
17 / 31
NCA9539-Q100
Nexperia
Symbol
ICC
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
Parameter
supply current
Conditions
Tamb = -40 °C
to +125 °C
Unit
Min
Typ
[1]
Max
VCC = 3.6 V to 5.5 V
-
13
29
μA
VCC = 2.3 V to 3.6 V
-
6.4
12
μA
VCC = 1.65 V to 2.3 V
-
3
6.5
μA
VCC = 3.6 V to 5.5 V
-
1.5
4
μA
VCC = 2.3 V to 3.6 V
-
0.95
3
μA
VCC = 1.65 V to 2.3 V
-
0.5
2
μA
VCC = 3.6 V to 5.5 V
-
15
60
μA
VCC = 2.3 V to 3.6 V
-
7.4
27
μA
VCC = 1.65 V to 2.3 V
-
3.5
11
μA
SCL, SDA; one input at VCC - 0.6 V, other
inputs at VCC or GND; VCC = 1.65 V to 5.5 V
-
-
10
μA
P port, A0, A1, RESET;
one input at VCC - 0.6 V, other inputs at
VCC or GND; VCC = 1.65 V to 5.5 V
-
-
18
μA
SDA, P port, A0, A1, RESET;
VI on SDA = VCC or GND;
VI on P port and A0, A1, RESET = VCC;
IO = 0 mA; I/O = inputs; fSCL = 400 kHz
(tr = 30 ns)
SCL, SDA, P port, A0, A1, RESET;
VI on SCL, SDA = VCC or GND;
VI on P port and A0, A1, RESET = VCC;
IO = 0 mA; I/O = inputs; fSCL = 0 kHz
Active mode; P port, A0, A1, RESET;
VI on P port, A0, A1, RESET = VCC;
IO = 0 mA; I/O = inputs;
fSCL = 400 kHz (tr = 30 ns), continuous
register read
ΔICC
additional quiescent supply
current
Ci
input capacitance
VI = VCC or GND; VCC = 1.65 V to 5.5 V
-
1.5
3.5
pF
Cio
input/output capacitance
VI/O = VCC or GND; VD = 1.65 V to 5.5 V
-
3
5
pF
[1]
[2]
[3]
[4]
For ICC, all typical values are at nominal supply voltage (1.8 V, 3.3 V or 5 V VCC) and Tamb = 25 °C. Except for ICC, the typical values
are at VCC = 3.3 V and Tamb = 25 °C.
Typical value for Tamb = 25 °C. VOL = 0.4 V and VCC = 3.3 V.
Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 200 mA.
The total current sourced by all I/Os must be limited to 160 mA.
NCA9539_Q100
Product data sheet
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Nexperia B.V. 2023. All rights reserved
18 / 31
NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
12.1. Typical characteristics
ICC
(µA)
aaa-035957
25
ICC
(μA)
20
aaa-035958
2
(8)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
1.5
15
(8)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
10
1
0.5
5
0
-40
-10
20
50
80
110
Tamb (°C)
0
-40
140
fSCL = 400 kHz
(1) VCC = 1.65 V
(2) VCC = 1.8 V
(3) VCC = 2.3 V
(4) VCC = 2.5 V
(5) VCC = 3.3 V
(6) VCC = 3.6 V
(7) VCC = 5.0 V
(8) VCC = 5.5 V
-10
20
50
80
110
Tamb (°C)
140
(1) VCC = 1.65 V
(2) VCC = 1.8 V
(3) VCC = 2.3 V
(4) VCC = 2.5 V
(5) VCC = 3.3 V
(6) VCC = 3.6 V
(7) VCC = 5.0 V
(8) VCC = 5.5 V
Fig. 19. Standby supply current versus ambient
temperature
Fig. 18. Supply current versus ambient temperature
ICC
(μA)
aaa-035959
25
20
15
10
5
0
1.5
2
2.5
3
3.5
4
4.5
5
VCC (V)
5.5
Tamb = 25 °C; fSCL = 400 kHz
Fig. 20. Supply current versus supply voltage
NCA9539_Q100
Product data sheet
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©
Nexperia B.V. 2023. All rights reserved
19 / 31
NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
Isink
(mA)
aaa-035961
25
Isink
(mA)
20
20
(1)
(2)
(3)
(4)
15
10
5
5
0
0.05
0.1
0.15
0.2
0.25
0.3 0.35
VOL (V)
40
Isink
(mA)
(1)
(2)
(3)
(4)
10
10
0.05
0.1
0.15
0.2
0.25
0.3 0.35
VOL (V)
0
0.4
c. VCC = 2.5 V
aaa-035965
Isink
(mA)
40
30
0.3 0.35
VOL (V)
0.4
(1)
(2)
(3)
(4)
0
0.05
0.1
0.15
0.2
0.25
0.3 0.35
VOL (V)
0.4
10
10
0.15
0.2
aaa-035966
(1)
(2)
(3)
(4)
30
20
0.1
0.25
50
20
0.05
0.2
aaa-035964
40
(1)
(2)
(3)
(4)
0
0.15
d. VCC = 3.3 V
50
0
0.1
30
20
0
0.05
40
20
0
0
b. VCC = 1.8 V
aaa-035963
30
Isink
(mA)
0
0.4
a. VCC = 1.65 V
Isink
(mA)
(1)
(2)
(3)
(4)
15
10
0
aaa-035962
25
0.25
0.3 0.35
VOL (V)
0
0.4
e. VCC = 5.0 V
0
0.05
0.1
0.15
0.2
0.25
0.3 0.35
VOL (V)
0.4
f. VCC = 5.5 V
(1) Tamb = -40 °C
(2) Tamb = 25 °C
(3) Tamb = 85 °C
(4) Tamb = 125 °C
Fig. 21. I/O sink current versus LOW-level output voltage
NCA9539_Q100
Product data sheet
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©
Nexperia B.V. 2023. All rights reserved
20 / 31
NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
aaa-035967
30
Isource
(mA)
25
(1)
(2)
(3)
(4)
20
aaa-035968
40
Isource
(mA)
(1)
(2)
(3)
(4)
30
15
20
10
10
5
0
0
0.1
0.2
0.3
0.4
0.5
VCC - VOH (V)
0
0.6
a. VCC = 1.65 V
0
0.1
0.2
0.3
0.4
0.5
VCC - VOH (V)
0.6
b. VCC = 1.8 V
aaa-035969
50
Isource
(mA)
aaa-035970
60
Isource
(mA)
50
40
(1)
(2)
(3)
(4)
30
(1)
(2)
(3)
(4)
40
30
20
20
10
0
10
0
0.1
0.2
0.3
0.4
0.5
VCC - VOH (V)
0
0.6
c. VCC = 2.5 V
aaa-035971
(1)
(2)
(3)
(4)
60
0.3
0.4
0.5
VCC - VOH (V)
0.6
20
20
0.2
0.3
aaa-035972
(1)
(2)
(3)
(4)
60
40
0.1
0.2
80
Isource
(mA)
40
0
0.1
d. VCC = 3.3 V
80
Isource
(mA)
0
0
0.4
0.5
VCC - VOH (V)
0
0.6
e. VCC = 5.0 V
0
0.1
0.2
0.3
0.4
0.5
VCC - VOH (V)
0.6
f. VCC = 5.5 V
(1) Tamb = -40 °C
(2) Tamb = 25 °C
(3) Tamb = 85 °C
(4) Tamb = 125 °C
Fig. 22. I/O source current versus HIGH-level output voltage
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Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
aaa-035973
250
VOL
(mV)
aaa-035974
300
VCC - VOH
(mV)
250
200
200
150
(1)
(2)
(3)
(4)
100
(1)
(3)
(2)
(4)
150
100
50
0
-40
50
-10
20
50
80
110
Tamb (°C)
0
-40
140
(1) VCC = 1.8 V; Isink = 10 mA
(2) VCC = 5 V; Isink = 10 mA
(3) VCC = 1.8 V; Isink = 1 mA
(4) VCC = 5 V; Isink = 1 mA
-10
20
50
80
110
Tamb (°C)
140
(1) VCC = 1.8 V; Isource = -10 mA
(2) VCC = 5 V; Isource = -10 mA
(3) VCC = 1.8 V; Isource = -1 mA
(4) VCC = 5 V; Isource = -1 mA
Fig. 23. LOW-level output voltage versus temperature
Fig. 24. I/O high voltage versus temperature
13. Dynamic characteristics
Table 17. I²C-bus interface timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Fig. 25.
Symbol Parameter
Conditions
Standard-mode
I²C-bus
Fast-mode
I²C-bus
Unit
Min
Max
Min
Max
0
100
0
400
fSCL
SCL clock frequency
tHIGH
HIGH period of the SCL clock
4
-
0.6
-
μs
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
μs
tSP
pulse width of spikes that must
be suppressed by the input filter
0
50
0
50
ns
tSU;DAT
data set-up time
250
-
100
-
ns
tHD;DAT
data hold time
0
-
0
-
ns
tr
rise time of both SDA and SCL signals
-
1000
20
300
ns
tf
fall time of both SDA and SCL signals
-
300
20 ×
(VCC/5.5 V)
300
ns
tBUF
bus free time between a STOP and
START condition
4.7
-
1.3
-
μs
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
μs
tHD;STA
hold time (repeated) START condition
4
-
0.6
-
μs
tSU;STO
set-up time for STOP condition
4
-
0.6
-
μs
tVD;DAT
data valid time
SCL LOW to SDA
output valid
-
3.45
-
0.9
μs
tVD;ACK
data valid acknowledge time
ACK signal from
SCL LOW to SDA
(out) LOW
-
3.45
-
0.9
μs
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Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
Table 18. Reset timing requirements
Over recommended operating free air temperature range; CL ≤ 100 pF; unless otherwise specified. See Fig. 28.
Symbol
Parameter
Conditions
Standard-mode
I²C-bus
Fast-mode
I²C-bus
Min
Max
Min
Max
Unit
tw(rst)
reset pulse width
6
-
6
-
ns
trec(rst)
reset recovery time
0
-
0
-
ns
trst
reset time
550
-
550
-
ns
[1]
[1]
Minimum time for SDA to become HIGH or minimum time to wait before doing a START.
Table 19. Switching characteristics
Over recommended operating free air temperature range; CL ≤ 100 pF; unless otherwise specified. See Fig. 26 and Fig. 27.
Symbol
Parameter
Conditions
Standard-mode
I²C-bus
Fast-mode
I²C-bus
Min
Max
Min
Max
Unit
tv(INT)
valid time on pin INT
from P port to INT
-
1
-
1
μs
trst(INT)
reset time on pin INT
from SCL to INT
-
1
-
1
μs
tv(Q)
data output valid time
from SCL to P port
-
300
-
300
ns
tsu(D)
data input set-up time
from P port to SCL
-50
-
-50
-
ns
th(D)
data input hold time
from P port to SCL
240
-
240
-
ns
NCA9539_Q100
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NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
14. Parameter measurement information
VCC
RL = 1 k
DUT
SDA
CL = 50 pF
aaa-035847
a. SDA load configuration
two bytes for read Input port register(1)
STOP
START
condition condition
(P)
(S)
Address
Bit 7
(MSB)
Address
Bit 1
R/W
Bit 0
(LSB)
Data
Bit 7
(MSB)
ACK
(A)
Data
Bit 0
(LSB)
STOP
condition
(P)
002aag952
b. Transaction format
tHIGH
tLOW
tSP
0.7 × VCC
0.3 × VCC
SCL
tBUF
tr
tVD;DAT
tf
tf(o)
tVD;ACK
tSU;STO
tSU;STA
0.7 × VCC
SDA
tf
tHD;STA
tr
tSU;DAT
tHD;DAT
0.3 × VCC
tVD;ACK
repeat START condition
STOP condition
aaa-035843
c. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω;
tr/tf ≤ 30 ns.
All parameters and waveforms are not applicable to all devices.
Byte 1 = I²C-bus address; Byte 2, byte 3 = P port data.
(1) See Fig. 8.
Fig. 25. I²C-bus interface load circuit and voltage waveforms
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Product data sheet
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NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
VCC
RL = 4.7 k
INT
DUT
CL = 100 pF
aaa-035848
a. Interrupt load configuration
acknowledge
from slave
START condition
R/W
8 bits (one data byte)
from port
slave address
SDA S
SCL
1
1
1
1
2
3
0
4
1 A1 A0 1
5
6
7
8
acknowledge
from slave
A
DATA 1
no acknowledge
from master
STOP
condition
data from port
A
DATA 2
1
P
9
B
trst(INT) B
trst(INT)
INT
tv(INT)
data into
port
A
A
tsu(D)
ADDRESS
INT
DATA 1
SCL
0.5 × VCC
DATA 2
R/W
tv(INT)
0.3 × VCC
trst(INT)
0.5 × VCC
Pn
0.7 × VCC
A
0.5 × VCC
INT
View A - A
View B - B
aaa-036344
b. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω;
tr/tf ≤ 30 ns.
All parameters and waveforms are not applicable to all devices.
Fig. 26. Interrupt load circuit and voltage waveforms
NCA9539_Q100
Product data sheet
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25 / 31
NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
500
Pn
DUT
CL = 50 pF
2 × VCC
500
aaa-036323
a. P port load configuration
SCL
P0
A
P7
0.7 × VCC
0.3 × VCC
SDA
tv(Q)
Pn
unstable
data
last stable bit
A
P7
aaa-035845
b. Write mode (R/W = 0)
SCL
P0
tsu(D)
0.7 × VCC
0.3 × VCC
th(D)
Pn
aaa-035846
c. Read mode (R/W = 1)
CL includes probe and jig capacitance.
tv(Q) is measured from 0.7 × VCC on SCL to 50 % I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω;
tr/tf ≤ 30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Fig. 27. P port load circuit and voltage waveforms
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Product data sheet
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26 / 31
NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
VCC
RL = 1 k
DUT
SDA
500
Pn
DUT
CL = 50 pF
CL = 50 pF
aaa-036323
aaa-035847
a. SDA load configuration
SCL
2 × VCC
500
b. P port load configuration
START
ACK or read cycle
SDA
0.3 × VCC
trst
0.5 × VCC
RESET
trec(rst)
tw(rst)
trst
0.5 × VCC
Pn
aaa-036345
c. RESET timing:
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω;
tr/tf ≤ 30 ns.
The outputs are measured one at a time, with one transition per measurement.
I/Os are configured as inputs.
All parameters and waveforms are not applicable to all devices.
Fig. 28. Reset load circuits and voltage waveforms
NCA9539_Q100
Product data sheet
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27 / 31
NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
15. Package outline
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
D
SOT355-1
E
A
X
c
HE
y
v M A
Z
13
24
Q
A2
pin 1 index
(A 3 )
A1
A
θ
Lp
1
L
12
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT355-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig. 29. Package outline SOT355-1 (TSSOP24)
NCA9539_Q100
Product data sheet
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NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
16. Abbreviations
Table 20. Abbreviations
Acronym
Description
ACPI
Advanced Configuration and Power Interface
CBT
Cross-Bar Technology
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
ESD
ElectroStatic Discharge
FET
Field-Effect Transistor
FF
Flip-Flop
GPIO
General Purpose Input/Output
HBM
Human Body Model
I²C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
LED
Light Emitting Diode
SMBus
System Management Bus
17. Revision history
Table 21. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
NCA9539_Q100 v 1
Product data sheet
-
-
NCA9539_Q100
Product data sheet
20230331
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NCA9539-Q100
Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
18. Legal information
Data sheet status
Document status
[1][2]
Product
status [3]
Definition
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification
This document contains data from
the preliminary specification.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Product [short]
data sheet
Production
This document contains the product
specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or
completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Draft — The document is a draft version only. The content is still under
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warranties as to the accuracy or completeness of information included herein
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
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Nexperia
Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and
configuration registers
Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Block diagram...............................................................2
5. Pinning information......................................................3
5.1. Pinning.........................................................................3
5.2. Pin description............................................................. 3
6. Functional description................................................. 4
6.1. Device address............................................................4
6.2. Registers......................................................................4
6.2.1. Pointer register and command byte..........................4
6.2.2. Input port register pair (00h, 01h)............................. 5
6.2.3. Output port register pair (02h, 03h).......................... 5
6.2.4. Polarity inversion register pair (04h, 05h)................. 6
6.2.5. Configuration register pair (06h, 07h)....................... 6
6.3. I/O port........................................................................ 7
6.4. Power-on reset............................................................ 7
6.5.
RESET input.............................................................. 7
6.6. Interrupt output............................................................ 8
7. Bus transactions.......................................................... 8
7.1. Writing to the port registers......................................... 8
7.2. Reading the port registers......................................... 10
8. Application design-in information.............................13
8.1. Minimizing ICC when the I/Os are used to control
LEDs................................................................................... 13
8.2. Power-on reset requirements.................................... 14
9. Limiting values........................................................... 16
10. Recommended operating conditions......................16
11. Thermal characteristics............................................16
12. Static characteristics................................................17
12.1. Typical characteristics..............................................19
13. Dynamic characteristics.......................................... 22
14. Parameter measurement information..................... 24
15. Package outline........................................................ 28
16. Abbreviations............................................................ 29
17. Revision history........................................................29
18. Legal information......................................................30
©
Nexperia B.V. 2023. All rights reserved
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For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 31 March 2023
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