O322525MEDH4MI

【晶振全系列独立与授权型供应商-深圳扬兴科技有限公司】 www.yxc.hk YSO8008MR Features: F  Low Power Programmable Oscillator  Any frequency between 1 MHz and 110 MHz accurate to 6 decimal places  100% pin-to-pin drop-in replacement to quartz-based XO  Operating temperature from -40°C to 85°C.  Low power consumption of 3.5 mA typical at 1.8V  Standby mode for longer battery life, fast startup time of 5 ms  LVCMOS/HCMOS compatible output  Industry-standard packages: 2.0 x 1.6, 2.5 x 2.0, 3.2 x 2.5, 5.0 x 3.2, 7.0 x 5.0 mm x mm F Applications:  Ideal for DSC, DVC, DVR, IP CAM, Tablets, e-Books, SSD, GPON, EPON, etc  Ideal for high-speed serial protocols such as: USB, SATA, SAS, Firewire, 100M / 1G / 10G Ethernet, etc. Electrical Specifications Table 1. Electrical Characteristics All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise stated. Typical values are at 25°C and nominal supply voltage. Parameters Symbol Min. Typ. Max. Unit Condition Frequency Range Output Frequency Range f 1 – 110 MHz Frequency Stability and Aging Frequency Stability F_stab -20 – +20 ppm -25 – +25 ppm – +50 ppm -50 Inclusive of initial tolerance at 25°C, 1st year aging at 25°C, and variations over operating temperature, rated power supply voltage and load. Operating Temperature Range Operating Temperature Range T_use -20 – +70 °C Extended Commercial -40 – +85 °C Industrial Supply Voltage and Current Consumption Supply Voltage Current Consumption OE Disable Current Standby Current Vdd Idd I_OD I_std 1.62 1.8 1.98 V 2.25 2.5 2.75 V 2.52 2.8 3.08 V 2.7 3.0 3.3 V 2.97 3.3 3.63 V 2.25 – 3.63 V – 3.8 4.5 mA No load condition, f = 20 MHz, Vdd = 2.8V to 3.3V – 3.7 4.2 mA No load condition, f = 20 MHz, Vdd = 2.5V – 3.5 4.1 mA No load condition, f = 20 MHz, Vdd = 1.8V – – 4.2 mA Vdd = 2.5V to 3.3V, OE = GND, Output in high-Z state – – 4.0 mA Vdd = 1.8V, OE = GND, Output in high-Z state – 2.1 4.3 A ST = GND, Vdd = 2.8V to 3.3V, Output is weakly pulled down – 1.1 2.5 A ST = GND, Vdd = 2.5V, Output is weakly pulled down – 0.2 1.3 A ST = GND, Vdd = 1.8V, Output is weakly pulled down LVCMOS Output Characteristics Duty Cycle Rise/Fall Time DC 45 – 55 % All Vdds. See Duty Cycle definition in Figure 3 and Footnote 8 Tr, Tf – 1 2 ns Vdd = 2.5V, 2.8V, 3.0V or 3.3V, 20% - 80% – 1.3 2.5 ns Vdd =1.8V, 20% - 80% – – 2 ns Vdd = 2.25V - 3.63V, 20% - 80% Output High Voltage VOH 90% – – Vdd IOH = -4 mA (Vdd = 3.0V or 3.3V) IOH = -3 mA (Vdd = 2.8V and Vdd = 2.5V) IOH = -2 mA (Vdd = 1.8V) Output Low Voltage VOL – – 10% Vdd IOL = 4 mA (Vdd = 3.0V or 3.3V) IOL = 3 mA (Vdd = 2.8V and Vdd = 2.5V) IOL = 2 mA (Vdd = 1.8V) come visit our site http://www.yxc.hk 1/9 【晶振全系列独立与授权型供应商-深圳扬兴科技有限公司】 www.yxc.hk YSO8008MR Table 1. Electrical Characteristics (continued) Parameters Symbol Min. Typ. Max. Unit Condition Input Characteristics Input High Voltage VIH 70% – – Vdd Input Low Voltage VIL – – 30% Vdd Pin 1, OE or ST Input Pull-up Impedance Z_in 50 87 150 k Pin 1, OE logic high or logic low, or ST logic high – – M Pin 1, ST logic low 2 Pin 1, OE or ST Startup and Resume Timing Startup Time T_start – – 5 ms T_oe – – 130 ns f = 110 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles T_resume – – 5 ms Measured from the time ST pin crosses 50% threshold T_jitt – 1.8 3 ps f = 75 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V – 1.8 3 ps f = 75 MHz, Vdd = 1.8V 12 25 ps f = 75 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V Enable/Disable Time Resume Time Measured from the time Vdd reaches its rated minimum value Jitter RMS Period Jitter Peak-to-peak Period Jitter T_pk – – 14 30 ps f = 75 MHz, Vdd = 1.8V RMS Phase Jitter (random) T_phj – 0.5 0.9 ps f = 75 MHz, Integration bandwidth = 900 kHz to 7.5 MHz – 1.3 2 ps f = 75 MHz, Integration bandwidth = 12 kHz to 20 MHz Table 2. Pin Description Pin 1 Symbol OE/ ST/NC H[1]: specified frequency output L: output is high impedance. Only output driver is disabled. Standby H[1]: specified frequency output L: output is low (weak pull down). Device goes to sleep mode. Supply current reduces to I_std. No Connect 2 Top View Functionality Output Enable Any voltage between 0 and Vdd or Open[1]: Specified frequency output. Pin 1 has no function. GND Power 3 OUT Output Oscillator output 4 VDD Power Power supply voltage[2] OE/ST/NC 1 4 VDD GND 2 3 OUT Electrical ground Figure 1. Pin Assignments Notes: 1. In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use the NC option. 2. A capacitor of value 0.1 µF or higher between Vdd and GND is required. Dimensions and Patterns Package Size – Dimensions (Unit: mm)[3] Recommended Land Pattern (Unit: mm)[4] 2.0 x 1.6 x 0.75 mm come visit our site http://www.yxc.hk 2/9 【晶振全系列独立与授权型供应商-深圳扬兴科技有限公司】 www.yxc.hk YSO8008MR Dimensions and Patterns Package Size – Dimensions (Unit: mm)[3] Recommended Land Pattern (Unit: mm)[4] 2.5 x 2.0 x 0.75 mm 2.5 ± 0.05 #3 #2 #2 1.5 1.9 #1 1.0 1.2 #1 0.5 YXXXX 1.9 2.2 #4 1.1 YXC 100.000 1.00 #3 2.0 ± 0.05 #4 0.75 ± 0.05 0.75 1.4 1.1 3.2 x 2.5 x 0.75 mm 3.2 ± 0.05 2.1 #3 #3 #2 #1 0.9 0.75 ± 0.05 #2 1.2 #1 1.9 YXXXX 0.7 YXC 100.000 2.2 #4 0.9 2.5 ± 0.05 #4 1.4 5.0 x 3.2 x 0.75 mm 2.54 5.0 ± 0.05 #3 #2 #1 1.6 #2 0.75 ± 0.05 #1 2.2 YXXXX #4 1.1 3.2 ± 0.05 YXC 100.000 #3 0.8 #4 2.39 1.15 1.5 7.0 x 5.0 x 0.90 mm 5.08 0.90 ± 0.10 3.81 2.0 1.1 YXXXX 5.08 2.6 YXC 100.000 5.0 ± 0.05 7.0 ± 0.05 1.4 2.2 Notes: 3. Top marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of the device. 4. A capacitor of value 0.1 µF or higher between Vdd and GND is required. Dimensions Frequency Supply voltage (V) (Hz) Frequency Stability Output Overall (ppm) come visit our site http://www.yxc.hk 3/9 Pin Material Operating Temp. Range 【晶振全系列独立与授权型供应商-深圳扬兴科技有限公司】 www.yxc.hk YSO8008MR N Table 3. Absolute Maximum Limits Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings. Min. Max. Unit Storage Temperature Parameter -65 150 °C Vdd -0.5 4 V Electrostatic Discharge – 2000 V Soldering Temperature (follow standard Pb free soldering guidelines) – 260 °C Junction Temperature[5] – 150 °C Note: 5. Exceeding this temperature for extended period of time may damage the device. Table 4. Thermal Consideration[6] JA, 4 Layer Board JA, 2 Layer Board JC, Bottom 7050 142 273 30 5032 97 199 24 3225 109 212 27 Package (°C/W) (°C/W) (°C/W) 2520 117 222 26 2016 152 252 36 Note: 6. Refer to JESD51 for JA and JC definitions, and reference layout used to determine the JA and JC values in the above table. Table 5. Maximum Operating Junction Temperature[7] Max Operating Temperature (ambient) Maximum Operating Junction Temperature 70°C 80°C 85°C 95°C Note: 7. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature. Table 6. Environmental Compliance Condition/Test Method Parameter Mechanical Shock MIL-STD-883F, Method 2002 Mechanical Vibration MIL-STD-883F, Method 2007 Temperature Cycle JESD22, Method A104 Solderability MIL-STD-883F, Method 2003 Moisture Sensitivity Level MSL1 @ 260°C come visit our site http://www.yxc.hk 4/9 【晶振全系列独立与授权型供应商-深圳扬兴科技有限公司】 www.yxc.hk YSO8008MR Test Circuit and Waveform[8] Vdd Vout 0.1µF tr 3 4 Power Supply Test Point 1 tf 80% Vdd 50% 15pF (including probe and fixture capacitance) 2 20% Vdd High Pulse (TH) Low Pulse (TL) Period Vdd 1k OE/ST Function Figure 3. Waveform Figure 2. Test Circuit Note: 8. Duty Cycle is computed as Duty Cycle = TH/Period. Timing Diagrams Vdd 90% Vdd Vdd T_start Pin 4 Voltage 50% Vdd [9] T_resume ST Voltage No Glitch during start up CLK Output CLK Output HZ HZ T_resume: Time to resume from ST T_start: Time to start from power-off Figure 4. Startup Timing (OE/ST Mode) Figure 5. Standby Resume Timing (ST Mode Only) u Vdd Vdd 50% Vdd OE Voltage OE Voltage 50% Vdd T_oe T_oe CLK Output CLK Output HZ HZ T_oe: Time to re-enable the clock output T_oe: Time to put the output in High Z mode Figure 6. OE Enable Timing (OE Mode Only) Figure 7. OE Disable Timing (OE Mode Only) Note: 9. YSO8008MR has “no runt” pulses and “no glitch” output during startup or resume. come visit our site http://www.yxc.hk 5/9 【晶振全系列独立与授权型供应商-深圳扬兴科技有限公司】 www.yxc.hk YSO8008MR Performance Plots[10] 1.8 2.5 2.8 3.0 3.3 6.0 DUT2 DUT3 DUT4 DUT5 DUT6 DUT7 DUT8 DUT9 DUT10 20 15 5.5 10 Frequency (ppm) 5.0 Idd (mA) DUT1 4.5 4.0 5 0 -5 -10 3.5 -15 -20 3.0 0 10 20 30 40 50 60 70 80 90 100 -30 -40 110 -20 -10 Frequency (MHz) 2.8 V 3.0 V 20 30 40 50 60 70 80 Figure 9. Frequency vs Temperature 3.3 V 1.8 V 4.0 55 3.5 54 2.5 V 2.8 V 3.0 V 3.3 V 53 3.0 52 Duty cycle (%) RMS period jitter (ps) 2.5 V 10 Temperature (°C) Figure 8. Idd vs Frequency 1.8 V 0 2.5 2.0 1.5 1.0 51 50 49 48 47 0.5 46 0.0 0 10 20 30 40 50 60 70 80 90 100 45 110 0 Frequency (MHz) 10 2.8 V 3.0 V 3.3 V 1.8 V 2.5 2.5 2.0 2.0 1.5 50 60 70 80 90 100 110 1.0 2.5 V 2.8 V 3.0 V 3.3 V 1.5 1.0 0.5 0.5 0.0 -40 -15 10 35 60 0.0 85 -40 -15 Temperature (°C) 1.8 V 2.5 V 2.8 V 3.0 V 10 35 60 85 Temperature (°C) Figure 12. 20%-80% Rise Time vs Temperature Figure 13. 20%-80% Fall Time vs Temperature 3.3 V 1.8 V 2.0 0.9 1.8 0.8 1.6 0.7 IPJ (ps) IPJ (ps) 40 Figure 11. Duty Cycle vs Frequency Fall time (ns) Rise time (ns) 2.5 V 30 Frequency (MHz) Figure 10. RMS Period Jitter vs Frequency 1.8 V 20 ) s p ( 1.4 J P I 1.2 2.5 V 2.8 V 3.0 V 3.3 V 0.6 0.5 1.0 10 30 50 70 90 0.4 110 10 30 50 70 90 110 Frequency (MHz) Frequency (MHz) (MHz) Frequency Figure 14. RMS Integrated Phase Jitter Random (12 kHz to 20 MHz) vs Frequency[11] Figure 15. RMS Integrated Phase Jitter Random (900 kHz to 20 MHz) vs Frequency[11] Notes: 10. All plots are measured with 15 pF load at room temperature, unless otherwise stated. 11. Phase noise plots are measured with Agilent E5052B signal source analyzer. Integration range is up to 5 MHz for carrier frequencies below 40 MHz. come visit our site http://www.yxc.hk 6/9 【晶振全系列独立与授权型供应商-深圳扬兴科技有限公司】 www.yxc.hk YSO8008MR Programmable Drive Strength The YSO8008MR includes a programmable drive strength feature to provide a simple, flexible tool to optimize the clock rise/fall time for specific applications. Benefits from the programmable drive strength feature are: • Improves system radiated electromagnetic interference (EMI) by slowing down the clock rise/fall time • Improves the downstream clock receiver’s (RX) jitter by decreasing (speeding up) the clock rise/fall time. • Ability to drive large capacitive loads while maintaining full EMI Reduction by Slowing Rise/Fall Time Figure 16 shows the harmonic power reduction as the rise/fall times are increased (slowed down). The rise/fall times are expressed as a ratio of the clock period. For the ratio of 0.05, the signal is very close to a square wave. For the ratio of 0.45, the rise/fall times are very close to near-triangular waveform. These results, for example, show that the 11th clock harmonic can be reduced by 35 dB if the rise/fall edge is increased from 5% of the period to 45% of the period.   YSO8008MR Drive Strength Selection Tables 7 through 11 define the rise/fall time for a given capacitive load and supply voltage. 1. Select the table that matches the YSO8008MR nominal supply voltage (1.8V, 2.5V, 2.8V, 3.0V, 3.3V). 2. Select the capacitive load column that matches the application requirement (5 pF to 60 pF) 3. Under the capacitive load column, select the desired rise/fall times. 4. The left-most column represents the part number code for the corresponding drive strength. 5. Add the drive strength code to the part number for ordering purposes. trise=0.05 trise=0.1 trise=0.15 trise=0.2 10 0 Harmonic amplitude (dB) The YSO8008MR can support up to 60 pF or higher in maximum capacitive loads with drive strength settings. Refer to the Rise/Tall Time Tables (Table 7 to 11) to determine the proper drive strength for the desired combination of output load vs. rise/fall time. trise=0.25 trise=0.3 trise=0.35 trise=0.4 trise=0.45 -10 -20 -30 -40 -50 -60 -70 -80 1 3 5 7 9 11 Harm onic num ber Figure 16. Harmonic EMI reduction as a Function of Slower Rise/Fall Time Jitter Reduction with Faster Rise/Fall Time Power supply noise can be a source of jitter for the downstream chipset. One way to reduce this jitter is to speed up the rise/fall time of the input clock. Some chipsets may also require faster rise/fall time in order to reduce their sensitivity to this type of jitter. Refer to the Rise/Fall Time Tables (Table 7 to Table 11) to determine the proper drive strength. High Output Load Capability The rise/fall time of the input clock varies as a function of the actual capacitive load the clock drives. At any given drive strength, the rise/fall time becomes slower as the output load increases. As an example, for a 3.3V YSO8008 MR device with default drive strength setting, the typical rise/fall time is 1 ns for 15 pF output load. The typical rise/fall time slows down to 2.6 ns when the output load increases to 45 pF. One can choose to speed up the rise/fall time to 1.83 ns by then increasing the drive strength setting on the YSO8008MR. come visit our site http://www.yxc.hk 7/9 【晶振全系列独立与授权型供应商-深圳扬兴科技有限公司】 www.yxc.hk YSO8008MR Rise/Fall Time (20% to 80%) vs CLOAD Tables Table 7. Vdd = 1.8V Rise/Fall Times for Specific CLOAD Table 8. Vdd = 2.5V Rise/Fall Times for Specific CLOAD Rise/Fall Time Typ (ns) Rise/Fall Time Typ (ns) Drive Strength \ CLOAD 5 pF 15 pF 30 pF 45 pF 60 pF Drive Strength \ CLOAD 5 pF 15 pF 30 pF 45 pF 60 pF L A R  B T E U F or "‐": default 6.16 3.19 2.11 1.65 0.93 0.78 0.70 0.65 11.61 6.35 4.31 3.23 1.91 1.66 1.48 1.30 22.00 11.00 7.65 5.79 3.32 2.94 2.64 2.40 31.27 16.01 10.77 8.18 4.66 4.09 3.68 3.35 39.91 21.52 14.47 11.08 6.48 5.74 5.09 4.56 L A R  B T E or "‐": default U F  4.13 2.11 1.45 1.09 0.62 8.25 4.27 2.81 2.20 1.28 12.82 7.64 5.16 3.88 2.27 21.45 11.20 7.65 5.86 3.51 27.79 14.49 9.88 7.57 4.45 0.54 0.43 0.34 1.00 0.96 0.88 2.01 1.81 1.64 3.10 2.79 2.54 4.01 3.65 3.32 Table 9. Vdd = 2.8V Rise/Fall Times for Specific CLOAD Table 10. Vdd = 3.0V Rise/Fall Times for Specific CLOAD Rise/Fall Time Typ (ns) Rise/Fall Time Typ (ns) Drive Strength \ CLOAD 5 pF 15 pF 30 pF 45 pF 60 pF Drive Strength \ CLOAD 5 pF 15 pF 30 pF 45 pF 60 pF L A R  B T 3.77 1.94 1.29 0.97 0.55 7.54 3.90 2.57 2.00 1.12 12.28 7.03 4.72 3.54 2.08 19.57 10.24 7.01 5.43 3.22 25.27 13.34 9.06 6.93 4.08 E or "‐": default U F 0.44 0.34 0.29 1.00 0.88 0.81 1.83 1.64 1.48 2.82 2.52 2.29 3.67 3.30 2.99 L A R  B T or "‐": default E U F 3.60 1.84 1.22 0.89 0.51 0.38 0.30 0.27 7.21 3.71 2.46 1.92 1.00 0.92 0.83 0.76 11.97 6.72 4.54 3.39 1.97 1.72 1.55 1.39 18.74 9.86 6.76 5.20 3.07 2.71 2.40 2.16 24.30 12.68 8.62 6.64 3.90 3.51 3.13 2.85 Table 11. Vdd = 3.3V Rise/Fall Times for Specific CLOAD Rise/Fall Time Typ (ns) Drive Strength \ CLOAD 5 pF 15 pF 30 pF 45 pF 60 pF L A R  B 3.39 1.74 1.16 0.81 6.88 3.50 2.33 1.82 11.63 6.38 4.29 3.22 17.56 8.98 6.04 4.52 23.59 12.19 8.34 6.33 T or "‐": default E U F 0.46 0.33 0.28 0.25 1.00 0.87 0.79 0.72 1.86 1.64 1.46 1.31 2.60 2.30 2.05 1.83 3.84 3.35 2.93 2.61 come visit our site http://www.yxc.hk 8/9 【晶振全系列独立与授权型供应商-深圳扬兴科技有限公司】 www.yxc.hk YSO8008MR Pin 1 Configuration Options (OE, ST, or NC) Pin 1 of the YSO8008MR can be factory-programmed to support three modes: Output Enable (OE), standby (ST) or No Connect (NC). Output Enable (OE) Mode In the OE mode, applying logic Low to the OE pin only disables the output driver and puts it in Hi-Z mode. The core of the device continues to operate normally. Power consumption is reduced due to the inactivity of the output. When the OE pin is pulled High, the output is ty pically enabled in