TPL51200 Series
3-A Sink and Source DDR Termination Regulator
Features
Description
◼
VIN Voltage: Support 2.5-V, 3.3-V and 5-V Power Rails
With the development of main processors in PCs and servers,
◼
VLDOIN Voltage Range: 1.1 V to 3.5 V
more and more source double-data-rate (DDR) memories are
◼
Flexible Input Voltage Tracking Directly from REFIN or
required in the mainboard, where the input voltage becomes
Through External Resistor Divider
lower and lower, and space limitation becomes higher and
3-A Sink and Source Current Capability for DDR
higher.
◼
Termination
◼
Integrated Power MOSFETs
The TPL51200 series devices are 3-A sink and source DDR
◼
Output Remote Sensing
termination regulators specifically designed for the DDR
◼
Fast Load-Transient Response
applications with heavy space limitation. The TPL51200 series
◼
Open-Drain Power Good to Monitor OUT Regulation
devices implement a fast load-transient response and only
◼
Built in Soft-Start and UVLO, Current Limit and Thermal
requires a minimum output capacitance of 20 μF.
Shutdown Protection
Support DDR, DDR2, DDR3, DDR3L, Low Power DDR3
The TPL51200 series devices support a remote-sensing
and DDR4 VTT Applications
function and all power requirements for DDR VTT bus
◼
Operating Temperature Range: –40°C to +125°C
termination. In addition, the TPL51200 series devices provide
◼
Small Package with 3×3 DFN-10
an open-drain PG signal for VTT regulation indication and an
◼
Pb−Free and are RoHS Compliant
EN signal that can be used to discharge VTT for DDR
◼
applications.
Applications
◼
The TPL51200 series devices are available in the thermally
Memory VTT Regulator for DDR, DDR2, DDR3, DDR3L,
efficient 10-pin 3×3 DFN package with thermal pad, and support
Low Power DDR3 and DDR4
the operating temperature range from –40°C to +125°C.
◼
Notebooks, Desktops, and Workstations
◼
Servers, Networking equipment and Datacenters
◼
Telecom and Base Station
Typical Application Schematic
10 kΩ
VDDQ = 1.2 V
1
1 nF
REFIN
IN 10
10 kΩ
VLD OIN = VDDQ = 1.2 V
10 μF
10 μF
10 μF
10 μF
GND
www.3peakic.com.cn
VIN = 3.3 V
100 kΩ
0.1 μF
2
LDOIN
TPL51200
VTT = 0.6 V
4.7 μF
3
OUT
4
PGND
5
SNS
1 / 18
PG
9
GND
8
EN
7
REFOUT
6
PG Sig nal to I/O
Ena ble Signa l
0.1 μF
VTTRE F = 0.6 V
Rev.A.1
TPL51200 Series
3-A Sink and Source DDR Termination Regulator
Product Family Table
Part Number
Output Current
Orderable Number
Package
Transport Media, Quantity
MSL
Marking information
TPL51200
3A
TPL51200-DF8R
3×3 DFN-10
4,000
MSL3
L200
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2 / 18
Rev.A.1
TPL51200 Series
3-A Sink and Source DDR Termination Regulator
Table of Contents
Features ........................................................................................................................................................................... 1
Applications ..................................................................................................................................................................... 1
Description....................................................................................................................................................................... 1
Typical Application Schematic ...................................................................................................................................... 1
Product Family Table ...................................................................................................................................................... 2
Table of Contents ............................................................................................................................................................ 3
Revision History .............................................................................................................................................................. 4
Pin Configuration and Functions .................................................................................................................................. 5
Specifications .................................................................................................................................................................. 6
Absolute Maximum Ratings .......................................................................................................................................................... 6
ESD Ratings ................................................................................................................................................................................. 6
Recommended Operating Conditions ........................................................................................................................................... 6
Thermal Information ...................................................................................................................................................................... 6
Electrical Characteristics ............................................................................................................................................................... 7
Typical Performance Characteristics............................................................................................................................................. 9
Detailed Description ..................................................................................................................................................... 12
Overview ..................................................................................................................................................................................... 12
Functional Block Diagram ........................................................................................................................................................... 12
Feature Description ..................................................................................................................................................................... 12
Application and Implementation.................................................................................................................................. 14
Application Information................................................................................................................................................................ 14
Typical Application ...................................................................................................................................................................... 14
Layout Requirements .................................................................................................................................................................. 15
Tape and Reel Information .............................................................................................................................................. 16
Package Outline Dimensions ....................................................................................................................................... 17
3×3 DFN-10 ................................................................................................................................................................................ 17
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3 / 18
Rev.A.1
TPL51200 Series
3-A Sink and Source DDR Termination Regulator
Revision History
Date
Revision
2019/11/30
Rev.Pre
Preliminary Version
2020/05/15
Rev.A.0
Initial Released
2020/12/22
Rev.A.1
www.3peakic.com.cn
Notes
1. Add Tape and Reel Information
2. Update Package Outline Dimensions
4 / 18
Rev.A.1
TPL51200 Series
3-A Sink and Source DDR Termination Regulator
Pin Configuration and Functions
TPL51200 Series
DFN-20 Package
Top View
REFIN
1
LDOIN
2
Exposed
PAD
10
IN
9
PG
8
GND
OUT
3
PGND
4
7
EN
SNS
5
6
REFOUT
Pin Functions
NAME
PIN NUMBER
TYPE
DESCRIPTION
EN
7
I
GND
8
−
IN
10
I
LDOIN
2
I
OUT
3
O
PG
9
O
Open-drain power-good output pin.
PGND
4
−
Power ground pin. Connect PGND pin to PCB ground plane directly.
REFIN
1
I
Reference input pin. For DDR application, set to VDDQ/2 through resistor divider.
REFOUT
6
O
Reference output pin. Connect to ground through a 0.1-μF to 1-μF ceramic capacitor.
SNS
5
I
Regulator enable pin. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For
automatic startup, connect EN to VIN directly.
Ground reference pin. Connect GND pin to PCB ground plane directly.
Regulator power supply input pin. A 1-μF or larger ceramic capacitor from IN to ground (as close as
possible to IN pin) is required to reduce the jitter from previous-stage power supply.
LDO power supply input pin.
LDO output voltage pin. Total capacitance of 20-μF or larger from OUT to ground (as close as possible
to OUT pin) is required to ensure regulator stability.
LDO output voltage sense pin. Connect SNS to the remote DDR termination bypass capacitors to get
accurate remote feedback sensing of OUT voltage.
(1) Exposed PAD must be connected to a large-area ground plane to maximum the thermal performance.
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5 / 18
Rev.A.1
TPL51200 Series
3-A Sink and Source DDR Termination Regulator
Specifications
Absolute Maximum Ratings
MIN
MAX
UNIT
EN, IN, LDOIN, PG, REFIN, SNS
–0.3
6
V
PGND to GND
–0.3
0.3
V
OUT, REFOUT
–0.3
3.6
V
TJ
Junction Temperature Range
–40
150
°C
TSTG
Storage Temperature Range
–55
150
°C
TL
Lead Temperature (Soldering 10 sec)
260
°C
(1) Stresses beyond the Absolute Maximum Ratings may permanently damage the device.
(2) All voltage values are with respect to GND.
ESD Ratings
Condition
Minimum Level
Unit
HBM
Human Body Model ESD
ANSI/ESDA/JEDEC JS-001
±2000
V
CDM
Charged Device Model ESD
ANSI/ESDA/JEDEC JS-002
±1500
V
Recommended Operating Conditions
MIN
MAX
UNIT
IN
Regulator input voltage
2.375
5.5
V
LDOIN
LDO input voltage
–0.1
3.5
V
EN
Regulator enable voltage
–0.1
3.5
V
OUT
LDO output voltage
–0.1
3.5
V
SNS
LDO output sense voltage
–0.1
3.5
V
REFIN
Reference input voltage
0.5
1.8
V
REFOUT
Reference output voltage
–0.1
1.8
V
PG
Power-good pull-up voltage
–0.1
3.5
V
PGND
Power ground voltage to GND
–0.1
0.1
V
TJ
Junction Temperature Range
–40
125
°C
Thermal Information
PACKAGE
θJA
θJC
UNIT
3×3 DFN-10
77.66
16.33
°C/W
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6 / 18
Rev.A.1
TPL51200 Series
3-A Sink and Source DDR Termination Regulator
Electrical Characteristics
TJ = –40°C to +125°C (typical value at TJ = +25°C), VIN = VEN = 3.3 V; VLDOIN = 1.8 V, VREFIN = 0.9 V, VSNS = 0.9 V, CIN = 10 µF, and COUT = 3 x 10 µF;
unless otherwise noted unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5.5
V
3.5
V
2.375
V
Supply Input Voltage and Current
VIN
Input supply voltage range
VLDOIN
LDO input voltage range
UVLOIN
Input supply UVLO
2.375
TA = +25°C, VIN rising
2.3
Hysteresis
IIN
Input supply current of IN
IIN_SD
Shutdown current of IN
ILDOIN
Input current of LDOIN
ILDOIN_SD
Shutdown current of LDOIN
50
mV
TA = +25°C, VEN = 3.3 V, IOUT = 0 mA
0.8
1
mA
TA = +25°C, VEN = 0 V, VREFIN = 0 V, IOUT = 0 mA
65
80
µA
TA = +25°C, VEN = 0 V, VREFIN > 0.4 V, IOUT = 0 mA
200
400
µA
TA = +25°C, VEN = 3.3 V, IOUT = 0 mA
1
50
µA
TA = +25°C, VEN = 0 V, IOUT = 0 mA
1
50
µA
1.8
V
420
mV
Reference Input and Output
VREFIN
UVLOREFIN
Reference input voltage
Reference input UVLO
0.5
TA = +25°C, VREFIN rising
360
Hysteresis
IREFIN
Input current of REFIN
VREFOUT
Reference output voltage
VREFOUT_TOL
Tolerance of REFOUT to REFIN
IREFOUT_SRCL
IREFOUT_SNKL
VEN = 3.3 V
390
20
mV
1
µA
VREFIN
V
−1 mA ≤ IREFOUT ≤ 1 mA, 0.5 V ≤ VREFIN ≤ 1.8 V
−12
12
mV
−10 mA ≤ IREFOUT ≤ 10 mA, 0.5 V ≤ VREFIN ≤ 1.8 V
−15
15
mV
Source current limit of REFOUT
VREFOUT = 0.5 V
10
60
mA
Sink current limit of REFOUT
VREFOUT = 1.5 V
10
60
mA
1.25
V
Regulated Output Voltage and Current
VREFOUT = 1.25 V (DDR1), IOUT = 0 A
Tolerance
−15
VREFOUT = 0.9 V (DDR2), IOUT = 0 A
Tolerance
VOUT
Output voltage
15
0.9
−15
VREFOUT = 0.75 V (DDR3), IOUT = 0 A
Tolerance
0.75
VREFOUT = 0.675 V (DDR3L), IOUT = 0 A
Tolerance
V
15
−15
0.675
VREFOUT = 0.6 V (DDR4), IOUT = 0 A
mV
V
15
−15
mV
mV
V
15
0.6
mV
V
Tolerance
−15
15
mV
−25
25
mV
ΔVOUT
Tolerance of OUT to REFOUT
–2A < IOUT < 2A
IOUT_SRCL
Source current limit of OUT
VSNS = 90% × VREFOUT
3
4.5
A
IOUT_SNKL
Sink current limit of OUT
VSNS = 110% × VREFOUT
3.2
5.5
A
RDIS
Discharge resistance
TA = +25°C, VREFIN = 0 V, VOUT = 0.3 V, VEN = 0 V
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7 / 18
12
Ω
Rev.A.1
TPL51200 Series
3-A Sink and Source DDR Termination Regulator
Electrical Characteristics (continued)
TJ = –40°C to +125°C (typical value at TJ = +25°C), VIN = VEN = 3.3 V; VLDOIN = 1.8 V, VREFIN = 0.9 V, VSNS = 0.9 V, CIN = 10 µF, and COUT = 3 x 10 µF;
unless otherwise noted unless otherwise noted.
Enable Control
VEN
EN High-level input voltage
Device enable
EN Low-level input voltage of
Device disable
1.7
0.5
Hysteresis
IEN
V
0.25
–1
V
V
Leakage current of EN
TA = +25°C, VEN = 0 V to 6.5 V
1
PG lower threshold
With respect to REFOUT
–23.5%
–20%
–17.5%
PG upper threshold
With respect to REFOUT
17.5
20%
23.5%
µA
Power Good
VPG
Hysteresis
5%
IPG
Leakage current of PG
1
µA
VOL(PG)
PG low-level output voltage
Source 4 mA to PG pin
0.4
V
tDLY(PG)
PG start-up delay
Startup rising edge, VSNS within 15% of VREFOUT
2
ms
tDLY(PG_B)
PG start-up bad delay
VSNS is beyond the ±20% PG trip threshold
10
µs
Temperature increasing
155
°C
25
°C
Temperature Range
Thermal shutdown threshold
TSD
TJ
Hysteresis
Operating junction temperature
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–40
8 / 18
125
Rev.A.1
°C
TPL51200 Series
3-A Sink and Source DDR Termination Regulator
Typical Performance Characteristics
TJ = –40°C to +125°C (typical value at TJ = +25°C), VIN = VEN = 3.3 V; VLDOIN = 1.8 V, VREFIN = 0.9 V, VSNS = 0.9 V, CIN = 10 µF, and COUT = 3 x 10 µF;
unless otherwise noted unless otherwise noted.
1.29
0.920
−40°C
0°C
1.27
Output Voltage (V)
Output Voltage (V)
−40°C
25°C
85°C
1.25
1.23
1.21
0°C
0.910
25°C
85°C
0.900
0.890
0.880
-3
-2
-1
0
1
2
3
-3
-2
Output Current (A)
-1
0
1
VIN = 3.3 V
DDR
VIN = 3.3 V
Figure 1 OUT Load Regulation
DDR2
0.695
−40°C
−40°C
0°C
0.76
Output Voltage (V)
Output Voltage (V)
3
Figure 2 OUT Load Regulation
0.77
25°C
85°C
0.75
0.74
0.73
0°C
0.685
25°C
85°C
0.675
0.665
0.655
-3
-2
-1
0
1
2
3
-3
-2
Output Current (A)
VIN = 3.3 V
-1
0
1
2
3
Output Current (A)
DDR3
VIN = 3.3 V
Figure 3 OUT Load Regulation
DDR3L
Figure 4 OUT Load Regulation
0.620
1.300
−40°C
−40°C
0°C
0.610
Output Voltage (V)
Output Voltage (V)
2
Output Current (A)
25°C
85°C
0.600
0.590
0.580
0°C
1.275
25°C
85°C
1.250
1.225
1.200
-3
-2
-1
0
1
2
3
-3
Output Current (A)
VIN = 3.3 V
-1
0
1
2
Output Current (A)
LP DDR3 or DDR4
Figure 5 OUT Load Regulation
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-2
VIN = 2.5 V
DDR
Figure 6 OUT Load Regulation
9 / 18
Rev.A.1
3
TPL51200 Series
3-A Sink and Source DDR Termination Regulator
Typical Performance Characteristics (continued)
TJ = –40°C to +125°C (typical value at TJ = +25°C), VIN = VEN = 3.3 V; VLDOIN = 1.8 V, VREFIN = 0.9 V, VSNS = 0.9 V, CIN = 10 µF, and COUT = 3 x 10 µF;
unless otherwise noted unless otherwise noted.
0.950
0.800
−40°C
0°C
0.925
Output Voltage (V)
Output Voltage (V)
−40°C
25°C
85°C
0.900
0.875
0.850
0°C
0.775
25°C
85°C
0.750
0.725
0.700
-3
-2
-1
0
1
2
3
-3
-2
-1
Output Current (A)
0
1
2
VIN = 2.5 V
DDR2
VIN = 2.5 V
DDR3
Figure 7 OUT Load Regulation
Figure 8 OUT Load Regulation
0.725
0.650
−40°C
0°C
0.700
Output Voltage (V)
Output Voltage (V)
−40°C
25°C
85°C
0.675
0.650
0.625
0°C
0.625
25°C
85°C
0.600
0.575
0.550
-3
-2
-1
0
1
2
3
-3
-2
-1
Output Current (A)
0
1
2
3
Output Current (A)
VIN = 2.5 V
DDR3L
VIN = 2.5 V
Figure 9 OUT Load Regulation
LP DDR3 or DDR4
Figure 10 OUT Load Regulation
1.253
0.903
−40°C
1.252
0°C
1.251
25°C
REFOUT Output Voltage (V)
REFOUT Output Voltage (V)
3
Output Current (A)
85°C
1.250
1.249
1.248
1.247
0.902
0.901
0.900
−40°C
0.899
0°C
25°C
0.898
85°C
0.897
-10
-5
0
5
10
-10
REFOUT Output Current (mA)
-5
0
5
DDR
DDR2
Figure 11 REFOUT Load Regulation
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10
REFOUT Output Current (mA)
Figure 12 REFOUT Load Regulation
10 / 18
Rev.A.1
TPL51200 Series
3-A Sink and Source DDR Termination Regulator
Typical Performance Characteristics (continued)
TJ = –40°C to +125°C (typical value at TJ = +25°C), VIN = VEN = 3.3 V; VLDOIN = 1.8 V, VREFIN = 0.9 V, VSNS = 0.9 V, CIN = 10 µF, and COUT = 3 x 10 µF;
unless otherwise noted unless otherwise noted.
0.678
REFOUT Output Voltage (V)
REFOUT Output Voltage (V)
0.753
0.752
0.751
0.750
−40°C
0.749
0°C
25°C
0.748
85°C
0.747
-10
-5
0.677
0.676
0.675
−40°C
0.674
0°C
25°C
0.673
85°C
0.672
0
5
10
-10
REFOUT Output Current (mA)
-5
0
5
DDR3
DDR3L
Figure 14 REFOUT Load Regulation
0.603
1.2
0.602
1
Output Voltage (V)
REFOUT Output Voltage (V)
Figure 13 REFOUT Load Regulation
0.601
0.600
−40°C
0.599
0°C
25°C
0.598
-10
-5
0.8
−40°C
0.6
0°C
0.4
25°C
85°C
0.2
125°C
85°C
0.597
10
REFOUT Output Current (mA)
0
0
5
10
2.1
REFOUT Output Current (mA)
2.15
2.2
2.25
2.3
Input Voltage (V)
DDR4
Figure 15 REFOUT Load Regulation
Figure 16 UVLO Rising
500 µs/div
10 µs/div
Figure 17 Load Transient
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Figure 18 Output Short-to-GND Protection
11 / 18
Rev.A.1
TPL51200 Series
3-A Sink and Source DDR Termination Regulator
Detailed Description
Overview
The TPL51200 series devices are 3-A sink and source DDR termination regulators specifically designed for the DDR applications
with heavy space limitation. The TPL51200 series devices implement a fast load-transient response and only requires a minimum
output capacitance of 20 μF.
The TPL51200 series devices support a remote-sensing function and all power requirements for DDR VTT bus termination. In addition,
the TPL51200 series devices provide an open-drain PG signal for VTT regulation indication and an EN signal that can be used to
discharge VTT for DDR1 to DDR4 applications.
Functional Block Diagram
LDOIN
IN
EN
OUT
AMP
UVLO
ENABL E
Device
Control
Regula tion
Control
Discha rge
SNS
AMP
PGND
–
EA
+
REFIN
REFOUT
BUF
GND
Power Goo d
Control
Discha rge
PG
Figure 19 Functional Block Diagram
Feature Description
Sink and Source Regulator (OUT and SNS)
The TPL51200 series devices are 3-A sink and source DDR termination regulators specifically designed for the DDR applications
with heavy space limitation. The TPL51200 series integrate a high-performance, low-dropout linear regulator with fast-feedback loop
that can support fast load transient response with small ceramic capacitors. To get tight regulation tolerance, the remote sensing pin,
SNS pin, must be connected to OUT pin through a separate trace from high current path.
Voltage Reference (REFIN and REFOUT)
The TPL51200 series uses the voltage at the REFIN pin as the reference voltage, and the output voltage at the REFOUT pin exactly
follow the REFIN voltage within the tolerance of VREFOUT_TOL. When the TPL51200 series are configured for standard DDR
applications, the voltage at the REFIN pin is divided through an external voltage divider from the DDR supply bus, VDDQ.
The TPL51200 series support the REFIN input voltage range from 0.5 V to 1.8 V. When the REFIN voltage is higher than rising UVLO
threshold of REFIN and IN voltage is ready, there is voltage regulated at the REFOUT pin, which the REFOUT pin is independent
with EN status.
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Rev.A.1
TPL51200 Series
3-A Sink and Source DDR Termination Regulator
Enable Control (EN)
The TPL51200 series integrate the high-active device enable control feature. Connect this pin to the GPIO of an external processor
or digital logic control circuit to enable and disable the device.
Under-voltage Lockout (IN UVLO)
The TPL51200 series use an under-voltage lockout circuit to keep the regulator shut off until IN voltage exceeds the rising UVLO
threshold of IN.
Power-Good Indicator (PG)
The TPL51200 series integrate an open-drain output power good indicator. After regulator startup, the PG pin keeps low impendence
until the output voltage enters the power-good window, ±20% of REFOUT voltage. When output voltage enters the power-good
window, the PG pin turns to high output impedance, and PG is pulled up to high-voltage level after 2-ms delay to indicate the output
voltage is ready. It is recommended to connect a 100-kΩ pull-up resistor between PG pin and the pull-up voltage supply.
Over-Current Protection
The TPL51200 series integrate a constant over-current protection. When the output voltage exists the power-good window, ±20% of
REFOUT voltage, the current-limit level reduces 50% of the full level. After the output voltage enters the power-good window, the
current-limit level is released to the full level.
Over-Temperature Protection
The recommended operating junction temperature range is –40°C to 125°C. When the junction temperature is between 125°C and
the thermal shutdown (TSD) threshold, the regulator can still work well, but it will reduce the device lifetime for long-term using.
The over-temperature protection works when the junction temperature exceeds the thermal shutdown (TSD) threshold, which turns
off the regulator immediately. Until when the device cools down and the junction temperature falls below the thermal shutdown
threshold minus thermal shutdown hysteresis, the regulator turns on again.
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13 / 18
Rev.A.1
TPL51200 Series
3-A Sink and Source DDR Termination Regulator
Application and Implementation
NOTE
Information in the following applications sections is not part of the 3PEAK’s component specification and 3PEAK does
not warrant its accuracy or completeness. 3PEAK’s customers are responsible for determining suitability of
components for their purposes. Customers should validate and test their design implementation to confirm system
functionality.
Application Information
The TPL51200 series devices are 3-A sink and source DDR termination regulators specifically designed for the DDR applications.
The following application schematic shows a typical usage of the TPL51200 series.
Typical Application
Adjustable Output Operation
Figure 20 shows the typical application schematic of the TPL51200 series in DDR4 applications.
10 kΩ
VDDQ = 1.2 V
1
1 nF
REFIN
IN 10
10 kΩ
VLD OIN = VDDQ = 1.2 V
10 μF
10 μF
10 μF
VIN = 3.3 V
100 kΩ
0.1 μF
2
LDOIN
TPL51200
VTT = 0.6 V
4.7 μF
10 μF
GND
3
OUT
4
PGND
5
SNS
PG
9
GND
8
EN
7
REFOUT
6
PG Sig nal to I/O
Ena ble Signa l
0.1 μF
VTTRE F = 0.6 V
Figure 20 Typical Application Schematic
IN Input Capacitor
3PEAK recommends placing a 1-μF or greater capacitor with a 0.1-μF bypass capacitor in parallel close to IN pin to keep the input
voltage stable. The voltage rating of the capacitors must be greater than the maximum input voltage.
LDOIN Input Capacitor
3PEAK recommends placing a 10-μF or greater capacitor with a 0.1-μF bypass capacitor in parallel close to LDOIN pin to keep the
voltage stable during transient. More input capacitors are required if there are large output capacitors used at the OUT pin. It is
suggested to place input capacitors with a half of the output capacitance value at the LDOIN pin.
Output Capacitor
To ensure stable operation, the TPL51200 series requires output capacitors of 20 μF or greater. 3PEAK recommends selecting three
10-μF X5R-or X7R-type ceramic capacitor in parallel to minimize the equivalent series resistance (ESR) and equivalent series
inductance (ESL). The output capacitors must be placed as close to the OUT pin as possible.
Power Dissipation
During normal operation, LDO junction temperature should not exceed 125°C. Using below equations to calculate the power
dissipation and estimate the junction temperature.
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Rev.A.1
TPL51200 Series
3-A Sink and Source DDR Termination Regulator
The power dissipation can be calculated using Equation 1.
PD = ( VIN − VOUT ) IOUT + VIN IGND
(1)
The junction temperature can be estimated using Equation 2. θJA is the junction-to-ambient thermal resistance.
TJ = TA + PD JA
(2)
Layout Requirements
•
Both input capacitors and output capacitors must be placed as close to the device pins as possible.
•
Suggest bypass the input pin to ground with a 0.1 μF bypass capacitor. The loop area formed by the bypass capacitor
connection, voltage input pin and the ground pin of the system must be as small as possible.
•
Suggest use wide trace lengths or thick copper weight to minimize I×R drop and heat dissipation.
•
The GND pin and the PGND pin must be connected to the thermal pad with multiple thermal vias as many as possible
connected to the internal ground planes.
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Rev.A.1
TPL51200 Series
3-A Sink and Source DDR Termination Regulator
Tape and Reel Information
Order Number
Package
TPL51200-DF8R
3×3 DFN-10
www.3peakic.com.cn
D1
W1
A0
B0
K0
P0
W0
Pin1
(mm)
(mm)
(mm)
(mm)
(mm)
(mm)
(mm)
Quadrant
330
17.6
3.3
3.3
1.1
8
12
Q2
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Rev.A.1
TPL51200 Series
3-A Sink and Source DDR Termination Regulator
Package Outline Dimensions
3×3 DFN-10
Nd
D
L
SYMBOL
R1
E
E2
D2
A
MILLIMETER
MIN
NOM
MAX
0.70
0.75
0.80
A1
0
0.02
0.05
b
0.20
0.25
0.30
b1
0.23REF
c
0.203REF
2.90
3.00
3.10
2.35
2.40
2.45
R
D
D2
k
Nd
PIN 1(Laser Mark)
e
EXPOSED THERMAL
BOTTOM VIEW
PAD ZONE
A
A1
TOP VIEW
0.50BSC
e
b1
b
2.00BSC
E
2.90
3.00
3.10
E2
1.60
1.65
1.70
L
0.35
0.40
0.45
R
0.20REF
R1
0.075REF
k
0.35REF
**
特殊设计：D2和E2尺寸的公差是±0.05；
c
引脚根部缩小较少；
SIDE VIEW
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17 / 18
Rev.A.1
TPL51200 Series
3-A Sink and Source DDR Termination Regulator
3PEAK and the 3PEAK logo are registered trademarks of 3PEAK INCORPORATED. All
other trademarks are the property of their respective owners.
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18 / 18
Rev.A.1
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