MC3635 3-Axis Accelerometer
GENERAL DESCRIPTION
The MC3635 is an ultra-low power, lownoise, integrated digital output 3-axis
accelerometer with a feature set optimized
for wearables and consumer product
motion sensing. Applications include
wearable consumer products, IoT devices,
user interface control, gaming motion input,
electronic compass tilt compensation for
cell phones, game controllers, remote
controls and portable media products.
Low noise and low power are inherent in
the monolithic fabrication approach, where
the MEMS accelerometer is integrated in a
single-chip with the electronics integrated
circuit.
In the MC3635 the internal sample rate can
be set from 14 to 1300 samples / second.
Specific tap or sample acquisition
conditions can trigger an interrupt to a
remote MCU. Alternatively, the device
supports the reading of sample and event
status via polling.
Information furnished by MEMSIC is believed to be accurate and reliable.
However, no responsibility is assumed by MEMSIC for its use, or for any
infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any
patent or patent rights of MEMSIC.
FEATURES
Range, Sampling & Power
±2, 4, 8, 12 or 16g ranges
8, 10 or 12-bit resolution with FIFO
o 14-bit single samples
Sample rate 14 - 1300 samples/sec
o Sample trigger via internal oscillator,
clock pin or software command
Sniff and Wake modes
o 0.3 μA Sniff current @ 1Hz
o Separate or combined sniff/wake
Ultra-Low Power with 32 sample FIFO
o 0.9 μA typical current @ 25Hz
o 1.6 μA typical current @ 50Hz
o 2.8 μA typical current @ 100Hz
o 36 μA typical current @ 1300Hz
Simple System Integration
I2C interface, up to 1 MHz
SPI Interface, up to 8 MHz
1.6 × 1.6 × 0.94 mm 10-pin package
Single-chip 3D silicon MEMS
Low noise to 2.3mgRMS
ROHS Compliant
MEMSIC Semiconductor (Tianjin) Co., Ltd.
Room 4-501, Financial Center, No. 158, West Third Road,
Tianjin Airport Economic Zone, Tianjin, China, 300308
Tel: +86 022-59896226
www.memsic.com
MEMSIC MC3635 APS-048-0044 v1.8
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TABLE OF CONTENTS
1
Order Information............................................................................................................. 5
2
Functional Block Diagram ................................................................................................ 6
3
Packaging and Pin Description ........................................................................................ 7
3.1
Package Outline ................................................................................................................... 7
3.2
Package Orientation ............................................................................................................. 8
3.3
Pin Description ..................................................................................................................... 9
3.4
Typical Application Circuits ................................................................................................ 10
3.5
Tape and Reel ................................................................................................................... 13
3.6
Soldering Profile ................................................................................................................. 15
3.7
Shipping and Handling Guidelines ..................................................................................... 15
3.8
Moisture Sensitivity Level Control ...................................................................................... 15
4
Specifications................................................................................................................. 16
4.1
Absolute Maximum Ratings ................................................................................................ 16
4.2
Sensor Characteristics ....................................................................................................... 17
4.3
Electrical and Timing Characteristics.................................................................................. 18
4.3.1
Electrical Power and Internal Characteristics .................................................................. 18
4.3.2
Electrical Characteristics ................................................................................................ 19
4.3.3
I2C Timing Characteristics .............................................................................................. 20
4.3.4
SPI Timing Characteristics.............................................................................................. 21
5
General Operation ......................................................................................................... 22
5.1
Sensor Sampling ................................................................................................................ 22
5.2
Offset and Gain Calibration ................................................................................................ 22
5.3
Reset ................................................................................................................................. 22
5.4
Reload ............................................................................................................................... 23
5.5
Operational Modes ............................................................................................................. 24
5.6
Mode State Machine Flow .................................................................................................. 25
6
Interfaces ....................................................................................................................... 26
6.1
SPI vs I2C Operation Modes .............................................................................................. 26
6.2
I2C Physical Interface ........................................................................................................ 26
6.3
I2C Message Format .......................................................................................................... 27
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6.4
SPI Physical Interface ........................................................................................................ 28
6.5
SPI 3-Wire Mode ................................................................................................................ 28
6.6
SPI Protocol ....................................................................................................................... 28
6.7
SPI Register Write Cycle - Single ....................................................................................... 29
6.8
SPI Register Write Cycle - Burst ........................................................................................ 29
6.9
SPI Register Read Cycle - Single ....................................................................................... 29
6.10
SPI Register Read Cycle - Burst ........................................................................................ 30
6.11
SPI Status Option............................................................................................................... 30
6.12
SPI High-Speed Mode........................................................................................................ 31
7
Register Interface .......................................................................................................... 32
7.1
Register Summary ............................................................................................................. 33
7.2
(0x00) Extended Status Register 1 ..................................................................................... 35
7.3
(0x01) Extended Status Register 2 ..................................................................................... 36
7.4
(0x02 – 0x07) XOUT, YOUT & ZOUT Data Output Registers ............................................. 37
7.5
(0x08) Status Register 1..................................................................................................... 38
7.6
(0x09) Status Register 2..................................................................................................... 40
7.7
(0x0D) Feature Register 1 .................................................................................................. 42
7.8
(0x0E) Feature Register 2 .................................................................................................. 44
7.9
(0x0F) Initialization Register 1 ............................................................................................ 47
7.10
(0x10) Mode Control Register ............................................................................................ 48
7.11
(0x11) Rate Register 1 ....................................................................................................... 50
7.12
(0x12) Sniff Control Register .............................................................................................. 52
7.13
(0x13) Sniff Threshold Control Register ............................................................................. 55
7.14
(0x14) Sniff Configuration Register .................................................................................... 58
7.15
(0x15) Range and Resolution Control Register .................................................................. 60
7.16
(0x16) FIFO Control Register ............................................................................................. 62
7.17
(0x17) Interrupt Control Register ........................................................................................ 63
7.18
(0x1A) Initialization Register 3 ............................................................................................ 65
7.19
(0x1B) Scratchpad Register ............................................................................................... 66
7.20
(0x1C) Power Mode Control Register ................................................................................. 67
7.21
(0x20) Drive Motion X Register .......................................................................................... 69
7.22
(0x21) Drive Motion Y Register .......................................................................................... 70
7.23
(0x22) Drive Motion Z Register........................................................................................... 71
7.24
(0x24) Reset Register ........................................................................................................ 72
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7.25
(0x28) Initialization Register 2 ............................................................................................ 73
7.26
(0x29) Trigger Count Register ............................................................................................ 74
7.27
(0x2A – 0x2B) X-Axis Offset Registers ............................................................................... 75
7.28
(0x2C – 0x2D) Y-Axis Offset Registers .............................................................................. 76
7.29
(0x2E – 0x2F) Z-Axis Offset Registers ............................................................................... 77
7.30
(0x2B & 0x30) X-Axis Gain Registers ................................................................................. 78
7.31
(0x2D & 0x31) Y-Axis Gain Registers................................................................................. 79
7.32
(0x2F & 0x32) Z-Axis Gain Registers ................................................................................. 80
8
Index of Tables .............................................................................................................. 81
9
Revision History ............................................................................................................. 83
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1 ORDER INFORMATION
Table 1. Order Information
Part Number
Resolution
Order Number
Package
Shipping
MC3635
8 to 14-bit
MC3635
LGA-10
Tape & Reel, 5Ku
Table 2. Top Marking Specification
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2 FUNCTIONAL BLOCK DIAGRAM
VDDIO
Regulators
and Bias
Sensors
Oscillator/
Clock
Generator
X
Interrupt
Mode Logic
SCK_SCL
Event Sniff
VDD
14
Y
C to V
A/D Converter
(Sigma Delta)
Offset/
Gain
Adjust
Registers
(64 x 8)
Range &
Scale
SPI / I2C
Slave
Interface
FIFO
12
Z
DIN_SDA
DOUT_A1
status
X,Y,Z
data paths
GND
INTN
CSN
OTP
Memory
VPP
Figure 1. Block Diagram
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3 PACKAGING AND PIN DESCRIPTION
3.1 PACKAGE OUTLINE
SYMBOL COMMON DIMENSIONS
MIN. NOR. MAX.
TOTAL THICKNESS
A
0.88 0.94
1
D
1.6 BSC
BODY SIZE
E
1.6 BSC
LEAD WIDTH
W
0.15
0.2
0.25
LEAD LENGTH
L
0.25
0.3
0.35
e
0.4 BSC
LEAD PITCH
n
10
LEAD COUNT
D1
1.2 BSC
EDGE LEAD CENTER TO CENTER
E1
1.1 BSC
BODY CENTER TO CONTACT LEAD
SD
0.2 BSC
aaa
0.07
PACKAGE EDGE TOLERANCE
bbb
0.2
MOLD FLATNESS
ddd
0.08
COPLANARITY
NOTES:
1 PARALLELISM MEASUREMENT SHALL EXCLUDE ANY
EFFECT OF MARK ON TOP SURFACE OF PACKAGE.
Figure 2. Package Outline and Mechanical Dimensions
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3.2 PACKAGE ORIENTATION
Top View
a.
Direction of
Earth gravity
acceleration
Top
Pin 1
Side View
e.
b.
XOUT = +1g
YOUT = 0g
ZOUT = 0g
c.
XOUT = 0g
YOUT = 0g
ZOUT = +1g
f.
XOUT = 0g
YOUT = -1g
ZOUT = 0g
d.
XOUT = 0g
YOUT = +1g
ZOUT = 0g
XOUT = 0g
YOUT = 0g
ZOUT = -1g
XOUT = -1g
YOUT = 0g
ZOUT = 0g
Figure 3. Package Orientation
+Z
+X
+Y
-Y
-X
-Z
Figure 4. Package Axis Reference
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3.3 PIN DESCRIPTION
Pin
Name
Function
1
DOUT_A1
2
DIN_SDA 1
3
NC
No connect
4
VPP
Connect to GND
5
INTN 2
6
VDDIO
Power supply for interface
7
VDD
Power supply for internal
8
GND
Ground
9
CSN
SPI Chip Select
10
SCK_SCL 1
SPI Clock
I2C serial clock input
SPI data output
I2C address bit 1
SPI data In
I2C serial data input/output
Interrupt active LOW
3
Table 3. Pin Description
Notes:
1) When using the I2C interface, this pin requires a pull-up resistor, typically 4.7kΩ to pin
VDDIO. Refer to I2C Specification for Fast-Mode devices. Higher resistance values can
be used (typically done to reduce current leakage) but such applications are outside the
scope of this datasheet.
2) This pin can be configured by software to operate either as an open-drain output or
push-pull output. If set to open-drain, then it requires a pull-up resistor, typically 4.7kΩ to
pin VDDIO.
3) INTN pin polarity is programmable.
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3.4 TYPICAL APPLICATION CIRCUITS
}
To Fast-Mode I2C
circuitry1
10
SCK_SCL
Rp
Rp
1
2
3
4
DOUT_A1
CSN
DIN_SDA
GND
NC
VDD
VPP
VDDIO
9
8
7
6
0.1µF
Rp
(optional) To MCU
interrupt input2
From power
supply
INTN
Place cap close
to VDD and
GND on PCB
5
NOTE1: Rp are typically 4.7kΩ pullup resistors to VDDIO, per I2C specification. When VDDIO
is powered down, DIN_SDA and SCK_SCL will be driven low by internal ESD diodes.
NOTE2: Attach typical 4.7kΩ pullup resistor if INTN is defined as open-drain.
Figure 5. Typical I2C Application Circuit
In typical applications, the interface power supply may contain significant noise from external
sources and other circuits which should be kept away from the device. Therefore, for some
applications a lower-noise power supply might be desirable to power the device.
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To 4-wire
SPI master
10
SCK_SCL
1
2
3
4
DOUT_A1
CSN
DIN_SDA
GND
NC
VDD
VPP
VDDIO
9
8
7
6
0.1µF
From
power
supply
INTN
(optional)
To MCU
interrupt input
Place cap close
to VDD and
GND on PCB
5
Rp
NOTE Rp: Attach typical 4.7kΩ pullup resistor if INTN is defined as open-drain.
Figure 6. Typical 4-wire SPI Application Circuit
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To 3-wire
SPI master
10
SCK_SCL
1
2
3
4
DOUT_A1
CSN
DIN_SDA
GND
NC
VDD
VPP
VDDIO
9
8
7
6
0.1µF
From
power
supply
INTN
(optional)
To MCU
interrupt input
Place cap close
to VDD and
GND on PCB
5
Rp
NOTE Rp: Attach typical 4.7kΩ pullup resistor if INTN is defined as open-drain.
Figure 7. Typical 3-wire SPI Application Circuit
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3.5 TAPE AND REEL
Devices are shipped in reels, in standard cardboard box packaging. See Figure 8. MC3635
Tape Dimensions and Figure 9. MC3635 Reel Dimensions.
Figure 8. MC3635 Tape Dimensions
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Dimensions in mm.
Figure 9. MC3635 Reel Dimensions
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3.6 SOLDERING PROFILE
The LGA package follows the reflow soldering classification profiles described in Joint Industry
Standard, Moisture/Reflow Sensitivity Classification for Nonhermetic Surface Mount Devices,
document number J-STD-020E. Reflow soldering has a peak temperature (Tp) of 260⁰C
3.7 SHIPPING AND HANDLING GUIDELINES
Shipping and handling follow the standards described in Joint Industry Standard, Handling,
Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices, document
number J-STD-033C.
The following are additional handling guidelines (refer to the MEMSIC document, PCB Design,
Device Handling and Assembly Guidelines, for more information):
While the mechanical sensor is designed to handle high-g shock events, direct
mechanical shock to the package should be avoided.
SMT assembly houses should use automated assembly equipment with either plastic
nozzles or nozzles with compliant tips (for example, soft rubber or silicone).
Avoid g-forces beyond the specified limits during transportation.
Handling and mounting of sensors should be done in a defined and qualified installation.
3.8 MOISTURE SENSITIVITY LEVEL CONTROL
The Moisture Sensitivity Level, MSL, for MC3635 (10-pin LGA package) is MSL3.
Refer to IPC/JEDEC J-STD-020D.1 “Joint Industry Standard: Moisture/Reflow Sensitivity
Classification for Non-hermetic Solid State Surface Mount Devices” and IPC/JEDEC J
STD033A “Joint Industry Standard: Handling, Packing, Shipping and Use of Moisture/Reflow
Sensitive Surface Mount Devices.”
The following are storage recommendations (refer to the MEMSIC document, PCB Design,
Device Handling and Assembly Guidelines, for more information):
Store the tape and reel in the unopened dry pack, until required on the assembly floor.
If the dry pack has been opened or the reel has been removed from the dry pack, reseal
the reel inside of the dry pack with a black protective belt. Avoid crushing the tape and
reel.
Store the cardboard box in a vertical position.
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4 SPECIFICATIONS
4.1 ABSOLUTE MAXIMUM RATINGS
Parameters exceeding the Absolute Maximum Ratings may permanently damage the device.
Minimum / Maximum
Value
Unit
Pins VDD,
VDDIO
-0.3 / +3.6
V
Acceleration, any axis, 100 µs
g MAX
10000
g
Ambient operating temperature
TOP
-40 / +85
⁰C
Storage temperature
TSTG
-40 / +125
⁰C
ESD human body model
HBM
± 2000
V
Input voltage to non-power pin
Pins CSN,
DIN_SDA,
DOUT_A1,
INTN, and
SCK_SCL
-0.3 / (VDDIO + 0.3) or
3.6 whichever is lower
V
Rating
Symbol
Supply Voltages
Table 4. Absolute Maximum Ratings
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4.2 SENSOR CHARACTERISTICS
VDD = VDDIO = 1.8V, Top = 25 ⁰C unless otherwise noted
Parameter
Conditions
Min
Typ
Max
Unit
±2
±4
Acceleration
range
±8
g
±12
±16
Sensitivity
Sensitivity
Temperature
Coefficient 1
Zero-g Offset
Zero-g Offset
Temperature
Coefficient 1
8
Post-board mount, ODR 0x04)
Current (µA)
(Hz)
CWAKE ODR
(Hz)
Current (µA)
14
1
14
5
0x06
25
0.9
28
1.6
28
10
0x07
50
1.6
54
2.7
55
18
0x08
100
2.8
105
5
80
25
0x09
190
5.5
210
11
n/a
0x0A
380
10
400
19
n/a
0x0B
750
18
600
26
n/a
0x0C
1100
26
0x0F*NOTE
1300
36
n/a
750
R/W
n/a
36
100
36
Table 24. Rate Register 1 Settings
NOTE: Specific setup steps are required in order to set up Register 0x11 value 0x0F (“Rate
15”), as shown below. These steps are not required when using the other modes:
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Values To Be Written
Step
Write Register
Address
1
0x10
0x01
2
0x15
(0x04 or other)
3
0x16
(0x5D or other)
4
0x1C
5
0x11
0x10
Point to set wake/sniff settings
6
0x29
0x03
Rate 15 setup 1 for CWAKE
7
0x11
0x20
Rate 15 setup 2 for CWAKE
8
0x29
0x01
Rate 15 setup 3 for CWAKE
9
0x11
0x40
Point to value 1
10
0x29
11
0x11
12
0x29
13
0x11
0x0F
Apply the values
14
0x10
0x05
Go to CWAKE
ULP
LP
0x03
0x52
0x00
0x72
Precision
Go to standby
0x04
0x32
0x50
0x01
0x02
Comment
Choose mode
Write value 1
Point to value 2
0x12
Write value 2
Table 25. Setup Steps for CWAKE Using “Rate 15”
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7.12 (0X12) SNIFF CONTROL REGISTER
This register selects the sample rate for SNIFF mode and the clock rate for STANDBY mode.
NOTE: The power mode bits referenced in 0x1C are different than for the WAKE rates.
NOTE: Software must always write 0 to bit 4.
Bit
Addr
Name
7
0x12
SNIFF_C
6
5
4
STB_RATE[2] STB_RATE[1] STB_RATE[0]
3
2
1
0
POR
Value
SNIFF_SR SNIFF_SR SNIFF_SR SNIFF_SR
00000000
[3]
[2]
[1]
[0]
0
Bit
Name
Description
[3:0]
SNIFF_SR[3:0]
Approximate typical maximum clock rate
R/W
RW
when trigger count > 1 (Hz)
Ultra-Low Power
Low Power
Precision
Bit Field
(0x1C[6:4]=>0x03)
(0x1C[6:4]=>0x00)
(0x1C[6:4]=>0x04)
0000
(default)
6
7
7
0001
0.4
0.4
0.2
0010
0.8
0.8
0.4
0011
1.5
1.5
0.9
0100
6
7
7
0101
13
14
14
0110
25
28
28
0111
50
54
55
1000
100
105
80
1001
190
210
n/a
1010
380
400
n/a
1011
750
600
n/a
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4
0
[7:5]
STB_RATE[2:0]
1100
1100
n/a
n/a
1101
n/a
n/a
n/a
1110
n/a
n/a
n/a
1111*NOTE
1300
750
100
Software must always write 0 to this bit.
Approximate typical maximum clock rate
when trigger count > 1 (Hz)
Ultra-Low Power
Low Power
Precision
Bit Field
(0x1C[6:4]=>0x03)
(0x1C[6:4]=>0x00)
(0x1C[6:4]=>0x04)
000
(default)
1
0.5
0.1
001
3
1
0.2
010
5
3
0.4
011
10
6
0.8
100
23
12
1.5
101
45
24
3
110
90
48
5
111
180
100
10
Table 26. Sniff Control Register Settings
NOTE: Specific setup steps are required in order to set up Register 0x12 value 0x0F (“Rate
15”) for sniff, as shown below. These steps are not required when using the other modes:
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Step
Write
Register
Address
Values To Be Written
1
0x10
0x01
2
0x15
(0x04 or other)
3
0x16
(0x5D or other)
4
0x1C
5
0x11
0x10
Point to set wake/sniff settings
6
0x29
0x30
Rate 15 setup 1 for sniff
7
0x11
0x30
Rate 15 setup 2 for sniff
8
0x29
0x01
Rate 15 setup 3 for sniff
9
0x11
0x60
Point to value 1
10
0x29
11
0x11
12
0x29
13
0x11
0x0F
Apply the values
14
0x10
0x02
Go to sniff
ULP
0x30
0x52
LP
Precision
0x00
0x72
Go to standby
0x40
0x32
0x70
0x01
0x02
Comment
Choose mode
Write value 1
Point to value 2
0x12
Write value 2
Table 27. Setup Steps For Sniff Using “Rate 15”
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7.13 (0X13) SNIFF THRESHOLD CONTROL REGISTER
This register sets the threshold values used by the SNIFF logic for activity detection. For each
axis, a delta count is generated and compared to the threshold. When the delta count is
greater than the threshold, a SNIFF wakeup event occurs. There is a unique sniff threshold for
each axis, and an optional “false detection count” which requires multiple sniff detection events
to occur before a wakeup condition is declared. These features are set by six shadow registers
accessed by register 0x13[5:0] and register 0x14 bits [2:0].
The SNIFF block supports the logical AND or OR of the X/Y/Z SNIFF wakeup flags when
generating a SNIFF wakeup interrupt.
The SNIFF block supports two methods of calculating SNIFF delta counts:
Current Sample to Previous Sample (C2P)
o The current sample and the immediate previous sample are subtracted to
generate a delta
Current Sample to Baseline (C2B)
o The current sample and the first sample captured when entering SNIFF mode
are subtracted to generate a delta.
Bit
Addr
Name
7
6
5
4
3
2
1
0x13
SNIFFTH_C
SNIFF_
MODE
SNIFF_
AND_OR
SNIFF_TH[5]
SNIFF_TH[4]
SNIFF_TH[3]
SNIFF_TH[2]
SNIFF_TH[1]
Bit
[5:0]
Name
SNIFF_TH[5:0]
0
POR
Value
SNIFF_TH[0] 00000000
R/W
RW
Description
This 6-bit field accesses six shadow registers behind address
0x13. Register 0x14 bits [2:0] control which register is accessed.
Reg 0x14
Reg 0x13
SNIFF_T_ADDR[2:0]
SNIFF_TH[5:0]
000
None
001
SNIFF Threshold, X-axis
SNIFF_TH_X[5:0], unsigned threshold
value 0 to 63 (independent from Y and
Z thresholds).
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010
SNIFF Threshold, Y-axis
SNIFF_TH_Y[5:0], unsigned threshold
value 0 to 63 (independent from X and
Z thresholds).
011
SNIFF Threshold, Z-axis
SNIFF_TH_Z[5:0], unsigned threshold
value 0 to 63 (independent from X and
Y thresholds).
100
None
101
SNIFF Detection Count, X-axis
SNIFF_X_COUNT[5:0], unsigned SNIFF
event count, 1 to 62 events,
independent from other channels. The
detection count is COUNT-1 for the
desired number of events (for 1 event
= 1-1 => 0 loaded into register).
110
SNIFF Detection Count, Y-axis
SNIFF_Y_COUNT[5:0], unsigned SNIFF
event count, 1 to 62 events,
independent from other channels. The
detection count is COUNT-1 for the
desired number of events (for 1 event
= 1-1 => 0 loaded into register).
111
SNIFF Detection Count, Z-axis
SNIFF_Z_COUNT[5:0], unsigned SNIFF
event count, 1 to 62 events,
independent from other channels. The
detection count is COUNT-1 for the
desired number of events (for 1 event
= 1-1 => 0 loaded into register).
MEMSIC MC3635 APS-048-0044 v1.8
Page 56 of 83
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6
SNIFF_AND_OR
Sets the logical mode for combining of X/Y/Z SNIFF wakeup
events before an interrupt is generated. To remove one of the
channels (axis) from the equation, use the corresponding axis PD
bit in register 0x10 bits [6:4].
0: OR - SNIFF wakeup/interrupt is triggered when any of the
active channels have met detection threshold and count
requirements (default).
Sniff Wakeup =
Δ(abs(X) – X Sniff Threshold) or
Δ(abs(Y) – Y Sniff Threshold) or
Δ(abs(Z) – Z Sniff Threshold)
1: AND - SNIFF wakeup/interrupt is triggered when all active
channels have met detection threshold and count requirements.
Sniff Wakeup =
Δ(abs(X) – X Sniff Threshold) and
Δ(abs(Y) – Y Sniff Threshold) and
Δ(abs(Z) – Z Sniff Threshold)
7
SNIFF_MODE
This bit determines how the SNIFF block computes its delta
count.
0: C2P Mode (Current to Previous): The delta count between
current and previous samples is a moving window. The SNIFF
logic uses the current sample and the immediate previous
sample to compute a delta (default).
1: C2B Mode (Current to Baseline): The delta count is generated
from subtracting the current sample from the first sample stored
when entering SNIFF mode.
Table 28. Sniff Threshold Control Register Settings
MEMSIC MC3635 APS-048-0044 v1.8
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7.14 (0X14) SNIFF CONFIGURATION REGISTER
This register selects which of the six shadow registers is being accessed in register 0x13, and
controls settings of the SNIFF hardware.
Bit
Addr
Name
7
6
5
4
3
2
1
0
POR
Value
0x14
SNIFFCF_C
SNIFF_
RESET
SNIFF_
MUX[2]
SNIFF_
MUX[1]
SNIFF_
MUX[0]
SNIFF_
CNTEN
SNIFF_
THADR[2]
SNIFF_
THADR[1]
SNIFF_
THADR[0]
00000
000
Bit
Name
[2:0]
SNIFF_ THADR[2:0]
3
SNIFF_ CNTEN
R/W
RW
Description
Bit Field
Register selected by 0x13[5:0]
000
None
001
SNIFF Threshold, X-axis
010
SNIFF Threshold, Y-axis
011
SNIFF Threshold, Z-axis
100
None
101
SNIFF Detection Count, X-axis
110
SNIFF Detection Count, Y-axis
111
SNIFF Detection Count, Z-axis
This bit enables the SNIFF detection counts for all channels.
0: Do not use SNIFF detection counters. (default)
1: Enable SNIFF detection counts, required for valid SNIFF
wakeup
[6:4]
SNIFF_ MUX[2:0]
MEMSIC MC3635 APS-048-0044 v1.8
This field determines which 6-bits of the 11-bit delta count
will be compared against the 6-bit threshold value for each
channel. Clamp logic allows any SNIFF delta exceeding the
selected 6-bit range to still be detected as a valid event. See
examples below.
Page 58 of 83
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7
SNIFF_ RESET
Bit Field
Bit range selected
000
DELTA[5:0]
001
DELTA[6:1]
010
DELTA[7:2]
011
DELTA[8:3]
100
DELTA[9:4]
101
DELTA[10:5]
110
DELTA[10:5]
111
DELTA[10:5]
This is the manual reset bit for the SNIFF block. This bit is not
self-clearing, and can be used to re-enable the SNIFF block
after a SNIFF event has been detected in SWAKE mode.
0: SNIFF block reset is not applied (default).
1: SNIFF block reset is applied.
Table 29. Sniff Configuration Register Settings
Some example settings for the SNIFF_MUX field are shown below:
Sniff Noise/Power
Configuration
Ultra-Low Power
Low Power
Precision
Δg
Threshold
[5:0]
Sniff Mux
Sel [2:0]
Low
3
0
Med
10
0
High
28
0
Low
5
0
Med
5
0
High
56
0
X Low
3
0
Low
37
0
Med
37
2
High
56
3
MEMSIC MC3635 APS-048-0044 v1.8
Example Use Case
Human motion detection @ SR = 6.5 Hz and Sniff Mode =
“Current to Baseline”
Tap detection @ SR = 51 Hz and Sniff Mode = “Current to
Previous”
Page 59 of 83
Formal release date: 2020/07/08
7.15 (0X15) RANGE AND RESOLUTION CONTROL REGISTER
The RANGE register sets the resolution and range options for the accelerometer. All numbers
are sign-extended, 2’s complement format. All results are reported in registers 0x02 to 0x07.
When the FIFO is enabled, only 6 to 12-bit resolutions are supported due to the 12-bit width of
the FIFO.
Bit
Addr
Name
7
6
5
4
3
2
1
0
POR Value
R/W
0x15
RANGE_C
RESV
RANGE[2]
RANGE[1]
RANGE[0]
RESV
RES[2]
RES[1]
RES[0]
00000000
RW
Bit
[2:0]
3
[6:4]
Name
RES[2:0]
RESV
RANGE[2:0]
Description
Bit Field
Bit Width of Accelerometer Data
000
6 bits
001
7 bits
010
8 bits
011
10 bits
100
12 bits
101
14 bits (only 12-bits if FIFO enabled)
110
Reserved
111
Reserved
Reserved
Bit Field
G Range Selection
000
±2g
001
±4g
010
±8g
011
±16g
MEMSIC MC3635 APS-048-0044 v1.8
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7
RESV
100
±12g
101
Reserved
110
Reserved
111
Reserved
Reserved
Table 30. Range and Resolution Control Register Settings
MEMSIC MC3635 APS-048-0044 v1.8
Page 61 of 83
Formal release date: 2020/07/08
7.16 (0X16) FIFO CONTROL REGISTER
This register selects the FIFO threshold level, operation mode, FIFO reset and enable. With
the exception of FIFO_RESET, the FIFO_EN bit must be ‘1’ for any FIFO interrupts,
thresholds, or modes to be enabled. The FIFO flags in register 0x08 will continue to report
FIFO defaults even if the FIFO_EN is ‘0’.
Bit
Addr
Name
7
6
5
4
3
2
1
0
POR Value
R/W
0x16
FIFO_C
FIFO_
RESET
FIFO_EN
FIFO_
MODE
FIFO_TH
[4]
FIFO_TH
[3]
FIFO_TH
[2]
FIFO_TH
[1]
FIFO_TH
[0]
00000000
RW
Bit
Name
Description
[4:0]
FIFO_TH[4:0]
The FIFO threshold level selects the number of samples in the FIFO for
different FIFO events. The threshold value may be 1 to 31 (00001 to
11111).
5
FIFO_MODE
0: Normal operation, the FIFO continues to accept new sample data as long
as there is space remaining (default)
1: Watermark, once the amount of samples in the FIFO reaches or exceeds
the threshold level, the FIFO stops accepting new sample data. Any
additional sample data is “dropped”.
6
FIFO_EN
FIFO enable control. All FIFO operations are gated by this bit.
0: No FIFO operation, sample data written directly to output registers.
1: FIFO enabled, all sample data written to FIFO write port if there is room.
The FIFO write clock is controlled by this enable, resulting in higher
dynamic power.
7
FIFO_RESET
Asynchronous FIFO reset.
0: FIFO reset is disabled, normal operation (default)
1: FIFO read and write pointers are cleared, FIFO contents returned to 0
Table 31. FIFO Control Register Settings
MEMSIC MC3635 APS-048-0044 v1.8
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7.17 (0X17) INTERRUPT CONTROL REGISTER
Bit
Addr
Name
7
6
5
4
3
2
1
0
POR Value
R/W
0x17
INTR_C
INT_
SWAKE
INT_FIFO_
THRESH
INT_FIFO_
FULL
INT_FIFO_
EMPTY
INT_ACQ
INT_
WAKE
IAH
IPP
00000000
RW
Bit
Name
Description
0
IPP
INTN pin interrupt pin mode control.
0: INTN pin is configured for open-drain mode (external pullup to
VDDIO required) (default).
1: INTN pin is configured for active drive or “push-pull” mode. Drive
level is to VDDIO.
1
IAH
Interrupt level control, sets the active drive level of the INTN pin.
0: Interrupt request is active low (default).
1: Interrupt request is active high.
2
INT_WAKE
WAKE interrupt (SNIFF to WAKE) enable
0: No interrupt is generated when SNIFF activity is detected and the
device auto-transitions to CWAKE mode (default).
1: Generate an interrupt when activity is detected in SNIFF mode and
the device auto-transitions to CWAKE mode.
3
INT_ACQ
Interrupt on sample or acquisition enable
0: No interrupt generated when new sample data is acquired
(default).
1: Generate an interrupt when new sample data is acquired (applies
to new data written to output registers or FIFO). This enable is paired
with the NEW_DATA flag in register 0x08.
4
INT_FIFO_EMPTY
FIFO empty interrupt enable.
0: No interrupt is generated when the FIFO is empty or completely
drained of sample data (default).
1: Generate an interrupt when the FIFO is empty. This interrupt is
paired with the FIFO_EMPTY flag in register 0x08. Note that this
interrupt is independent of the FIFO threshold level, and will only
activate when the FIFO sample count has reached a value of 0.
MEMSIC MC3635 APS-048-0044 v1.8
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5
INT_FIFO_FULL
FIFO full interrupt enable.
0: No interrupt is generated when the FIFO is empty or completely
filled of sample data (default).
1: Generate an interrupt when the FIFO is full. This interrupt is paired
with the FIFO_FULL flag in register 0x08. Note that this interrupt is
independent of the FIFO threshold level, and will only activate when
the FIFO sample count has reached a value of 32.
6
INT_FIFO_THRESH
FIFO threshold interrupt enable.
0: No interrupt is generated when the FIFO threshold level is reached
(default).
1: Generate an interrupt when the FIFO threshold level is reached.
7
INT_SWAKE
This interrupt is valid only in SWAKE mode.
0: No interrupt generated when SNIFF activity is detected (default).
1: Generate an interrupt when SNIFF activity is detected.
Table 32. Interrupt Control Register Settings
MEMSIC MC3635 APS-048-0044 v1.8
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7.18 (0X1A) INITIALIZATION REGISTER 3
Software must write a fixed value to this register immediately after power-up or reset.
Bit
Addr
Name
7
6
5
4
3
2
1
0
0x1A
INIT_3
0
0
0
0
0
0
0
0
Bit
Name
[7:0]
INIT_3
POR Value R/W
00000000
RW
Description
Software must write ‘0’ to these bits
Table 33. Initialization Register 3 Settings
MEMSIC MC3635 APS-048-0044 v1.8
Page 65 of 83
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7.19 (0X1B) SCRATCHPAD REGISTER
This register can store any 8-bit value and has no effect on hardware.
Bit
Addr
Name
7
6
5
4
3
2
1
0
0x1B
SCRATCH
0
0
0
0
0
0
0
0
Bit
[7:0]
Name
SCRATCH
POR Value R/W
00000000
RW
Description
Any value can be written and read-back.
Table 34. Scratchpad Register
MEMSIC MC3635 APS-048-0044 v1.8
Page 66 of 83
Formal release date: 2020/07/08
7.20 (0X1C) POWER MODE CONTROL REGISTER
This register selects the power setting for CWAKE, SWAKE and SNIFF modes.
Bit
Addr
Name
7
6
5
4
3
2
1
0
POR Value
R/W
0x1C
PMCR
SPI_HS_EN
SPM[2]
SPM[1]
SPM[0]
RESV
CSPM[2]
CSPM[1]
CSPM[0]
00000000
RW
Bit
[2:0]
Name
CSPM
Description
CWAKE, SWAKE Power Mode
000: Low Power Mode (nominal noise levels) (default)
001: Reserved
010: Reserved
011: Ultra-Low Power Mode (highest noise levels)
100: Precision Mode (lowest noise levels)
101: Reserved
110: Reserved
111: Reserved
3
RESV
Reserved
[6:4]
SPM
SNIFF Power Mode
000: Low Power Mode (nominal noise levels) (default)
001: Reserved
010: Reserved
011: Ultra-Low Power Mode (highest noise levels)
100: Precision Mode (lowest noise levels)
101: Reserved
110: Reserved
111: Reserved
7
SPI_HS_EN
SPI High-Speed Enable
0: This bit will always return a ‘0’ when read. Software must keep track
of the state of this bit.
MEMSIC MC3635 APS-048-0044 v1.8
Page 67 of 83
Formal release date: 2020/07/08
Follow sequence from 6.12 SPI High-Speed Mode to enable high-speed
SPI mode.
Table 35. Power Mode Control Register Settings
MEMSIC MC3635 APS-048-0044 v1.8
Page 68 of 83
Formal release date: 2020/07/08
7.21 (0X20) DRIVE MOTION X REGISTER
This register controls the test mode which moves the sensor in the X axis direction and
initializes specific hardware bits.
NOTE: Software must always write 0 to bits [7:4] and 1.
NOTE: Software must always write 1 to bit 0.
Bit
Addr
Name
7
6
5
4
3
2
1
0
0x20
DMX
0
0
0
0
DNX
DPX
0
1
Bit
Name
POR Value R/W
00000000
W
Description
0
1
Reserved. Always write 1 to this bit
1
0
Reserved. Always write 0 to this bit.
2
DPX
0: Disabled (default)
1: Move the sensor in X Positive direction
3
DNX
0: Disabled (default)
1: Move the sensor in X Negative direction
[7:4]
0000
Reserved. Always write 0 to these bits.
Table 36. Drive Motion X Register Settings
MEMSIC MC3635 APS-048-0044 v1.8
Page 69 of 83
Formal release date: 2020/07/08
7.22 (0X21) DRIVE MOTION Y REGISTER
This register controls the test mode which moves the sensor in the Y axis direction and
initializes specific hardware bits.
NOTE: Software must always write 0 to bits [6:4] and [1:0].
NOTE: Software must always write 1 to bit 7 after writing to register 0x20[0].
Bit
Addr
Name
7
6
5
4
3
2
1
0
POR Value R/W
0x21
DMY
1
0
0
0
DNY
DPY
0
0
(See table)
Mode (MCTLR[2:0] bits in MODE_C Register
0x10)
Read-back Value
SNIFF, CWAKE, SWAKE, TRIG
0x80
SLEEP, STANDBY
0x00
RW
Table 37. Register 0x21 Read-Back Value
Bit
[1:0]
2
Name
Description
00
Reserved. Always write 0 to these bits.
DPY
0: Disabled (default)
1: Move the sensor in Y Positive direction
3
DNY
0: Disabled (default)
1: Move the sensor in Y Negative direction
[6:4]
7
000
Reserved. Always write 0 to these bits.
1
Reserved. Always write 1 to this bit.
Table 38. Drive Motion Y Register Settings
MEMSIC MC3635 APS-048-0044 v1.8
Page 70 of 83
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7.23 (0X22) DRIVE MOTION Z REGISTER
This register controls the test mode which moves the sensor in the Z axis direction.
NOTE: Software must always write 0 to bits [7:4] and [1:0].
Bit
Addr
Name
7
6
5
4
3
2
1
0
0x22
DMZ
0
0
0
0
DNZ
DPZ
0
0
Bit
Name
POR Value R/W
00000000
RW
Description
[1:0]
00
Reserved. Always write 0 to these bits.
2
DPZ
0: Disabled (default)
1: Move the sensor in Z Positive direction
3
DNZ
0: Disabled (default)
1: Move the sensor in Z Negative direction
[7:4]
0000
Reserved. Always write 0 to these bits.
Table 39. Drive Motion Z Register Settings
MEMSIC MC3635 APS-048-0044 v1.8
Page 71 of 83
Formal release date: 2020/07/08
7.24 (0X24) RESET REGISTER
This register can be used to reset the device. Anytime there is a reset to the device, a POR
event, or a power cycle the SPI 3-wire configuration will reset to 4-wire mode.
Bit
Addr
Name
7
6
5
4
3
2
1
0
0x24
RESET
RELOAD
RESET
RESV
RESV
RESV
RESV
RESV
RESV
Bit
[5:0]
6
Name
POR Value R/W
00000000
RW
Description
Reserved
Reserved
RESET
0: Normal operation (default)
1: Force a power-on-reset (POR) sequence.
OTP contents are reloaded into registers, AOFS contents are
decompressed, and any other registers are returned to their
default. This bit is self-clearing.
7
RELOAD
0: Normal operation (default)
1: Reloads the registers from OTP.
A RELOAD operation enables OTP core for reading, performs a
complete read of OTP into the register file, and then disables
the OTP. Use register 0x01 bit 5 to monitor the OTP_BUSY bit.
This bit must be cleared by software
Table 40. Reset Register Settings
MEMSIC MC3635 APS-048-0044 v1.8
Page 72 of 83
Formal release date: 2020/07/08
7.25 (0X28) INITIALIZATION REGISTER 2
Software must write a fixed value to this register immediately after power-up or reset.
Bit
Addr
Name
7
6
5
4
3
2
1
0
0x28
INIT_2
0
0
0
0
0
0
0
0
Bit
Name
Description
[7:0]
INIT_2
Software must write ‘0’ to these bits
POR Value R/W
00000000
RW
Table 41. Initialization Register 2 Settings
MEMSIC MC3635 APS-048-0044 v1.8
Page 73 of 83
Formal release date: 2020/07/08
7.26 (0X29) TRIGGER COUNT REGISTER
This register selects the number of samples to be taken after the one-shot trigger is started.
Bit
Addr
Name
7
6
5
4
3
2
1
0
0x29
TRIGC
TRIGC[7]
TRIGC[6]
TRIGC[5]
TRIGC[4]
TRIGC[3]
TRIGC[2]
TRIGC[1]
TRIGC[0]
Bit
[7:0]
Name
TRIGC[7:0]
POR Value R/W
00000000
RW
Description
Selects the number of samples to be captured after the oneshot trigger is started. Range from 1 to 254. When value 255 is
chosen, the device will run continuously until the mode in
register 0x10 is changed.
Table 42. Trigger Register Settings
MEMSIC MC3635 APS-048-0044 v1.8
Page 74 of 83
Formal release date: 2020/07/08
7.27 (0X2A – 0X2B) X-AXIS OFFSET REGISTERS
This register contains a signed 2’s complement 15-bit value applied as an offset adjustment to
the output of the acceleration values, prior to being sent to the OUT_EX registers. The PowerOn-Reset value for each chip is unique and is set as part of factory calibration. If necessary,
this value can be overwritten by software.
NOTE: When modifying these registers with new gain or offset values, software should
perform a read-modify-write type of access to ensure that unrelated bits do not get
changed inadvertently.
Addr
Name
0x2A
XOFFL
0x2B
Bit 7
Bit 6
POR Value
R/W
XOFF[3] XOFF[2] XOFF[1] XOFF[0]
Per chip
W
XOFFH XGAIN[8] XOFF[14] XOFF[13] XOFF[12] XOFF[11] XOFF[10] XOFF[9] XOFF[8]
Per chip
W
XOFF[7] XOFF[6]
Bit 5
Bit 4
XOFF[5]
XOFF[4]
Bit 3
Bit 2
Bit 1
Bit 0
Table 43. X-Axis Offset Registers
MEMSIC MC3635 APS-048-0044 v1.8
Page 75 of 83
Formal release date: 2020/07/08
7.28 (0X2C – 0X2D) Y-AXIS OFFSET REGISTERS
This register contains a signed 2’s complement 15-bit value applied as an offset adjustment to
the output of the acceleration values, prior to being sent to the OUT_EX registers. The PowerOn-Reset value for each chip is unique and is set as part of factory calibration. If necessary,
this value can be overwritten by software.
NOTE: When modifying these registers with new gain or offset values, software should
perform a read-modify-write type of access to ensure that unrelated bits do not get
changed inadvertently.
Bit 2
Bit 1
Bit 0
POR
Value
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
R/W
0x2C
YOFFL
YOFF[7]
YOFF[6]
YOFF[5]
YOFF[4]
YOFF[3]
YOFF[2] YOFF[1] YOFF[0] Per chip
W
0x2D
YOFFH YGAIN[8] YOFF[14] YOFF[13] YOFF[12] YOFF[11] YOFF[10] YOFF[9] YOFF[8] Per chip
W
Table 44. Y-Axis Offset Registers
MEMSIC MC3635 APS-048-0044 v1.8
Page 76 of 83
Formal release date: 2020/07/08
7.29 (0X2E – 0X2F) Z-AXIS OFFSET REGISTERS
This register contains a signed 2’s complement 15-bit value applied as an offset adjustment to
the output of the acceleration values, prior to being sent to the OUT_EX registers. The PowerOn-Reset value for each chip is unique and is set as part of factory calibration. If necessary,
this value can be overwritten by software.
NOTE: When modifying these registers with new gain or offset values, software should
perform a read-modify-write type of access to ensure that unrelated bits do not get
changed inadvertently.
Addr
Name
Bit 7
0x2E
ZOFFL ZOFF[7]
Bit 6
Bit 5
ZOFF[6]
ZOFF[5]
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR Value
R/W
ZOFF[4] ZOFF[3] ZOFF[2] ZOFF[1] ZOFF[0]
Per chip
W
0x2F ZOFFH ZGAIN[8] ZOFF[14] ZOFF[13] ZOFF[12] ZOFF[11] ZOFF[10] ZOFF[9] ZOFF[8]
Per chip
W
Table 45. Z-Axis Offset Registers
MEMSIC MC3635 APS-048-0044 v1.8
Page 77 of 83
Formal release date: 2020/07/08
7.30 (0X2B & 0X30) X-AXIS GAIN REGISTERS
The gain value is an unsigned 9-bit number.
NOTE: When modifying these registers with new gain or offset values, software should
perform a read-modify-write type of access to ensure that unrelated bits do not get
changed inadvertently.
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x2B XOFFH XGAIN[8] XOFF[14] XOFF[13] XOFF[12] XOFF[11] XOFF[10] XOFF[9] XOFF[8]
0x30
XGAIN
XGAIN[7] XGAIN[6] XGAIN[5] XGAIN[4] XGAIN[3] XGAIN[2] XGAIN[1] XGAIN[0]
POR Value
R/W
Per chip
W
Per chip
W
Table 46. X-Axis Gain Registers
MEMSIC MC3635 APS-048-0044 v1.8
Page 78 of 83
Formal release date: 2020/07/08
7.31 (0X2D & 0X31) Y-AXIS GAIN REGISTERS
The gain value is an unsigned 9-bit number.
NOTE: When modifying these registers with new gain or offset values, software should
perform a read-modify-write type of access to ensure that unrelated bits do not get
changed inadvertently.
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0x2D YOFFH YGAIN[8] YOFF[14] YOFF[13] YOFF[12] YOFF[11] YOFF[10] YOFF[9]
0x31
YGAIN
Bit 0
POR Value
R/W
YOFF[8]
Per chip
W
Per chip
W
YGAIN[7] YGAIN[6] YGAIN[5] YGAIN[4] YGAIN[3] YGAIN[2] YGAIN[1] YGAIN[0]
Table 47. Y-Axis Gain Registers
MEMSIC MC3635 APS-048-0044 v1.8
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7.32 (0X2F & 0X32) Z-AXIS GAIN REGISTERS
The gain value is an unsigned 9-bit number.
NOTE: When modifying these registers with new gain or offset values, software should
perform a read-modify-write type of access to ensure that unrelated bits do not get
changed inadvertently.
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR Value
R/W
ZOFF[8]
Per chip
W
ZGAIN ZGAIN[7] ZGAIN[6] ZGAIN[5] ZGAIN[4] ZGAIN[3] ZGAIN[2] ZGAIN[1] ZGAIN[0]
Per chip
W
0x2F ZOFFH ZGAIN[8] ZOFF[14] ZOFF[13] ZOFF[12] ZOFF[11] ZOFF[10] ZOFF[9]
0x32
Table 48. Z-Axis Gain Registers
MEMSIC MC3635 APS-048-0044 v1.8
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8 INDEX OF TABLES
Table 1. Order Information ..................................................................................................................... 5
Table 2. Top Marking Specification ........................................................................................................ 5
Table 3. Pin Description ......................................................................................................................... 9
Table 4. Absolute Maximum Ratings.................................................................................................... 16
Table 5. Sensor Characteristics ........................................................................................................... 17
Table 6. Electrical Characteristics – Voltage and Current .................................................................... 18
Table 7. Electrical Characteristics – Interface ...................................................................................... 19
Table 8. I2C Timing Characteristics ..................................................................................................... 20
Table 9. SPI Interface Timing Parameters ........................................................................................... 21
Table 10. Recommended Initialization Sequence for I2C Interface ...................................................... 22
Table 11. Recommended Initialization Sequence for SPI Interface ...................................................... 23
Table 12. Operational Modes ............................................................................................................... 24
Table 13. I2C Address Selection .......................................................................................................... 26
Table 14. Register Summary ............................................................................................................... 34
Table 15. Extended Status Register 1 Settings .................................................................................... 35
Table 16. Extended Status Register 2 Settings .................................................................................... 36
Table 17. XOUT, YOUT, ZOUT Data Output Registers........................................................................ 37
Table 18. Status Register 1 Settings .................................................................................................... 39
Table 19. Status Register 2 Settings .................................................................................................... 41
Table 20. Feature Register 1 Settings.................................................................................................. 43
Table 21. Feature Register 2 Settings.................................................................................................. 46
Table 22. Initialization Register 1 Settings ........................................................................................... 47
Table 23. Mode Control Register Settings............................................................................................ 49
Table 24. Rate Register 1 Settings ...................................................................................................... 50
Table 25. Setup Steps for CWAKE Using “Rate 15” ............................................................................. 51
Table 26. Sniff Control Register Settings ............................................................................................. 53
Table 27. Setup Steps For Sniff Using “Rate 15” ................................................................................. 54
Table 28. Sniff Threshold Control Register Settings ............................................................................. 57
Table 29. Sniff Configuration Register Settings .................................................................................... 59
Table 30. Range and Resolution Control Register Settings ................................................................. 61
Table 31. FIFO Control Register Settings ............................................................................................ 62
Table 32. Interrupt Control Register Settings ....................................................................................... 64
Table 33. Initialization Register 3 Settings ........................................................................................... 65
MEMSIC MC3635 APS-048-0044 v1.8
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Table 34. Scratchpad Register............................................................................................................. 66
Table 35. Power Mode Control Register Settings................................................................................. 68
Table 36. Drive Motion X Register Settings.......................................................................................... 69
Table 37. Register 0x21 Read-Back Value .......................................................................................... 70
Table 38. Drive Motion Y Register Settings.......................................................................................... 70
Table 39. Drive Motion Z Register Settings .......................................................................................... 71
Table 40. Reset Register Settings ....................................................................................................... 72
Table 41. Initialization Register 2 Settings ........................................................................................... 73
Table 42. Trigger Register Settings...................................................................................................... 74
Table 43. X-Axis Offset Registers ........................................................................................................ 75
Table 44. Y-Axis Offset Registers ........................................................................................................ 76
Table 45. Z-Axis Offset Registers ........................................................................................................ 77
Table 46. X-Axis Gain Registers .......................................................................................................... 78
Table 47. Y-Axis Gain Registers .......................................................................................................... 79
Table 48. Z-Axis Gain Registers .......................................................................................................... 80
MEMSIC MC3635 APS-048-0044 v1.8
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9 REVISION HISTORY
Date
Revision
Description
2015-10
2015-12
2015-12
APS-048-0044v1.0
APS-048-0044v1.1
APS-048-0044v1.2
2016-02
APS-048-0044v1.3
2017-03
2017-09
APS-048-0044v1.4
APS-048-0044v1.5
2019-02
2019-11
2020-06
APS-048-0044v1.6
APS-048-0044v1.7
APS-048-0044v1.8
First release.
Added register details.
Updated SPI clock speed parameters. Corrected pinouts in table. Added
scratchpad register. Corrected some typos.
Updated 5.3 initialization sequence. Updated Rate 15 sequences for CWAKE and
SNIFF.
Updated SPI clock speed and added description of sequence.
Added soldering profile, shipping and handling guidelines, moisture sensitivity
level control
Fixed a typo by changing “Sensitivity Temperature Coefficient” from 0.15 to
0.015 %/⁰C
Updated Zero-g Offset condition
Updated SPI initialization sequence (Table 11)
Add MSL3 spec to section 3.8.
Change to MEMSIC format based on the License Agreement with mCube
MEMSIC MC3635 APS-048-0044 v1.8
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