MC20902

MC20902 MC20902 FPGA Bridge IC for MIPI D-PHY Systems and LVDS to SLVS Conversion DATASHEET Version 1.07 August 2016 Meticom GmbH Meticom Page 1 of 17 MC20902 Revision History MC20902 Version Date of Issue 1.00 May 31, 2013 1.01 June 04, 2013 1.02 June 07, 2013 1.03 August 22, 2013 • Table 3, Table 4: values updated 1.04 March 14, 2014 • BTA description details added 1.05 April 4, 2014 1.06 August 19, 2014 1.07 August 11, 2016 Meticom Change • First Draft • • • • • Table 7, correct data, Definition for BTA Minor changes in drawings Corrected supply current IDD / IDDIO (Table 3) Added LP supply current (Table 3) • Package drawing update • Application note added - input to output signal diagram • Table 4: Propagation delay and delay mismach added • Package dimensions updated • Figure 5: Signal name error corrected • ‘Preliminary’ status of data sheet removed • Chapter 6.8 Figure number corrected Page 2 of 17 MC20902 Table of Contents 1   General Description ........................................................................................................................ 4   2   Key Features ................................................................................................................................... 4   3   Block Diagram ................................................................................................................................. 5   3.1   Block Diagram ........................................................................................................................... 5   4   Parametrics ..................................................................................................................................... 6   4.1   Absolute Maximum Ratings ....................................................................................................... 6   4.2   Recommended Operating Conditions ....................................................................................... 6   4.3   DC Characteristics..................................................................................................................... 7   4.4   AC Characteristics ..................................................................................................................... 8   5   Package Information ....................................................................................................................... 9   5.1   TQLMP-48 Package .................................................................................................................. 9   5.2   Pin Description .......................................................................................................................... 9   5.3   Package Information................................................................................................................ 11   6   Application Notes ......................................................................................................................... 12   6.1   Application Overview ............................................................................................................... 12   6.2   FPGA to D-PHY Bridge Application......................................................................................... 13   6.3   FPGA to D-PHY Bridge Application with Bus Turnaround ...................................................... 14   6.4   Signal Levels ........................................................................................................................... 15   6.4.1   HS-X-P and HS-X-N LVDS Inputs *) ................................................................................ 15   6.4.2   LP-X-P and LP-X-N CMOS Inputs *) ................................................................................ 15   6.4.3   D-PHY-X-P and D-PHY-X-N Outputs *) ........................................................................... 15   6.4.4   GPIO-0, GPIO-1, BTA, PINSWAP CMOS inputs ............................................................. 15   6.5   Configuration Using GPIO-0 and GPIO-1................................................................................ 15   6.6   Configuration Using BTA ......................................................................................................... 15   6.7   Configuration Using PINSWAP ............................................................................................... 15   6.8   Input to Output Signal Diagram ............................................................................................... 16   7   Legal Disclaimer Notice ............................................................................................................... 17   8   Contact Information ...................................................................................................................... 17   Meticom Page 3 of 17 MC20902 1 General Description The MC20902 is a 5 Channel, high performance FPGA bridge IC, which converts incoming LVDS high speed and incoming CMOS low speed data streams into a MIPI D-PHY compliant output stream. The MC20902 can also convert an LVDS signal into an SLVS signal. The MC20902 can be connected to any signal source, for example FPGAs or DSPs. Data rates can be from 0 Mbps to 2.5 Gbps in HS (High Speed) mode and up to 20 Mbps in LPDT (Low Power Data Transmission) mode. 2 Key Features • • • • • • • • • Output is compliant to MIPI D-PHY interfaces using the DSI, CSI-1 and CSI-2 standards o HS mode data rate: up to a maximum of 2.5 Gbps o LPDT mode data rate: up to 20 Mbps BTA supported (Bus Turnaround at Channel A or E) Pin Swap possibility 5 Channel device Conversion of LVDS input to SLVS output o LVDS data rate: up to a maximum of 2.5 Gbps No additional level shifters needed Arbitrary power up sequence Available as a bare die o RoHS compliant, Pb-free Available in a TQLMP-48 package o 7mm * 7mm * 0.9mm o 0.5mm pitch o RoHS compliant, Pb-free Meticom Page 4 of 17 MC20902 3 Block Diagram 3.1 Block Diagram VDDIO HS-E-P VDD GND D-PHY-E-P Level Shifter HS-E-N D-PHY-E-N CH-E LP-E-P LP Level Shifter LP-E-N HS-D-P BTA D-PHY-D-P Level Shifter HS-D-N D-PHY-D-N CH-D LP-D-P LP Level Shifter LP-D-N HS-C-P D-PHY-C-P Level Shifter HS-C-N D-PHY-C-N CH-C LP-C-P LP Level Shifter LP-C-N HS-B-P D-PHY-B-P Level Shifter HS-B-N D-PHY-B-N CH-B LP-B-P LP Level Shifter LP-B-N HS-A-P D-PHY-A-P Level Shifter HS-A-N D-PHY-A-N CH-A LP-A-P LP-A-N GPIO-0 GPIO-1 BTA PIN SWAP LP Level Shifter BTA State Machine Figure 1: Functional Block Diagram of the MC20902 Meticom Page 5 of 17 MC20902 4 Parametrics 4.1 Absolute Maximum Ratings Symbol Parameter VDDIO VDD TSTG TJ Supply voltage Supply voltage Storage temperature Junction temperature Condition VESD Electrostatic discharge voltage capability VESD-Dout Electrostatic discharge voltage capability at differential I/Os (HBM; 100 pF, 1.5 kΩ) (HBM; 100 pF, 1.5 kΩ) Min Max Unit -0.5 -0.5 -55 -55 3.6 2.0 125 125 V V °C °C 2.0 kV 500 V Table 1: Absolute Maximum Ratings Notes: Absolute Maximum Ratings may not be exceeded to the device without causing permanent damage or degradation. Exposures to these values for extended periods may affect device reliability. If the device is operated beyond the range of Operating Conditions functionality is not guaranteed. 4.2 Recommended Operating Conditions Symbol Parameter VDDIO VDD GND Supply voltage Supply voltage Ground Maximum allowed supply noise on VDD Ambient temperature Vnoise,VDD TA Condition Min 2.3 1.1 Typ 2.5 1.2 Max 2.7 1.3 Unit V V 100 100 mVpp ºC 0 V see Figure 2 -40 25 Table 2: Operating Conditions VDD 0 < fnoise < 10 GHz V noise ≤ 100 mVpp Supply voltage may not exceed 1.3V or drop below 1.1V at any time! Figure 2: Maximum Allowed Supply Noise on VDD Meticom Page 6 of 17 MC20902 4.3 DC Characteristics (At recommended operating conditions) Symbol IDD IDDIO IDD IDDIO Parameter Condition HS mode supply current including SLVS output HS mode supply current D-PHY HS Mode / LVDS to SLVS D-PHY HS Mode / LVDS to SLVS LP mode supply current LP mode supply current Min Typ Max Unit 10 14.0 18 mA 0.6 1.25 1.6 mA 0.5 1.25 1.5 mA 0.9 2.0 2.8 mA VDDIO 1 VDDIO 0.5 100 100 1.5 V V nA nA pF 700 70 80 1200 200 100 1600 600 125 mV mV Ω 150 200 250 mV 150 180 250 mVpp 80 100 125 Ω Single Ended Input (LP-X-P, LP-X-N, GPIO-0, GPIO-1, BTA, PINSWAP) *) VIH VIL IIH IIL CIN High level input voltage Low level input voltage High level input current Low level input current Input capacitance 0.7 0 VIN ≥ VDDIO - 0.2 VIN ≤ 0.2 Including package HS Input (HS-X-P, HS-X-N) *) VCM-IN |VIN-Diff| ZIN Differential Output (DPHY-X-P, DPHY-X-N) *) VCM-OUT Output common mode voltage |VDO_DIFF| Differential output voltage ZOD Output impedance @VDD=1.2V |VDPHY-P - VDPHY-N| @ VDD=1.2V Differential *) X means the Channels A … E Table 3: DC Characteristics Meticom Page 7 of 17 MC20902 4.4 AC Characteristics (At recommended operating conditions) Symbol Parameter Condition Min Typ Max Unit Notes HS Input (HS-X-P, HS-X-N) *) S11 tR,HS_Tx , tF_HS_Tx BR Input return loss f