APM32F407ZGT6

Datasheet APM32F405xG APM32F407xExG Arm® Cortex® -M4 core-based 32-bit MCU Version: V1.2 1 Product Characteristics  Core – 32-bit Arm® Cortex®-M4 core with FPU Up to 168MHz working frequency – – – – Up to 140 I/O All I/O can be mapped to external interrupt vector Up to 138 FT input I/O  Communication peripherals –  Memory and interface – Flash: The capacity is up to 1MB SRAM: System (192KB) + backup (4KB) EMMC: Support CF card, SRAM, PSRAM, SDRAM, NOR and NAND memories – – – – – 4 USART, 2 UART, supporting ISO7816, LIN and IrDA functions 3 I2C, supporting SMBus/PMBus 3 SPI (2 reusable I2S) 2 CAN 3 USB_OTG controllers 1 SDIO interface  Analog peripherals Clock – – – –  – – – – – –  – – – – –  –  –  – –  HSECLK: 4~26MHz external crystal/ceramic oscillator supported LSECLK: 32.768KHz crystal/ceramic oscillator supported HSICLK: 16MHz RC oscillator calibrated by factory LSICLK: 28KHz RC oscillator supported PLL1: Phase locked loop; output frequency is configured by four parameters PLL2: Phase locked loop specially used to provide clock signals to I2S; output frequency is configured by three parameters  – – – Reset and power management VDD range: 1.8～3.6V VDDA range: 1.8～3.6V VBAT range of backup domain power supply: 1.65V～3.6V Power-on/power-down/brown-out reset (POR/PDR/BOR) supported Programmable power supply voltage detector (PVD) supported Low-power mode Sleep, stop and standby modes supported DMA Two DMA; each DMA has 8 data streams, 16 in total – – –  – – 3 12-bit ADCs 2 12-bit DACs Timer 2 16-bit advanced timers TMR1/8 that can provide 7-channel PWM output, support dead zone generation and braking input functions 2 32-bit general-purpose timers TMR2/5, each with up to 4 independent channels to support input capture, output comparison, PWM, pulse count and other functions 8 16-bit general-purpose timers TMR/3/4/9/10/11/12/13/14, each with up to 2 independent channels to support input capture, output comparison, PWM, pulse count and other functions 2 16-bit basic timers TMR6/7 2 watchdog timers: one independent watchdog IWDT and one window watchdog WWDT 1 24-bit autodecrement SysTick Timer RTC Support calendar function Alarm and regular wake-up from stop/standby mode  CRC computing unit  96-bit unique device ID Debugging interface JTAG SWD I/O w w w. g e e h y. c o m Page 1 Contents 1 Product Characteristics .................................................................................................................. 1 2 Product Information ........................................................................................................................ 6 3 Pin Information ................................................................................................................................ 7 3.1 Pin distribution ................................................................................................................................... 7 3.2 Pin function description ................................................................................................................... 10 3.3 GPIO Multiplexing Function Configuration ...................................................................................... 28 4 Function Description .................................................................................................................... 51 4.1 System architecture......................................................................................................................... 52 4.1.1 System block diagram ..................................................................................................................... 52 4.1.2 Address mapping ............................................................................................................................ 53 4.1.3 Startup configuration ....................................................................................................................... 54 4.2 Core ................................................................................................................................................. 54 4.3 Interrupt controller ........................................................................................................................... 54 4.3.1 Nested Vector Interrupt Controller (NVIC) ...................................................................................... 54 4.3.2 External Interrupt/Event Controller (EINT) ...................................................................................... 54 4.4 On-chip memory .............................................................................................................................. 54 4.4.1 Configurable external memory controller (EMMC) ......................................................................... 55 4.4.2 LCD parallel interface (LCD) ........................................................................................................... 55 4.5 Clock ................................................................................................................................................ 55 4.5.1 Clock tree ........................................................................................................................................ 55 4.5.2 Clock source .................................................................................................................................... 56 4.5.3 System clock ................................................................................................................................... 57 4.5.4 Bus clock ......................................................................................................................................... 57 4.5.5 Phase locked loop ........................................................................................................................... 57 4.6 Power and power management ...................................................................................................... 57 4.6.1 Power supply scheme ..................................................................................................................... 57 4.6.2 Voltage regulator ............................................................................................................................. 57 4.6.3 Power supply voltage monitor ......................................................................................................... 58 w w w. g e e h y. c o m Page2 4.7 Low-power mode ............................................................................................................................. 58 4.8 DMA ................................................................................................................................................. 58 4.9 GPIO ................................................................................................................................................ 59 4.10 Communication peripherals ............................................................................................................ 59 4.10.1 USART/UART .................................................................................................................................. 59 4.10.2 I2C ................................................................................................................................................... 59 4.10.3 SPI/I2S ............................................................................................................................................ 60 4.10.4 CAN ................................................................................................................................................. 60 4.10.5 USB_OTG ....................................................................................................................................... 60 4.10.6 Ethernet ........................................................................................................................................... 60 4.10.7 SDIO ................................................................................................................................................ 60 4.11 Analog peripherals .......................................................................................................................... 61 4.11.1 ADC ................................................................................................................................................. 61 4.11.2 DAC ................................................................................................................................................. 61 4.12 Timer ................................................................................................................................................ 61 4.13 RTC ................................................................................................................................................. 63 4.13.1 Backup domain ................................................................................................................................ 63 4.14 RNG ................................................................................................................................................. 63 4.15 DCI................................................................................................................................................... 63 4.16 CRC ................................................................................................................................................. 64 5 Electrical Characteristics ............................................................................................................. 64 5.1 Test conditions of electrical characteristics ..................................................................................... 64 5.1.1 Maximum and minimum values....................................................................................................... 64 5.1.2 Typical value .................................................................................................................................... 64 5.1.3 Typical curve.................................................................................................................................... 64 5.1.4 Power supply scheme ..................................................................................................................... 65 5.1.5 Load capacitance ............................................................................................................................ 66 5.2 Test under general operating conditions ......................................................................................... 66 5.3 Absolute maximum ratings .............................................................................................................. 67 5.3.1 Maximum temperature characteristics ............................................................................................ 67 w w w. g e e h y. c o m Page3 5.3.2 Maximum rated voltage characteristics........................................................................................... 67 5.3.3 Maximum rated current characteristics ........................................................................................... 67 5.3.4 Electro-static discharge (ESD) ........................................................................................................ 68 5.3.5 Static latch-up (LU).......................................................................................................................... 68 5.4 On-chip memory .............................................................................................................................. 68 5.4.1 Flash characteristics........................................................................................................................ 68 5.5 Clock ................................................................................................................................................ 69 5.5.1 Characteristics of external clock source ......................................................................................... 69 5.5.2 Characteristics of internal clock source .......................................................................................... 70 5.5.3 PLL Characteristics ......................................................................................................................... 71 5.6 Reset and power management ....................................................................................................... 71 5.6.1 Test of Embedded Reset and Power Control Module Characteristics............................................ 71 5.7 Power consumption ......................................................................................................................... 73 5.7.1 Power consumption test environment ............................................................................................. 73 5.7.2 Power consumption in run mode..................................................................................................... 74 5.7.3 Power consumption in sleep mode ................................................................................................. 77 5.7.4 Power consumption in stop mode ................................................................................................... 78 5.7.5 Power consumption in standby mode ............................................................................................. 78 5.7.6 Peripheral power consumption........................................................................................................ 79 5.7.7 Backup Domain Power Consumption ............................................................................................. 81 5.8 Wake-up time in low-power mode ................................................................................................... 81 5.9 I/O port characteristics .................................................................................................................... 82 5.10 NRST pin characteristics ................................................................................................................. 84 5.11 Communication peripherals ............................................................................................................ 85 5.11.1 I2C peripheral characteristics.......................................................................................................... 85 5.11.2 SPI peripheral characteristics ......................................................................................................... 86 5.12 Analog peripherals .......................................................................................................................... 88 5.12.1 ADC ................................................................................................................................................. 88 5.12.2 DAC ................................................................................................................................................. 89 6 Package Information ..................................................................................................................... 91 w w w. g e e h y. c o m Page4 6.1 LQFP176 package information ....................................................................................................... 91 6.2 LQFP144 package information ....................................................................................................... 93 6.3 LQFP100 package information ....................................................................................................... 96 6.4 LQFP64 package information ......................................................................................................... 99 7 Packaging Information................................................................................................................ 102 7.1 Reel packaging .............................................................................................................................. 102 7.2 Tray packaging .............................................................................................................................. 103 8 Ordering Information .................................................................................................................. 105 9 Commonly Used Function Module Denomination................................................................... 106 10 Version History ............................................................................................................................ 107 w w w. g e e h y. c o m Page5 2 Product Information See the following table for APM32F405xG 407xExG product functions and peripheral configuration. Table 1 Functions and Peripherals of APM32F405xG 407xExG Series Chips Product APM32F407 Model RET6 Package RGT6 VET6 LQFP64 VGT6 LQFP100 ZET6 ZGT6 32-bit Working voltage Flash(KB) 1024 512 1024 512 LQFP176 512 51 82 114 LQFP144 1024 140 4/2 SPI/I2S 3/2 I2C 3 Communication OTG_FS 1 interface OTG_HS 2 CAN 2 0 1024 1 0 51 82 1 114 0 SDIO 1 16-bit advanced 2 32-bit general 2 16-bit general 8 16-bit basic 2 System tick timer 1 Watchdog 2 Real-time clock 1 0 1 RNG 0 1 Unit 12 位 DAC LQFP100 1 USART/UART 12-bit ADC LQFP64 0 0 DCI ZGT6 1 DMC Timer VGT6 192+4 0 Ethernet RGT6 Cortex®-M4@168MHz 1024 System + backup SRAM(KB) GPIOs IGT6 1.8~3.6V 512 SMC IET6 LQFP144 Arm® Core and maximum working frequency APM32F405 External channel 3 13 21 Internal channel 3 Unit 2 Channel 2 Operating temperature w w w. g e e h y. c o m 13 21 Ambient temperature: -40°C to 85°C Junction temperature: -40℃ to 105℃ Page6 3 Pin Information 3.1 Pin distribution 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 PI7 PI6 PI5 PI4 VDD PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 VDD VSS PI3 PI2 Figure 1 Distribution Diagram of APM32F407xExG Series LQFP176 Pins 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 LQFP176 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PI1 PI0 PH15 PH14 PH13 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 VDD VSS PH12 PH4 PH5 PA3 BYPASS_REG VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD PH6 PH7 PH8 PH9 PH10 PH11 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 PE2 PE3 PE4 PE5 PE6 VBAT PI8 PC13 PC14 PC15 PI9 PI10 PI11 VSS VDD PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0 PH1 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 PH2 PH3 w w w. g e e h y. c o m Page7 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 2 Distribution Diagram of APM32F405xG 407xExG Series LQFP144 Pins 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14 PC15 PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0 PH1 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 w w w. g e e h y. c o m Page8 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 3 Distribution Diagram of APM32F405xG 407xExG Series LQFP100 Pins 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14 PC15 VSS VDD PH0 PH1 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 w w w. g e e h y. c o m Page9 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDD VSS PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 4 Distribution Diagram of APM32F405xG 407xExG Series LQFP64 Pins 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LQFP64 VDD VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VCAP_1 VDD 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VBAT PC13 PC14 PC15 PH0 PH1 NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 3.2 Pin function description Table 2 Legends/Abbreviations Used in Output Pin Table Name Pin name Pin type I/O structure Notes Pin Default multiplexing function function w w w. g e e h y. c o m Abbreviation Definition Unless otherwise specified in parentheses below the pin name, the pin functions during and after reset are the same as the actual pin name P Power pin I Only input pin I/O I/O pin 5T FT I/O STDA 3.3V standard I/O, directly connected to ADC STD 3.3V standard I/O B Dedicated Boot0 pin RST Bidirectional reset pin with built-in pull-up resistor Unless otherwise specified in the notes, all I/O is set as floating input during and after reset Function directly selected/enabled through peripheral register Page10 Name Abbreviation Redefining function Definition Select this function through AFIO remapping register Table 3 Description of APM32F405xG 407xExG by Pin Number Name (Function after Type Structure reset) Multiplexing Additional LQFP LQFP LQFP LQFP function function 64 100 144 176 - - 1 1 1 - - 2 2 2 - - 3 3 3 - - 4 4 4 - - 5 5 5 - 1 6 6 6 - - - 7 2 7 7 8 TRACECK, PE2 I/O 5T SMC_A23, ETH_MII_TXD3, EVENTOUT TRACED0, PE3 I/O 5T SMC_A19, EVENTOUT TRACED1, PE4 I/O 5T SMC_A20, DCI_D4, EVENTOUT TRACED2, SMC_A21, PE5 I/O 5T TMR9_CH1, DCI_D6, EVENTOUT TRACED3, SMC_A22, PE6 I/O 5T TMR9_CH2, DCI_D7, EVENTOUT VBAT PI8 P I/O - 5T EVENTOUT, DMC_CAS RTC_TAMP1, RTC_TAMP2, RTC_TS RTC_OUT, PC13 I/O 5T EVENTOUT RTC_TAMP1, RTC_TS PC14- OSC32_IN （PC14） PC15- OSC32_OUT （PC15） I/O 5T EVENTOUT OSC32_IN 3 8 8 9 I/O 5T EVENTOUT OSC32_OUT 4 9 9 10 - - - - 11 - - - - 12 CAN1_RX, PI9 I/O 5T EVENTOUT, DMC_RAS PI10 w w w. g e e h y. c o m I/O 5T ETH_MII_RX_ER, P a g e 11 Name (Function after Type Structure reset) Multiplexing Additional LQFP LQFP LQFP LQFP function function 64 100 144 176 - - - - 13 EVENTOUT, DMC_CS OTG_HS_ULPI_DIR, PI11 I/O 5T EVENTOUT, DMC_BA VSS P - - - - - - 14 VDD P - - - - - - 15 - - - 10 16 - - - 11 17 - - - 12 18 ADC3_IN9 - - 13 19 ADC3_IN14 - - 14 20 ADC3_IN15 - - 15 21 SMC_A0, PF0 I/O 5T DMC_A10, I2C2_SDA, EVENTOUT SMC_A1, PF1 I/O 5T DMC_A0, I2C2_SCL, EVENTOUT SMC_A2, PF2 I/O 5T DMC_A1, I2C2_SMBAI, EVENTOUT SMC_A3, PF3 I/O 5T DMC_A2, EVENTOUT SMC_A4, PF4 I/O 5T DMC_A3, EVENTOUT SMC_A5, PF5 I/O 5T VSS P - - - - 10 16 22 VDD P - - - - 11 17 23 ADC3_IN4 - - 18 24 ADC3_IN5 - - 19 25 ADC3_IN6 - - 20 26 EVENTOUT TMR10_CH1, PF6 I/O 5T SMC_NIORD, DMC_A4, EVENTOUT TMR11_CH1, PF7 I/O 5T SMC_NREG, DMC_A5, EVENTOUT PF8 w w w. g e e h y. c o m I/O 5T TMR13_CH1, SMC_NIOWR, Page12 Name (Function after Type Structure reset) Multiplexing Additional LQFP LQFP LQFP LQFP function function 64 100 144 176 ADC3_IN7 - - 21 27 ADC3_IN8 - - 22 28 DMC_A6, EVENTOUT TMR14_CH1, PF9 I/O 5T SMC_CD, DMC_A7 EVENTOUT SMC_INTR, PF10 I/O 5T DMC_A8 EVENTOUT PH0-OSC_IN I/O 5T EVENTOUT OSC_IN 5 12 23 29 I/O 5T EVENTOUT OSC_OUT 6 13 24 30 NRST I/O RST - - 7 14 25 31 PC0 I/O 5T ADC123_IN10 8 15 26 32 PC1 I/O 5T ADC123_IN11 9 16 27 33 ADC123_IN12 10 17 28 34 ADC123_IN13 11 18 29 35 (PH0) PH1-OSC_OUT (PH1) OTG_HS_ULPI_STP, EVENTOUT ETH_MDC, EVENTOUT SPI2_MISO, OTG_HS_ULPI_DIR, PC2 I/O 5T ETH_MII_TXD2, I2S2ext_SD, EVENTOUT SPI2_MOSI, I2S2_SD, PC3 I/O 5T OTG_HS_ULPI_NXT, ETH_MII_TX_CLK, EVENTOUT VDD P - - - - 19 30 36 VSSA P - - - 12 20 31 37 VREF+ P - - - - 21 32 38 VDDA P - - - 13 22 33 39 14 23 34 40 USART2_CTS, UART4_TX, PA0-WKUP (PA0) ETH_MII_CRS, I/O 5T TMR2_CH1_ETR, TMR5_CH1, WKUP, ADC123_IN0 TMR8_ETR, EVENTOUT w w w. g e e h y. c o m Page13 Name (Function after Type Structure reset) Multiplexing Additional LQFP LQFP LQFP LQFP function function 64 100 144 176 ADC123_IN1 15 24 35 41 ADC123_IN2 16 25 36 42 - - - - 43 - - - - 44 - - - - 45 - - - - 46 ADC123_IN3 17 26 37 47 USART2_RTS, UART4_RX, ETH_RMII_REF_CLK, PA1 I/O 5T ETH_MII_RX_CLK, TMR5_CH2, TMR2_CH2, EVENTOUT USART2_TX, TMR5_CH3, PA2 I/O 5T TMR9_CH1, TMR2_CH3, ETH_MDIO, EVENTOUT PH2 I/O 5T ETH_MII_CRS, EVENTOUT ETH_MII_COL, PH3 I/O 5T EVENTOUT, DMC_A9 I2C2_SCL, PH4 I/O 5T OTG_HS_ULPI_NXT, EVENTOUT PH5 I/O 5T I2C2_SDA, EVENTOUT USART2_RX, TMR5_CH4, TMR9_CH2, PA3 I/O 5T TMR2_CH4, OTG_HS_ULPI_D0, ETH_MII_COL, EVENTOUT, DMC_CKE VSS P - - - 18 27 38 - BYPASS_REG I 5T - - - - - 48 VDD P - - - 19 28 39 49 20 29 40 50 SPI1_NSS, SPI3_NSS, PA4 I/O STDA USART2_CK, DAC_OUT1, DCI_HSYNC, ADC12_IN4 OTG_HS_SOF, I2S3_WS, w w w. g e e h y. c o m Page14 Name (Function after Type Structure reset) Multiplexing Additional LQFP LQFP LQFP LQFP function function 64 100 144 176 21 30 41 51 ADC12_IN6 22 31 42 52 ADC12_IN7 23 32 43 53 ADC12_IN14 24 33 44 54 ADC12_IN15 25 34 45 55 ADC12_IN8 26 35 46 56 ADC12_IN9 27 36 47 57 - 28 37 48 58 EVENTOUT SPI1_SCK, OTG_HS_ULPI_CK, PA5 I/O STDA TMR2_CH1_ETR, TMR8_CH1N, DAC_OUT2, ADC12_IN5 EVENTOUT SPI1_MISO, TMR8_BKIN, TMR13_CH1, PA6 I/O 5T DCI_PIXCLK, TMR3_CH1, TMR1_BKIN, EVENTOUT SPI1_MOSI, TMR8_CH1N, TMR14_CH1, PA7 I/O 5T TMR3_CH2, ETH_MII_RX_DV, TMR1_CH1N, ETH_RMII_CRS_DV, EVENTOUT ETH_RMII_RX_D0, PC4 I/O 5T ETH_MII_RX_D0, EVENTOUT ETH_RMII_RX_D1, PC5 I/O 5T ETH_MII_RX_D1, EVENTOUT TMR3_CH3 TMR8_CH2N, PB0 I/O 5T OTG_HS_ULPI_D1, ETH_MII_RXD2, TMR1_CH2N, EVENTOUT TMR3_CH4 TMR8_CH3N, PB1 I/O 5T OTG_HS_ULPI_D2, ETH_MII_RXD3, TMR1_CH3N, EVENTOUT PB2-BOOT w w w. g e e h y. c o m I/O 5T EVENTOUT Page15 Name (Function after Type Structure reset) Multiplexing Additional LQFP LQFP LQFP LQFP function function 64 100 144 176 - - - 49 59 - - - 50 60 (PB2) DCI_D12, PF11 I/O 5T EVENTOUT, DMC_UDQM SMC_A6, PF12 I/O 5T VSS P - - - - - 51 61 VDD P - - - - - 52 62 PF13 I/O 5T - - - 53 63 PF14 I/O 5T - - - 54 64 PF15 I/O 5T - - - 55 65 PG0 I/O 5T - - - 56 66 - - - 57 67 - - 38 58 68 - - 39 59 69 - - 40 60 70 EVENTOUT SMC_A7, EVENTOUT SMC_A8, EVENTOUT SMC_A9, EVENTOUT SMC_A10, EVENTOUT SMC_A11, PG1 I/O 5T DMC_CK, EVENTOUT SMC_D4, PE7 I/O 5T TMR1_ETR, EVENTOUT SMC_D5, PE8 I/O 5T TMR1_CH1N, EVENTOUT SMC_D6, PE9 I/O 5T TMR1_CH1, EVENTOUT VSS P - - - - - 61 71 VDD P - - - - - 62 72 - - 41 63 73 - - 42 64 74 - - 43 65 75 SMC_D7, PE10 I/O 5T TMR1_CH2N, EVENTOUT SMC_D8, PE11 I/O 5T TMR1_CH2, EVENTOUT SMC_D9, PE12 I/O 5T TMR1_CH3N, EVENTOUT w w w. g e e h y. c o m Page16 Name (Function after Type Structure reset) Multiplexing Additional LQFP LQFP LQFP LQFP function function 64 100 144 176 - - 44 66 76 - - 45 67 77 - - 46 68 78 - 29 47 69 79 - 30 48 70 80 SMC_D10, PE13 I/O 5T TMR1_CH3, EVENTOUT SMC_D11, PE14 I/O 5T TMR1_CH4, EVENTOUT SMC_D12, PE15 I/O 5T TMR1_BKIN, EVENTOUT SPI2_SCK, I2S2_CK, I2C2_SCL, PB10 I/O 5T USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER, TMR2_CH3, EVENTOUT I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, PB11 I/O 5T ETH_RMII_TX_EN, ETH_MII_TX_EN, TMR2_CH4, EVENTOUT VCAP_1 P - - - 31 49 71 81 VDD P - - - 32 50 72 82 - - - - 83 - - - - 84 - - - - 85 - - - - 86 I2C2_SMBAI, PH6 I/O 5T TMR12_CH1, ETH_MII_RXD2, EVENTOUT I2C3_SCL, PH7 I/O 5T ETH_MII_RXD3, EVENTOUT I2C3_SDA, PH8 I/O 5T DCI_HSYNC, EVENTOUT, DMC_DQ8 I2C3_SMBAI, PH9 I/O 5T TMR12_CH2, DCI_D0, w w w. g e e h y. c o m Page17 Name (Function after Type Structure reset) Multiplexing Additional LQFP LQFP LQFP LQFP function function 64 100 144 176 - - - - 87 - - - - 88 - - - - 89 EVENTOUT TMR5_CH1, PH10 I/O 5T DCI_D1, EVENTOUT, DMC_DQ9 TMR5_CH2, PH11 I/O 5T DCI_D2, EVENTOUT TMR5_CH3, PH12 I/O 5T DCI_D3, EVENTOUT VSS P - - - - - - 90 VDD P - - - - - - 91 - 33 51 73 92 OTG_HS_VBUS 34 52 74 93 - 35 53 75 94 SPI2_NSS, I2S2_WS, I2C2_SMBAI, USART3_CK, TMR1_BKIN, PB12 I/O 5T CAN2_RX, OTG_HS_ULPI_D5, ETH_RMII_TXD0, ETH_MII_TXD0, OTG_HS_ID, EVENTOUT SPI2_SCK, I2S2_CK, USART3_CTS, TMR1_CH1N, PB13 I/O 5T CAN2_TX, OTG_HS_ULPI_D6, ETH_RMII_TXD1, ETH_MII_TXD1, EVENTOUT SPI2_MISO, TMR1_CH2N, TMR12_CH1, PB14 I/O 5T OTG_HS_DM, USART3_RTS, TMR8_CH2N, I2S2ext_SD, w w w. g e e h y. c o m Page18 Name (Function after Type Structure reset) Multiplexing Additional LQFP LQFP LQFP LQFP function function 64 100 144 176 RTC_REFIN 36 54 76 95 - - 55 77 96 - - 56 78 97 - - 57 79 98 - - 58 80 99 - - 59 81 100 - - 60 82 101 EVENTOUT SPI2_MOSI, I2S2_SD, TMR1_CH3N, PB15 I/O 5T TMR8_CH3N TMR12_CH2, OTG_HS_DP, EVENTOUT SMC_D13, PD8 I/O 5T USART3_TX, EVENTOUT SMC_D14, PD9 I/O 5T USART3_RX, EVENTOUT SMC_D15, PD10 I/O 5T DMC_DQ10 USART3_CK, EVENTOUT SMC_CLE, PD11 I/O 5T SMC_A16, USART3_CTS, EVENTOUT SMC_ALE, SMC_A17, PD12 I/O 5T DMC_DQ11, TMR4_CH1, USART3_RTS, EVENTOUT SMC_A18, PD13 I/O 5T DMC_DQ12 TMR4_CH2, EVENTOUT VSS P - - - - - 83 102 VDD P - - - - - 84 103 - - 61 85 104 - - 62 86 105 SMC_D0, PD14 I/O 5T DMC_DQ13, TMR4_CH3, EVENTOUT PD15 w w w. g e e h y. c o m I/O 5T SMC_D1, Page19 Name (Function after Type Structure reset) Multiplexing Additional LQFP LQFP LQFP LQFP function function 64 100 144 176 - - - 87 106 - - - 88 107 - - - 89 108 - - - 90 109 - - - 91 110 - - - 92 111 - - - 93 112 DMC_DQ14, TMR4_CH4, EVENTOUT SMC_A12, PG2 I/O 5T DMC_DQ15, EVENTOUT SMC_A13, PG3 I/O 5T DMC_DQ0, EVENTOUT SMC_A14, PG4 I/O 5T DMC_DQ1, EVENTOUT SMC_A15, PG5 I/O 5T DMC_DQ2, EVENTOUT SMC_INT2, PG6 I/O 5T DMC_DQ3 EVENTOUT SMC_INT3, PG7 I/O 5T USART6_CK, EVENTOUT DMC_DQ4 PG8 I/O 5T USART6_RTS, ETH_PPS_OUT, EVENTOUT VSS P - - - - - 94 113 VDD P - - - - - 95 114 - 37 63 96 115 - 38 64 97 116 I2S2_MCK, TMR8_CH1, SDIO_D6, PC6 I/O 5T USART6_TX, DCI_D0, TMR3_CH1, EVENTOUT I2S3_MCK, TMR8_CH2, PC7 I/O 5T SDIO_D7, USART6_RX, DCI_D1, TMR3_CH2, w w w. g e e h y. c o m Page20 Name (Function after Type Structure reset) Multiplexing Additional LQFP LQFP LQFP LQFP function function 64 100 144 176 - 39 65 98 117 - 40 66 99 118 - 41 67 100 119 OTG_FS_VBUS 42 68 101 120 - 43 69 102 121 - 44 70 103 122 - 45 71 104 123 EVENTOUT TMR8_CH3, SDIO_D0, PC8 I/O 5T TMR3_CH3, USART6_CK, DCI_D2, EVENTOUT I2S_CKIN, MCO2, TMR8_CH4, PC9 I/O 5T SDIO_D1, I2C3_SDA, DCI_D3, TMR3_CH4, EVENTOUT USART1_CK, TMR1_CH1, PA8 I/O 5T MCO, I2C3_SCL, OTG_FS_SOF, EVENTOUT USART1_TX, TMR1_CH2, PA9 I/O 5T I2C3_SMBAI, DCI_D0, EVENTOUT USART1_RX, TMR1_CH3, PA10 I/O 5T OTG_FS_ID, DCI_D1, EVENTOUT USART1_CTS, CAN1_RX, PA11 I/O 5T TMR1_CH4, OTG_FS_DM, EVENTOUT USART1_RTS, PA12 I/O 5T CAN1_TX, TMR1_ETR, OTG_FS_DP, w w w. g e e h y. c o m Page21 Name (Function after Type Structure reset) Multiplexing Additional LQFP LQFP LQFP LQFP function function 64 100 144 176 PA13 46 72 105 124 EVENTOUT PA13 JTMS-SWDIO, I/O 5T VCAP_2 P - - - 47 73 106 125 VSS P - - - - 74 107 126 VDD P - - - 48 75 108 127 - - - - 128 - - - - 129 - - - - 130 - - - - 131 - - - - 132 - - - - 133 - - - - 134 (JTMS-SWDIO) EVENTOUT TMR8_CH1N, PH13 I/O 5T CAN1_TX, EVENTOUT, DMC_DQ5 TMR8_CH2N, PH14 I/O 5T DCI_D4, EVENTOUT TMR8_CH3N, PH15 I/O 5T DCI_D11, EVENTOUT, DMC_DQ6 TMR5_CH4, SPI2_NSS, PI0 I/O 5T I2S2_WS, DCI_D13, EVENTOUT SPI2_SCK, PI1 I/O 5T I2S2_CK, DCI_D8, EVENTOUT TMR8_CH4, SPI2_MISO, PI2 I/O 5T DCI_D9, I2S2ext_SD, EVENTOUT TMR8_ETR, SPI2_MOSI, PI3 I/O 5T I2S2_SD, DCI_D10, EVENTOUT, DMC_DQ7 VSS P - - - - - - 135 VDD P - - - - - - 136 w w w. g e e h y. c o m Page22 Name (Function after Type Structure I/O 5T reset) PA14 (JTCK/SWCLK) Multiplexing Additional LQFP LQFP LQFP LQFP function function 64 100 144 176 - 49 76 109 137 - 50 77 110 138 - 51 78 111 139 - 52 79 112 140 - 53 80 113 141 - - 81 114 142 - - 82 115 143 - 54 83 116 144 JTCK-SWCLK, EVENTOUT JTDI, SPI3_NSS, PA15 (JTDI) I/O 5T I2S3_WS, TMR2_CH1_ETR, SPI1_NSS, EVENTOUT SPI3_SCK, I2S3_CK, UART4_TX, PC10 I/O 5T SDIO_D2, DCI_D8, USART3_TX, EVENTOUT UART4_RX, SPI3_MISO, SDIO_D3, PC11 I/O 5T DCI_D4, USART3_RX, I2S3ext_SD, EVENTOUT UART5_TX, SDIO_CK, DCI_D9, PC12 I/O 5T SPI3_MOSI, I2S3_SD, USART3_CK, EVENTOUT SMC_D2, PD0 I/O 5T CAN1_RX, EVENTOUT SMC_D3, PD1 I/O 5T CAN1_TX, EVENTOUT TMR3_ETR, UART5_RX, PD2 I/O 5T SDIO_CMD, DCI_D11, EVENTOUT w w w. g e e h y. c o m Page23 Name (Function after Type Structure reset) Multiplexing Additional LQFP LQFP LQFP LQFP function function 64 100 144 176 - - 84 117 145 - - 85 118 146 - - 86 119 147 SMC_CLK, PD3 I/O 5T USART2_CTS, EVENTOUT SMC_NOE, PD4 I/O 5T USART2_RTS, EVENTOUT SMC_NWE, PD5 I/O 5T USART2_TX, EVENTOUT VSS P - - - - - 120 148 VDD P - - - - - 121 149 - - 87 122 150 - - 88 123 151 - - - 124 152 - - - 125 153 - - - 126 154 - - - 127 155 - - - 128 156 - - - 129 157 SMC_NWAIT, PD6 I/O 5T USART2_RX, EVENTOUT SMC_NE1, PD7 I/O 5T SMC_NCE2, USART2_CK, EVENTOUT SMC_NE2, PG9 I/O 5T SMC_NCE3, USART6_RX, EVENTOUT SMC_NCE4_1, PG10 I/O 5T SMC_NE3, EVENTOUT SMC_NCE4_2, PG11 I/O 5T ETH_MII_TX_EN, ETH_RMII_TX_EN, EVENTOUT SMC_NE4, PG12 I/O 5T USART6_RTS, EVENTOUT SMC_A24, USART6_CTS, PG13 I/O 5T ETH_MII_TXD0, ETH_RMII_TXD0, EVENTOUT SMC_A25, PG14 I/O 5T USART6_TX, ETH_MII_TXD1, w w w. g e e h y. c o m Page24 Name (Function after Type Structure reset) Multiplexing Additional LQFP LQFP LQFP LQFP function function 64 100 144 176 ETH_RMII_TXD1, EVENTOUT VSS P - - - - - 130 158 VDD P - - - - - 131 159 - - - 132 160 - 55 89 133 161 - 56 90 134 162 - 57 91 135 163 - 58 92 136 164 - 59 93 137 165 DMC_LDQM, PG15 I/O 5T USART6_CTS, DCI_D13, EVENTOUT JTDO, TRACESWO, PB3 (JTDO/TRACESWO) SPI3_SCK, I/O 5T I2S3_CK, TMR2_CH2, SPI1_SCK, EVENTOUT NJTRST, SPI3_MISO, PB4 (NJTRST) I/O 5T TMR3_CH1, SPI1_MISO, I2S3ext_SD, EVENTOUT I2C1_SMBAI, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, PB5 I/O - TMR3_CH2, SPI1_MOSI, SPI3_MOSI, DCI_D10, I2S3_SD, EVENTOUT I2C1_SCL, TMR4_CH1, PB6 I/O 5T CAN2_TX, DCI_D5, USART1_TX, EVENTOUT I2C1_SDA, PB7 I/O 5T SMC_NL, DCI_VSYNC, w w w. g e e h y. c o m Page25 Name (Function after Type Structure reset) Multiplexing Additional LQFP LQFP LQFP LQFP function function 64 100 144 176 VPP 60 94 138 166 - 61 95 139 167 - 62 96 140 168 - - 97 141 169 - - 98 142 170 USART1_RX, TMR4_CH2, EVENTOUT BOOT0 I B TMR4_CH3, SDIO_D4, TMR10_CH1, PB8 I/O 5T DCI_D6, ETH_MII_TXD3, I2C1_SCL, CAN1_RX, EVENTOUT SPI2_NSS, I2S2_WS, TMR4_CH4, TMR11_CH1, PB9 I/O 5T SDIO_D5, DCI_D7, I2C1_SDA, CAN1_TX, EVENTOUT TMR4_ETR, PE0 I/O 5T SMC_NBL0, DCI_D2, EVENTOUT SMC_NBL1, PE1 I/O 5T DCI_D3, EVENTOUT VSS P - - - 63 99 - - PDR_ON I 5T - - - - 143 171 VDD P - - - 64 100 144 172 - - - - 173 - - - - 174 - - - - 175 TMR8_BKIN, PI4 I/O 5T DCI_D5, EVENTOUT TMR8_CH1, PI5 I/O 5T DCI_VSYNC, EVENTOUT PI6 w w w. g e e h y. c o m I/O 5T TMR8_CH2, DCI_D6, Page26 Name (Function after Type Structure reset) Multiplexing Additional LQFP LQFP LQFP LQFP function function 64 100 144 176 - - - - 176 EVENTOUT TMR8_CH3, PI7 I/O 5T DCI_D7, EVENTOUT, DMC_WE Note: (1) PC13, PC14 and PC15 are powered through the power switch. Since the switch only sinks limited current (3mA), the use of GPIO from PC13 to PC15 in output mode is limited: ① The speed shall not exceed 2MHz when the heavy load is 30pF; ② Not used for current source (e.g. driving LED). w w w. g e e h y. c o m Page27 GPIO Multiplexing Function Configuration 3.3 Table 4 GPIOA Multiplexing Function Configuration AF0 Port SYS P A - 0 AF1 AF2 TMR1/ TMR 2 3/4/5 TMR2_ TMR CH1_E 5_C TR H1 AF3 TMR8 /9/10/ 11 TMR8 _ETR AF4 I2C1/ 2/3 - AF5 AF6 AF7 AF8 AF9 AF10 SPI1/SPI2 SPI3/I2 USART1 UART4/ CAN1/2T OTG_F /I2S2/I2S2 Sext/I2 /2/3/I2S3 5/USAR MR12/13 S/OTG_ ext S3 ext T6 /14 HS - - USART2 UART4 _CTS _TX - - AF11 AF12 AF13 SMC/DMC/ ETH SDIO/OTG DCI _CRS F AF1 1 5 4 _FS ETH_MII A EVE - - - NTO UT ETH_MII P A - 1 TMR2_ CH2 _RX_CL TMR 5_C - - - - H2 USART2 UART4 _RTS _RX - - K ETH_RM EVE - - - NTO UT II_REF_ CLK Po rt_ P A A - 2 P A - 3 TMR2_ CH3 TMR2_ CH4 TMR 5_C H3 TMR 5_C H4 TMR9 _CH1 TMR9 _CH2 - - - - - _TX USART2 _RX - - OTG_H - - S_ULPI _D0 ETH_MD IO ETH_MII _COL EVE - - - 4 w w w. g e e h y. c o m - - - SPI1_NS NSS USART2 S I2S3_ _CK WS - - - - - - NTO UT EVE DMC_CKE - - NTO UT SPI3_ P A - USART2 OTG_HS_ SOF DCI_ HSY NC EVE - NTO UT Pa g e 2 8 AF0 Port SYS P A - 5 P A - 6 AF1 AF2 TMR1/ TMR 2 3/4/5 AF3 TMR8 /9/10/ 11 TMR2_ TMR8 CH1_E _CH1 TR N TMR1_ BKIN TMR TMR8 3_C _BKI H1 N AF4 I2C1/ 2/3 - - AF5 AF6 AF7 AF8 AF9 AF10 SPI1/SPI2 SPI3/I2 USART1 UART4/ CAN1/2T OTG_F /I2S2/I2S2 Sext/I2 /2/3/I2S3 5/USAR MR12/13 S/OTG_ ext S3 ext T6 /14 HS SPI1_SC K SPI1_MIS O AF11 AF12 AF13 SMC/DMC/ ETH SDIO/OTG DCI A F AF1 1 5 4 _FS OTG_H - - - S_ULPI EVE - - - - _CK - - - TMR13_ CH1 UT DCI_ - NTO - - PIXC EVE - K NTO UT ETH_MII P A - 7 TMR1_ CH1N TMR TMR8 3_C _CH1 H2 N - SPI1_MO SI - - - TMR14_ CH1 _RX_DV - ETH_RM EVE - - - II_CRS_ NTO UT DV P A MCO1 8 P A - 9 TMR1_ CH1 TMR1_ CH2 I2C3 - - _SC - - L I2C3 - - _SM - - BA USART1 _CK USART1 _TX - - - - OTG_F S_SOF - EVE - - - - UT - - DCI_ D0 EVE - 1 - TMR1_ CH3 - - - - - USART1 _RX - - OTG_F S_ID - - DCI_ D1 EVE - A 11 - TMR1_ CH4 w w w. g e e h y. c o m - - - - - USART1 _CTS - CAN1_R OTG_F X S_DM NTO UT 0 P NTO UT P A NTO EVE - - - - NTO UT Pa g e 2 9 AF0 Port SYS AF1 AF2 TMR1/ TMR 2 3/4/5 AF3 TMR8 /9/10/ 11 AF4 I2C1/ 2/3 AF5 AF6 AF7 AF8 AF9 AF10 SPI1/SPI2 SPI3/I2 USART1 UART4/ CAN1/2T OTG_F /I2S2/I2S2 Sext/I2 /2/3/I2S3 5/USAR MR12/13 S/OTG_ ext S3 ext T6 /14 HS CAN1_T OTG_F X S_DP AF11 AF12 AF13 SMC/DMC/ ETH SDIO/OTG DCI A F AF1 1 5 4 _FS P A 1 - TMR1_ ETR - - - - - USART1 _RTS - EVE - - - - UT 2 P A 1 3 P A 1 4 JTMS _SWD EVE - - - - - - - - - - - - - NTO UT JTCK EVE _SWC - - - - - - - - - - - - - - LK A CH1 JTDI NTO UT TMR2_ 5 - IO P 1 NTO TMR2_ ETR w w w. g e e h y. c o m SPI3_ - - - SPI1_NS NSS S I2C3_ WS EVE - - - - - - - - NTO UT Pa g e 3 0 Table 5 GPIOB Multiplexing Function Configuration AF0 Port AF1 AF2 AF3 TMR8 TMR1 TMR /2 3/4/5 TMR1 TMR TMR8 _CH2 3_C _CH2 0 N H3 N P TMR1 TMR TMR8 _CH3 3_C _CH3 N H4 N SYS P B B - - 1 /9/10/ 11 AF4 I2C1/ 2/3 - AF5 AF6 AF7 AF8 AF9 AF10 SPI1/SPI2 SPI3/I2 USART1/ UART4/ CAN1/2T OTG_F /I2S2/I2S2 Sext/I2 2/3/I2S3e 5/USAR MR12/13/ S/OTG_ ext S3 xt T6 14 HS - - - - OTG_HS - - - - - _ULPI_D 2 AF11 SMC/DMC/ ETH ETH_M S_ULPI II_RXD _D1 2 _RXD3 SDIO/OTG _FS OTG_H ETH_MII AF12 AF 13 A F DC 1 I 4 EVE - - - EVE - - - - EVE - - - - - - - - - - - - - - - P JTDO/T rt_ B RACES B 3 WO SPI3_S TMR2 _CH2 - - TMR NJTRST - 3_C 4 H1 P TMR - - 3_C 5 H2 P TMR - - SPI1_SCK CK I2S3_C EVE - - - - - - - - - 6 w w w. g e e h y. c o m 4_C H1 SPI1 - _MIS O I2C1_ SMBA I2C1_ SCL SPI3_MIS I2S3ext O _SD SPI1 SPI3_MO _MO SII2S3_S SI D - - - USART 1_TX NTO UT K P B NTO UT Po B NTO UT 2 B NTO UT P B AF15 EVE - - - - - - - - NTO UT CAN2_R X - OTG_H S_ULPI _D7 CAN2_T X ETH_PP S_OUT - DCI_D 10 EVE - - - NTO UT EVE - - - DCI_D5 - - NTO UT Pa g e 3 1 AF0 Port SYS AF1 TMR1 TMR /2 3/4/5 P B AF2 TMR - - 4_C AF3 TMR8 /9/10/ 11 I2C1_ SDA AF4 I2C1/ 2/3 - 7 H2 P TMR TMR1 I2C1 4_C 0_CH _SC H3 1 L TMR TMR1 I2C1 4_C 1_CH _SD H4 1 A B - - 8 P B - - 9 P B 1 - TMR2 _CH3 I2C2 - - _SC L 0 AF5 AF6 AF7 AF8 AF9 AF10 SPI1/SPI2 SPI3/I2 USART1/ UART4/ CAN1/2T OTG_F /I2S2/I2S2 Sext/I2 2/3/I2S3e 5/USAR MR12/13/ S/OTG_ ext S3 xt T6 14 HS - - SPI2_NSS I2S2_WS SPI2_SCK I2S2_CK USART 1_RX - - - - - - USART3 _TX - - - - - CAN1_R X CAN1_T X - - AF11 AF12 SMC/DMC/ ETH SDIO/OTG _FS SMC_N DCI_VSYN L C ETH_M - II_TXD AF 13 A F DC 1 I 4 EVE - - 3 I_D EVE - 6 - SDIO_D5 I_D EVE - 7 OTG_H ETH_M S_ULPI II_RX_ _D3 ER NTO UT DC - NTO UT DC SDIO_D4 AF15 NTO UT EVE - - - NTO UT ETH_M P B - 11 TMR2 _CH4 I2C2 - - _SD - - A USART3 _RX OTG_H - - S_ULPI _D4 II_TX_ EN ETH EVE - - - NTO UT _RMII_ TX_EN P B 1 2 TMR1 - _BKI N w w w. g e e h y. c o m I2C2 - - _SM BA SPI2_NSS I2S2_WS - USART3 _CK - CAN2_R X OTG_H ETH_R S_ULPI MII_TX _D5 D0 OTG_HS_I D EVE - - NTO UT Pa g e 3 2 AF0 Port SYS AF1 AF2 TMR1 TMR /2 3/4/5 AF3 TMR8 /9/10/ 11 AF4 I2C1/ 2/3 AF5 AF6 AF7 AF8 AF9 AF10 SPI1/SPI2 SPI3/I2 USART1/ UART4/ CAN1/2T OTG_F /I2S2/I2S2 Sext/I2 2/3/I2S3e 5/USAR MR12/13/ S/OTG_ ext S3 xt T6 14 HS AF11 AF12 SMC/DMC/ ETH SDIO/OTG _FS AF 13 A F DC 1 I 4 - - AF15 ETH_M II_TXD 0 ETH_R P B 1 TMR1 - _CH1 - - - N 3 SPI2_SCK I2S2_CK - USART3 _CTS - CAN2_T X OTG_H S_ULPI _D6 MII_TX D1 ETH_M EVE - NTO UT II_TXD 1 P B 1 TMR1 - 4 P B RTC_R 1 EFIN 5 _CH2 TMR8 - _CH2 N N TMR1 TMR8 _CH3 N w w w. g e e h y. c o m - _CH3 N - SPI2_MIS I2S2ext USART3 O _SD _RTS - SPI2_MO - SII2S2_S D - - - TMR12_ CH1 TMR12_ CH2 - - - - OTG_HS_ DM OTG_HS_ DP EVE - - NTO UT EVE - - NTO UT Pa g e 3 3 Table 6 GPIOC Multiplexing Function Configuration Port AF AF 0 1 SY S TM R1/ 2 AF2 TMR 3/4/5 AF3 TMR8/ 9/10/1 1 AF4 I2C1 /2/3 AF5 AF6 AF7 AF8 AF9 AF10 SPI1/SPI2/I SPI3/I2 USART1/ UART4/ CAN1/2T OTG_FS 2S2/I2S2ex Sext/I2 2/3/I2S3e 5/USAR MR12/13/ /OTG_H t S3 xt T6 14 S P C - - - - - - - - - - _ULPI_ - - - - - - - - - - - 1 P - - - - - 2 Po rt_ C P C AF 13 F1 SMC/DMC/S ETH DIO/OTG_F A DCI SPI2_MIS I2S2ext O _SD OTG_HS - - - DIR SPI2_MOS - - - - - 3 I - _ULPI_ - - - I2S2_SD AF15 4 S EVE - - - - STP P C AF12 OTG_HS 0 C AF11 NTO UT ETH_M DC ETH_MI I_TXD2 OTG_HS ETH _ULPI_ _MII_TX NXT _CLK EVE - - - NTO UT EVE - - - NTO UT EVE - - - NTO UT ETH_MI P C I_RXD0 - - - - - - - - - - - 4 ETH_R EVE - - - MII_RX NTO UT D0 ETH_MI P C I_RXD1 - - 5 - - - - - - - - - ETH_R MII_RX EVE - - - NTO UT D1 w w w. g e e h y. c o m Pa g e 3 4 Port AF AF 0 1 SY S TM R1/ 2 P C AF2 TMR 3/4/5 TMR - - 3_CH 6 1 P TMR C - - 3_CH 7 2 P C TMR - - 3_CH 8 3 P M C C 9 O2 TMR - 3_CH 4 AF3 TMR8/ 9/10/1 1 TMR8 _CH1 TMR8 _CH2 TMR8 _CH3 TMR8 _CH4 AF4 I2C1 /2/3 - - - AF5 AF6 AF7 AF8 AF9 AF10 SPI1/SPI2/I SPI3/I2 USART1/ UART4/ CAN1/2T OTG_FS 2S2/I2S2ex Sext/I2 2/3/I2S3e 5/USAR MR12/13/ /OTG_H t S3 xt T6 14 S I2S2_MCK - - _SD I2S_CKIN - - - USART6 _RX USART6 _CK ETH DIO/OTG_F - - - - - - - - - CK/ USART3_ UART4_ I2S3_C TX/ TX - - - - - 11 SPI3_M USART3_ UART4_ D ISO/ RX RX - - - - - - SDIO_D6 SDIO_D7 OSI USART3_ UART5_ - - 12 w w w. g e e h y. c o m - - - I2S3_S CK TX - D F1 DCI _D EVE - - - SDIO_D0 - - - SDIO_D1 - - - SDIO_D2 - - - SDIO_D3 - - - SDIO_CK NTO 0 UT DCI EVE _D - _D NTO UT DCI - AF15 4 1 SPI3_M P A DCI K I2S3ext_S 13 S SPI3_S P C CK _TX AF SMC/DMC/S A 10 C I2S3_M - AF12 I2C3 P C - USART6 AF11 EVE - NTO 2 UT DCI EVE _D - NTO 3 UT DCI EVE _D - NTO 8 UT DCI EVE _D - NTO 4 UT DCI EVE _D 9 - NTO UT Pa g e 3 5 Port AF AF 0 1 SY S TM R1/ 2 AF2 TMR 3/4/5 AF3 TMR8/ 9/10/1 1 AF4 I2C1 /2/3 AF5 AF6 AF7 AF8 AF9 AF10 AF11 SPI1/SPI2/I SPI3/I2 USART1/ UART4/ CAN1/2T OTG_FS 2S2/I2S2ex Sext/I2 2/3/I2S3e 5/USAR MR12/13/ /OTG_H t S3 xt T6 14 S AF12 AF 13 F1 SMC/DMC/S ETH DIO/OTG_F A DCI 4 S P C AF15 EVE - - - - - - - - - - - - - - - NTO 13 UT P EVE C - - - - - - - - - - - - - - - 14 UT P C NTO EVE - - - - - - - - - - - - - - - 15 NTO UT Table 7 GPIOD Multiplexing Function Configuration A F 0 AF 1 A AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 F1 AF12 1 AF1 3 Port A F1 P Por D0 t_D P D1 S TM Y R1/ S 2 - - TMR3 TMR8/ /4/5 9/10/11 - - - - - - w w w. g e e h y. c o m I2C E SPI3/I2S USART1/2 UART4/5 CAN1/2TM OTG_FS/ 2S2/I2S2ext ext/I2S3 /3/I2S3ext /USART6 R12/13/14 OTG_HS - - - - - CAN1_RX - - SMC_D2 - - - - - - - CAN1_TX - - SMC_D3 - - 3 T H SMC/DMC/S 4 SPI1/SPI2/I 1/2/ DIO/OTG_FS AF15 DCI EVEN TOUT EVEN TOUT Pa g e 3 6 A F 0 AF 1 A AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 F1 AF12 1 AF1 3 Port A F1 P D2 P D3 P D4 P D5 P D6 P D7 P D8 P D9 S TM Y R1/ S 2 - - TMR3 TMR8/ /4/5 9/10/11 TMR3 _ETR - I2C 1/2/ 3 - SPI1/SPI2/I SPI3/I2S USART1/2 UART4/5 CAN1/2TM OTG_FS/ 2S2/I2S2ext ext/I2S3 /3/I2S3ext /USART6 R12/13/14 OTG_HS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - w w w. g e e h y. c o m - USART2_ CTS USART2_ RTS USART2_ TX USART2_ RX USART2_ CK USART3_ TX USART3_ RX UART5_ RX E T H SMC/DMC/S DIO/OTG_FS 4 DCI DCI - - - SDIO_CMD _D1 - 1 - - - - SMC_CLK - - - - - - SMC_NOE - - - - - - SMC_NWE - - - - - - SMC_NWAIT - - - - - - - - - - - - SMC_D13 - - - - - - SMC_D14 - - SMC_NE1/S MC_NCE2 AF15 EVEN TOUT EVEN TOUT EVEN TOUT EVEN TOUT EVEN TOUT EVEN TOUT EVEN TOUT EVEN TOUT Pa g e 3 7 A F 0 AF 1 A AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 F1 AF12 1 AF1 3 Port A F1 S TM Y R1/ S 2 - - TMR3 TMR8/ /4/5 9/10/11 - - I2C 1/2/ 3 SPI1/SPI2/I SPI3/I2S USART1/2 UART4/5 CAN1/2TM OTG_FS/ 2S2/I2S2ext ext/I2S3 /3/I2S3ext /USART6 R12/13/14 OTG_HS - - - - - P D1 - 0 P D1 - - - - - - - - - - - - - 1 P D1 2 P D1 - - 3 P D1 - - 4 P D1 5 - - TMR4 _CH1 TMR4 _CH2 TMR4 _CH3 TMR4 _CH4 w w w. g e e h y. c o m USART3_ CK USART3_ CTS USART3_ RTS E T H SMC/DMC/S DIO/OTG_FS 4 DCI SMC_D15 - - - - - - - - - - - - - DMC_DQ10 - - - - - - - - SMC_A16 SMC_A17 DMC_DQ11 SMC_A18 - - - - - - - - DMC_DQ12 SMC_D0 - - - - - - - - DMC_DQ13 SMC_D1 - - - - - - - - DMC_DQ14 AF15 EVEN TOUT EVEN TOUT EVEN TOUT EVEN TOUT EVEN TOUT EVEN TO Pa g e 3 8 Table 8 GPIOE Multiplexing Function Configuration AF0 Port SYS AF1 AF2 TMR1 TMR /2 3/4/5 P E AF3 AF 4 AF5 AF6 AF7 AF8 AF9 AF10 TMR8/ I2C SPI1/SPI2/ SPI3/I2 USART1/ UART4/ CAN1/2T OTG_FS 9/10/1 1/2/ I2S2/I2S2e Sext/I2 2/3/I2S3e 5/USAR MR12/13/ /OTG_H 1 3 xt S3 xt T6 14 S AF11 AF12 SMC/DMC/ ETH SDIO/OTG_ FS TMR - - 0 4_ET - - - - - - - - - SMC_NBL0 R - - - 13 DC I A F1 - - - - - - - - - SMC_NBL1 1 I_D EVE - TRA E CEC UT DC EVE I_D - 2 LK Po P TRA rt_ E CED E 3 0 P TRA E CED 4 1 P TRA E CED 5 2 P TRA E CED 6 3 - - - - - - - - - MII_TX NTO UT ETH_ - NTO 2 3 P AF15 4 DC P E AF EVE SMC_A23 - - D3 NTO UT EVE - - - - - - - - - - - SMC_A19 - - NTO UT DC - - - w w w. g e e h y. c o m - - - - TMR9 _CH1 TMR9 _CH2 - - - - - - - - - - - - - - - - - - - - - - - - SMC_A20 SMC_A21 SMC_A22 I_D EVE - NTO 4 UT DC EVE I_D - NTO 6 UT DC EVE I_D 7 - NTO UT Pa g e 3 9 AF0 Port SYS P E - 7 P E - - 9 P - - 11 P - - 13 P E TMR1 _ETR AF7 AF8 AF9 AF10 TMR8/ I2C SPI1/SPI2/ SPI3/I2 USART1/ UART4/ CAN1/2T OTG_FS 9/10/1 1/2/ I2S2/I2S2e Sext/I2 2/3/I2S3e 5/USAR MR12/13/ /OTG_H 1 3 xt S3 xt T6 14 S AF11 AF12 SMC/DMC/ ETH SDIO/OTG_ FS AF 13 DC I A F1 _CH1 TMR1 _CH1 _CH2 TMR1 _CH2 _CH3 - TMR1 _CH3 TMR1 _CH4 w w w. g e e h y. c o m AF15 4 EVE - - - - - - - - - - SMC_D4 - - NTO UT EVE - - - - - - - - - - SMC_D5 - - NTO UT EVE - - - - - - - - - - SMC_D6 - - NTO UT EVE - - - - - - - - - - SMC_D7 - - NTO UT EVE - - - - - - - - - - SMC_D8 - - NTO UT EVE - - - - - - - - - - SMC_D9 - - N P 14 3/4/5 AF6 TMR1 12 E /2 4 AF5 N P E TMR AF TMR1 10 E TMR1 AF3 N P E AF2 TMR1 8 E AF1 NTO UT EVE - - - - - - - - - - SMC_D10 - - NTO UT EVE - - - - - - - - - - SMC_D11 - - NTO UT Pa g e 4 0 AF0 Port SYS P AF1 AF2 TMR1 TMR /2 3/4/5 AF AF3 4 AF5 AF6 AF7 AF8 AF9 AF10 TMR8/ I2C SPI1/SPI2/ SPI3/I2 USART1/ UART4/ CAN1/2T OTG_FS 9/10/1 1/2/ I2S2/I2S2e Sext/I2 2/3/I2S3e 5/USAR MR12/13/ /OTG_H 1 3 xt S3 xt T6 14 S - - - - - - - - AF11 AF12 SMC/DMC/ ETH SDIO/OTG_ AF 13 DC I FS A F1 4 TMR1 E - _BKI 15 - - SMC_D12 - AF15 - N EVE NTO Table 9 GPIOF Multiplexing Function Configuration A F 0 Port P F0 P F1 Po rt_ F P F2 P F3 P F4 P F5 AF 1 A AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 F1 AF12 1 S TM Y R1/ S 2 - - - - - - - - - - - - - - - - - - - - - - TMR 3/4/5 w w w. g e e h y. c o m TMR8/ CAN1/2T I2C1/ SPI1/SPI2/I SPI3/I2S USART1/2 UART4/5 2/3 2S2/I2S2ext ext/I2S3 /3/I2S3ext /USART6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9/10/1 1 I2C2_ SDA I2C2_ SCL I2C2_ SMBA MR12/13/1 4 OTG_FS/ E OTG_HS T H AF1 3 A F1 SMC/DMC/S DIO/OTG_FS SMC_A0 DMC_A10 SMC_A1 DMC_A0 SMC_A2 DMC_A1 SMC_A3 DMC_A2 SMC_A4 DMC_A3 SMC_A5 DCI AF15 4 - - - - - - - - - - - - EVEN TOUT EVEN TOUT EVEN TOUT EVEN TOUT EVEN TOUT EVEN TOUT Pa g e 4 1 A F 0 Port P F6 P F7 P F8 P F9 AF 1 A AF2 TM Y R1/ S 2 - - - - - - - AF4 AF5 AF6 AF7 AF8 AF9 AF10 F1 TMR 3/4/5 - TMR8/ 9/10/1 1 TMR1 0_CH1 TMR11 _CH1 - CAN1/2T I2C1/ SPI1/SPI2/I SPI3/I2S USART1/2 UART4/5 2/3 2S2/I2S2ext ext/I2S3 /3/I2S3ext /USART6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - MR12/13/1 4 TMR13_C H1 TMR14_C H1 OTG_FS/ E OTG_HS T H - - - 3 A F1 SMC/DMC/S DIO/OTG_FS SMC_NIORD DMC_A4 SMC_NREG DMC_A5 DCI R - - - - SMC_CD DMC_A7 SMC_INTR DMC_A8 P - - - - - - - - - - DCI - - - - - - - - - - - - DMC_UDQM 1 _D1 - 2 P F1 - - - - - - - - - - - - SMC_A6 - - - - - - - - - - - - - - SMC_A7 - - 2 P F1 3 w w w. g e e h y. c o m AF15 4 DMC_A6 0 F1 AF1 SMC_NIOW P F1 AF12 1 S - AF3 EVEN TOUT EVEN TOUT EVEN TOUT EVEN TOUT EVEN TOUT EVEN TOUT EVEN TOUT EVEN TOUT Pa g e 4 2 A F 0 Port AF 1 A AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 F1 AF12 1 S TM Y R1/ S 2 - - - - - - TMR 3/4/5 TMR8/ CAN1/2T E 3 A F1 SPI1/SPI2/I SPI3/I2S USART1/2 UART4/5 2/3 2S2/I2S2ext ext/I2S3 /3/I2S3ext /USART6 - - - - - - - - - SMC_A8 - - - - - - - - - - - SMC_A9 - - 1 MR12/13/1 T OTG_HS 4 H SMC/DMC/S DIO/OTG_FS DCI P F1 4 P F1 AF15 4 I2C1/ 9/10/1 OTG_FS/ AF1 5 EVEN TOUT EVEN TOUT Table 10 GPIOG Multiplexing Function Configuration A F 0 Port AF 1 AF2 AF3 AF 4 AF5 AF6 AF7 AF8 AF9 AF10 S TM TMR TMR8/ I2C SPI1/SPI2/I SPI3/I2 USART1/ UART4/5 CAN1/2T OTG_FS Y R1/ 3/4/ 9/10/1 1/2/ 2S2/I2S2ex Sext/I2 2/3/I2S3e /USART MR12/13/ /OTG_H S 2 5 1 3 t S3 xt 6 14 S AF11 AF12 AF1 3 F1 SMC/DMC/S ETH DIO/OTG_F A DCI 4 S P Por t_ G G EVE - - - - - - - - - - - - SMC_A10 - - 0 NTO UT P G AF15 - - - 1 w w w. g e e h y. c o m - - - - - - - - - SMC_A11 DMC_CK EVE - - NTO UT Pa g e 4 3 A F 0 Port AF 1 AF2 AF3 AF 4 AF5 AF6 AF7 AF8 AF9 AF10 S TM TMR TMR8/ I2C SPI1/SPI2/I SPI3/I2 USART1/ UART4/5 CAN1/2T OTG_FS Y R1/ 3/4/ 9/10/1 1/2/ 2S2/I2S2ex Sext/I2 2/3/I2S3e /USART MR12/13/ /OTG_H S 2 5 1 3 t S3 xt 6 14 S AF11 - - - - - - - - - - - ETH - P - - - - - - - - - - - - 3 P G - - - - - - - - - - - - 4 P G - - - - - - - - - - - - 5 P G - - - - - - - - - - - - 6 P G - - - - - - - - 7 P G - - - 8 w w w. g e e h y. c o m - - - - - USART6 _CK USART6 _RTS 3 DIO/OTG_F A F1 DCI AF15 4 S 2 G AF1 SMC/DMC/S P G AF12 SMC_A12 DMC_DQ15 SMC_A13 DMC_DQ0 SMC_A14 DMC_DQ1 SMC_A15 DMC_DQ2 SMC_INT2 DMC_DQ3 EVE - - NTO UT EVE - - NTO UT EVE - - NTO UT EVE - - NTO UT EVE - - NTO UT EVE - - - SMC_INT3 - - NTO UT - - ETH_PP S_OUT EVE DMC_DQ4 - - NTO UT Pa g e 4 4 A F 0 Port AF 1 AF2 AF3 AF 4 AF5 AF6 AF7 AF8 AF9 AF10 S TM TMR TMR8/ I2C SPI1/SPI2/I SPI3/I2 USART1/ UART4/5 CAN1/2T OTG_FS Y R1/ 3/4/ 9/10/1 1/2/ 2S2/I2S2ex Sext/I2 2/3/I2S3e /USART MR12/13/ /OTG_H S 2 5 1 3 t S3 xt 6 14 S P G - - - - - - - - 9 USART6 _RX - - AF11 AF1 3 ETH DIO/OTG_F A F1 SMC/DMC/S DCI 4 - SMC_NE2/S MC_NCE3 EVE - - - - - - - - - - - - - 10 _1/SMC_NE NTO UT SMC_NCE4 - AF15 S P G AF12 EVE - - 3 NTO UT ETH_MII P G _TX_EN - - - - - - - - - - - 11 ETH_RM II_TX_E SMC_NCE4 _2 EVE - - NTO UT N P G - - - - - - - - 12 - - - - - - - - 13 - - - SMC_NE4 - - USART6 _CTS - - _TXD0 ETH_RM EVE SMC_A24 - - - - 14 w w w. g e e h y. c o m - - - - - USART6 _TX - - _TXD1 ETH_RM II_TXD1 NTO UT ETH_MII - NTO UT II_TXD0 P G _RTS EVE ETH_MII P G USART6 EVE SMC_A25 - - NTO UT Pa g e 4 5 A F 0 Port AF 1 AF2 AF3 AF 4 AF5 AF6 AF7 AF8 AF9 AF10 S TM TMR TMR8/ I2C SPI1/SPI2/I SPI3/I2 USART1/ UART4/5 CAN1/2T OTG_FS Y R1/ 3/4/ 9/10/1 1/2/ 2S2/I2S2ex Sext/I2 2/3/I2S3e /USART MR12/13/ /OTG_H S 2 5 1 3 t S3 xt 6 14 S P G - - - - - - - USART6 - _CTS 15 AF11 AF12 AF1 3 F1 SMC/DMC/S ETH DIO/OTG_F A DCI 4 S DCI - - AF15 - DMC_LDQM _D1 EVE - 3 NTO UT Table 11 GPIOH Multiplexing Function Configuration A F 0 Port AF 1 S TM Y R1/ S 2 AF2 TMR 3/4/5 AF3 TMR8/ 9/10/1 1 AF4 I2C1/ 2/3 AF5 AF6 AF7 AF8 AF9 SPI1/SPI2/ SPI3/I2 USART1/ UART4/ CAN1/2T I2S2/I2S2e Sext/I2 2/3/I2S3e 5/USAR MR12/13/ xt S3 xt T6 14 AF10 OTG_FS/ OTG_HS AF11 AF12 AF13 F1 SMC/DMC/ ETH SDIO/OTG_ A DCI 4 FS P H AF15 EVE - - - - - - - - - - - - - - - NTO 0 UT Po P EVE rt_ H H 1 - - - - - - - - - - - - - - NTO UT P H - - - - 2 w w w. g e e h y. c o m - - - - - - - - ETH_M II_CRS EVE - - - NTO UT Pa g e 4 6 A F 0 Port AF 1 S TM Y R1/ S 2 AF2 TMR 3/4/5 AF3 TMR8/ 9/10/1 1 AF4 I2C1/ 2/3 AF5 AF6 AF7 AF8 AF9 SPI1/SPI2/ SPI3/I2 USART1/ UART4/ CAN1/2T I2S2/I2S2e Sext/I2 2/3/I2S3e 5/USAR MR12/13/ xt S3 xt T6 14 AF10 OTG_FS/ OTG_HS P H - - - - - - - - - - - 3 P H - - - - 4 P H - - - - 5 P H - - - - - - - - 7 P - - - - 8 P H I2C2 _SDA - - - - _SM I2C3 _SCL I2C3 _SDA - - 9 w w w. g e e h y. c o m - _SM BA F1 SMC/DMC/ ETH SDIO/OTG_ A DCI - _ULPI_N AF15 4 FS ETH_M II_COL EVE DMC_A9 - - NTO UT EVE - - - - NTO UT EVE - - - - - - - - - - NTO UT - - - - - - - - TMR12_C H1 - ETH_M - - II_RXD EVE - - - UT ETH_M EVE II_RXD - - - - - - - - - DMC_DQ8 HSY EVE - NC - - - - TMR12_C H2 - - NTO UT DCI_ - NTO 2 3 I2C3 - AF13 XT BA P H _SCL AF12 OTG_HS I2C2 6 H I2C2 AF11 - DCI_ D0 NTO UT EVE - NTO UT Pa g e 4 7 A F 0 Port AF 1 S TM Y R1/ S 2 P H AF2 TMR 3/4/5 - - 5_C H1 P TMR - - 5_C 11 H2 P TMR H - - 12 5_C 9/10/1 1 - - - - - - _CH1 N P TMR8 - - - _CH2 14 N P TMR8 H 2/3 AF6 AF7 AF8 AF9 SPI1/SPI2/ SPI3/I2 USART1/ UART4/ CAN1/2T I2S2/I2S2e Sext/I2 2/3/I2S3e 5/USAR MR12/13/ xt S3 xt T6 14 AF10 OTG_FS/ OTG_HS AF11 AF12 - - - - - - - - - - - - - - - - - - - - - AF13 F1 SMC/DMC/ ETH SDIO/OTG_ A DCI - - - 15 w w w. g e e h y. c o m _CH3 N AF15 4 FS - - - DMC_DQ9 - - DCI_ D1 DCI_ D2 DCI_ D3 EVE - NTO UT EVE - NTO UT EVE - NTO UT TMR8 13 H I2C1/ AF5 H3 P H TMR8/ AF4 TMR 10 H AF3 EVE - - - - - CAN1_TX - - DMC_DQ5 - - NTO UT - - - - - - - - - - - - - - - - - DMC_DQ6 DCI_ D4 DCI_ D11 EVE - NTO UT EVE - NTO UT Pa g e 4 8 Table 12 GPIOI Multiplexing Function Configuration A F Port PI 0 PI 1 PI 2 Po rt_ I PI 3 PI 4 PI 5 PI 6 0 AF 1 S TM Y R1/ S 2 AF2 TMR 3/4/5 AF3 AF 4 - 5_CH - - - - - - - - - - - - - - - - - w w w. g e e h y. c o m AF7 AF8 AF9 I2C SPI1/SPI2/I SPI3/I2 USART1/ UART4/ CAN1/2T 9/10/1 1/2/ 2S2/I2S2ex Sext/I2 2/3/I2S3e 5/USAR MR12/13/ 1 3 t S3 xt T6 14 - - 4 - AF6 TMR8/ TMR - AF5 - TMR8 _CH4 TMR8 _ETR TMR8 _BKIN TMR8 _CH1 TMR8 _CH2 - - SPI2_NSS I2S2_WS SPI2_SCK I2S2_CK - - SPI2_MIS I2S2ext O _SD - - - - - - - - - AF10 OTG_FS/ OTG_HS - - - AF11 AF12 ETH DIO/OTG_F I - - - - - - - - - - - DCI 4 - - - - - - - DMC_DQ7 - - DCI_ D13 DCI_ D8 DCI_ D9 DCI_ D10 DCI_ D5 EVE - - - - - - - - - VSYN EVE - - - - - - - - - - D6 NTO UT EVE - NTO UT EVE - NTO UT EVE - NTO UT EVE - C DCI_ NTO UT DCI_ - AF15 S I2S2_SD - A F1 SMC/DMC/S SPI2_MOS - AF13 NTO UT EVE - NTO UT Pa g e 4 9 A F Port PI 7 PI 8 PI 9 0 AF 1 S TM Y R1/ S 2 - - AF2 TMR 3/4/5 - AF3 AF 4 AF5 AF6 AF7 AF8 AF9 TMR8/ I2C SPI1/SPI2/I SPI3/I2 USART1/ UART4/ CAN1/2T 9/10/1 1/2/ 2S2/I2S2ex Sext/I2 2/3/I2S3e 5/USAR MR12/13/ 1 3 t S3 xt T6 14 TMR8 _CH3 - - - - - - AF10 OTG_FS/ OTG_HS - - - - - - - - - - - - AF13 F1 SMC/DMC/S ETH DIO/OTG_F A DCI AF15 4 S - DMC_WE DCI_ D7 EVE - NTO UT - DMC_CAS - - NTO UT EVE - - - - - - - - - CAN1_RX - - DMC_RAS - - NTO UT ETH_MI - - - - - - - - - - - 0 I_RX_E EVE DMC_CS - - R PI 1 AF12 EVE PI 1 AF11 UT OTG_HS - - - 1 w w w. g e e h y. c o m - - - - - - - _ULPI_DI R NTO EVE - DMC_BA - - NTO UT Pa g e 5 0 4 Function Description This chapter mainly introduces the system architecture, interrupt, on-chip memory, clock, power supply and peripheral features of APM32F405xG 407xExG series products; for information about the Arm® Cortex®-M4 core, please refer to the Arm® Cortex®-M4 Technical Reference Manual, which can be downloaded from Arm’s website. w w w. g e e h y. c o m Page51 4.1 System architecture 4.1.1 System block diagram Figure 5 APM32F405xG 407xExG System Block Diagram NVIC M4 with FPU I Code Ethernet MAC ART D Code Flash CCM Data RAM D-bus FMC I-bus S-bus JTAG/SWD Fast USB OTG Main SRAM1 Annex SRAM2 DMA1 AHB bus matrix DMA2 EMMC SRAM/External memory AHB1 GPIO A-I AHB2 Fast USB OTG CRC RCM RNG AHB/APB1 TMR2/3/4/5/6/7/12/13 /14 RTC AHB/APB2 TMR1/8/9/10/11 USART1/6 WWDT ADC1/2/3 IWDT SDIO SPI2/I2S2 SPI1 SPI3/I2S3 SYSCFG USART2/3 UART4/5 Camera interface EINT T-Sensor I2C1/2/3 CAN1/2 DAC1/2 w w w. g e e h y. c o m Page52 4.1.2 Address mapping Figure 6 APM32F405xG 407xExG Series Address Mapping Diagram 0xFFFF FFFF 0xE000 0000 Reserved M4 core Peripheral Reserved AHB Peripheral 0x4002 0000 Reserved APB2 Peripheral 0x4001 0000 Reserved APB1 Peripheral 0x4000 0000 0x2002 0000 Reserved SRAM 0x2000 0000 0x1FFF F008 Reserved Option Bytes 0x1FFF C000 0x1FFF F000 System storage area Reserved Flash 0x0800 0000 Mapping area 0x0000 0000 EMMC Reg. 0xA000 0000 Reserved RNG Reserved DCI Reserved USB OTG_FS Reserved 0x5006 0C00 0x5006 0800 USB OTG_HS1/2 Reserved MAC Reserved DMA2 DMA1 Reserved Backup SRAM FMC Reg. RCM Reserved CRC Reserved GPIOA-I 0x5000 0000 0x4008 0000 0x4004 0000 0x4002 9400 0x4002 8000 0x4002 6800 0x4002 6400 0x4002 6000 0x4002 5000 0x4002 0x4002 0x4002 0x4002 0x4002 0x4002 0x4002 0x4001 0800 TMR8 TMR1 0x4001 0400 0x4001 0000 DAC PMU Reserved CAN2 CAN1 Reserved I2C3 I2C2 I2C1 UART5 UART4 USART3 USART2 I2S3ext SPI3/I2S3 SPI2/I2S2 I2S2ext TMR14 TMR13 TMR12 TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 0x9FFF FFFF 0x9000 0000 EMMC bank 3 NAND (NAND2) 0x8000 0000 EMMC bank 2 NAND (NAND1) 0x7000 0000 EMMC bank 1 NOR/PSRAM 4/SDRAM 0x6C00 0000 EMMC bank 1 NOR/PSRAM 3/SDRAM 0x6800 0000 EMMC bank 1 NOR/PSRAM 2/SDRAM 0x6400 0000 EMMC bank 1 NOR/PSRAM 1/SDRAM 0x6000 0000 4000 3C00 3800 3400 3000 2400 0000 TMR11 TMR10 TMR9 EINT SYSCFG Reserved SPI1 SDIO Reserved ACD1/2/3 Reserved USART6 USART1 Reserved IWDT WWDT RTC Reserved w w w. g e e h y. c o m 0x5005 0400 0x5005 0000 0x5004 0000 EMMC bank4 PCCARD 0x4001 4800 0x4001 4400 0x4001 4000 0x4001 3C00 0x4001 3800 0x4001 0x4001 0x4001 0x4001 0x4001 0x4001 0x4001 3400 3000 2C00 2400 2000 1800 1400 0x4001 1000 0x4000 7400 0x4000 7000 0x4000 6C00 0x4000 6800 0x4000 6400 0x4000 6000 0x4000 0x4000 0x4000 0x4000 0x4000 0x4000 0x4000 5C00 5800 5400 5000 4C00 4800 4400 0x4000 4000 0x4000 3C00 0x4000 0x4000 0x4000 0x4000 3800 3400 3000 2C00 0x4000 2800 0x4000 2400 0x4000 2000 0x4000 1C00 0x4000 1800 0x4000 1400 0x4000 1000 0x4000 0x4000 0x4000 0x4000 0C00 0800 0400 0000 Page53 4.1.3 Startup configuration At startup, the user can select one of the following three startup modes by setting the high and low levels of the Boot pin:  Startup from main memory  Startup from BootLoader  Startup from built-in SRAM The user can use serial interface to reprogram the user Flash if starting up from BootLoader. 4.2 Core The core of APM32F405xG 407xExG is Arm® Cortex®-M4 with FPU computing unit. Based on this platform, the development cost is low and the power consumption is low. It can provide excellent computing performance and advanced system interrupt response, and is compatible with all Arm tools and software. 4.3 Interrupt controller 4.3.1 Nested Vector Interrupt Controller (NVIC) It embeds a nested vectored interrupt controller (NVIC) that can handle up to 79 maskable interrupt channels (not including 16 interrupt lines of Cortex®-M4) and 8 priority levels. The interrupt vector entry address can be directly transmitted to the core, so that the interrupt response processing with low delay can give priority to the late higher priority interrupt. 4.3.2 External Interrupt/Event Controller (EINT) The external interrupt/event controller consists of 23 edge detectors, and each detector includes edge detection circuit and interrupt/event request generation circuit; each detector can be configured as rising edge trigger, falling edge trigger or both and can be masked independently. Up to 140 GPIOs can be connected to 16 external interrupt lines. 4.4 On-chip memory On-chip memory includes main memory area, SRAM and information block; the information block includes system memory area and option byte; the system memory area stores BootLoader, 96-bit unique device ID and capacity information of main memory area; the system memory area has been written into the program when leaving the factory and cannot be erased. Table 13 On-chip Memory Area Memory Maximum capacity Function Main memory area 1MB Store user programs and data SRAM 192 KB CPU can access at 0 wait cycle (read/write) System memory area 30KB w w w. g e e h y. c o m Store BootLoader, 96-bit unique device ID, and main memory area capacity information Page54 4.4.1 Memory Maximum capacity Option byte 16Bytes Function Configure main memory area read-write protection and MCU working mode Configurable external memory controller (EMMC) APM32F405xG 407xExG series integrates EMMC module, consists of SMC (static memory controller), DMC (dynamic memory controller), and supports PC card, SRAM, SDRAM, PSRAM, NorFlash and NandFlash. Function introduction:  Three EMMC interrupt sources, connected to NVIC unit through logic or  Write FIFO  The code can run in off-chip memories except NAND flash and PC card  Connect to LCD 4.4.2 LCD parallel interface (LCD) EMMC can be configured to seamlessly connect with most graphic LCD controllers, and supports the modes of Intel 8080 and Motorola 6800, and can flexibly connect with specific LCD interface. This LCD parallel interface can be used to easily build a simple graphics application environment or the high-performance scheme of the special acceleration controller can be used. 4.5 Clock 4.5.1 Clock tree Clock tree of APM32F405xG 407xExG is shown in the figure below: w w w. g e e h y. c o m Page55 Figure 7 APM32F405xG 407xExG Clock Tree MACTXCLK PHY ETH 25-50MHz /2,20 SYSCFG_PMCFG[ETHSEL] MACRXCLK MACRMIICLK USB2.0 PHY 24-60MHz OTG_HS ULPI Cortex System Clock /8 LSICLK 40KHz IWDTCLK FCLK RTCSEL[1:0] SMCCLK OSC32_OUT OSC32_IN OSC_OUT OSC_IN LSECLK OSC 32.768 KHz /2,4 RTC /2...31 SW 4-26MHz HSECLK OSC 168MHz MAX SYSCLK 168MHz MAX 16MHz HSICLK HSECLK DMCCLK /B PLL A 42MHz MAX SCSEL C1 PLL1 D HCLK AHB Prescaler /1,2,4 512 APB1 Rrescaler /1,2,4,8,16 TMR2,3,4,5,6,7,12,13,14 if(APB1 prescaler=1)×1 else×2 42MHz MAX PLL48CLK TMRxCLK PCLK1 C2 C1 I2SSEL PLL2 D C2 I2S_CKIN I2SCLK MCOSEL1 LSECLK /2...5 ADCCLK (Analog) TMR1,8,9,10,11 if(APB2 prescaler=1)×1 else×2 TMRxCLK 84MHz MAX HSICLK MCO1 (Analog)ADC Prescaler /2,4,6,8 APB2 PRESCLAER /1,2,4,8,16 HSECLK PLL1CLK 84MHz MAX PCLK2 MCOSEL2 SYSCLK MCO2 /2...5 ETH PTP PLL2CLK HSECLK PLL1CLK 4.5.2 Clock source Clock source is divided into high-speed clock and low-speed clock according to the speed; the high-speed clock includes HSICLK and HSECLK, and the low-speed clock includes LSECLK w w w. g e e h y. c o m Page56 and LSICLK; besides, some modules may have additional clock source pins to obtain the required clock frequency through external circuits. 4.5.3 System clock HSICLK, PLLCLK and HSECLK can be selected as system clock; the clock source of PLLCLK can be HSICLK or HSECLK; the required system clock can be obtained by configuring PLL clock multiplier factor and frequency division factor. When the product is reset and started, HSICLK is selected as the system clock by default, and then the user can choose one of the above clock sources as the system clock. When HSECLK failure is detected, the system will automatically switch to the HSICLK, and if an interrupt is enabled, the software can receive the related interrupt. 4.5.4 Bus clock AHB, APB1 and APB2 buses are built in. The clock source of AHB is SYSCLK, and the clock source of APB1 and APB2 is HCLK; the required clock can be obtained by configuring the frequency division factor. The maximum frequency of AHB is 168MHz, the maximum frequency of APB2 is 84MHz, and the maximum frequency of APB1 is 42MHz. 4.5.5 Phase locked loop APM32F405xG 407xExG series product has two PLL, one is PLL (PLL1), and the other is PLL (PLL2) specially used to provide specific clock frequency for I2S. They all need to generate different clock frequencies by configuring parameters. Please refer to the User Manual for specific parameters and configuration registers. 4.6 Power and power management 4.6.1 Power supply scheme Table 14 Power Supply Scheme Name Voltage range VDD 1.8～3.6V VDDA/VSSA 1.8～3.6V VBAT 1.8～3.6V 4.6.2 Description I/O (see pin distribution diagram for specific IO) and internal voltage regulator are powered through VDD pin. Supply power for ADC, DAC, reset module, RC oscillator and PLL analog part; when ADC or DAC is used, VDDA and VSSA must be connected to VDD and VSS. When VDD is disabled, RTC, external 32KHz oscillator and backup register are powered through internal power switch. Voltage regulator Table 15 Regulator Operating Mode Name Description Master mode (MR) Used in run mode Low-power mode (LPR) Used in stop mode w w w. g e e h y. c o m Page57 Name Description Used in standby mode; when the voltage regulator has high-impedance output, the core Power-down mode circuit is powered down, the power consumption of the voltage regulator is zero, and all data of registers and SRAM will be lost. Note: The voltage regulator is always in working state after reset, and outputs with high impedance in power-down mode. 4.6.3 Power supply voltage monitor Power-on reset (POR), power-down reset (PDR) and brown-out reset circuits are integrated inside the product. These three circuits are always in working condition. When the power-down reset circuit monitors that the power supply voltage is lower than the specified threshold value (VPOR/PDR), even if the external reset circuit is used, the system will remain reset. The product has a built-in programmable power supply voltage monitor (PVD) that can monitor VDD and compare it with VPVD threshold. When VDD is outside the VPVD threshold range and the interrupt is enabled, the MCU can be set to a safe state through the interrupt service program. 4.7 Low-power mode APM32F405xG 407xExG supports three low-power modes, namely, sleep mode, stop mode and standby mode, and there are differences in power, wake-up time and wake-up mode among these three modes. The low-power mode can be selected according to the actual application requirements. Table 16 Low-power Mode Mode Description Sleep mode The core stops working, all peripherals are working, and it can be woken up through interrupts/events Under the condition that SRAM and register data are not lost, the lowest power consumption can be achieved in stop mode; The clock of the internal 1.3V power supply module will stop, HSECLK crystal resonator, HSICLK Stop mode and PLL will be disabled, and the voltage regulator can be configured in normal mode or low-power mode; Any external interrupt line can wake up MCU, and the external interrupt lines include one of the 16 external interrupt lines, PVD output, RTC and USB_OTG. The power consumption in this mode is the lowest; Internal voltage regulator is turned off, all 1.3V power supply modules are powered down, HSECLK Standby mode crystal resonator, and HSICLK clocks are disabled, SRAM and register data disappear, RTC area and backup register contents remain, and the standby circuit still works; The external reset signal on NRST, IWDT reset, rising edge on WKUP pin or RTC event will wake MCU out of standby mode. 4.8 DMA 2 built-in DMA, 16 data streams in total. Each data stream corresponds to 8 channels, but each w w w. g e e h y. c o m Page58 data stream can only use 1 channel at the same time. The peripherals supporting DMA requests are ADC, SPI, USART, I2C, and TMRx. Four levels of DMA channel priority can be configured. Support "memory→memory, memory→peripheral, peripheral→memory" data transmission (the memory includes Flash、SRAM、SDRAM). 4.9 GPIO GPIO can be configured as general input, general output, multiplexing function and analog input and output. The general input can be configured as floating input, pull-up input and pull-down input; the general output can be configured as push-pull output and open-drain output; the multiplexing function can be used for digital peripherals; and the analog input and output can be used for analog peripherals and low-power mode; the enable and disable pull-up/pull-down resistor can be configured; the speed of 2MHz, 10MHz and 50MHz can be configured; the higher the speed is, the greater the power and the noise will be. 4.10 Communication peripherals 4.10.1 USART/UART Up to 6 universal synchronous/asynchronous transmitter receivers are built in the chip. The USART1/6 interfaces can communicate at a rate of 10.5Mbit/s, while other USART/UART interfaces can communicate at a rate of 5.25Mbit/s. All USART/UART interfaces can configure baud rate, parity check bit, stop bit, and data bit length; they all can support DMA. USART/UART function differences are shown in the table below: Table 17 USART/UART Function Differences USART mode/function USART1 USART2 USART3 UART4 UART5 USART6 Hardware flow control of modem √ √ √ — — √ Smart card mode √ √ √ — — √ IrDA SIR coder-encoder functions √ √ √ √ √ √ LIN mode √ √ √ √ √ √ Standard characteristics √ √ √ √ √ √ SPI host √ √ √ — — √ 5.25 2.62 2.62 2.62 2.62 5.25 10.50 5.25 5.25 5.25 5.25 10.5 APB2 APB1 APB1 APB1 APB1 APB2 Maximum baud rate under 16-time oversampling (Mbit/s) Maximum baud rate under 8-time oversampling (Mbit/s) APB mapping Note: √ = support. 4.10.2 I2C I2C1/2/3 bus interfaces are built-in and they all can work in multiple-master or slave modes, w w w. g e e h y. c o m Page59 support 7-bit or 10-bit addressing, and support dual-slave addressing in 7-bit slave mode; the communication rate supports standard mode (up to 100kbit/s) and fast mode (up to 400kbit/s); hardware CRC generator/checker are built in; they can operate with DMA and support SMBus 2.0 version/PMBus. 4.10.3 SPI/I2S 3 built-in SPI, support full-duplex and half-duplex communication in master mode and slave mode, can use DMA controller, and can configure 4~16 bits per frame, and 3 SPI can communicate at a rate of up to 42Mbit/s, 21MBit/s and 21MBit/s respectively. 2 built-in I2S (multiplexed with SPI2 and SPI3 respectively), support half-duplex communication in master mode and slave mode, support synchronous transmission, and can be configured with 16-bit, 24-bit and 32-bit data transfer with 16-bit or 32-bit resolution. The configurable range of audio sampling rate is 8kHz~192kHz; when one or two I2S interfaces are configured as the master mode, the master clock can be output to external DAC or decoder (CODEC) at 256-time sampling frequency. 4.10.4 CAN 2 built-in CAN, compatible with 2.0A and 2.0B (active) specification, and can communicate at a rate of up to 1Mbit/s. It can receive and transmit standard frame of 11-bit identifier and extended frame of 29-bit identifier. It has 3 sending mailboxes and 2 receiving FIFO, and 14 3-level adjustable filters. 4.10.5 USB_OTG Three USB controllers, namely, one OTG_FS and two OTG_HS, are embedded in the product. They all can support both host and slave functions to comply with the On-The-Go supplementary standard of USB 2.0 specification, and can also be configured as "Host only" or "Slave only" mode, to fully comply with USB 2.0 specification. OTG_FS clock (48MHz) is output by specific PLL, and OTG_HS clock (60MHz) is provided by external PHY. 4.10.6 Ethernet Provides an IEEE-802.3-2002 compatible MAC for Ethernet LAN communication over MII or RMII. This MCU requires a PHY connection to a physical LAN bus. The PHY connects to the MII port, uses 17 signals for MII or 9 signals for RMII, and can use a 25MHz clock (MII) from the kernel. 4.10.7 SDIO The secure digital input/output interface can connect SD card, SD I/O card, multi-media card (MMC) and CE-ATA card master interfaces, and provide data transmission between APB2 system bus and SD memory card, SD I/O card, MMC and CE-ATA device. w w w. g e e h y. c o m Page60 4.11 Analog peripherals 4.11.1 ADC 3 built-in ADC with 12-bit accuracy, up to 21 external channels and 3 internal channels for each ADC. The internal channels measure the temperature sensor voltage, reference voltage and backup voltage respectively. A/D conversion mode of each channel has single, continuous, scan or intermittent modes, ADC conversion results can be left aligned or right aligned and stored in 16-bit data register; they support analog watchdog, and DMA. 4.11.1.1 Temperature sensor 1 temperature sensor (TSensor) is built in, which is internally connected with ADC_IN16 channel. The voltage generated by the sensor changes linearly with temperature and the converted voltage value can be obtained by ADC and converted into temperature. 4.11.1.2 Internal reference voltage Built-in reference voltage VREFINT, internally connected to ADC_IN17 channel; VREFINT can be obtained through ADC; VREFINT provides stable voltage output for ADC. 4.11.2 DAC 2 built-in 12-bit DAC, each corresponding to an output channel, which can be configured as 8bit and 12-bit modes, and the DMA function is supported. The waveform generation supports noise wave and triangle wave. The conversion mode supports independent or simultaneous conversion and the trigger mode supports external signal trigger and internal timer update trigger. 4.12 Timer 2 built-in 16-bit advanced timers (TMR1/8), 8 16-bit general-purpose timers (TMR3/4/9/10/11/12/13/14), 2 32-bit general timers (TMR2/5), 2 16-bit basic timers (TMR6/7), 1 independent watchdog timer, 1 window watchdog timer and 1 system tick timer. Watchdog timer can be used to detect whether the program is running normally. The system tick timer is the peripheral of the core with automatic reloading function. When the counter is 0, it can generate a maskable system interrupt, which can be used for real-time operating system and general delay. Table 18 Function Comparison between Advanced/General-purpose/Basic and System Tick Timers System tick Timer type Timer name timer Basic timer General-purpose timer Sys Tick Timer TMR6/7 TMR2/5 24 bits 16 bits 32 bits Counter resolution w w w. g e e h y. c o m TMR3/4/9/10/1 1/12/13/14 16 bits Advanced timer TMR1/8 16 bits Page61 System tick Timer type Basic timer General-purpose timer Advanced timer Up Up, down, up/down Up, down, up/down Any integer between Any integer between 1 and Any integer between 1 and 1 and 65536 65536 65536 - OK OK OK - - 4 4 - None None Yes timer Counter type Down Prescaler - factor Generate DMA request Capture/comp are register Complementar y output 1-way external trigger signal input pin; Pin - characteristics - 1-way external trigger 1-way braking input signal signal input pin; pin; 4-way non-complementary 3-pair complementary channel pin. channel pins; 1-way non-complementary channel pin. It has complementary Special for real- PWM output with dead time operating Function Description system. Synchronization or event Automatic chaining function provided. reloading Timers in debug mode can function Used to generate be frozen. supported. DAC trigger signals. Can be used to generate When the Can be used as a 16- PWM output. counter is 0, it bit general-purpose Each timer has can generate a timebase counter. independent DMA request When configured as a 16bit standard timer, it has the same function as the TMRx timer. When configured as a 16bit PWM generator, it has maskable mechanism. system interrupt. It can handle incremental Can program encoder signals. the clock band insertion. full modulation capability (0~100%). In debug mode, the timer can be frozen, and PWM output is disabled. Synchronization or event source. chaining function provided. Table 19 Function Comparison between IWDT and WWDT Name Independent watchdog w w w. g e e h y. c o m Counter resolution Counter type Prescaler factor Any integer 12 bits Down between 1 and 256 Function description The clock is provided by an internally independent RC oscillator of 28KHz, which is independent of the master clock, so it can run in stop and standby modes. Page62 Name Counter resolution Counter type Prescaler Function description factor The whole system can be reset in case of problems. It can provide timeout management for applications as a free-running timer. It can be configured as a software or hardware startup watchdog through option bytes. Timers in debug mode can be frozen. Can be set for free running. The whole system can be reset in case of Window watchdog 7 bits Down - problems. Driven by the master clock, it has early interrupt warning function; Timers in debug mode can be frozen. 4.13 RTC 1 RTC is built in, and there are LSECLK signal input pins (OS32_IN and OS32_OUT) and 2 TAMP input signal detection pins (RTC_TAMP1/2); the clock source can select external 32.768kHz crystal oscillator, resonator or oscillator, LSICLK and HSECLK/128; it is powered by VDD by default; when VDD is powered off, it can be automatically switched to VBAT power supply, and RTC configuration and time data will not be lost; RTC configuration and time data will not be lost in case of system reset, software reset and power-on reset; it supports clock and calendar functions. 4.13.1 Backup domain 4KB backup SRAM and 20 backup registers are built in, and are powered by VDD by default; when VDD is powered off, it can be automatically switched to VBAT power supply, and the data in backup register will not be lost; the data in backup register will not be lost in case of system reset, software reset and power-on reset. 4.14 RNG A RNG is embedded, and it provides 32-bit random number generated by the integrated simulation. 4.15 DCI DCI is used to receive high-speed data streams from CMOS camera. It supports different data formats and is applicable to black-and-white cameras, X24 cameras and so on. w w w. g e e h y. c o m Page63 4.16 CRC 1 CRC (cyclic redundancy check) computing unit is built in, which can generate CRC codes and operate 8-bit, 16-bit and 32-bit data. 5 Electrical Characteristics 5.1 Test conditions of electrical characteristics 5.1.1 Maximum and minimum values Unless otherwise specified, all products are tested on the production line at TA=25℃. Its maximum and minimum values can support the worst environmental temperature, power supply voltage and clock frequency. In the notes at the bottom of each table, it is stated that the data are obtained through comprehensive evaluation, design simulation or process characteristics and are not tested on the production line; on the basis of comprehensive evaluation, after passing the sample test, take the average value and add and subtract three times the standard deviation (average ±3∑) to get the maximum and minimum values. 5.1.2 Typical value Unless otherwise specified, typical data are measured based on TA=25℃, VDD=VDDA=3.3V. These data are only used for design guidance. 5.1.3 Typical curve Unless otherwise specified, typical curves will only be used for design guidance and will not be tested. w w w. g e e h y. c o m Page64 5.1.4 Power supply scheme Figure 8 Power Supply Scheme MCU VBAT VBAT Power switch GPIOs 2×2.2μF LSECLK, RTC, backup register Input Schmidt trigger, output buffer VCAP_1 VCAP_2 VDD VDDX Voltage regulator x×100nF＋ 1×4.7μF Core, Flash, SRAM, I/O logic, digital peripheral VSS BYPASS_REG PDR_ON VDD VDDA 1×100nF＋1×1μF Reset controller RC oscillator, analog peripheral VSSA VDD VREF+ ADC、DAC 1×100nF＋1×1μF VREF- Notes: VDDx in the figure means the number of VDD is x w w w. g e e h y. c o m Page65 5.1.5 Load capacitance Figure 9 Load conditions when measuring pin parameters MCU pin c=50p Figure 10 Pin Input Voltage Measurement Scheme MCU pin VIN Figure 11 Power Consumption Measurement Scheme VDD A IDDA A VBAT MCU IDD VDDX VSS VREF+ VDDA VSSA IDD_VBAT A VREF- VBAT Test under general operating conditions 5.2 Table 20 General Operating Conditions Minimum Maximum value value - - 168 Internal APB1 clock frequency - - 42 fPCLK2 Internal APB2 clock frequency - - 84 VDD Main power supply voltage - 1.8 3.6 V VDDA Analog power supply voltage Must be the same 1.8 2.4 V Symbol Parameter Conditions fHCLK Internal AHB clock frequency fPCLK1 w w w. g e e h y. c o m Unit MHz Page66 Symbol Parameter Conditions (When neither ADC nor DAC is used) as VDD Minimum Maximum value value 2.4 3.6 1.65 3.60 V -40 85 ℃ Analog power supply voltage (When ADC and DAC are used) 5.3 VBAT Power supply voltage of backup domain TA Ambient temperature (temperature number 6) Maximum power dissipation Unit Absolute maximum ratings If the load on the device exceeds the absolute maximum rating, it may cause permanent damage to the device. Here, only the maximum load that can be borne is given, and there is no guarantee that the device functions normally under this condition. 5.3.1 Maximum temperature characteristics Table 21 Temperature Characteristics Symbol Description Value Unit TSTG Storage temperature range -65 ~ +150 ℃ TJ Maximum junction temperature 125 ℃ 5.3.2 Maximum rated voltage characteristics All power supply (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the power supply within the external limited range. Table 22 Maximum Rated Voltage Characteristics Minimum Maximum value value External main power supply voltage -0.3 4.0 Input voltage on FT pins VSS-0.3 VDD+4 Input voltage on other pins VSS-0.3 4.0 | ΔVDDx | Voltage difference between different power supply pins - 50 | VSSx-VSS | Voltage difference between different grounding pins - 50 Symbol Description VDD - VSS Unit V VIN mV 5.3.3 Maximum rated current characteristics Table 23 Current Characteristics Maximum Symbol Description IVDD Total current through VDD/VDDA power line (supply current) (1) 240 IVSS Total current through VSS ground line (outflow current) (1) 240 w w w. g e e h y. c o m value Unit mA Page67 Symbol Maximum Description value Sink current on any I/O and control pin 25 Source current on any I/O and control pin 25 Injection current of 5T pin -5/+0 Injection current of other pins ±5 Total injection current on all I/O and control pins (4) ±25 Unit IIO IINJ(PIN) (2) ΣIINJ(PIN)(2) 1． All power supply (VDD, VDDA) and ground (VSS, VSSA) must always be within the allowed range. 2． The outflow current will interfere with the analog performance of the device. 3． I/O cannot be injected positively: when VIN VDD, the current flows into the pins; when VIN25MHz, turn on PLL; otherwise, turn off PLL. (3) When the analog peripherals such as ADC, DAC, HSECLK, LSECLK, HSICLK and LSICLK are turned on, extra power consideration needs to be considered. w w w. g e e h y. c o m Page74 Table 36 Power Consumption in Run Mode when the Program is Executed in Flash (ART is turned off) Parameter Conditions HSECLK bypass (2) , enabling all peripherals (3) Power fHCLK Typical value (1) Maximum value (1) TA=25℃，VDD=3.3V TA=105℃，VDD=3.6V IDDA(μA) IDD(mA） IDDA(μA) IDD(mA) 168MHz 751.66 64.25 802.00 70.52 144MHz 693.58 51.09 745.30 56.05 120MHz 637.26 43.99 690.20 48.92 90MHz 780.86 34.91 831.40 39.97 60MHz 636.78 25.02 689.40 29.90 30MHz 636.66 14.33 689.00 19.32 25MHz 115.36 11.80 127.72 16.725 16MHz 115.36 7.83 127.75 12.53 8MHz 115.35 4.27 127.80 8.99 4MHz 115.35 2.45 127.88 7.13 2MHz 115.362 1.57 127.76 6.28 168MHz 750.94 24.71 801.40 30.85 144MHz 692.82 20.21 744.70 25.18 120MHz 636.76 17.96 689.80 22.91 90MHz 780.46 15.03 831.60 20.01 60MHz 636.46 11.19 689.80 16.13 30MHz 636.38 6.79 689.90 11.68 25MHz 115.33 5.26 128.50 10.15 16MHz 115.32 3.65 127.96 8.46 8MHz 115.36 2.14 127.82 6.80 4MHz 115.35 1.43 127.68 6.11 2MHz 115.53 1.07 127.90 5.82 consumption in run mode HSECLK bypass (2) , disabling all peripherals Note: (1) The data are obtained from a comprehensive evaluation and are not tested in production. (2) The external clock is 4MHz; when fHCLK>25MHz, turn on PLL; otherwise, turn off PLL. (3) When the analog peripherals such as ADC, DAC, HSECLK, LSECLK, HSICLK and LSICLK are turned on, extra power consideration needs to be considered. w w w. g e e h y. c o m Page75 Table 37 Power Consumption in Run Mode when the Program is Executed in RAM Parameter Conditions HSECLK bypass (2) , enabling all peripherals (3) Power fHCLK Typical value (1) Maximum value (1) TA=25℃，VDD=3.3V TA=105℃，VDD=3.6V IDDA(μA) IDD(mA) IDDA(μA) IDD(mA) 168MHz 752.14 70.29 803.80 76.51 144MHz 693.74 54.73 745.50 59.73 120MHz 637.60 46.22 690.40 51.16 90MHz 781.00 35.67 832.00 40.53 60MHz 637.02 24.70 689.8 29.65 30MHz 636.74 13.74 689.2 18.596 25MHz 115.42 11.23 127.85 16.02 16MHz 115.374 7.42 127.88 12.21 8MHz 115.37 4.05 127.81 8.836 4MHz 115.376 2.38 127.72 7.12 2MHz 115.347 1.53 127.76 6.28 168MHz 751.38 31.03 802.4 37.29 144MHz 693.00 24.11 744.7 29.11 120MHz 636.88 20.30 689.80 25.23 90MHz 780.56 15.81 931.60 20.74 60MHz 636.68 10.92 690.00 15.80 30MHz 636.62 6.19 689.70 11.02 25MHz 115.36 4.75 128.42 9.48 16MHz 115.35 3.26 128.79 8.07 8MHz 115.38 1.97 127.76 6.71 4MHz 115.36 1.33 127.73 6.04 2MHz 115.34 1.02 127.74 5.70 consumption in run mode HSECLK bypass (2) , disabling all peripherals Note: (1) The data are obtained from a comprehensive evaluation and are not tested in production. (2) The external clock is 4MHz, and when f HCLK>25MHz, turn on PLL, otherwise, turn off PLL. (3) When the analog peripherals such as ADC, DAC, HSECLK, LSECLK, HSICLK and LSICLK are turned on, extra power consideration needs to be considered. w w w. g e e h y. c o m Page76 5.7.3 Power consumption in sleep mode Table 38 Power Consumption in Sleep Mode when the Program is Executed in Flash (ART is turned off) Parameter Conditions HSECLK bypass (2), enabling all peripherals Power fHCLK Typical value (1) Maximum value (1) TA=25℃，VDD=3.3V TA=105℃，VDD=3.6V IDDA(μA) IDD(mA) IDDA(μA) IDD(mA) 168MHz 751.34 54.18 802.1 60.33 144MHz 693.26 42.25 745.00 47.12 120MHz 637.24 35.75 689.80 40.53 90MHz 780.60 27.69 831.20 32.539 60MHz 636.72 19.33 689.20 24.149 30MHz 636.46 11.02 689.20 15.8 25MHz 115.356 8.96 127.77 13.7 16MHz 115.34 5.99 127.71 10.68 8MHz 115.334 3.33 127.78 8.01 4MHz 115.332 2.00 127.84 6.669 2MHz 115.352 1.34 127.82 6.017 168MHz 750.52 13.91 801.00 19.86 144MHz 692.58 10.82 743.90 15.64 120MHz 636.46 9.20 689.00 13.99 90MHz 780.24 7.44 830.60 12.21 60MHz 636.42 5.33 689.00 10.07 30MHz 636.36 3.38 688.80 8.10 25MHz 115.37 2.41 127.84 7.08 16MHz 115.35 1.79 127.74 6.46 8MHz 115.35 1.23 127.83 5.91 4MHz 115.36 0.96 127.86 5.63 2MHz 115.42 0.83 127.84 5.54 consumption in sleep mode HSECLK bypass (2) , disabling all peripherals Note: (1) The data are obtained from a comprehensive evaluation and are not tested in production. (2) The external clock is 4MHz; when fHCLK>25MHz, turn on PLL; otherwise, turn off PLL. w w w. g e e h y. c o m Page77 5.7.4 Power consumption in stop mode Table 39 Power Consumption in Stop Mode Maximum Typical value (1), value (1), (TA=25℃) (VDD=3.6V) Conditions VDD=3.3V TA=105℃ VDD=3.6V IDDA IDD IDDA IDD IDDA IDD IDDA IDD (μA) (mA) (μA) (mA) (μA) (mA) (μA) (mA) 9.28 0.69 9.80 0.70 10.05 0.71 12.36 20.00 9.23 0.69 9.72 0.70 10.00 0.70 12.35 20.00 4.18 0.21 4.65 0.21 4.87 0.21 5.91 15.00 4.19 0.20 4.64 0.20 4.86 0.20 5.86 15.00 Flash is in stop mode, and RC The regulator is in run mode, and all oscillators are in off state internal oscillator and high-speed oscillator are turned off (with no independent watchdog) Flash is in power-down mode, and RC internal oscillator and highspeed oscillator are turned off (with no independent watchdog) Flash is in stop mode, and RC The regulator is in low-power mode, and all oscillators are in off state 5.7.5 VDD=2.4V internal oscillator and high-speed oscillator are turned off (with no independent watchdog) Flash is in power-down mode, and RC internal oscillator and highspeed oscillator are turned off (with no independent watchdog) Power consumption in standby mode Table 40 Power Consumption in Standby Mode Maximum value (1), Typical value (1), (TA=25℃) Conditions VDD=2.4V VDD=3.3V (VDD=3.6V) TA=105℃ VDD=3.6V IDDA IDD IDDA IDD IDDA IDD IDDA IDD (μA) (μA) (μA) (μA) (μA) (μA) (μA) (μA) 2.15 8.38 2.56 9.73 2.83 10.19 3.76 59.39 2.15 3.52 2.62 4.46 2.81 5.11 3.48 32.00 The backup SRAM is turned on, and the lowPower supply speed oscillator and RTC current in are turned on standby The backup SRAM is mode turned off, and the lowspeed oscillator and RTC are turned on w w w. g e e h y. c o m Page 78 Maximum value (1), Typical value (1), (TA=25℃) Conditions VDD=2.4V VDD=3.3V (VDD=3.6V) TA=105℃ VDD=3.6V IDDA IDD IDDA IDD IDDA IDD IDDA IDD (μA) (μA) (μA) (μA) (μA) (μA) (μA) (μA) 2.13 7.33 2.62 8.24 2.81 8.64 3.45 58.24 2.13 2.51 2.61 3.31 2.78 3.68 3.45 19.2 The backup SRAM is turned on, and the RTC is turned off The backup SRAM is turned off, and the RTC is turned off Note: (1) The data are obtained from a comprehensive evaluation and are not tested in production. 5.7.6 Peripheral power consumption Peripheral power consumption = current that enables the peripheral clock-current that disables the peripheral clock. Table 41 Peripheral Power Consumption Parameter AHB1 (up to 168MHz) Peripheral Typical value (1) TA=25℃, VDD=3.3V 168MHz 144MHz DMA1 5.4 4.21 DMA2 5.56 4.3 ETH 3 2.35 OTG_HS 4.21 3.26 GPIOA 0.32 0.25 GPIOB 0.31 0.24 GPIOC 0.32 0.24 GPIOD 0.3 0.23 GPIOE 0.31 0.25 GPIOF 0.33 0.26 GPIOG 0.3 0.24 GPIOH 0.3 0.24 GPIOI 0.3 0.24 CRC 0.03 0.03 BAKPR 0.07 0.05 OTG_FS 3.12 2.41 DCI 0.79 0.61 RNG 0.16 0.12 HASH 1.3 1 Unit μA/MHz AHB2 (up to 168MHz) w w w. g e e h y. c o m Page 79 Parameter AHB3 (up to 168MHz) APB1 (up to 42MHz) APB2 (up to 84MHz) w w w. g e e h y. c o m Peripheral Typical value (1) TA=25℃, VDD=3.3V 168MHz 144MHz CRYP 0.25 0.19 EMMC 1.68 1.3 TMR2 0.46 0.36 TMR3 0.35 0.27 TMR4 0.34 0.27 TMR5 0.46 0.35 TMR6 0.08 0.07 TMR7 0.08 0.06 TMR12 0.19 0.15 TMR13 0.14 0.11 TMR14 0.14 0.1 WWDT 0.02 0.02 SPI2/I2S2 0.12 0.1 SPI3/I2S3 0.12 0.1 USART2 0.11 0.09 USART3 0.12 0.09 UART4 0.11 0.08 UART5 0.11 0.08 I2C1 0.12 0.09 I2C2 0.12 0.09 I2C3 0.12 0.1 CAN1 0.18 0.14 CAN2 0.16 0.13 PMU 0.01 0.01 DAC 0.08 0.06 SDIO 0.41 0.32 TMR1 0.99 0.77 TMR8 0.97 0.77 TMR9 0.41 0.32 TMR10 0.27 0.21 TMR11 0.26 0.22 ADC1 0.27 0.22 Unit Page 80 Parameter Typical value (1) TA=25℃, VDD=3.3V Peripheral 168MHz 144MHz ADC2 0.27 0.22 ADC3 0.28 0.23 SPI1 0.12 0.11 USART1 0.22 0.18 USART6 0.21 0.18 SYSCFG 0.05 0.05 Unit Note: The data are obtained from a comprehensive evaluation and are not tested in production. 5.7.7 Backup Domain Power Consumption Table 42 VBAT Power Consumption Typical value (1), TA=25℃ Symbol Parameter Maximum value (1), Unit VBAT=3.6V Conditions VBAT=2.4V VBAT=3.3V TA=85℃ TA=105℃ 1.894 2.262 6 11 1.08 1.412 3 5 0.926 1.116 5 10 0.02 0.128 2 4 The backup SRAM is turned on, and the low-speed oscillator and RTC are turned on The backup SRAM is turned IDD_VBAT LSECLK off, and the low-speed and RTC oscillator and RTC are are in ON turned on state The backup SRAM is turned on, and the RTC is turned μA off The backup SRAM is turned off, and the RTC is turned off Note: (1) The data are obtained from a comprehensive evaluation and are not tested in production. 5.8 Wake-up time in low-power mode The measurement of wake-up time in low-power mode is from the start of wake-up event to the time when the user program reads the first instruction, in which VDD=VDDA. Table 43 Wake-up Time in Low-power Mode Symbol tWUSLEEP Parameter Wake-up from sleep mode w w w. g e e h y. c o m Conditions Min Typ Max Unit - 39.00 59 61.20 ns Page 81 Symbol Parameter Conditions The regulator is in run mode, and Flash is in stop state The regulator is in low-power mode, and Flash tWUSTOP Wake up from is in stop state the stop mode The regulator is in run mode, and Flash is in deep power-down mode The regulator is in low-power mode, and Flash is in deep power-down mode tWUSTDBY Wake up from - standby mode Min Typ Max Unit 12.51 13.602 14.99 15.51 19.552 22.93 125.63 133.156 135.16 133.52 136.956 139.60 173.03 214.056 227.96 μs Note: The data are obtained from a comprehensive evaluation and are not tested in production. 5.9 I/O port characteristics Table 44 DC Characteristics (TA=-40℃-105℃, VDD=2~3.6V) Symbol VIL VIH Vhys Parameter Conditions Min Typ Max STD and STDA I/O - - 0.3VDD-0.04 5T and 5Tf I/O - - 0.3VDD Boot0 pin - - 0.1DD+0.1 STD and STDA I/O 0.45VDD+0.3 - - 5T and 5Tf I/O 0.7VDD - - Boot0 pin 0.17VDD+0.7 - - Schmidt trigger STD, STDA and 5T, 5Tf I/O 10% VDD - - hysteresis Boot0 pin 0.1 - - - - ±1 Low-level input voltage High-level input voltage Ilkg RPU Weak pull-down equivalent resistance CIO V μA 5T and 5Tf I/O, VDDIOx≤VIN≤5V - - 3 Except PA10 and PB12, VIN=VSS 30 40 50 PA10 and PB12 7 10 14 Except PA10 and PB12, VIN=VDD 30 40 50 PA10 and PB12 7 10 14 - - 5 - equivalent resistance RPD VDDIOx≤VIN≤VDDA current Weak pull-up V mV STDA in digital mode, Input leakage Unit I/O pin capacitance w w w. g e e h y. c o m kΩ pF Page 82 Table 45 AC Characteristics (TA=25℃) SPEED[1:0] Symbol fmax(IO)out Parameter Conditions Min Max CL=50pF,VDD＞2.7V - 4 CL=50pF,VDD＞1.8V - 2 CL=10pF,VDD＞2.7V - 8 CL=10pF,VDD＞1.8V - 4 CL=50 pF,VDD=1.8 V-3.6V - 100 CL=50pF,VDD＞2.7V - 25 CL=50pF,VDD＞1.8V - 12.5 CL=10pF,VDD＞2.7V - 50 CL=10pF,VDD＞1.8V - 20 CL=30pF,VDD＞2.7V - 10 high to low level and rise CL=30pF,VDD＞1.8V - 20 time of output from low CL=10pF,VDD＞2.7V - 6 CL=10pF,VDD＞1.8V - 10 CL=30pF,VDD＞2.7V - 50 CL=30pF,VDD＞1.8V - 25 CL=10pF,VDD＞2.7V - 100 CL=10pF,VDD＞1.8V - 50 CL=30pF,VDD＞2.7V - 6 high to low level and rise CL=30pF,VDD＞1.8V - 10 time of output from low CL=10pF,VDD＞2.7V - 4 CL=10pF,VDD＞1.8V - 6 CL=30pF,VDD＞2.7V - 100 CL=30pF,VDD＞1.8V - 50 CL=10pF,VDD＞2.7V - 180 CL=10pF,VDD＞1.8V - 100 CL=30pF,VDD＞2.7V - 4 CL=30pF,VDD＞1.8V - 6 CL=10pF,VDD＞2.7V - 2.5 Maximum frequency 00 Unit MHz Fall time of output from tf(IO)out/tr(IO)out high to low level and rise time of output from low ns to high level fmax(IO)out Maximum frequency MHz 01 Fall time of output from tf(IO)out/tr(IO)out to high level fmax(IO)out Maximum frequency ns MHz 10 Fall time of output from tf(IO)out/tr(IO)out to high level fmax(IO)out Maximum frequency 11 Fall time of output from tf(IO)out/tr(IO)out high to low level and rise time of output from low to high level w w w. g e e h y. c o m ns MHz ns Page 83 SPEED[1:0] Symbol Parameter Conditions Min Max CL=10pF,VDD＞1.8V - 4 - 10 - Unit Pulse width of external - tEINTIpw signal detected by EINT controller Figure 12 I/O AC Characteristics Definition 90% 10% External output load 50% is 50pF 50% 90% 10% tr(IO)OUT tr(IO)OUT T If (tr+tf) is less than or equal to (2/3)T and the duty cycle is within (45~55%), it reaches the maximum frequency when the load is 50pf Table 46 Output Drive Voltage Characteristics (TA=25℃) Symbol Parameter Conditions Min Max VOL I/O pin outputs low voltage CMOS port, |IIO|=8mA, - 0.4 VOH I/O pin outputs high voltage 2.7 V < VDD < 3.6 V VDD-0.4 - VOL I/O pin outputs low voltage TTL port, |IIO|=20mA, - 0.4 VOH I/O pin outputs high voltage 2.7 V < VDD < 3.6 V 2.4 - VOL I/O pin outputs low voltage |IIO|=20mA, - 1.3 VOH I/O pin outputs high voltage 2.7 V < VDD < 3.6 V VDD-1.3 - VOL I/O pin outputs low voltage |IIO|=6mA, - 0.4 VOH I/O pin outputs high voltage 2.7 V < VDD < 3.6 V VDD-0.4 - Unit V V Note: The data are obtained from a comprehensive evaluation and are not tested in production. 5.10 NRST pin characteristics The NRST pin input drive adopts CMOS process, which is connected with a permanent pull-up resistor RPU. Table 47 NRST Pin Characteristics (TA=-40~105℃, VDD=2~3.6V) Symbol Parameter Conditions Min Typ Max VIL(NRST) NRST low-level input voltage TTL port, - - 0.8 VIH(NRST) NRST high-level input voltage 2.7V≤VDD≤3.6V 2 - - VIL(NRST) NRST low-level input voltage CMOS port, - - 0.3VDD w w w. g e e h y. c o m Unit V Page 84 Symbol Parameter Conditions Min Typ Max Unit VIH(NRST) NRST high-level input voltage 1.8V≤VDD≤3.6V 0.7VDD - - Vhys(NRST) NRST Schmidt trigger voltage hysteresis - - 200 - mV RPU Weak pull-up equivalent resistance VIN=VSS 30 40 50 kΩ VF(NRST) NRST input filter pulse - - - 100 VNF(NRST) NRST input unfiltered pulse VDD＞2.7V 300 - - TNRST_OUT Generated reset pulse duration Reset internal source 20 - - ns μs Communication peripherals 5.11 5.11.1 I2C peripheral characteristics To achieve maximum frequency of I2C in standard mode, fPCLK1 must be greater than 2MHz. To achieve maximum frequency of I2C in fast mode, fPCLK1 must be greater than 4MHz. Table 48 I2C Interface Characteristics (TA=25℃, VDD=3.3V) Standard I2C Symbol Fast I2C Parameter Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time 0 - 0 900 tr(SDA)/tr(SCL) SDA and SCL rise time - 1000 20+0.1Cb 300 tf(SDA)/tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.6 - tsu(STA) Setup time of repeated start condition 4.7 - 0.6 - tsu(STO) Setup time of stop condition 4.0 - 0.6 - 4.7 - 1.3 - - 400 - 400 μs ns tw(STO:STA) Cb Time from stop condition to start condition (the bus is idle) Capacitive load of each bus μs pF Note: The data are obtained from a comprehensive evaluation and are not tested in production. w w w. g e e h y. c o m Page 85 Figure 13 Bus AC Waveform and Measurement Circuit VDD 4.7KΩ VDD 4.7KΩ SDA I2C bus MCU SCL Repeated start condition tsu(STA) Start condition Start condition SDA tf(STA) th(STA) tr(SDA) tsu(SDA) tw(SCLH) tsu(STO:STA) Stop condition th(SDA) SCL tw(SCLL) tf(SCL) tf(SCL) tsu(STO) Note: The measuring points are set at CMOS levels: 0.3VDD and 0.7VDD. 5.11.2 SPI peripheral characteristics Table 49 SPI Characteristics (TA=25℃, VDD=3.3V) Symbol Parameter Conditions Min Max Master mode - 18 Slave mode - 18 SI clock rise and fall time Load capacitance: C=15pF - 6 tsu(NSS) NSS setup time Slave mode 4TPCLK - th(NSS) NSS hold time Slave mode 2TPCLK + 10 - TPCLK/2-2 TPCLK/2+1 Master mode 4 - Slave mode 5 - Master mode 4 - Slave mode 5 - fSCK SPI clock frequency 1/tc(SCK) tr(SCK) tf(SCK) tw(SCKH) tw(SCKL) SCK high and low time tsu(MI) MHz Master mode, fPCLK=36MHz, Prescaler factor=4 Data input setup time tsu(SI) th(MI) Unit ns Data input hold time th(SI) ta(SO) Data output access time Slave mode, fPCLK=20MHz 0 3TPCLK tdis(SO) Disable time of data output Slave mode 0 18 tv(SO) Effective time of data output - 22.5 w w w. g e e h y. c o m Slave mode (after enabling the edge) Page 86 Symbol Parameter Conditions tv(MO) Effective time of data output Max - 6.97 11.5 - 1 - 25 75 Master mode (after enabling the edge) Slave mode (after enabling th(SO) the edge) Data output hold time Min Master mode (after enabling th(MO) the edge) SPI clock frequency duty DuCy(SCK) Slave mode cycle Unit ％ Note: The data are obtained from a comprehensive evaluation and are not tested in production. Figure 14 SPI Timing Diagram - Slave Mode and CPHA=0 NSS input tSU(NSS) CPHA=0 CPOL=0 CPHA=0 CPOL=1 tc(SCK) th(NSS) th(SCKH) tW(SCKL) SCK input ta(SO) MISO output tV(SO) tr(SCK) tf(SCK) th(SO) Output the most significant bit tdls(SO) Output the least significant bit Output Bits 6~1 tSU(SI) Input the most significant bit Input Bits 6~1 Input the least significant bit MOSI input Figure 15 SPI Timing Diagram - Slave Mode and CPHA=1 NSS input tc(SCK) tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 SCK input MISO output th(NSS) tW(SCKH) tW(SCKL) tr(SCK) tf(SCK) tV(SO) ta(SO) Output the most significant bit tSU(SI) tdis(SO) th(SO) Output Bits 6~1 Output the least significant bit th(SI) Input the most significant bit Input Bits 6~1 Input the least significant bit MOSI input Note: The measuring points are set at CMOS levels: 0.3VDD and 0.7VDD. w w w. g e e h y. c o m Page 87 Figure 16 SPI Timing Diagram - Master Mode High level tc(SCK) NSS input CPHA=0 CPOL=0 CPHA=0 CPOL=1 SCK input CPHA=1 CPOL=0 CPHA=1 CPOL=1 SCK input tW(SCKH) tW(SCKL) tSU(MI) MISO input MOSI output Input the most significant bit th(MI) Output the most significant bit Input Bits 6~1 Output the least significant bit Output Bits 6~1 tv(MO) tr(SCK) tf(SCK) Input the least significant bit th(MO) Note: The measuring points are set at CMOS levels: 0.3VDD and 0.7VDD. 5.12 Analog peripherals 5.12.1 ADC Test parameter description:  Sampling rate: the number of conversion of analog quantity to digital quantity by ADC per second  Sample rate=ADC clock/(number of sampling periods + number of conversion periods) 5.12.1.1 12-bit ADC characteristics Table 50 12-bit ADC Characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply voltage - 1.8 - 3.6 V IDDA ADC power consumption - - 1.6 1.8 mA VDDA=1.8~2.4V 0.6 15 18 fADC ADC frequency MHz VDDA=2.4~3.6V 0.6 30 36 CADC Internal sampling and holding capacitance - - 4 - pF RADC Sampling resistor - - - 6000 Ω tS Sampling time fADC=30MHz 0.1 16 μs w w w. g e e h y. c o m Page 88 Symbol Parameter Conditions Min - 3 fADC=30MHz 12-bit resolution fADC=30MHz TCONV Sampling and conversion time 10-bit resolution fADC=30MHz 8-bit resolution fADC=30MHz 6-bit resolution Typ Max Unit 480 1/fADC 0.50 - 16.40 μs 0.43 - 16.34 μs 0.37 - 16.27 μs 0.30 - 16.20 μs Table 51 12-bit ADC Accuracy Symbol Parameter ET Composite error Conditions fPCLK=56MHz, Typ Max ±2 ±5 ±1.5 ±2.5 EO Offset error EG Gain error fADC=14MHz, ±1.5 ±3 ED Differential linear error VDDA=2.4V-3.6V ±1 ±2 EL Integral linear error ±1.5 ±3 TA=-40℃~105℃ Unit LSB Note: The data are obtained from a comprehensive evaluation and are not tested in production. 5.12.1.2 Test of Built-in Reference Voltage Characteristics Table 52 Built-in Reference Voltage Characteristics Symbol Parameter Conditions Min Typ Max Unit VREFINT Built-in Reference Voltage -40℃ < TA < +105℃ 1.19 1.20 1.20 V - 10 - - μs VDD=3V - 3 5 mV - - 30 50 ppm/℃ TS_vrefint Sampling time of ADC when reading out VRERINT internal reference voltage Built-in reference voltage extends to Tcoeff temperature range Temperature coefficient Note: The data are obtained from a comprehensive evaluation and are not tested in production. 5.12.2 DAC Test parameter description:  DNL differential non-linear error: the deviation between two consecutive codes is 1LSB  INL integral non-linear error: the difference between the measured value at code i and the value at code i on the connection between code 0 and the last code 4095 w w w. g e e h y. c o m Page 89 Table 53 DAC Characteristics Symbol VDDA Parameter Analog power supply voltage RLOAD Resistive load RO Output impedance CLOAD Capacitive load Conditions Min Typ Max Unit - 1.8 - 3.6 V The buffer is turned on 5 - - kΩ - - 15 kΩ - - 50 pF 0.2 - - V - - VDDA-0.2 V - 0.5 - mV - - Configured with 12-bit DAC - - ±2 LSB Configured with 12-bit DAC - - ±4 LSB The resistive load between DAC_OUT and VSS is 1.5MΩ with buffer off Maximum capacitive load at DAC_OUT pin with buffer on DAC_OUT Low DAC_OUT Maximum output offset of DAC, min voltage with buffer (0x0E0) corresponding to 12-bit input DAC_OUT Higher DAC_OUT code to VREF+= (0xF1C) at 3.6V and max voltage with buffer VREF+= (0x1C7) at 1.8V and (0xE38) DAC_OUT min DAC_OUT max DNL INL Low DAC_OUT voltage without buffer Higher DAC_OUT Maximum output offset of DAC voltage without buffer Differential nonlinear error Integral non-linear error VREF+1LSB V Offset Offset error VREF+=3.6V, configuring 12-bit DAC - - ±12 LSB Gain error Gain error Configured with 12-bit DAC - - ±0.5 % Note: The data are obtained from a comprehensive evaluation and are not tested in production. w w w. g e e h y. c o m Page 90 6 Package Information 6.1 LQFP176 package information Figure 17 LQFP176 Package Diagram w w w. g e e h y. c o m Page 91 (1) The figure is not drawn to scale. (2) All pins should be soldered to the PCB. S/N SYM DIMENSIONS REMARKS 1 A MAX. 1.600 OVERALL HEIGHT 2 A2 1.400±0.050 PKG THICKNESS 3 D 26.000±0.200 LEAD TIP TO TIP 4 D1 24.000±0.100 PKG LENGTH 5 E 26.000±0.200 LEAD TIP TO TIP 6 E1 24.000±0.100 PKG WDTH 7 L 0.600±0.150 FOOT LENGTH 8 L1 1.000 REF LEAD LENGTH 9 e 0.500 BASE LEAD PITCH 10 H（REF） （21.50） CUM LEAD PITCH 11 b 0.22±0.050 LEAD WIDTH Table 54 LQFP176 Package Data Note: Dimensions are marked in millimeters. Figure 18 LQFP176 -176 Pins, 24 x24mm Welding Layout Recommendations 1.2 1 176 0.5 133 132 21.8 26.7 0.3 44 45 89 88 1.2 21.8 26.7 w w w. g e e h y. c o m Page 92 Figure 19 LQFP176 -176 Pins, 24 x24mm Schematic Diagram Company Logo Product series Specific model APM32 F407IET6 XX XXXX Version number Year and week number Arm authorization logo PIN1 6.2 LQFP144 package information Figure 20 LQFP144 Package Diagram w w w. g e e h y. c o m Page 93 (1) The figure is not drawn to scale. (2) All pins should be soldered to the PCB. Table 55 LQFP144 Package Data S/N SYM DIMENSIONS REMARKS 1 A MAX. 1.600 OVERALL HEIGHT 2 A2 1.400±0.050 PKG THICKNESS 3 D 22.000±0.200 LEAD TIP TO TIP 4 D1 20.000±0.100 PKG LENGTH 5 E 22.000±0.200 LEAD TIP TO TIP 6 E1 20.000±0.100 PKG WDTH 7 L 0.600±0.150 FOOT LENGTH 8 L1 1.000 REF LEAD LENGTH 9 e 0.500 BASE LEAD PITCH 10 H（REF） （17.50） CUM LEAD PITCH 11 b 0.22±0.050 LEAD WIDTH Note: Dimensions are marked in millimeters. w w w. g e e h y. c o m Page 94 Figure 21 LQFP144-144 Pins, 20 x 20mm Welding Layout Recommendations Note: Dimensions are marked in millimeters. Figure 22 LQFP144 -144 Pins, 20 x20mm Schematic Diagram Company Logo Product series Specific model APM32 F407ZET6 XX XXXX Version number Year and week number Arm authorization logo PIN1 w w w. g e e h y. c o m Page 95 6.3 LQFP100 package information Figure 23 LQFP100 Package Diagram （1） The figure is not drawn to scale. （2） All pins should be soldered to the PCB. Table 56 LQFP100 Package Data w w w. g e e h y. c o m Page 96 DIMENSION LIST（FOOTPRINT: 2.00） S/N SYM DIMENSIONS REMARKS 1 A MAX. 1.600 OVERALL HEIGHT 2 A2 1.400±0.050 PKG THICKNESS 3 D 16.000±0.200 LEAD TIP TO TIP 4 D1 14.000±0.100 PKG LENGTH 5 E 16.000±0.200 LEAD TIP TO TIP 6 E1 14.000±0.100 PKG WDTH 7 L 0.600±0.150 FOOT LENGTH 8 L1 1.000 REF LEAD LENGTH 9 e 0.500 BASE LEAD PITCH 10 H（REF） （12.00） CUM LEAD PITCH 11 b 0.22±0.050 LEAD WIDTH Note: Dimensions are marked in millimeters. Figure 24 LQFP100 - 100 Pins, 14 x 14mm Welding Layout Recommendations Note: Dimensions are marked in millimeters. w w w. g e e h y. c o m Page 97 Figure 25 LQFP100 - 100 Pins, 14 x 14mm Package Schematic Diagram Company Logo Product series Specific model APM32 F407VET6 XX XXXX Version number Year and week number Arm authorization logo PIN1 w w w. g e e h y. c o m Page 98 6.4 LQFP64 package information Figure 26 LQFP64 Package Diagram （1） The figure is not drawn to scale. （2） All pins should be soldered to the PCB. w w w. g e e h y. c o m Page 99 Table 57 LQFP64 Package Data S/N SYM DIMENSIONS REMARKS 1 A MAX.1.600 OVERALLHEIGHT 2 A2 1.400±0.050 PKGTHICKNESS 3 D 12.000±0.200 LEADTIPTOTIP 4 D1 10.000±0.100 PKGLENGTH 5 E 12.000±0.200 LEADTIPTOTIP 6 E1 10.000±0.100 PKGWIDTH 7 L 0.600±0.150 FOOTLENGTH 8 L1 1.000REF. LEADLENGTH 9 e 0.500BASE LEADPITCH 10 H(REF.) (7.500) GUM.LEADPITCH 11 b 0.220±0.050 LEADWIDTH Note: Dimensions are marked in millimeters. Figure 27 LQFP64 Welding Layout Recommendations 48 33 49 0.30 32 0.5 10.3 12.7 10.3 17 64 1 16 1.2 7.8 12.7 Note: Dimensions are marked in millimeters. w w w. g e e h y. c o m Page 100 Figure 28 LQFP64 - 64 Pins, 10 x 10mm Package Schematic Diagram Company Logo Product series Specific model APM32 F407RET6 XX XXXX Version number Year and week number Arm authorization logo PIN1 w w w. g e e h y. c o m Page 101 7 Packaging Information 7.1 Reel packaging Figure 29 Specification Drawing of Reel Packaging A0 Dimension designed to accommodate the component width B0 Dimension designed to accommodate the component length K0 Dimension designed to accommodate the component thickness W Overall width of the carrier tape Quadrant Assignments for PIN1 Orientation in Tape Reel Dimensions w w w. g e e h y. c o m Page 102 All photos are for reference only, and the appearance is subject to the product. Table 58 Reel Packaging Parameter Specification Table Device Package Type Reel Pins SPQ Diameter （mm） A0 B0 K0 W Pin1 （mm） （mm） （mm） （mm） Quadrant APM32F407RET6 LQFP 64 1000 330 12.35 12.35 2.2 24 Q1 APM32F407RGT6 LQFP 64 1000 330 12.35 12.35 2.2 24 Q1 APM32F405RGT6 LQFP 64 1000 330 12.35 12.35 2.2 24 Q1 7.2 Tray packaging Figure 30 Tray Packaging Diagram Tray Dimensions w w w. g e e h y. c o m Page 103 All photos are for reference only, and the appearance is subject to the product Table 59 Tray Packaging Parameter Specification Table Device Package Type Pins SPQ X-Dimension Y-Dimension X-Pitch Y-Pitch （mm） （mm） （mm） （mm） Tray Tray Length Width （mm） （mm） APM32F407IET6 LQFP 176 400 27 27 30.4 31.5 322.6 135.9 APM32F407IGT6 LQFP 176 400 27 27 30.4 31.5 322.6 135.9 APM32F407ZET6 LQFP 144 600 22.06 22.06 25.4 25.2 322.6 135.9 APM32F407ZGT6 LQFP 144 600 22.06 22.06 25.4 25.2 322.6 135.9 APM32F407VET6 LQFP 100 900 16.6 16.6 20.3 21 322.6 135.9 APM32F407VGT6 LQFP 100 900 16.6 16.6 20.3 21 322.6 135.9 APM32F407RET6 LQFP 64 1600 12.3 12.3 15.2 15.7 322.6 135.9 APM32F407RGT6 LQFP 64 1600 12.3 12.3 15.2 15.7 322.6 135.9 APM32F405ZGT6 LQFP 144 600 22.06 22.06 25.4 25.2 322.6 135.9 APM32F405VGT6 LQFP 100 900 16.6 16.6 20.3 21 322.6 135.9 APM32F405RGT6 LQFP 64 1600 12.3 12.3 15.2 15.7 322.6 135.9 w w w. g e e h y. c o m Page 104 8 Ordering Information Figure 31 APM32F405xG 407xExG Series Ordering Information Diagram APM32 F 407 Z G T 6 XXX Product series APM32=Arm-based 32-bit MCU Option XX=Programmed device code R=Reel package Blank=Tray package Product type F=Foundation Temperature range 6=Industrial-grade temperature range, -40 -85 Product subseries 405/407=High-performance and DSP with FPU Package T=LQFP Number of pins R=64 pins V=100pins Z=144pins I=176pins Flash memory capacity E =512 KB G =1 MB Table 60 Ordering Information Table Order code FLASH（KB） SRAM（KB） Package SPQ Range of temperature APM32F407IGT6 1024 192+4 LQFP176 400 Industrial grade -40℃~85℃ APM32F407IET6 512 192+4 LQFP176 400 Industrial grade -40℃~85℃ APM32F407ZGT6 1024 192+4 LQFP144 600 Industrial grade -40℃~85℃ APM32F407ZET6 512 192+4 LQFP144 600 Industrial grade -40℃~85℃ APM32F407VGT6 1024 192+4 LQFP100 900 Industrial grade -40℃~85℃ APM32F407VET6 512 192+4 LQFP100 900 Industrial grade -40℃~85℃ APM32F407RGT6 1024 192+4 LQFP64 1600 Industrial grade -40℃~85℃ APM32F407RET6 512 192+4 LQFP64 1600 Industrial grade -40℃~85℃ APM32F407RGT6-R 1024 192+4 LQFP64 1000 Industrial grade -40℃~85℃ APM32F407RET6-R 512 192+4 LQFP64 1000 Industrial grade -40℃~85℃ APM32F405ZGT6 1024 192+4 LQFP144 600 Industrial grade -40℃~85℃ APM32F405VGT6 1024 192+4 LQFP100 900 Industrial grade -40℃~85℃ APM32F407RGT6 1024 192+4 LQFP64 1600 Industrial grade -40℃~85℃ APM32F405RGT6-R 1024 192+4 LQFP64 1000 Industrial grade -40℃~85℃ w w w. g e e h y. c o m Page 105 9 Commonly Used Function Module Denomination Table 61 Commonly Used Function Module Denomination Chinese description Abbreviations Reset management unit RMU Clock management unit CMU Reset and clock management RCM External interrupt EINT General-purpose IO GPIO Multiplexing IO AFIO Wake-up controller WUPT Buzzer BUZZER Independent watchdog timer IWDT Window watchdog timer WWDT Timer TMR CRC controller CRC Power Management Unit PMU DMA controller DMA Analog-to-digital converter ADC Real-time clock RTC External memory controller EMMC Controller local area network CAN I2C Interface I2C Serial peripheral interface SPI Universal asynchronous transmitter receiver UART Universal synchronous and asynchronous transmitter receiver USART Flash interface control unit FMC w w w. g e e h y. c o m Page 106 10 Version History Table 62 Document Version History Date Version Change History 2021.10 1.0 New creation 2022.4.1 1.1 (1) Modify pin definitions (2) The APM32F405xG model is added (1) Add 3.3 GPIO Multiplexing Function Configuration 2022.7.12 1.2 (2) Modify the Arm trademark (3) Add the statement (4) Add DMC pin description w w w. g e e h y. c o m Page 107 Statement This document is formulated and published by Geehy Semiconductor Co., Ltd. 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