Datasheet
APM32F107xBxC
APM32F105x8xBxC
Arm® Cortex®-M3 based 32-bit MCU
Version: V0.4(The current manual is draft and official
version will be released in April)
1. Product characteristics
Core
–
–
32-bit Arm Cortex -M3 core
Up to 96MHz working frequency
On-chip memory
–
Flash：up to 256KB
–
SRAM：up to 64KB
Clock
–
HSECLK:
3~25MHz
external
crystal/ceramic oscillator supported
LSECLK: 32.768KHz crystal/ceramic
oscillator supported
–
–
–
®
–
3 USART, 2 UART, support ISO7816,
LIN and IrDA functions
–
3 SPI (2 reusable I2S), maximum
transmission speed 18Mbps
–
–
–
2 CAN
1 USB OTG_FS Controller
Ethernet MAC
Analog peripherals
–
2 12-bit ADCs
–
2 12-bit DACs
Timer
–
1 16-bit advanced timers TMR1 that
can provide 7 channels PWM output,
support dead zone generation and
braking input functions
–
4 16-bit general-purpose timers
TMR2/3/4/5, each with up to 4
independent channels to support
input capture, output comparison,
PWM, pulse count and other
functions
–
–
2 16-bit basic timers TMR6/7
2 watchdog timers: one independent
watchdog IWDT and one window
watchdog WWDT
1 24-bit autodecrement SysTick
Timer
®
HSICLK:
8MHz
RC
calibrated by factory
LSICLK: 40KHz RC
supported
oscillator
oscillator
–
PLL: 3 configurable phase-locked
loops are provided
Reset and power
management
–
VDD range: 2.0～3.6V
–
VDDA range: 2.0～3.6V
–
VBAT range of backup domain power
supply: 1.8V～3.6V
–
Power-on/power-down
(POR/PDR) supported
–
Programmable power supply voltage
detector supported(PVD)
RTC
Low-power mode
–
Support calendar functions
–
Sleep, stop and standby modes
supported
DMA
84Bytes backup register
CRC computing unit
96-bit unique device ID
–
Two DMA; DMA1 supports 7
channels and DMA2 supports 5
channels
Debugging interface
–
–
JTAG
SWD
I/O
–
–
–
Up to 80 I/Os
All I/Os can be mapped to external
interrup vector
Up to 60 FT input I/Os
Communication peripherals
–
2 I2C interfaces (1Mbit/s), all of which
support SMBus/PMBus
www.geehy.com
reset
–
Page 1
Contents
1.
Product characteristics.............................................................................................. 1
2.
Product information ................................................................................................... 5
3.
Pin information ........................................................................................................... 6
3.1.
Pin distribution ................................................................................................................................... 6
3.2.
Pin function description ..................................................................................................................... 7
4.
Functional description ............................................................................................. 15
4.1.
System architecture ......................................................................................................................... 16
4.1.1. System block diagram ............................................................................................................................. 16
4.1.2. Address mapping ..................................................................................................................................... 17
4.1.3. Startup configuration ............................................................................................................................... 19
4.2.
Core ................................................................................................................................................. 19
4.3.
Interrupt controller............................................................................................................................ 19
4.3.1. Nested Vector Interrupt Controller (NVIC) ............................................................................................... 19
4.3.2. External Interrupt/Event Controller (EINT) .............................................................................................. 19
4.4.
On-chip memory .............................................................................................................................. 20
4.5.
Clock ................................................................................................................................................ 20
4.5.1. Clock tree................................................................................................................................................. 20
4.5.2. Clock source ............................................................................................................................................ 21
4.5.3. System clock ........................................................................................................................................... 22
4.5.4. Bus clock ................................................................................................................................................. 22
4.6.
Power supply and power management ........................................................................................... 22
4.6.1. Power supply scheme ............................................................................................................................. 22
4.6.2. Voltage regulator ..................................................................................................................................... 22
4.6.3. Power supply voltage monitor ................................................................................................................. 22
4.7.
Low-power mode ............................................................................................................................. 23
4.8.
DMA ................................................................................................................................................. 23
4.9.
GPIO ................................................................................................................................................ 23
4.10. Communication peripherals ............................................................................................................. 23
4.10.1. USART/UART .......................................................................................................................................... 23
4.10.2. I2C ........................................................................................................................................................... 24
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Page 2
4.10.3. SPI/I2S..................................................................................................................................................... 24
4.10.4. CAN ......................................................................................................................................................... 24
4.10.5. USB OTG_FS .......................................................................................................................................... 24
4.10.6. Ethernet ................................................................................................................................................... 24
4.11. Analog peripherals ........................................................................................................................... 25
4.11.1. ADC ......................................................................................................................................................... 25
4.11.2. DAC ......................................................................................................................................................... 25
4.12. Timer ................................................................................................................................................ 25
4.13. RTC .................................................................................................................................................. 26
4.13.1. Backup register ........................................................................................................................................ 27
4.14. CRC ................................................................................................................................................. 27
5.
Electrical characteristics ......................................................................................... 28
5.1.
Test conditions of electrical characteristics ..................................................................................... 28
5.1.1. Maximum and minimum values ............................................................................................................... 28
5.1.2. Typical value ............................................................................................................................................ 28
5.1.3. Typical curve ............................................................................................................................................ 28
5.1.4. Power supply scheme ............................................................................................................................. 29
5.1.5. Load capacitance .................................................................................................................................... 29
5.2.
Test under general operating conditions ......................................................................................... 30
5.3.
Absolute maximum ratings .............................................................................................................. 30
5.3.1. Maximum temperature characteristics .................................................................................................... 31
5.3.2. Maximum rated voltage characteristics ................................................................................................... 31
5.3.3. Maximum rated current features ............................................................................................................. 31
5.3.4. Electrostatic discharge (ESD).................................................................................................................. 32
5.3.5. Static latch-up (LU) .................................................................................................................................. 32
5.4.
On-chip memory .............................................................................................................................. 32
5.4.1. Flash characteristics ................................................................................................................................ 32
5.5.
Clock ................................................................................................................................................ 33
5.5.1. Characteristics of external clock source .................................................................................................. 33
5.5.2. Characteristics of internal clock source ................................................................................................... 33
5.5.3. PLL Characteristics.................................................................................................................................. 34
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Page 3
5.6.
Reset and power management ....................................................................................................... 35
5.6.1. Test of embedded reset and power control block characteristics............................................................ 35
5.7.
Power consumption ......................................................................................................................... 36
5.7.1. Power consumption test environment ..................................................................................................... 36
5.7.2. Power consumption in run mode ............................................................................................................. 37
5.7.3. Power consumption in sleep mode ......................................................................................................... 38
5.7.4. Power consumption in stop mode and standby mode ............................................................................ 39
5.7.5. Backup domain power consumption ....................................................................................................... 39
5.7.6. Peripheral power consumption ................................................................................................................ 39
5.8.
Wake-up time in low power mode ................................................................................................... 41
5.9.
Pin characteristics............................................................................................................................ 41
5.9.1. I/O pin characteristics .............................................................................................................................. 41
5.9.2. NRST pin characteristics ......................................................................................................................... 43
5.10. Communication peripherals ............................................................................................................. 43
5.10.1. I2C peripheral characteristics .................................................................................................................. 43
5.10.2. SPI peripheral characteristics .................................................................................................................. 45
5.11. Analog peripherals ........................................................................................................................... 46
5.11.1. ADC ......................................................................................................................................................... 46
5.11.2. DAC ......................................................................................................................................................... 48
6.
Package information ................................................................................................ 49
6.1.
LQFP100 package diagram............................................................................................................. 49
6.2.
LQFP64 package diagram............................................................................................................... 52
7.
Packaging information ............................................................................................. 54
7.1.
Reel packaging ................................................................................................................................ 54
7.2.
Tray packaging ................................................................................................................................ 55
8.
Ordering information................................................................................................ 57
9.
Commonly used function module denomination .................................................. 58
10.
Version history ......................................................................................................... 59
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Page 4
2. Product information
See the following table for APM32F107 105xx product functions and peripheral configuration.
Table 1 Functions and Peripherals of APM32F107 105xx Series Chips
Product
APM32F105
Model
R8T6
Package
RBT6
RCT6
V8T6
LQFP64
VBT6
Operating voltage
32-bit
128
256
64
51
128
LQFP64
256
80
VCT6
LQFP100
128
256
128
51
USART/UART
3/2
SPI/I2S
3/2
I2C
interface
USB OTG_FS
Ethernet
2
256
1
0
1
2
16-bit advanced
1
16-bit general
4
16-bit basic
2
System tick timer
1
Watchdog
2
1
Unit
2
External channel
16
Internal channel
2
Unit
2
Channel
2
Operating temperature
80
1
CAN
Real-time clock
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VBT6
64
Communication
12-bit DAC
RCT6
2.0~3.6V
64
GPIOs
12-bit ADC
RBT6
Cortex®-M3@96MHz
SRAM(KB)
Timer
VCT6
LQFP100
Arm®
Core and maximum working frequency
Flash(KB)
APM32F107
Ambient temperature:-40°C 至 85°C
Junction temperature:-40°C 至 105°C
Page 5
3. Pin information
3.1. Pin distribution
LQFP100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDD_2
VSS_2
NC
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
PE2
PE3
PE4
PE5
PE6
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
VDD_5
OSC_IN
OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREFVREF+
VDDA
PA0-WKUP
PA1
PA2
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VDD_3
VSS_3
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 1 Distribution Diagram of APM32F107 105xx Series LQFP100 Pins
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Page 6
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA15
PA14
Figure 2 Distribution Diagram of APM32F107 105xx Series LQFP64 Pins
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LQFP64
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0-OSC_IN
PD1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA0-WKUP
PA1
PA2
3.2. Pin function description
Table 2 Legends/Abbreviations Used in Output Pin Table
Name
Pin name
Pin type
Abbreviation
Definition
Unless otherwise specified in parentheses below the pin name, the pin functions during
and after reset are the same as the actual pin name
P
Power pin
I
Only input pin
I/O
I/O pin
5T
FT I/O
5Tf
FT I/O, FM+ function
STDA
I/O with 3.3 V standard, directly connected to ADC
STD
I/O with 3.3 V standard
B
Dedicated Boot0 pin
RST
Bidirectional reset pin with built-in pull-up resistor
I/O structure
Note
w w w. g e e h y. c o m
Unless otherwise specified in the notes, all I/O is set as floating input during and after reset
Page 7
Name
Abbreviation
Definition
Default
Pin
function
multiplexing
Function directly selected/enabled through peripheral register
function
Remap
Select this function through AFIO remapping register
Table3 Description of APM32F107 105xx by Pin Function
Name
(Function after
Type
Structure
PE2
I/O
5T
PE3
I/O
PE4
Default multiplexing
Remap
LQFP64
LQFP100
TRACECK
-
-
1
5T
TRACED0
-
-
2
I/O
5T
TRACED1
-
-
3
PE5
I/O
5T
TRACED2
-
-
4
PE6
I/O
5T
TRACED3
-
-
5
VBAT
P
-
-
-
1
6
I/O
STD
TAMPER_RTC
-
2
7
I/O
STD
OSC32_IN
-
3
8
I/O
STD
OSC32_OUT
-
4
9
VSS_5
P
-
-
-
-
10
VDD_5
P
-
-
-
-
11
OSC_IN
I
STD
-
-
5
12
OSC_OUT
O
STD
-
-
6
13
NRST
I/O
RST
-
-
7
14
PC0
I/O
STDA
ADC12_IN10
-
8
15
-
9
16
-
10
17
-
11
18
-
12
19
reset)
function
PC13TAMPER-RTC
(PC13)
PC14OSC32_IN
(PC14)
PC15OSC32_OUT
(PC15)
ADC12_IN11,
PC1
I/O
STDA
ETH_MII_MDC,
ETH_RMII_MDC
PC2
I/O
STDA
PC3
I/O
STDA
VSSA
P
-
w w w. g e e h y. c o m
ADC12_IN12,
ETH_MII_TXD2
ADC12_IN13,
ETH_MII_TX_CLK
-
Page 8
Name
(Function after
Type
Structure
VREF-
P
-
VREF+
P
VDDA
P
Default multiplexing
Remap
LQFP64
LQFP100
-
-
-
20
-
-
-
-
21
-
-
-
13
22
-
14
23
-
15
24
-
16
25
-
17
26
reset)
function
WKUP,
USART2_CTS,
PA0-WKUP
(PA0)
I/O
STDA
ADC12_IN0,
TMR2_CH1_ETR,
TMR5_CH1,
ETH_MII_CRS_WKUP
USART2_RTS,
ADC12_IN1,
PA1
I/O
STDA
TMR5_CH2,
TMR2_CH2,
ETH_MII_RX_CLK,
ETH_RMII_REF_CLK
USART2_TX,
TMR5_CH3,
PA2
I/O
STDA
ADC12_IN2,
TMR2_CH3,
ETH_MII_MDIO,
ETH_RMII_MDIO
USART2_RX,
TMR5_CH4,
PA3
I/O
STDA
ADC12_IN3,
TMR2_CH4,
ETH_MII_COL
VSS_4
P
-
-
-
18
27
VDD_4
P
-
-
-
19
28
20
29
-
21
30
TMR1_BKIN
22
31
TMR1_CH1N
23
32
SPI1_NSS,
PA4
I/O
STDA
USART2_CK,
SPI3_NSS,
DAC_OUT1,
I2S3_WS
ADC12_IN4
SPI1_SCK,
PA5
I/O
STDA
DAC_OUT2,
ADC12_IN5
SPI1_MISO,
PA6
I/O
STDA
ADC12_IN6
TMR3_CH1
PA7
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I/O
STDA
SPI1_MOSI,
Page 9
Name
(Function after
Type
Structure
reset)
Default multiplexing
function
Remap
LQFP64
LQFP100
-
24
33
-
25
34
TMR1_CH2N
26
35
TMR1_CH3N
27
36
ADC12_IN7,
TMR3_CH2,
ETH_MII_RX_DV,
ETH_RMII_CRS_DV
ADC12_IN14
PC4
I/O
STDA
ETH_MII_RXD0,
ETH_RMII_RXD0
ADC12_IN15,
PC5
I/O
STDA
ETH_MII_RXD1,
ETH_RMII_RXD1
ADC12_IN8,
PB0
I/O
STDA
TMR3_CH3,
ETH_MII_RXD2
ADC12_IN9,
PB1
I/O
STDA
TMR3_CH4,
ETH_MII_RXD3
PB2
I/O
5T
-
-
28
37
PE7
I/O
5T
-
TMR1_ETR
-
38
PE8
I/O
5T
-
TMR1_CH1N
-
39
PE9
I/O
5T
-
TMR1_CH1
-
40
PE10
I/O
5T
-
TMR1_CH2N
-
41
PE11
I/O
5T
-
TMR1_CH2
-
42
PE12
I/O
5T
-
TMR1_CH3N
-
43
PE13
I/O
5T
-
TMR1_CH3
-
44
PE14
I/O
5T
-
TMR1_CH4
-
45
PE15
I/O
5T
-
TMR1_BKIN
-
46
TMR2_CH3
29
47
TMR2_CH4
30
48
(PB2,BOOT1)
I2C2_SCL,
PB10
I/O
5T
USART3_TX,
ETH_MII_RX_ER
I2C2_SDA,
PB11
I/O
5T
USART3_RX,
ETH_MII_TX_EN,
ETH_RMII_TX_EN
VSS_1
P
-
-
-
31
49
VDD_1
P
-
-
-
32
50
PB12
I/O
5T
SPI2_NSS,
-
33
51
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P a ge 1 0
Name
(Function after
Type
Structure
reset)
Default multiplexing
function
Remap
LQFP64
LQFP100
-
34
52
-
35
53
-
36
54
-
55
-
56
-
57
-
58
-
59
I2S2_WS,
I2C2_SMBAI,
USART3_CK,
TMR1_BKIN,
CAN2_RX,
ETH_MII_TXD0,
ETH_RMII_TXD0
SPI2_SCK,
I2S2_CK,
USART3_CTS,
PB13
I/O
5T
TMR1_CH1N,
CAN2_TX,
ETH_MII_TXD1,
ETH_RMII_TXD1
SPI2_MISO,
PB14
I/O
5T
TMR1_CH2N,
USART3_RTS
SPI2_MOSI,
PB15
I/O
5T
I2S2_SD,
TMR1_CH3N
USART3_TX,
PD8
I/O
5T
-
ETH_MII_RX_DV,
ETH_RMII_CRS_DV
USART3_RX,
PD9
I/O
5T
-
ETH_MII_RXD0,
ETH_RMII_RXD0
USART3_CK,
PD10
I/O
5T
-
ETH_MII_RXD1,
ETH_RMII_RXD1
PD11
I/O
5T
-
USART3_CTS,
ETH_MII_RXD2
TMR4_CH1,
PD12
I/O
5T
-
USART3_RTS,
ETH_MII_RXD3
PD13
I/O
5T
-
TMR4_CH2
-
60
PD14
I/O
5T
-
TMR4_CH3
-
61
PD15
I/O
5T
-
TMR4_CH4
-
62
PC6
I/O
5T
I2S2_MCK
TMR3_CH1
37
63
PC7
I/O
5T
I2S3_MCK
TMR3_CH2
38
64
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P a ge 11
Name
(Function after
Type
Structure
PC8
I/O
5T
PC9
I/O
5T
reset)
Default multiplexing
Remap
LQFP64
LQFP100
-
TMR3_CH3
39
65
-
TMR3_CH4
40
66
-
41
67
-
42
68
-
43
69
-
44
70
-
45
71
function
USART1_CK,
PA8
I/O
5T
TMR1_CH1,
MCO,
OTG_FS_SOF
USART1_TX,
PA9
I/O
5T
TMR1_CH2,
OTG_FS_VBUS
USART1_RX,
PA10
I/O
5T
TMR1_CH3,
OTG_FS_ID
USART1_CTS,
PA11
I/O
5T
OTG_FS_DM,
CAN1_RX,
TMR1_CH4
USART1_RTS,
PA12
I/O
5T
OTG_FS_DP,
CAN1_TX,
TMR1_ETR
PA13
I/O
5T
-
PA13
46
72
NC
-
-
Not connected
-
-
73
VSS_2
P
-
-
-
47
74
VDD_2
P
-
-
-
48
75
I/O
5T
-
PA14
49
76
50
77
51
78
52
79
53
80
-
81
(JTMS,SWDIO)
PA14
(JTCK,SWCLK)
PA15
(JTDI)
TMR2_CH1_ETR,
I/O
5T
SPI3_NSS,I2S3_WS
PA15,
SPI1_NSS
USART3_TX,
PC10
I/O
5T
UART4_TX
SPI3_SCK,
I2S3_CK
PC11
I/O
5T
UART4_RX
USART3_RX,
SPI3_MISO
USART3_CK,
PC12
I/O
5T
UART5_TX
SPI3_MOSI,
I2S3_SD
PD0
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I/O
5T
-
CAN1_RX,
P a ge 1 2
Name
(Function after
Type
Structure
reset)
Default multiplexing
function
(OSC_IN)
PD1
Remap
LQFP64
LQFP100
-
82
-
54
83
OSC_IN
5T
PD2
I/O
5T
PD3
I/O
5T
-
USART2_CTS
-
84
PD4
I/O
5T
-
USART2_RTS
-
85
PD5
I/O
5T
-
USART2_TX
-
86
PD6
I/O
5T
-
USART2_RX
-
87
PD7
I/O
5T
-
USART2_CK
-
88
55
89
56
90
57
91
58
92
USART1_RX
59
93
-
-
60
94
TMR4_CH3,
I2C1_SCL,
ETH_MII_TXD3
CAN1_RX
61
95
62
96
(OSC_OUT)
-
CAN1_TX,
I/O
TMR3_ETR,
UART5_RX,
OSC_OUT
PB3,
PB3
(JTDO)
I/O
5T
SPI3_SCK,
TRACESWO,
I2S3_CK
TMR2_CH2,
SPI1_SCK
PB4
(NJTRST)
PB4,
I/O
5T
SPI3_MISO
TMR3_CH1,
SPI1_MISO
I2C1_SMBAI,
PB5
I/O
STD
SPI3_MOSI,
TMR3_CH2,
I2S3_SD,
SPI1_MOSI,
ETH_MII_PPS_OUT,
CAN2_RX
ETH_RMII_PPS_OUT
I2C1_SCL,
USART1_TX,
TMR4_CH1
CAN2_TX
PB6
I/O
5T
PB7
I/O
5T
BOOT0
I
B
PB8
I/O
5T
PB9
I/O
5T
TMR4_CH4
PE0
I/O
5T
TMR4_ETR
-
-
97
PE1
I/O
5T
-
-
-
98
VSS_3
P
-
-
-
63
99
VDD_3
P
-
-
-
64
100
I2C1_SDA,
TMR4_CH2
I2C1_SDA,
CAN1_TX
Note:
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P a ge 1 3
（1） Function availability depends on the chosen device. For devices having reduced
peripheral counts, it is always the lower number of peripheral that is included. For example,
if a device has only one SPI and two USARTs, they will be called SPI1 and USART1 &
USART2, respectively.
（2） PC13, PC14 and PC15 are supplied through the power switch since the switch only
sinks a limited amount of current (3mA). The use of GPIOs from PC13 to PC15 in output
mode is limited: only one GPIO can be used at a Time, the speed should not exceed 2
MHz with a maximum load of 30pF and these IOs must not be used as a current source
(e.g. to drive an LED).
（3） Main function after the first backup domain power-up. Later on, it depends on the
contents of the Backup registers even after reset (because these registers are not reset by
the main reset). For details on how to manage these IOs, refer to the Battery backup
domain and BAKPR register description sections in the reference manual.
（4） This alternate function can be remapped by software to some other port pins (if
available on the used package). For more details, refer to the Alternate Function I/O and
Debug Configuration section in the reference manual.
（5） SPI2/I2S2 and I2C2 are not available when the Ethernet is being used.
（6） Pin5 and pin6 in the LQFP64 package are configured as OSC_IN/OSC_OUT after
reset, however the functionality of PD0 and PD1 can be remapped by software on these
pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no
need for remapping. For more details, refer to the Alternate Function I/O and Debug
Configuration section in the reference manual. The use of PD0 and PD1 in output mode is
limited as they can only be used at 50 MHz in output mode.
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P a ge 1 4
4. Functional description
This chapter mainly introduces the system architecture, interrupt, on-chip memory, clock, power
supply and peripheral features of APM32F107 105xx series products; for information about the
Arm® Cortex®-M3 core, please refer to the Arm® Cortex®-M3 technical reference manual, which
can be downloaded from Arm’s website.
w w w. ge e h y. c o m
P a ge 1 5
4.1. System architecture
4.1.1. System block diagram
Figure 3APM32F107 105xx System Block Diagram
Arm® Cortex®-M3
I-Code
D-Code
Systen Bus
JTAG/SWD
FMC
DMA
Ethernet MAC
Bus Matrix
FLASH
DMA1/2
AHB BUS
USB
OTG
AHB/APB1 BRIDGE
SRAM
CRC
AHB/APB2 BRIDGE
TMR2/3/4/5/6/7
AFIO
RTC
EINT
WWDT
GPIO A/B/C/D/E
IWDT
ADC1/2
SPI2(I2S2)
TMR1
SPI3(I2S3)
SPI1
USART2/3
USART1
UART4/5
I2C1/2
CAN1/2
BAKPR
PMU
DAC1/2
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P a ge 1 6
4.1.2. Address mapping
Table 4 APM32F107 105xx Series Address Mapping Diagram
Region
Start Address
Peripheral Name
0x0000 0000
Code Mapping Area
0x0004 0000
Reserved
0x0800 0000
Flash Main Storage Area
0x0804 0000
Reserved
0x1FFF B000
System Memory Area
0x1FFF F800
Option Byte
SRAM
0x2000 0000
SRAM
—
0x2001 0000
Reserved
0x4000 0000
TMR2
0x4000 0400
TMR3
0x4000 0800
TMR4
0x4000 0C00
TMR5
0x4000 1000
TMR6
0x4000 1400
TMR7
0x4000 1800
Reserved
0x4000 2800
RTC
0x4000 2C00
WWDT
0x4000 3000
IWDT
0x4000 3400
Reserved
0x4000 3800
SPI2/I2S2
0x4000 3C00
SPI3/I2S3
0x4000 4000
Reserved
0x4000 4400
USART2
0x4000 4800
USART3
0x4000 4C00
UART4
0x4000 5000
UART5
Code Area
APB1 Bus
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P a ge 1 7
Region
APB2 Bus
AHB Bus
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Start Address
Peripheral Name
0x4000 5400
I2C1
0x4000 5800
I2C2
0x4000 5C00
Reserved
0x4000 6400
CAN1
0x4000 6800
CAN2
0x4000 6C00
BAKPR
0x4000 7000
PMU
0x4000 7400
DAC
0x4000 7800
Reserved
0x4001 0000
AFIO
0x4001 0400
EINT
0x4001 0800
GPIOA
0x4001 0C00
GPIOB
0x4001 1000
GPIOC
0x4001 1400
GPIOD
0x4001 1800
GPIOE
0x4001 1C00
Reserved
0x4001 2400
ADC1
0x4001 2800
ADC2
0x4001 2C00
TMR1
0x4001 3000
SPI1
0x4001 3400
Reserved
0x4001 3800
USART1
0x4001 3C00
Reserved
0x4002 0000
DMA1
0x4002 0400
DMA2
0x4002 0800
Reserved
P a ge 1 8
Region
Start Address
Peripheral Name
0x4002 1000
RCM
0x4002 1400
Reserved
0x4002 2000
Flash Interface
0x4002 2400
Reserved
0x4002 3000
CRC
0x4002 3400
Reserved
0x4002 8000
Ethernet
0x4003 0000
Reserved
0x5000 0000
USB OTG_FS
0x5000 0400
Reserved
—
4.1.3. Startup configuration
At startup, the user can select one of the following three startup modes by setting the high and
low levels of the Boot pin:
Startup from main memory
Startup from BootLoader
Startup from built-in SRAM
The user can use USART interface to reprogram the user Flash if boot from BootLoader.
4.2. Core
The core of APM32F107 105xx is Arm® Cortex®-M3. Based on this platform, the development
cost is low and the power consumption is low. It can provide excellent computing performance
and advanced system interrupt response, and is compatible with all Arm tools and software.
4.3. Interrupt controller
4.3.1. Nested Vector Interrupt Controller (NVIC)
It embeds a nested vectored interrupt controller (NVIC) that can handle up to 68 maskable
interrupt channels (not including 16 interrupt lines of Cortex®-M3) and 16 priority levels. The
interrupt vector entry address can be directly transmitted to the core, so that the interrupt
response processing with low delay can give priority to the late higher priority interrupt.
4.3.2. External Interrupt/Event Controller (EINT)
The external interrupt/event controller consists of 20 edge detectors, and each detector
includes edge detection circuit and interrupt/event request generation circuit; each detector can
be configured as rising edge trigger, falling edge trigger or both and can be masked
independently. Up to 80 GPIOs can be connected to the 16 external interrupt lines.
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P a ge 1 9
4.4. On-chip memory
On-chip memory includes main memory area, SRAM and information block; the information
block includes system memory area and option byte; the system memory area stores
BootLoader, 96-bit unique device ID and capacity information of main memory area; the system
memory area has been written into the program and cannot be erased.
Table5 On-chip Memory Area
Memory
Maximum
capacity
Function
Main memory
area
256 KB
Store user programs and data.
SRAM
64 KB
System memory
area
18KB
Option byte
16Bytes
CPU can access at 0 waiting cycle (read/write).
Store BootLoader, 96-bit unique device ID, and main memory area
capacity information
Configure main memory area read-write protection and MCU working
mode
4.5. Clock
4.5.1.
Clock tree
Clock tree of APM32F107 105xx is shown in the figure below:
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P a ge 2 0
Figure 4 APM32F107 105xx Clock Tree
ETH_MII_TX_CLK
MACTXCLK
ETH PHY
AFIO_REMAP
[MACEISEL]
/2,20
ETH_MII_RX_CLK
MACRXCLK
DPLL1CLK
(PLL1CLK*2)
MACRMIICLK
OTGFSPSC
48MHz
/2,3,4,5
LSICLK
40KHz
OTGFSCLK
IWDTCLK
RTCSEL[1:0]
OSC32_OUT
OSC32_IN
LSECLK
OSC
32.768
KHz
Cortex
System
Clock
/8
RTC
FCLK
/128
CSS
OSC_OUT
OSC_IN
96MHz MAX
3-25MHz
HSECLK
OSC
PLLPSC1SRC
PLLSEL
PLLPSC1
PLL1CLK
/1,2,
x4\x5\
...16
PLL2CLK
x6\x6.5
\x7\x8\
/2
x9
SYSCLK
96MHz MAX
8MHz
HSICLK
HSECLK
AHB
Prescaler
/1,2...512
48MHz MAX
FMCCLK
/1,2,
...16
x8，x9...x14，
x16，x20
SCLKSEL
APB1
Rrescaler
/1,2,4,8,16
48MHz MAX
ADC
Prescaler
/2,4,6,8
MCOSEL
MCO
TMR2,3,4,5,6,7
if(APB1 prescaler=1)×1
else×2
PLL2CLK
PLL3CLK
x8，x9...x14，
x16，x20
DPLL3CLK
(PLL3CLK*2)
HSECLK
HSICLK
SYSCLK
PLL1CLK/2
PLL2CLK
PLL3CLK/2
PLL3CLK
OSCCLK
HCLK to
core
memory
and DMA
14MHz MAX
TMRxCLK
(x=2,3.
..7)
PCLK1
ADCCLK
(ADC1,2)
96MHz MAX
APB2
PRESCLAER
/1,2,4,8,16
TMR1
if(APB2 prescaler=1)×1
else×2
96MHz MAX
TMR1CLK
PCLK2
I2S2CLK
I2S3CLK
4.5.2. Clock source
Clock source is divided into high-speed clock and low-speed clock according to the speed; the
high-speed clock includes HSICLK and HSECLK, and the low-speed clock includes LSECLK
and LSICLK; clock source is divided into internal clock and external clock according to the chip
inside/outside; the internal clock includes HSICLK and LSICLK, and the external clock includes
HSECLK and LSECLK, among which HSICLK is calibrated by the factory to ±1% accuracy.
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P a ge 2 1
4.5.3. System clock
HSICLK, PLL1CLK and HSECLK can be selected as system clock; the clock source of
PLL1CLK can be one of HSICLK and HSECLK; the required system clock can be obtained by
configuring PLL clock multiplier factor and frequency dividing coefficient.
When the product is reset and started, HSICLK is selected as the system clock by default, and
then the user can choose one of the above clock sources as the system clock by himself. When
HSECLK failure is detected, the system will automatically switch to the HSICLK, and if an
interrupt is enabled, the software can receive the related interrupt.
4.5.4. Bus clock
AHB, APB1 and APB2 are built in. The clock source of AHB is SYSCLK, and the clock source of
APB1 and APB2 is HCLK; the required clock can be obtained by configuring the frequency
dividing coefficient. The maximum frequency of AHB and high-speed APB2 is 96MHz, and the
maximum frequency of APB1 is 48MHz.
4.6. Power supply and power management
4.6.1. Power supply scheme
Table6 Power Supply Scheme
Name
Voltage range
VDD
2.0～3.6V
VDDA/VSSA
2.0～3.6V
VBAT
1.8～3.6V
Instruction
I/Os (see pin distribution diagram for specific IO) and internal voltage regulator
are powered through VDD pin.
Power supply of ADC, DAC, reset module, RC oscillator and PLL analog part;
when ADC or DAC is us-ed, VDDA shall not be less than 2.4V; VDDA and VSSA
must be connected to VDD and VSS.
When VDD is closed, RTC, external 32.768KHz oscillator and backup register
are supplied through internal power switch.
4.6.2. Voltage regulator
Table7 Regulator Operating Mode
Name
Instruction
Master mode (MR)
Used in run mode
Low-power mode (LPR)
Used in stop mode
Used in standby mode, when the voltage regulator has high impedance output, the core
circuit is powered down, the power consumption of the voltage regulator is zero, and all
data of registers and SRAM will be lost.
Note: The voltage regulator is always in working state after reset, and outputs with high impedance in power-down
Power-down mode
mode.
4.6.3. Power supply voltage monitor
Power-on reset (POR) and power-down reset (PDR) circuits are integrated inside the product.
These two circuits are always in working condition. When the power-down reset circuit monitors
that the power supply voltage is lower than the specified threshold value (VPOR/PDR), even if the
external reset circuit is used, the system will remain reset.
The product has a built-in programmable voltage regulator (PVD) that can monitor VDD and
compare it with VPVD threshold. When VDD is outside the VPVD threshold range and the interrupt
is enabled, the MCU can be set to a safe state through the interrupt service program.
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4.7. Low-power mode
APM32F107 105xx supports three low-power modes, namely, sleep mode, stop mode and
standby mode, and there are differences in power, wake-up time and wake-up mode among
these three modes. The low-power mode can be selected according to the actual application
requirements.
Table8 Low Power Consumption Mode
Mode
Instruction
Sleep mode
The core stops working, all peripherals are working, and it can be woken up through interrupts/events
Stop mode
Standby mode
Under the condition that SRAM and register data are not lost, the stop mode can achieve the lowest
power consumption;
The clock of the internal 1.5V power supply module will stop, HSECLK crystal resonator, HSICLK and
PLL will be prohibited, and the voltage regulator can be configured in normal mode or low power mode;
Any external interrupt line can wake up MCU, and the external interrupt lines include one of the 16
external interrupt lines, PVD output, RTC and USB OTG_FS.
The power consumption in this mode is the lowest;
Internal voltage regulator is turned off, all 1.3V power supply modules are powered off, HSECLK crystal
resonator, HSICLK and PLL clocks are turned off, SRAM and register data disappear, RTC area and
backup register contents remain, and standby circuit still works;
The external reset signal on NRST, IWDT reset, rising edge on WKUP pin or RTC event will wake
MCU out of standby mode.
4.8. DMA
2 built-in DMAs; DMA1 supports 7 channels and DMA2 supports 5 channels. Each channel
supports multiple DMA requests, but only one DMA request is allowed to enter the DMA
channel at the same time. The peripherals supporting DMA requests are ADC, SPI, USART,
I2C, and TMRx. Four levels of DMA channel priority can be configured. Support
"memory→memory, memory→peripheral, peripheral→memory" transfer of data (the memory
includes Flash、SRAM)
4.9. GPIO
GPIO can be configured as general input, general output, multiplexing function and analog
input、output. The general input can be configured as floating input, pull-up input and pull-down
input; the general output can be configured as push-pull output and open-drain output; the
multiplexing function can be used for digital peripherals; and the analog input and output can be
used for analog peripherals and low-power mode; the enable and disable pull-up/pull-down
resistor can be configured; the speed of 2MHz, 10MHz and 50MHz can be configured; the
higher the speed is, the greater the power and the noise will be.
4.10. Communication peripherals
4.10.1. USART/UART
Up to 5 universal synchronous/asynchronous transmitter receivers are built in the chip. The
USART1 interface can communicate at a rate of 4.5Mbit/s, while other USART/UART interfaces
can communicate at a rate of 2.25Mbit/s. All USART/UART interfaces can configure baud rate,
parity check bit, stop bit, and data bit length; except UART5, all the other USART/UART can
support DMA. USART/UART function differences are shown in the table below:
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Table9 USART/UART Function Differences
USART mode/function
USART1
USART2
USART3
UART4
UART5
Hardware flow control of modem
√
√
√
—
—
Synchronous mode
√
√
√
√
√
Smart card mode
√
√
√
—
—
IrDASIR coder-encoder functions
√
√
√
√
√
LIN mode
√
√
√
√
√
Single-line half-duplex mode
√
√
√
√
√
Support DMA function
√
√
√
√
—
Note: √ = support.
4.10.2. I2C
I2C1/2 bus interfaces are built in. I2C1/2 both can work in multiple master modes or slave
modes, support 7-bit or 10-bit addressing, and support dual-slave addressing in 7-bit slave
mode; the communication rate supports standard mode (up to 100kbit/s) and fast mode (up to
400kbit/s); hardware CRC generator/checker are built in; they can operate with DMA and
support SMBus 2.0 version/PMBus.
4.10.3. SPI/I2S
Three built-in SPIs, support full duplex and half duplex communication in master mode and
slave mode, can use DMA controller, and can configure 4~16 bits per frame, and communicate
at a rate of up to 18Mbit/s.
2 built-in I2S (multiplexed with SPI2 and SPI3 respectively), support half duplex communication
in master mode and slave mode, support synchronous transmission, and can be configured
with 16-bit, 24-bit and 32-bit data transfer with 16-bit or 32-bit resolution. The configurable
range of audio sampling rate is 8kHz~48kHz; when one or two I2S interfaces are configured as
the master mode, the master clock can be output to external DAC or decoder (CODEC) at 256
times of sampling frequency.
4.10.4. CAN
2 built-in CANs (CAN1 and CAN2 can be used at the same time), compatible with 2.0A and
2.0B (active) specification, and can communicate at a rate of up to 1Mbit/s. It can receive and
send standard frame of 11-bit identifier and extended frame of 29-bit identifier. It has 3 sending
mailboxes and 2 receiving FIFO, 28 3-level adjustable filters.
4.10.5. USB OTG_FS
1 USB controllers, namely, OTG_FS can support both host and slave functions to comply with
the On-The-Go supplementary standard of USB 2.0 specification, and can also be configured
as "Host only" or "Slave only" mode, to fully comply with USB 2.0 specification. OTG_FS clock
(48MHz) is output by specific PLL1.
4.10.6. Ethernet
Provides an IEEE-802.3-2002 compatible MAC for Ethernet LAN communication over MII or
RMII. This MCU requires a PHY connection to a physical LAN bus. The PHY connects to the
MII port, uses 17 signals for MII or 9 signals for RMII, and can use a 25MHz clock (MII) from the
kernel.
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4.11. Analog peripherals
4.11.1. ADC
2 built-in ADCs with 12-bit accuracy, up to 16 external channels and 2 internal channels for
each ADC. The internal channels measure the temperature sensor voltage and reference
voltage respectively. A/D conversion mode of each channel has single, continuous, scan or
intermittent modes, ADC conversion results can be left aligned or right aligned and stored in 16
bit data register; they support analog watchdog, and DMA.
4.11.1.1. Internal reference voltage
Built-in reference voltage VREFINT, internally connected to ADC_IN17 channel, which can be
obtained through ADC; VREFINT provides stable voltage output for ADC.
4.11.2. DAC
Two built-in 12-bit DACs, and each corresponding to an output channel, which can be
configured in 8-bit and 12-bit modes, and the DMA function is supported. The waveform
generation supports noise wave and triangle wave. The conversion mode supports independent
or simultaneous conversion and the trigger mode supports external signal trigger and internal
timer update trigger.
4.12. Timer
1 built-in 16-bit advanced timers (TMR1), 4 general-purpose timers (TMR2/3/4/5), 2 basic
timers (TMR6/7), 1 independent watchdog timer, 1 window watchdog timer and 1 system tick
timer.
Watchdog timer can be used to detect whether the program is running normally.
The system tick timer is the peripheral of the core with automatic reloading function. When the
counter is 0, it can generate a maskable system interrupt, which can be used for real-time
operating system and general delay.
Table10 Function Comparison between Advanced/General-purpose/Basic and System Tick Timers
Timer type
System tick
timer
Timer name
Sys Tick Timer
Counter resolution
24-bit
16 bits
16 bits
Counter type
Down
Up
Up, down, up/down
Prescaler coefficient
-
Any integer
between 1 and
65536
Any integer between 1 and
65536
General DMA request
-
OK
OK
OK
Capture/Comparison
channel
-
-
4
4
Complementary outputs
-
No
No
Yes
Pin characteristics
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-
Basic timer
TMR6
TMR7
-
General-purpose timer
TMR2
TMR3
TMR4
TMR5
There are 5 pins in total:
1-way external trigger signal
input pins,
4-way channel (noncomplementary channel) pins
Advanced timer
TMR1
16 bits
Up, down,
up/down
Any integer
between 1 and
65536
There are 9 pins
in total:
1-way external
trigger signal
input pins,
1-way braking
input signal pins,
P a ge 2 5
System tick
timer
Timer type
Function
Instruction
Special for realtime operating
system
Automatic
reloading function
supported
When the counter
is 0, it can
generate a
maskable system
interrupt
Can program the
clock source
Basic timer
Used to generate
DAC trigger
signals.
Can be used as
a 16-bit generalpurpose
timebase
counter.
General-purpose timer
Synchronization or event
chaining function provided
Timers in debug mode can be
frozen.
-Can be used to generate PWM
output Each timer has
independent DMA request
generation.
It can handle incremental
encoder signals
Advanced timer
3-pair
complementary
channel pins,
1-way channel
(noncomplementary
channel) pins
It has
complementary
PWM output with
dead band
insertion
When configured
as a 16-bit
standard timer, it
has the same
function as the
TMRx timer.
When configured
as a 16-bit PWM
generator, it has
full modulation
capability
(0~100%).
In debug mode,
the timer can be
frozen, and PWM
output is
disabled.
Synchronization
or event chaining
function provided.
Table11 Independent Watchdog and Window Watchdog Timers
Name
Counter
resolution
Counter
type
Prescaler
coefficient
Independent
watchdog
12-bit
Down
Any integer
between 1 and
256
Window
watchdog
7-bit
Down
-
Functional Description
The clock is provided by an internally independent RC
oscillator of 40KHz, which is independent of the
master clock, so it can run in stop and standby
modes.
The whole system can be reset in case of problems.
It can provide timeout management for applications
as a free-running timer.
It can be configured as a software or hardware startup
watchdog through option bytes.
Timers in debug mode can be frozen.
Can be set for free running.
The whole system can be reset in case of problems.
Driven by the master clock, it has early interrupt
warning function;
Timers in debug mode can be frozen.
4.13. RTC
1 RTC is built in, and there are LSECLK signal input pins (OSC32_IN and OSC32_OUT) and 1
TAMP input signal detection pin (TAMP); the clock source can select external 32.768kHz crystal
oscillator, resonator or oscillator, LSICLK and HSECLK/128; it is supplied by VDD by default;
when VDD is powered off, it can be automatically switched to VBAT power supply, and RTC
configuration and time data will not be lost; RTC configuration and time data are not lost in case
of system resetting, software resetting and power resetting; it supports clock and calendar
functions.
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4.13.1. Backup register
84Bytes backup register is built in, and is supplied by VDD by default; when VDD is powered off, it
can be automatically switched to VBAT power supply, and the data in backup register will not be
lost; the data in backup register will not be lost in case of system resetting, software resetting
and power resetting.
4.14. CRC
A CRC (cyclic redundancy check) calculation unit is built in, which can generate CRC codes
and operate 8-bit, 16-bit and 32-bit data.
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5. Electrical characteristics
5.1. Test conditions of electrical characteristics
5.1.1. Maximum and minimum values
Unless otherwise specified, all products are tested on the production line at TA=25℃. Its
maximum and minimum values can support the worst environmental temperature, power supply
voltage and clock frequency.
In the notes at the bottom of each table, it is stated that the data are obtained through
comprehensive evaluation, design simulation or process characteristics and are not tested on
the production line; on the basis of comprehensive evaluation, after passing the sample test,
take the average value and add and subtract three times the standard deviation (average ±3∑)
to get the maximum and minimum values.
5.1.2. Typical value
Unless otherwise specified, typical data are measured based on TA=25℃, VDD=VDDA=3.3V.
these data are only used for design guidance.
5.1.3. Typical curve
Unless otherwise specified, typical curves will only be used for design guidance and will not be
tested.
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5.1.4. Power supply scheme
Figure 5 Power Supply Scheme
MCU
VBAT
VBAT
VDD
Power switch
LSECLK, RTC,
backup register
VSS
VDDX
x×100nF＋
1×4.7μF
Input Schmitt
trigger,
output buffer
Core,
Flash,
SRAM,
Voltage regulator
I/O logic,
Input Schmitt
trigger,
output buffer
VDD
VDDA
RC oscillator,
analog peripheral
1×10nF＋
1×1μF
VDD
1×10nF＋
1×1μF
digital
peripheral
VSSA
VREF+
ADC、DAC
VREF-
Notes: VDDx in the figure means the number of VDD is x
5.1.5. Load capacitance
Figure 6 Load conditions when measuring pin parameters
MCU pin
c=50p
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Figure 7 Pin Input Voltage Measurement Scheme
MCU pin
VIN
Figure 8 Power Consumption Measurement Scheme
VDD
A
IDDA
A
VBAT
MCU
IDD
VDDX
VSS
VREF+
VDDA
VSSA
IDD_VBAT
A
VREF-
VBAT
5.2. Test under general operating conditions
Table12 General Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
Internal AHB clock frequency
-
-
96
fPCLK1
Internal APB1 clock frequency
-
-
48
fPCLK2
Internal APB2 clock frequency
-
-
96
VDD
Main power supply voltage
-
2
3.6
Must be the same
as VDD
VDD
3.6
VDDA
Analog power supply voltage
(When neither ADC nor DAC is used)
Analog power supply voltage
(When ADC and DAC are used)
2.4
3.6
VBAT
Power supply voltage of backup domain
-
1.8
3.6
V
TA
Ambient temperature (temperature
number 6)
Maximum power
dissipation
-40
85
℃
MHz
V
V
5.3. Absolute maximum ratings
If the load on the device exceeds the absolute maximum rating, it may cause permanent
damage to the device. Here, only the maximum load that can be borne is given, and there is no
guarantee that the device functions normally under this condition.
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5.3.1. Maximum temperature characteristics
Table13 Temperature Characteristics
Symbol
Description
Numerical Value
Unit
TSTG
Storage temperature range
-55 ~ +150
℃
TJ
Maximum junction temperature
105
℃
5.3.2. Maximum rated voltage characteristics
All power supply (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the
power supply within the external limited range.
Table14 Maximum Rated Voltage Characteristics
Symbol
Description
Minimum
value
Maximum
value
VDD - VSS
External main power supply voltage
-0.3
4.0
VDDA-VSSA
External analog power supply voltage
-0.3
4.0
VBAT-VSS
Power supply voltage of external backup domain
-0.3
4.0
VDD-VDDA
Voltage difference allowed by VDD>VDDA
-
0.3
Input voltage on FT pins
VSS-0.3
5.5
Input voltage on other pins
VSS-0.3
VDD + 0.3
| ΔVDDx |
Voltage difference between different power supply
pins
-
50
| VSSx-VSS |
Voltage difference between different grounding pins
-
50
Unit
V
VIN
mV
5.3.3. Maximum rated current features
Table15 Current Characteristics
Symbol
Description
Maximum
IVDD
Total current into VDD/VDDA power lines (source)(1)
150
IVSS
Total current out of VSS ground lines (sink)(1)
150
Irrigation current on any I/O and control pins
25
Source current on any I/O and control pins
-25
Injection current of 5T pin(3)
-5/+0
Injection current of other pins(4)
±5
Total injection current on all I/O and control pins (5)
±25
Unit
IIO
IINJ(PIN)
mA
(2)
ΣIINJ(PIN)(2)
Notes:
（1） All power (VDD，VDDA) and ground (VSS，VSSA) pins must always be connected to a power
supply within the external allowable range.
（2） Negative injection disturbs the analog performance of the device.
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（3） Positive injection is not possible on these I/Os. a negative injection is induced by VINVDD while a negative injection is induced by VIN8MHz, turn on PLL, otherwise, turn off PLL.
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5.7.3. Power consumption in sleep mode
Table29 Power Consumption in Sleep Mode when the Program is Executed in Flash or SRAM
Parameter
Conditions
TA=25℃，VDD=3.3V
TA=105℃，VDD=3.6V
IDD(mA）
IDDA(μA)
IDD(mA)
96 MHz
376.86
12.27
423.00
13.06
72MHz
242.56
9.36
274.46
9.58
48MHz
194.82
6.61
221.60
7.18
36MHz
179.99
5.68
204.54
6.13
24MHz
157.53
4.08
181.12
4.65
16MHz
172.24
3.05
196.76
3.56
8MHz
111.03
1.94
132.61
2.44
96 MHz
376.19
4.66
423.80
5.14
72MHz
242.28
3.61
274.45
4.00
48MHz
194.68
2.74
221.70
3.22
36MHz
179.90
2.44
205.52
2.90
24MHz
157.45
1.94
181.58
2.41
16MHz
172.15
1.63
197.04
2.11
8MHz
111.02
1.22
133.28
1.73
36MHz
183.47
5.71
196.38
6.56
HSICLK (2) , enabling all
24MHz
160.89
4.08
172.68
4.53
peripherals
16MHz
175.62
3.06
188.03
3.53
8MHz
113.95
1.94
123.99
2.39
36MHz
183.41
2.44
196.20
2.87
HSICLK (2) , turning off all
24MHz
160.80
1.93
172.43
2.37
peripherals
16MHz
175.55
1.63
187.81
2.07
8MHz
113.94
1.22
123.89
1.66
peripherals
consumption
Maximum value (1)
IDDA(μA)
HSECLK bypass (2) , enabling all
Power
fHCLK
Typical value (1)
HSECLK bypass
(2)
, turning off all
peripherals
in sleep mode
Note:
(1) It is obtained from a comprehensive evaluation and is not tested in production.
(2) The external clock is 8MHz, and when fHCLK>8MHz, turn on PLL, otherwise, turn off PLL
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5.7.4. Power consumption in stop mode and standby mode
Table30 Power Consumption in Stop Mode and Standby Mode
Maximum
value (1),
(VDD=3.6V)
Typical value (1), (TA=25℃)
Parameter
Power
consumption
in stop mode
Power
consumption
in standby
mode
Conditions
VDD=2.4V
Regulator in run
mode, low-speed and
high-speed internal
RC oscillators and
high-speed oscillator
OFF(no independent
watchdog)
Regulator in lowpower mode, lowspeed and high-speed
internal RC oscillators
and high-speed
oscillator OFF(no
independent
watchdog)
Low-speed internal
RC oscillator and
independent watchdog
ON
Low-speed internal
RC oscillator on,
independent watchdog
OFF
Low-speed internal
RC oscillator and
independent watchdog
OFF, low-speed
oscillator and RTC
OFF
VDD=3.3V
VDD=3.6V
Unit
TA=105℃
IDDA
IDD
IDDA
IDD
IDDA
IDD
IDDA
IDD
3.667
42.441
4.282
42.169
4.594
43.11
6.16
386.35
3.662
32.30
4.282
32.093
4.589
32.623
6.18
353.42
μA
2.885
0.164
3.781
0.346
4.218
0.503
5.32
4.74
2.883
0.042
3.781
0.189
4.221
0.323
5.30
4.41
2.336
0.01
2.957
0.064
3.271
0.018
4.43
3.95
Note: (1) It is obtained from a comprehensive evaluation and is not tested in production.
5.7.5. Backup domain power consumption
Table31 Backup Domain Power Consumption
Typical value (1), TA=25℃
Symbol
Maximum value (1), VBAT=3.6V
Conditions
VBAT=2.0V
VBAT=2.4V
VBAT=3.3V
TA=25℃
The low-speed
0.867
0.956
1.278
1.5
oscillator and RTC
are in ON state
Note: (1) It is obtained from a comprehensive evaluation and is not tested in production.
IDD_VBAT
TA=85℃
TA=105℃
2.4
3.5
Uni
t
μA
5.7.6. Peripheral power consumption
The HSECLK Bypass 1M is adopted as clock source, fPCLK=fHCLK=1M.
Peripheral power consumption = current that enables the peripheral clock-current that disables
the peripheral clock.
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Table32 Peripheral Power Consumption
Parameter
AHB
APB1
Peripheral
Typical value (1) TA =25℃, VDD =3.3V
DMA1
0.09
DMA2
0.07
CRC
0.71
Ethernet
1.08
USB OTG_FS
1.75
TMR2
0.29
TMR3
0.26
TMR4
0.26
TMR5
0.26
TMR6
0.05
TMR7
0.05
WWDT
0.80
IWDT
0.06
SPI2/I2S2
0.24
SPI3/I2S3
0.05
USART2
0.10
USART3
0.09
UART4
0.09
UART5
0.10
I2C1
0.07
I2C2
0.08
CAN1
0.15
CAN2
0.14
BAKPR
0.01
DAC
0.05
PMU
0.03
GPIOA
0.08
GPIOB
0.11
GPIOC
0.10
GPIOD
0.10
GPIOE
0.10
ADC1
0.33
Unit
mA
APB2
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Parameter
Peripheral
Typical value (1) TA =25℃, VDD =3.3V
ADC2
0.31
TMR1
0.38
SPI1
0.19
USART1
0.17
Unit
Note: It is obtained from a comprehensive evaluation and is not tested in production.
5.8. Wake-up time in low power mode
The measurement of wake-up time in low power mode is from the start of wake-up event to the
time when the user program reads the first instruction, in which VDD=VDDA.
Table33 Wake Up Time in Low-power Mode
Typical value (TA=25℃)
Symbol
Parameter
Conditions
tWUSLEEP
Wake-up
from sleep
mode
tWUSTOP
Wake up from
stop mode
Min
Max
2V
3.3V
3.6V
Unit
-
0.51
0.58
0.57
0.58
0.64
The voltage regulator is in run mode
1.78
2.18
1.88
1.83
2.22
The voltage regulator is in low power
mode
2.58
4.06
2.90
2.77
4.55
68.63
66.97
93.10
μs
Wake up from
62.78
80.03
standby
mode
Note: It is obtained from a comprehensive evaluation and is not tested in production.
tWUSTDBY
5.9. Pin characteristics
5.9.1. I/O pin characteristics
Table34 DC Characteristics (test condition of VDD=2.7~3.6V, TA=-40~105℃)
Symbol
Parameter
Conditions
Minimum value
Typical
value
VIL
Standard I/O low level input voltage
-
-0.3
-
VIH
I/O FT high level input voltage
-
-0.3
-
VIL
Standard I/O low level input voltage
-
0.41*(VDD-2V)+1.3V
-
VDD+0.3
Standard I/O high level input voltage
VDD>2V
-
5.5
Unit
0.28*(VDD2V)+0.8V
0.32*(VDD2V)+0.75V
V
0.42*(VDD-2V)+1V
VIH
Vhys
Maximum
value
I/O FT high level input voltage
VDD≤2V
Standard I/O Schmitt trigger voltage
hysteresis
I/O FT Schmitt trigger voltage
hysteresis
-
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5.2
200
-
-
mV
5%VDD
-
-
mV
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Symbol
Ilkg
RPU
RPD
Parameter
Conditions
Input leakage current
VSS ≤ VIN ≤
VDD
Standard
I/O port
VIN=5V，
I/O FT port
Weak pull-up equivalent resistance
of all pins except PA10
Weak pull-up equivalent resistance
of PA10
Weak pull-down equivalent
resistance of all pins except PA10
Weak pull-down equivalent
resistance of PA10
CIO
Minimum value
Typical
value
Maximum
value
-
-
±1
Unit
μA
-
-
3
30
40
50
8
11
15
30
40
50
8
11
15
-
2.6
-
pF
VIN=VSS
kΩ
VIN=VDD
IO pin capacitance
-
Note: It is obtained from a comprehensive evaluation and is not tested in production.
Table35 AC Characteristics
MODEy[1:0]
Configuration
10
(2MHz)
Symbol
Parameter
Conditions
Minimum
value
Maximum
value
Unit
fmax(IO)out
Maximum frequency
CL=50 pF，
VDD=2~3.6V
-
2
MHz
Output fall time from high to low
level
Output rise time from low to high
level
CL=50 pF，
VDD =2~3.6V
-
125
-
125
Maximum frequency
CL=50 pF，
VDD =2~3.6V
-
10
Output fall time from high to low
level
Output rise time from low to high
level
CL=50 pF，
VDD =2~3.6V
-
25
-
25
Maximum frequency
CL=50 pF，
VDD =2.7~3.6V
-
50
tf(IO)out
tr(IO)out
fmax(IO)out
01
(10MHz)
tf(IO)out
tr(IO)out
fmax(IO)out
11
(50MHz)
ns
MHz
ns
Output fall time from high to low
12
level
CL=50 pF，
Output rise time from low to high
VDD =2.7~3.6V
12
tr(IO)out
level
Note: (1) The rate of I/O port can be configured through the corresponding register (see the user manual).
MHz
tf(IO)out
ns
(2) The data are obtained from a comprehensive evaluation and is not tested in production.
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Figure 9 I/O AC Characteristics Definition
90%
The external
output load
is 50pF
10%
50%
50%
90%
10%
tr(IO)OUT
tr(IO)OUT
T
If (tr+tf) is less than or equal to (2/3) T and the
duty cycle is (45~55%)
When the load is 50pF, it reaches the maximum
frequency
Note: It is obtained from a comprehensive evaluation and is not tested in production.
Table36 Output Drive Current Characteristics (test condition VDD=2.7~3.6V, TA=-40~105℃)
Symbol
VOL
VOH
VOL
VOH
Parameter
Conditions
Output low level voltage for an I/O pin when
8 pins are sunk at same time
Output high level voltage for an I/O pin when
8 pins are sourced at same time
Output low level voltage for an I/O pin when
8 pins are sunk at same time
Output high level voltage for an I/O pin when
8 pins are sourced at same time
IIO = +8mA
2.7V
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