APM32F030CCT6

Datasheet APM32F030xC Arm® Cortex® -M0+ based 32-bit MCU Version: V1.2 1 Product characteristics  Core 32-bit Up to 29 FT I/Os Arm® Cortex® -M0+ core  Up to 48MHz working frequency   2 I2C interfaces (1Mbit/s), all of which support SMBus/PMBus On-chip memory Flash：256KB 6 USARTs, support synchronous transmission function SRAM：32KB 2 SPI (18Mbit/s) interfaces Clock  HSECLK: 4~32MHz external crystal/ceramic oscillator supported LSECLK: 32.768KHz crystal/ceramic oscillator supported  5 16-bit general-purpose timers TMR3/14/15/16 and TMR17, with up to 4 independent channels to support input capture, output comparison, PWM, pulse count and other functions. LSICLK: 40KHz RC oscillator supported PLL: Phase locked loop, 2~16 times of frequency supported 2 16-bit basic timers TMR6/7 Reset and power management 2 watchdog timers: one independent watchdog IWDT and one window watchdog WWDT VDD range: 2.0～3.6V VDDA range: VDD～3.6V  1 24-bit autodecrement SysTick Timer  Low-power mode DMA 5-channel DMA controller  RTC Support calendar function Sleep, stop and standby modes supported  Timer 1 16-bit advanced timer TMR1 that can provide 7-channel PWM output, support dead zone generation and braking input functions HSICLK14: 14MHz RC oscillator supported Power-on/power-down reset (POR/PDR) supported Analog peripherals 1 12-bit ADC, support up to 16 external channels HSICLK: 8MHz RC oscillator calibrated by factory  Communication peripherals Alarm and periodic wake-up from stop/standby mode  CRC computing unit  96-bit unique device ID (UID) Debugging interface SWD  I/O Up to 51 I/Os All I/Os can be mapped to external interrupt vector www.geeh y.com P age 1 Contents 1 Product characteristics .............................................................................................. 1 2 Product information ................................................................................................... 5 3 Pin information ........................................................................................................... 6 3.1 Pin distribution ................................................................................................................................... 6 3.2 Pin function description ..................................................................................................................... 7 4 Functional description ............................................................................................. 14 4.1 System architecture ......................................................................................................................... 14 4.1.1 System Block Diagram ............................................................................................................................ 14 4.1.2 Memory mapping ..................................................................................................................................... 14 4.1.3 Startup configuration ............................................................................................................................... 16 4.2 Core ................................................................................................................................................. 17 4.3 Interrupt controller............................................................................................................................ 17 4.3.1 Nested Vector Interrupt Controller (NVIC) ............................................................................................... 17 4.3.2 External Interrupt/Event Controller (EINT) .............................................................................................. 17 4.4 On-chip memory .............................................................................................................................. 17 4.5 Clock ................................................................................................................................................ 17 4.5.1 Clock source ............................................................................................................................................ 18 4.5.2 System clock ........................................................................................................................................... 18 4.5.3 Bus clock ................................................................................................................................................. 19 4.6 Reset and power management ....................................................................................................... 19 4.6.1 Power supply scheme ............................................................................................................................. 19 4.6.2 Voltage regulator ..................................................................................................................................... 19 4.6.3 Power supply voltage monitor ................................................................................................................. 19 4.7 Low-power mode ............................................................................................................................. 19 4.8 DMA ................................................................................................................................................. 20 4.9 GPIO ................................................................................................................................................ 20 4.10 Communication peripherals ............................................................................................................. 20 4.10.1 USART ..................................................................................................................................................... 20 4.10.2 I2C ........................................................................................................................................................... 21 4.10.3 SPI ........................................................................................................................................................... 21 w w w. g e e h y. c o m Page 2 4.11 Analog peripherals ........................................................................................................................... 21 4.11.1 ADC ......................................................................................................................................................... 21 4.12 Timer ................................................................................................................................................ 22 4.13 RTC .................................................................................................................................................. 23 4.14 CRC ................................................................................................................................................. 24 5 Electrical characteristics ......................................................................................... 25 5.1 Test conditions of electrical characteristics ..................................................................................... 25 5.1.1 Maximum and minimum values ............................................................................................................... 25 5.1.2 Typical values .......................................................................................................................................... 25 5.1.3 Typical curve ............................................................................................................................................ 25 5.1.4 Power supply scheme ............................................................................................................................. 26 5.1.5 Load capacitance .................................................................................................................................... 26 5.2 Test under general operating conditions ......................................................................................... 27 5.3 Absolute maximum ratings .............................................................................................................. 28 5.3.1 Maximum temperature characteristics .................................................................................................... 28 5.3.2 Maximum rated voltage characteristics ................................................................................................... 28 5.3.3 Maximum rated current features ............................................................................................................. 28 5.3.4 ESD characteristics ................................................................................................................................. 29 5.3.5 Static latch-up .......................................................................................................................................... 29 5.4 On-chip memory .............................................................................................................................. 30 5.4.1 Flash characteristics ................................................................................................................................ 30 5.5 Clock ................................................................................................................................................ 30 5.5.1 Characteristics of external clock source .................................................................................................. 30 5.5.2 Characteristics of internal clock source ................................................................................................... 31 5.5.3 PLL Characteristics.................................................................................................................................. 32 5.6 Reset and power management ....................................................................................................... 32 5.6.1 Test of Embedded Reset and Power Control Block Characteristics ....................................................... 32 5.7 Power consumption ......................................................................................................................... 33 5.7.1 Power consumption test environment ..................................................................................................... 33 5.7.2 Power consumption in run mode ............................................................................................................. 33 5.7.3 Power consumption in sleep mode ......................................................................................................... 35 5.7.4 Power consumption in stop mode and standby mode ............................................................................ 36 w w w. g e e h y. c o m Page 3 5.7.5 Peripheral power consumption ................................................................................................................ 37 5.8 Wake-up time in low power mode ................................................................................................... 38 5.9 Pin characteristics............................................................................................................................ 38 5.9.1 I/O pin characteristics .............................................................................................................................. 38 5.9.2 NRST pin characteristics ......................................................................................................................... 40 5.10 Communication peripherals ............................................................................................................. 41 5.10.1 I2C peripheral characteristics .................................................................................................................. 41 5.10.2 SPI peripheral characteristics .................................................................................................................. 42 5.11 Analog peripherals ........................................................................................................................... 44 5.11.1 ADC ......................................................................................................................................................... 44 6 Package information ................................................................................................ 46 6.1 LQFP64 Package Diagram.............................................................................................................. 46 6.2 LQFP48 Package Diagram.............................................................................................................. 48 7 Packaging Information ............................................................................................. 51 7.1 Reel Packaging................................................................................................................................ 51 7.2 Tray packaging ................................................................................................................................ 52 8 Ordering Information................................................................................................ 54 9 Commonly Used Function Module Denomination ................................................. 55 10 Revision History ....................................................................................................... 56 w w w. g e e h y. c o m Page 4 2 Product information See the following table for APM32F030xC product functions and peripheral configuration. Table 1 Functions and Peripherals of APM32F030xC Series Chips Product APM32F030 Model CCTx RCTx Package LQFP48 LQFP64 Core and maximum working frequency Arm® 32-bit Cortex®-M0+@48MHz Operating voltage 2.0~3.6V Flash(KB) 256 SRAM(KB) 32 GPIOs Communication interface Timer 37 USART 6 SPI 2 I2C 2 16-bit advanced 1 16-bit general 5 16-bit basic 2 System tick timer 1 Watchdog 2 Real-time clock 1 Unit 12-bit ADC 51 External channel Internal channel 1 10 16 2 Ambient temperature: -40℃ to 85℃/-40℃ to 105℃ Operating temperature Junction temperature: -40℃ to 105℃/-40℃ to 125℃ Note: (1) When x is 6, ambient temperature is: from -40℃ to 85℃, and the junction temperature is from -40℃ to 105℃. (2) When x is 7, ambient temperature is: from -40℃ to 105℃, and the junction temperature is from -40℃ to 125℃. w w w. g e e h y. c o m Page 5 3 Pin information 3.1 Pin distribution 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDD VSS PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 1 Distribution Diagram of APM32F030xCTx Series LQFP64 Pins 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LQFP64 VDD VSS PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS VDD 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD PC13 PC14-OSC32_IN PC15-OSC32_OUT PF0-OSC_IN PF1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0 PA1 PA2 48 47 46 45 44 43 42 41 40 39 38 37 VDD VSS PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 Figure 2 Distribution Diagram of APM32F030xCTx Series LQFP48 Pins 1 2 3 4 5 6 7 8 9 10 11 12 LQFP48 36 35 34 33 32 31 30 29 28 27 26 25 VDD VSS PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS VDD 13 14 15 16 17 18 19 20 21 22 23 24 VDD PC13 PC14-OSC32_IN PC15-OSC32_OUT PF0-OSC_IN PF1-OSC_OUT NRST VSSA VDDA PA0 PA1 PA2 w w w. g e e h y. c o m Page 6 Pin function description 3.2 Table 2 Legends/Abbreviations Used in Output Pin Table Name Pin name Abbreviation Definition Unless otherwise specified in parentheses below the pin name, the pin functions during and after reset are the same as the actual pin name P Power pin I Only input pin I/O I/O pin 5T FT I/O 5Tf FT I/O, FM + function STDA I/O with 3.3V standard, directly connected to ADC STD I/O with 3.3 V tolerance B Dedicated Boot0 pin RST Bidirectional reset pin with built-in pull-up resistor Pin type I/O structure Note Unless otherwise specified in the notes, all I/O is set as floating input during and after reset Default multiplexing Pin function Function directly selected/enabled through peripheral register function Additional Function selected through GPIO multiplexing function register function Table 3 Description of APM32F030xCTx by Pin Number Name (Function after reset) VDD Type Structure P - Default multiplexing Additional function function Digital power supply LQFP48 LQFP64 1 1 2 2 RTC_TAMP1, PC13 I/O STD RTC_TS, - RTC_OUT, WKUP2 PC14-OSC32_IN (PC14) PC15-OSC32_OUT (PC15) PF0-OSC_IN (PF0) PF1-OSC_OUT (PF1) NRST w w w. g e e h y. c o m I/O STD - OSC32_IN 3 3 I/O STD - OSC32_OUT 4 4 I/O STD I2C1_SDA OSC_IN 5 5 I/O STD I2C1_SCL OSC_OUT 6 6 I/O RST 7 7 Chip reset input/internal reset output (active low) Page 7 Name Type Structure PC0 I/O STDA PC1 I/O STDA PC2 I/O STDA PC3 I/O STDA VSSA P - VDDA P - (Function after reset) PA0 I/O STDA Default multiplexing Additional function function LQFP48 LQFP64 ADC_IN10 - 8 ADC_IN11 - 9 ADC_IN12 - 10 ADC_IN13 - 11 Analog ground 8 12 Analog power supply 9 13 10 14 11 15 12 16 13 17 EVENTOUT, USART6_TX EVENTOUT, USART6_RX SPI2_MISO, EVENTOUT SPI2_MOSI, EVENTOUT USART2_CTS, USART4_TX ADC_IN0, RTC_TAMP2, WKUP1 USART2_RTS, PA1 I/O STDA EVENTOUT, ADC_IN1 USART4_RX USART2_TX, ADC_IN2, TMR15_CH1 WKUP4 PA2 I/O STDA PA3 I/O STDA VSS P - Ground - 18 VDD P - Digital power supply - 19 ADC_IN4 14 20 ADC_IN5 15 21 ADC_IN6 16 22 ADC_IN7 17 23 USART2_RX, ADC_IN3 TMR15_CH2 SPI1_NSS, PA4 I/O STDA USART2_CK, TMR14_CH1, USART6_TX PA5 I/O STDA SPI1_SCK, USART6_RX SPI1_MISO, TMR3_CH1, PA6 I/O STDA TMR1_BKIN, TMR16_CH1, EVENTOUT, USART3_CTS SPI1_MOSI, TMR3_CH2, PA7 I/O STDA TMR14_CH1, TMR1_CH1N, TMR17_CH1, EVENTOUT w w w. g e e h y. c o m Page 8 Name Type Structure PC4 I/O STDA PC5 I/O STDA (Function after reset) Default multiplexing Additional function function EVENTOUT, LQFP48 LQFP64 - 24 - 25 ADC_IN8 18 26 ADC_IN9 19 27 - 20 28 - 21 29 - 22 30 ADC_IN14 USART3_TX ADC_IN15, USART3_RX WKUP5 TMR3_CH3, PB0 I/O STDA TMR1_CH2N, EVENTOUT, USART3_CK TMR3_CH4, PB1 I/O STDA TMR14_CH1, TMR1_CH3N, USART3_RTS PB2 I/O 5T SPI2_SCK, PB10 I/O 5T I2C2_SCL, USART3_TX I2C2_SDA, PB11 I/O 5T EVENTOUT, USART3_RX VSS P - Ground 23 31 VDD P - Digital power supply 24 32 - 25 33 - 26 34 - 27 35 28 36 SPI2_NSS, PB12 I/O 5T TMR1_BKIN, EVENTOUT, USART3_CK SPI2_SCK, PB13 I/O 5T I2C2_SCL, TMR1_CH1N, USART3_CTS SPI2_MISO, I2C2_SDA, PB14 I/O 5T TMR1_CH2N, TMR15_CH1, USART3_RTS SPI2_MOSI, PB15 I/O 5T TMR1_CH3N, RTC_REFIN, TMR15_CH1N, WKUP7 TMR15_CH2 PC6 I/O 5T TMR3_CH1 - - 37 PC7 I/O 5T TMR3_CH2 - - 38 w w w. g e e h y. c o m Page 9 Name Default multiplexing Additional function function 5T TMR3_CH3 5T TMR3_CH4 Type Structure PC8 I/O PC9 I/O (Function after reset) LQFP48 LQFP64 - - 39 - - 40 - 29 41 - 30 42 - 31 43 - 32 44 - 33 45 - 34 46 USART1_CK, PA8 I/O 5T TMR1_CH1, EVENTOUT, MCO USART1_TX, PA9 I/O 5T TMR1_CH2, TMR15_BKIN, I2C1_SCL USART1_RX, PA10 I/O 5T TMR1_CH3, TMR17_BKIN, I2C1_SDA USART1_CTS, PA11 I/O 5T TMR1_CH4, EVENTOUT, I2C2_SCL USART1_RTS, PA12 I/O 5T TMR1_ETR, EVENTOUT, I2C2_SDA PA13 I/O 5T VSS P - Ground 35 47 VDD P - Digital power supply 36 48 I/O 5T - 37 49 - 38 50 - - 51 - - 52 - - 53 (SWDIO) PA14 (SWCLK) IR_OUT,SWDIO USART2_TX, SWCLK SPI1_NSS, PA15 I/O 5T USART2_RX, USART4_RTS, EVENTOUT PC10 I/O 5T PC11 I/O 5T USART3_TX, USART4_TX USART3_RX, USART4_RX USART3_CK, PC12 I/O 5T USART4_CK, USART5_TX w w w. ge e h y. c o m P a ge 1 0 Name (Function after reset) Type Structure Default multiplexing Additional function function LQFP48 LQFP64 - - 54 - 39 55 - 40 56 WKUP6 41 57 - 42 58 - 43 59 44 60 - 45 61 - 46 62 TMR3_ETR, PD2 I/O 5T USART3_RTS, USART5_RX SPI1_SCK, PB3 I/O 5T EVENTOUT, USART5_TX SPI1_MISO, TMR3_CH1, PB4 I/O 5T EVENTOUT, TMR17_BKIN, USART5_RX SPI1_MOSI, I2C1_SMBA, PB5 I/O STD TMR16_BKIN, TMR3_CH2, USART5_CK_RTS I2C1_SCL, PB6 I/O 5Tf USART1_TX, TMR16_CH1N I2C1_SDA, PB7 I/O 5Tf USART1_RX, TMR17_CH1N, USART4_CTS BOOT0 I B PB8 I/O 5T Startup selection I2C1_SCL, TMR16_CH1 I2C1_SDA, IR_OUT, PB9 I/O 5T SPI2_NSS, TMR17_CH1, EVENTOUT VSS P - Ground 47 63 VDD P - Digital power supply 48 64 Note: （1） PC13, PC14 and PC15 are powered through power switch. Since the switch only sinks limited current (3mA), the use of GPIO from PC13 to PC15 in output mode is limited: the speed shall not exceed 2MHz when the heavy load is 30pF; not used for current source (e.g. driving LED). （2） After reset, PA13 and PA14 are configured as SWDIO and SWCLK multiplexing functions, and the internal pullup of SWDIO pin and the internal pull-down of SWCLK pin are activated. w w w. g e e h y. c o m P a ge 11 Table 4 Port A Multiplexing Function Configuration Pin name AF0 AF1 AF2 AF3 AF4 AF5 AF6 PA0 - USART2_CTS - - USART4_TX - - PA1 EVENTOUT USART2_RTS - - USART4_RX TMR15_CH1N - PA2 TMR15_CH1 USART2_TX - - - - - PA3 TMR15_CH2 USART2_RX - - - - - PA4 SPI1_NSS USART2_CK - - TMR14_CH1 USART6_TX - PA5 SPI1_SCK - - - - USART6_RX - PA6 SPI1_MISO TMR3_CH1 TMR1_BKIN - USART3_CTS TMR16_CH1 EVENTOUT PA7 SPI1_MOSI TMR3_CH2 TMR1_CH1N - TMR14_CH1 TMR17_CH1 EVENTOUT PA8 MCO USART1_CK TMR1_CH1 EVENTOUT - - - PA9 TMR15_BKIN USART1_TX TMR1_CH2 - I2C1_SCL MCO - PA10 TMR17_BKIN USART1_RX TMR1_CH3 - I2C1_SDA - - PA11 EVENTOUT USART1_CTS TMR1_CH4 - - SCL - PA12 EVENTOUT USART1_RTS TMR1_ETR - - SDA - PA13 SWDIO IR_OUT - - - - - PA14 SWCLK USART2_TX - - - - - PA15 SPI1_NSS USART2_RX - EVENTOUT USART4_RTS - - Table 5 Port B Multiplexing Function Configuration Pin name AF0 AF1 AF2 AF3 AF4 AF5 PB0 EVENTOUT TMR3_CH3 TMR1_CH2N - USART3_CK - PB1 TMR14_CH1 TMR3_CH4 TMR1_CH3N - USART3_RTS - PB2 - - - - - - PB3 SPI1_SCK EVENTOUT - - USART5_TX - PB4 SPI1_MISO TMR3_CH1 EVENTOUT - USART5_RX TMR17_BKIN PB5 SPI1_MOSI TMR3_CH2 TMR16_BKIN I2C1_SMBA USART5_CK_RTS - PB6 USART1_TX I2C1_SCL TMR16_CH1N - - - PB7 USART1_RX I2C1_SDA TMR17_CH1N - USART4_CTS - PB8 - I2C1_SCL TMR16_CH1 - - - PB9 IR_OUT I2C1_SDA TMR17_CH1 EVENTOUT - SPI2_NSS PB10 - I2C2_SCL - - USART3_TX SPI2_SCK PB11 EVENTOUT I2C2_SDA - - USART3_RX - PB12 SPI2_NSS EVENTOUT TMR1_BKIN - USART3_RTS TMR15 PB13 SPI2_SCK - TMR1_CH1N - USART3_CTS I2C2_SCL w w w. ge e h y. c o m P a ge 1 2 Pin name AF0 AF1 AF2 AF3 AF4 AF5 PB14 SPI2_MISO TMR15_CH1 TMR1_CH2N - USART3_RTS I2C2_SDA PB15 SPI2_MOSI TMR15_CH2 TMR1_CH3N TMR15_CH1N - - Table 6 Port C Multiplexing Function Configuration Pin name AF0 AF1 AF2 PC0 EVENTOUT - USART6_TX PC1 EVENTOUT - USART6_RX PC2 EVENTOUT SPI2_MISO - PC3 EVENTOUT SPI2_MOSI - PC4 EVENTOUT USART3_TX - PC5 - USART3_RX - PC6 TMR3_CH1 - - PC7 TMR3_CH2 - - PC8 TMR3_CH3 - - PC9 TMR3_CH4 - - PC10 USART4_TX USART3_TX - PC11 USART4_RX USART3_RX - PC12 USART4_CK USART3_CK USART5_TX PC13 - - - PC14 - - - PC15 - - - Table 7 Port D Multiplexing Function Configuration Pin name AF0 AF1 AF2 PD2 TMR3_ETR USART3_RTS USART5_RX Table 8 Port F Multiplexing Function Configuration Pin name AF0 AF1 PF0 - I2C1_SDA PF1 - I2C1_SCL w w w. ge e h y. c o m P a ge 1 3 4 Functional description This chapter mainly introduces the system architecture, interrupt, on-chip memory, clock, power supply and peripheral features of APM32F030xC series products; for information about the Arm® Cortex®-M0+ core, please refer to the Arm® Cortex®-M0+ technical reference manual, which can be downloaded from Arm’s website. 4.1 System architecture 4.1.1 System Block Diagram Figure 3 APM32F030xC System Block Diagram Arm® Cortex®-M0+ (Fmax:48MHz) SWD SCB STK System bus NVIC Flash AHB1 Bus Flash Interface RCM AHB2 Bus DMA Bus Bus matrix DMA AHB1/APB bridge CRC GPIOs (A-D,F) SRAM TMR1/3/6/7/1 4/15/16/17 PMU SYSCFG 4.1.2 APB Bus RTC WWDT IWDT EINT SPI1/2 ADC USART1-6 DBGMCU I2C1/2 Memory mapping Table 9 APM32F030xC Storage Mapping Table Region Start address Peripheral Name Code 0x0000 0000 Code mapping area Code 0x0004 0000 Reserved w w w. ge e h y. c o m P a ge 1 4 Region Start address Peripheral Name Code 0x0800 0000 Main memory area Code 0x0804 0000 Reserved Code 0x1FFF D800 System memory Code 0x1FFF F800 Option byte Code 0x1FFF FC00 Reserved SRAM 0x2000 0000 SRAM — 0x2000 8000 Reserved APB bus 0x4000 0400 TMR3 APB bus 0x4000 0800 Reserved APB bus 0x4000 1000 TMR6 APB bus 0x4000 1400 TMR7 APB bus 0x4000 1800 Reserved APB bus 0x4000 2000 TMR14 APB bus 0x4000 2400 Reserved APB bus 0x4000 2800 RTC APB bus 0x4000 2C00 WWDT APB bus 0x4000 3000 IWDT APB bus 0x4000 3400 Reserved APB bus 0x4000 3800 SPI2 APB bus 0x4000 3C00 Reserved APB bus 0x4000 4400 USART2 APB bus 0x4000 4800 USART3 APB bus 0x4000 4C00 USART4 APB bus 0x4000 5000 USART5 APB bus 0x4000 5400 I2C1 APB bus 0x4000 5800 I2C2 APB bus 0x4000 5C00 Reserved APB bus 0x4000 7000 PMU APB bus 0x4000 7400 Reserved — 0x4000 8000 Reserved APB bus 0x4001 0000 SYSCFG APB bus 0x4001 0400 EINT APB bus 0x4001 0800 Reserved APB bus 0x4001 1400 USART6 APB bus 0x4001 1800 Reserved APB bus 0x4001 2400 ADC APB bus 0x4001 2800 Reserved APB bus 0x4001 2C00 TMR1 w w w. ge e h y. c o m P a ge 1 5 Region Start address Peripheral Name APB bus 0x4001 3000 SPI1 APB bus 0x4001 3400 Reserved APB bus 0x4001 3800 USART1 APB bus 0x4001 3C00 Reserved APB bus 0x4001 4000 TMR15 APB bus 0x4001 4400 TMR16 APB bus 0x4001 4800 TMR17 APB bus 0x4001 4C00 Reserved APB bus 0x4001 5800 DBGMCU APB bus 0x4001 5C00 Reserved — 0x4001 8000 Reserved AHB1 bus 0x4002 0000 DMA AHB1 bus 0x4002 0400 Reserved AHB1 bus 0x4002 1000 RCM AHB1 bus 0x4002 1400 Reserved AHB1 bus 0x4002 2000 Flash interface AHB1 bus 0x4002 2400 Reserved AHB1 bus 0x4002 3000 CRC AHB1 bus 0x4002 3400 Reserved — 0x4002 4400 Reserved AHB2 bus 0x4800 0000 GPIOA AHB2 bus 0x4800 0400 GPIOB AHB2 bus 0x4800 0800 GPIOC AHB2 bus 0x4800 0C00 GPIOD AHB2 bus 0x4800 1000 Reserved AHB2 bus 0x4800 1400 GPIOF — 0x4800 1800 Reserved Core 0xE000 E010 STK Core 0xE000 E100 NVIC Core 0xE000 ED00 SCB — 0xE010 0000 Reserved 4.1.3 Startup configuration At startup, the user can select one of the following three startup modes by setting the high and low levels of the Boot pin:  Startup from main memory  Startup from BootLoader  Startup from internal SRAM w w w. ge e h y. c o m P a ge 1 6 The user can use USART interface to reprogram the user Flash if boot from BootLoader. 4.2 Core The core of APM32F030xC is Arm® Cortex®-M0+. Based on this platform, the development cost is low and the power consumption is low. It can provide excellent computing performance and advanced system interrupt response, and is compatible with all Arm tools and software. 4.3 Interrupt controller 4.3.1 Nested Vector Interrupt Controller (NVIC) It embeds a nested vectored interrupt controller (NVIC) able to handle up to 32 maskable interrupt channels (not including16 interrupt lines of Cortex-M0+) and 4 priority levels. The interrupt vector entry address can be directly transmitted to the core, so that the interrupt response processing with low delay can give priority to the late higher priority interrupt. 4.3.2 External Interrupt/Event Controller (EINT) The external interrupt/event controller consists of 32 edge detectors, and each detector includes edge detection circuit and interrupt/event request generation circuit; each detector can be configured as rising edge trigger, falling edge trigger or both and can be masked independently. Up to 51 GPIOs can be connected to the 16 external interrupt lines. 4.4 On-chip memory On-chip memory includes main memory area, SRAM and information block; the information block includes system memory area and option byte; the system memory area stores BootLoader, 96-bit unique device ID and capacity information of main memory area; the system memory area has been written into the program and cannot be erased. Table 10 On-chip Memory Area Memory Main memory area SRAM System memory area Option byte 4.5 Maximum capacity Function 256 KB Store user programs and data 32 KB CPU can access at 0 waiting cycle (read/write) 8KB 16Bytes Store BootLoader, 96-bit unique device ID, and main memory area capacity information Configure main memory area read-write protection and MCU working mode Clock Clock tree of APM32F030xC is shown in the figure below: w w w. ge e h y. c o m P a ge 1 7 Figure 4 APM32F030xC Clock Tree HSICLK HSICLK I2C1/2 Flash program interface HSICLK SW HSICLK AHB/Core/ MemorIes/ DMA /Core AHBPSC HSICLK 8MHz OSC_OUT OSC_IN PLLMUL PLLCLK /1,2 ×2,×3 16 ×16 /2 HSECLK OSC 4-32MHz SYSCLK /1,2 /512 HCLK /8 /1,/2, /4,/8, /16 System Timer APB_CLK APBPSC HSECLK ×1,×2 HSECLK LSECLK LSICLK SYSCLK HSICLK LSECLK RTC /2,/4 OSC32_IN LSECLK OSC 32.768kHz LSICLK HSICLK14 RC 14MHz 4.5.1 Clock output ADC MCOPRE /1,2,4...128 HSICLK14 IWDT /1,2 MCO USART1 LSECLK LSICLK LSICLK 40kHz TMR1/3/6/ 7/14/15 /16/17 CSS /32 OSC32_OUT APB peripheral PLLCLK SYSCLK HSECLK HSICLK HSICLK14 LSICLK LSECLK Clock source Clock source is divided into high-speed clock and low-speed clock according to the speed; the high-speed clock includes HSICLK, HSECLK and HSICLK14, and the low-speed clock includes LSECLK and LSICLK; clock source is divided into internal clock and external clock according to the chip inside/outside; the internal clock includes HSICLK, LSICLK and HSICLK14, and the external clock includes HSECLK and LSECLK, among which HSICLK is calibrated by the factory to ±1% accuracy. 4.5.2 System clock HSICLK, PLLCLK and HSECLK can be selected as system clock; the clock source of PLLCLK can be HSICLK or HSECLK; the requirred system clock can be obtained by configuring PLL clock multiplier factor and frequency division factor. When the system is reset, HSICLK is selected as the system clock by default, and then the user can choose one of the above clock sources as the system clock by itself. When it detectes w w w. ge e h y. c o m P a ge 1 8 HSECLK is disabled, the system will automatically switch to the HSICLK, and if an interrupt is enabled, the software can receive the related interrupt. 4.5.3 Bus clock AHB, APB1 and ABP2 buses are built in. The clock source of AHB is SYSCLK and the clock source of APB1 and APB2 is HCLK; the required clock can be obtained by configuring the frequency division factor. 4.6 Reset and power management 4.6.1 Power supply scheme Table 11 Power Supply Scheme Name Voltage range VDD/VSS 2.0～3.6V Instruction I/Os (see pin distribution diagram for specific IO) and internal voltage regulator are powered through VDD pin. It supplies power to the ADC, reset module, RC oscillator and PLL analog part, VDDA/VSSA VDD～3.6V and the voltage level of VDDA must always be greater than or equal to the voltage level of VDD, which should be provided preferentially. 4.6.2 Voltage regulator Table 12 Regulator Operating Mode Name Instruction Master mode (MR) Used in run mode Low-power mode (LPR) Used in stop mode Used in standby mode, when the voltage regulator has high impedance output, the core Power-down mode circuit is powered down, the power consumption of the voltage regulator is zero, and all data of registers and SRAM will be lost. Note: The voltage regulator is always in working state after reset, and outputs with high impedance in power-down mode. 4.6.3 Power supply voltage monitor Power-on reset (POR) and power-down reset (PDR) circuits are integrated inside the product. These two circuits are always in working condition. When the power-down reset circuit monitors that the power supply voltage is lower than the specified threshold value (VPOR/PDR), even if the external reset circuit is used, the system will remain reset. 4.7 Low-power mode APM32F030xC supports three low-power modes, namely, sleep mode, stop mode and standby mode, and there are differences in power, wake-up time and wake-up mode among these three modes. The low-power mode can be selected according to the actual application requirements. w w w. ge e h y. c o m P a ge 1 9 Table 13 Low-power Mode Mode Instruction Sleep mode The core stops working, all peripherals are working, and it can be woken up through interrupts/events Under the condition that SRAM and register data are not lost, the stop mode can achieve the lowest power consumption; Stop mode The clock of the internal 1.5V power supply module will stop, HSECLK crystal resonator, HSICLK and PLL will be prohibited, and the voltage regulator can be configured in normal mode or low power mode; Any external interrupt line can wake up MCU, and the external interrupt lines include one of the 16 external interrupt lines, and RTC. The power consumption in this mode is the lowest; Internal voltage regulator is turned off, all 1.5V power supply modules are powered off, HSECLK crystal Standby mode resonator, HSICLK and PLL clocks are turned off, SRAM and register data disappear, RTC area and backup register contents remain, and standby circuit still works; The external reset signal on NRST, IWDT reset, rising edge on WKUP pin or RTC event will wake MCU out of standby mode. 4.8 DMA A built-in DMA, supporting 5 channels. Each channel supports multiple DMA requests, but only one DMA request is allowed to enter the DMA channel at the same time. The peripherals supporting DMA requests are ADC, SPI, USART, I2C, and TMRx. Four levels of DMA channel priority can be configured. Data transmission of "Memory → Memory, Memory → Peripheral, Peripheral → Memory" can be supported (memory includes Flash and SRAM). 4.9 GPIO GPIO can be configured as general input, general output, multiplexing function and analog input and output. The general input can be configured as floating input, pull-up input and pull-down input; the general output can be configured as push-pull output and open-drain output; the multiplexing function can be used for digital peripherals; and the analog input and output can be used for analog peripherals and low-power mode; the enable and disable pull-up/pull-down resistor can be configured; the speed of 2MHz, 10MHz and 50MHz can be configured; the higher the speed is, the greater the power and the noise will be. 4.10 Communication peripherals 4.10.1 USART Up to 6 general-purpose synchronous/asynchronous transmitter receivers are embedded in the chip, and the communication rate can support 6Mbit/s at most. All USART interfaces can be provided by DMA controller. The functions of USART interfaces are shown in the following table. w w w. ge e h y. c o m P a ge 2 0 Table 14 USART Function Differences USART mode Hardware flow control USART1 USART2 USART3 USART4 USART5 USART6 √ √ √ √ — — √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ — √ √ √ √ √ √ √ √ √ — — — 4 4 4 — — — Multi-buffer communication (DMA) Multi-processor communication Synchronous Half duplex (single-line mode) Receiving timeout interrupt Support the baud rate automatic detection mode Note: （1） "√" means this function is supported, while "—" means that this function is not supported. 4.10.2 I2C I2C1/2 can work in master mode and slave mode, and supports 7-bit and 10-bit addressing modes. I2C1/2 supports standard mode (up to 100kbit/s) or fast mode (up to 400kbit/s). In addition, I2C1 has built-in programmable analog and digital noise filters, and also supports ultra-fast mode (up to 1 Mbit/s). In addition, I2C1 also provides hardware support for SMBus 2.0 and PMBus 1.1: ARP function, master notification protocol, hardware CRC(PEC) generation/verification, timeout verification and alarm protocol management. I2C supports DMA function. 4.10.3 SPI 2 built-in SPIs, support full duplex and half duplex communication in master mode and slave mode, can use DMA controller, and can configure 4~16 bits per frame, and communicate at a rate of up to 18Mbit/s. 4.11 Analog peripherals 4.11.1 ADC 1 built-in ADC with 12-bit accuracy, up to 16 external channels and 2 internal channels for each ADC. The internal channels measure the temperature sensor voltage and reference voltage respectively. A/D conversion mode of each channel has single, continuous, scan or intermittent w w w. ge e h y. c o m P a ge 2 1 modes, ADC conversion results can be left aligned or right aligned and stored in 16-bit data register; they support analog watchdog, and DMA. 4.11.1.1 Temperature sensor A temperature sensor (TSensor) is built in, which is internally connected with ADC_IN16 channel. The voltage generated by the sensor changes linearly with temperature, and the converted voltage value can be obtained by ADC and converted into temperature. 4.11.1.2 Internal reference voltage Built-in reference voltage VREFINT, internally connected to ADC_IN17 channel, which can be obtained through ADC; VREFINT provides stable voltage output for ADC. 4.12 Timer A built-in 16-bit advanced timer (TMR1), 5 general-purpose timers (TMR3/14/15/16/17), two basic timers (TMR6/7), an independent watchdog timer, a window watchdog timer and a system tick timer. Watchdog timer can be used to detect whether the program is running normally. The system tick timer is the peripheral of the core with automatic reloading function. When the counter is 0, it can generate a maskable system interrupt, which can be used for real-time operating system and general delay. Table 15 Function Comparison between Advanced/General-purpose/Basic and System Tick Timers Timer type Timer name System tick Sys Tick Timer Counter resolution Counter type TMR7 TMR3 Advanced timer TMR1 TMR1 TMR1 TMR1 4 5 6 7 TMR1 16 bits 16 bits 16 bits Down Up Up, down, up/down Up, down, up/down - between 1 and Any integer factor Any integer between 1 Any integer between 1 and 65536 and 65536 65536 General DMA request Capture/Comp arison channel Complementar y outputs Instruction TMR6 General-purpose timer 24 bits Prescaler Function Basic timer timer - OK OK - - 4 - No No Special for realtime system w w w. ge e h y. c o m operating Not OK OK OK OK 1 2 1 1 4 No Yes Yes Yes Yes OK Can be used as Synchronization a function provided 16-bit or event chaining general- Timers in debug mode can be frozen. purpose -Can be used to generate PWM output It has complementary PWM output with dead band insertion P a ge 2 2 System tick Timer type Basic timer timer General-purpose timer Automatic timebase Except reloading function counter. independent DMA request mechanism. bit standard timer, it has It can handle incremental encoder signals the same function as the supported TMR14, each timer Advanced timer has When configured as a 16- When the counter TMRx timer. is can When configured as a 16- a bit PWM generator, it has 0, it generate maskable system full modulation capability interrupt (0~100%). Can program the In debug mode, the timer clock source can be frozen, and PWM output is disabled. Synchronization or event chaining function provided. Table 16 Independent Watchdog and Window Watchdog Timers Name Counter Counter Prescaler resolution type factor Functional Description The clock is provided by an internally independent RC oscillator of 40KHz, which is independent of the master clock, so it can run in stop and standby modes. Independent watchdog 12-bit Down Any integer The whole system can be reset in case of problems. between 1 It can provide timeout management for applications as a and 256 free-running timer. It can be configured as a software or hardware startup watchdog through option bytes. Timers in debug mode can be frozen. Can be set for free running. Window watchdog The whole system can be reset in case of problems. 7-bit Down - Driven by the master clock, it has early interrupt warning function; Timers in debug mode can be frozen. 4.13 RTC A built-in RTC with LSECLK signal input pins (OSC32_IN, OSC32_OUT), 2 TAMP input signal detection pins (RTC_TAMP1/2), one reference clock input signal (RTC_REFIN), one output timestamp event output pin (RTC_TS), and one signal output pin RTC_OUT (it can be configured as calibration signal output or alarm clock signal output). The external crystal oscillator, resonator or oscillator, LSICLK and HSECLK/32 with external frequency of 32.768kHz can be selected as the clock source. w w w. ge e h y. c o m P a ge 2 3 With calendar function, it can display sub-seconds, seconds, minutes, hours (12 or 24 hours format), weeks, dates, months and years. It supports alarm clock function, and can output the alarm clock signal for external use, and wake up from low power consumption mode. It can receive signals to wake up from low power consumption mode. In terms of accuracy, it supports daylight saving time compensation, month angel compensation and leap year days compensation. In terms of precision, the error caused by crystal oscillator can be repaired by RTC digital calibration function, and the accuracy of calendar can be improved by using a more accurate second source clock (50 or 60Hz). 4.14 CRC A CRC (cyclic redundancy check) calculation unit is built in, which can generate CRC codes and operate 8-bit, 16-bit and 32-bit data. w w w. ge e h y. c o m P a ge 2 4 5 Electrical characteristics 5.1 Test conditions of electrical characteristics 5.1.1 Maximum and minimum values Unless otherwise specified, all products are tested on the production line at TA=25℃. Its maximum and minimum values can support the worst environmental temperature, power supply voltage and clock frequency. In the notes at the bottom of each table, it is stated that the data are obtained through comprehensive evaluation, design simulation or process characteristics and are not tested on the production line; on the basis of comprehensive evaluation, after passing the sample test, take the average value and add and subtract three times the standard deviation (average ±3∑) to get the maximum and minimum values. 5.1.2 Typical values Unless otherwise specified, typical data are measured based on TA=25℃, VDD=VDDA=3.3V. these data are only used for design guidance. 5.1.3 Typical curve Unless otherwise specified, typical curves will only be used for design guidance and will not be tested. w w w. ge e h y. c o m P a ge 2 5 5.1.4 Power supply scheme Figure 5 Power Supply Scheme MCU LSECLK、RTC、 Backup register VSS VDD 4×V DD 4×100nF +4.7μF Input schmitt trigger. Output buffer Core Flash SRAM 1/0 logic Digital peripheral Voltage regulator Input schmitt trigger Output buffer VDDA VDDA RC oscillator Analog peripherals 10nF+ 1μF VSSA VREF+ 5.1.5 ADC VREF- Load capacitance Figure 6 Load conditions when measuring pin parameters MCU pin c=50p w w w. ge e h y. c o m P a ge 2 6 Figure 7 Pin Input Voltage Measurement Scheme MCU pin VIN Figure 8 Power Consumption Measurement Scheme VDD MCU IDD A VDDX VSS IDDA A VDDA VSSA 5.2 Test under general operating conditions Table 17 General Operating Conditions Minimum Maximum value value - - 48 Internal APB1 clock frequency - - 48 Main power supply voltage - 2 3.6 VDD 3.6 Symbol Parameter Conditions fHCLK Internal AHB clock frequency fPCLK1 VDD Unit MHz Analog power supply voltage VDDA (When ADC is not used) Must be the Analog power supply voltage same as VDD (When ADC is used) TA w w w. ge e h y. c o m Ambient temperature (temperature Maximum power number 6) dissipation Ambient temperature (temperature Maximum power number 7) dissipation V V 2.4 3.6 -40 85 ℃ -40 105 ℃ P a ge 2 7 5.3 Absolute maximum ratings If the load on the device exceeds the absolute maximum rating, it may cause permanent damage to the device. Here, only the maximum load that can be borne is given, and there is no guarantee that the device functions normally under this condition. 5.3.1 Maximum temperature characteristics Table 18 Temperature Characteristics Symbol Description Numerical Value Unit TSTG Storage temperature range -55 ~ +150 ℃ TJ Maximum junction temperature 150 ℃ 5.3.2 Maximum rated voltage characteristics All power supply (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the power supply within the external limited range. Table 19 Maximum Rated Voltage Characteristics Minimum Maximum value value External main power supply voltage -0.3 4.0 VDDA-VSSA External analog power supply voltage -0.3 4.0 VDD-VDDA Voltage difference allowed by VDD>VDDA - 0.3 Input voltage on FT pins VSS-0.3 VDD+4.0 Input voltage on 3.3V pin VSS-0.3 4.0 Input voltage on other pins VSS-0.3 4.0 - 50 Symbol Description VDD - VSS Unit V VIN | ΔVDDx | | VSSx-VSS | Voltage difference between different power supply pins Voltage difference between different grounding pins mV - 50 5.3.3 Maximum rated current features 表格 20 Maximum Rated Current Features Symbol Description Maximum ΣIVDD Total current into sum of all VDD power lines (source)(1) 120 ΣIVSS Total current out of sum of all VSS ground lines (sink)(1) -120 IVDD（PIN） Maximum current into each VDD power pin (source)(1) 100 IVSS（PIN） Maximum current out of each VSS ground pin (sink)(1) -100 Output current sunk by any I/O and control pin 25 Output current source by any I/O and control pin -25 Unit mA IIO（PIN） w w w. ge e h y. c o m P a ge 2 8 Symbol Description Maximum Total output current sunk by sum of all I/Os and control pins (2) 80 Total output current sourced by sum of all I/Os and control pins (2) -80 Unit ΣIIO（PIN） Injected current on 5T and 5Tf pins IINJ(PIN) (3) ΣIINJ(PIN) -5/+0 （4） Injected current on STD and RST pin ±5 Injected current on STDA pins(5) ±5 Total injection current on all I/O and control pins (4) ±25 （1） All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. （2） This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. （3） A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. （4） Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. （5） On these I/Os, a positive injection is induced by VIN > VDDA. Negative injection disturbs the analog performance of the device. （6） When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values) 5.3.4 ESD characteristics Table 21 ESD Characteristics Symbol VESD(HBM) VESD(CDM) Parameter Electrostatic discharge voltage (human body model) Electrostatic discharge voltage (charging device model) Conditions TA=+25℃ Maximum value Unit 6000 V TA=+25℃ 2000 Note: The samples are measured by a third-party testing organization and are not tested in production. 5.3.5 Static latch-up Table 22 Static Latch-up Symbol Parameter Conditions Type LU Class of static latch-up TA=+25℃/105℃ Class II-A Note: The samples are measured by a third-party testing organization and are not tested in production. w w w. ge e h y. c o m P a ge 2 9 5.4 On-chip memory 5.4.1 Flash characteristics Table 23 Flash Memory Characteristics Symbol Parameter tprog 16-bit programming time tERASE Conditions Minimum Typical Maximum value values value - 48 - μs - 3 - ms - 12 - ms 2 - 3.6 V TA = -40~105℃ VDD=2.4~3.6V Page (2KBytes) erase TA = -40~105℃ time VDD=2.4~3.6V TA = 25℃ tME Whole erase time Vprog Programming voltage VDD=3.3V TA = -40~105℃ Unit Note: It is obtained from a comprehensive evaluation and is not tested in production. 5.5 Clock 5.5.1 Characteristics of external clock source High-speed external clock generated by crystal resonator For detailed parameters (frequency, package, precision, etc.) of crystal resonator, please consult the corresponding manufacturer. Table 24 HSECLK4~32MHz Oscillator Characteristics Symbol fOSC_IN Parameter Oscillator frequency Feedback RF resistance IDD(HSECLK) tSU(HSECLK) Minimum Typical Maximum value values value - 4 8 32 MHz - - 300 - kΩ - 0.29 - mA - 2 - ms Conditions HSECLK current VDD=3.3V, consumption CL=10pF@8MHz Startup time VDD is stable Unit Note: It is obtained from a comprehensive evaluation and is not tested in production. Low-speed external clock generated by crystal resonator For detailed parameters (frequency, package, precision, etc.) of crystal resonator, please consult the corresponding manufacturer. w w w. ge e h y. c o m P a ge 3 0 Table 25 LSECLK Oscillator Characteristics (fLSECLK=32.768KHz) Symbol fOSF_IN tSU(LSECLK)(1) IDD(LSECLK) Parameter Minimum Typical Maximum value values value - - 32.768 - KHz VDDIOx is stable - 2 - s - - 0.9 - μA Conditions Oscillator frequency Startup time LSECLK current consumption Unit Note: It is obtained from a comprehensive evaluation and is not tested in production. （1） tSU(HXT) is the startup time, which is measured from the time when LSECLK is enabled by software to the time when stable oscillation at 32.768KHz is obtained. This value is measured using a standard crystal resonator, which may vary greatly due to different crystal manufacturers. 5.5.2 Characteristics of internal clock source High speed internal (HSICLK) RC oscillator Table 26 HSICLK Oscillator Characteristics Minimu Symbol Parameter Conditions m value fHSICLK ACCHSICLK Frequency - IDDA(HSICLK) Unit value - MHz -1 - 1 % -3 - 3 % VDD=3.3V，TA=-40~105℃ 1 - 2 μs - - 80 100 μA Factory oscillator calibration HSICLK oscillator um 8 Accuracy of HSICLK Startup time of values Maxim - VDD=3.3V，TA=25℃(1) VDD=2-3.6V，TA=40~105℃ tSU(HSICLK) Typical Power consumption of HSICLK oscillator Note: (1) Except for calibration in production, other data are obtained from a comprehensive evaluation and is not tested in production. 14MHz high speed internal (HSICLK14) RC oscillator Table 27 HSICLK14 Oscillator Characteristics Symbol fHSICLK ACCHSICLK Parameter Conditions Frequency - Accuracy of HSICLK Factory oscillator calibration VDD=3.3V，TA=25℃(1) VDD=2-3.6V， TA=-40~105℃ w w w. ge e h y. c o m Maxim Minimu Typical m value values - 14 - MHz -1 - 1 % -3 - 3 % um Unit value P a ge 3 1 Symbol Typical m value values VDD=3.3V，TA=-40~105℃ 1 - 2 μs - - 100 150 μA Parameter Conditions Startup time of tSU(HSICLK) HSICLK oscillator Power consumption IDDA(HSICLK) Maxim Minimu of HSICLK oscillator um Unit value Note: (1) Except for calibration in production, other data are obtained from a comprehensive evaluation and is not tested in production. Low speed internal (LSICLK) RC oscillator Table 28 LSICLK Oscillator Characteristics Symbol Minim Typica Maxim um l um value values value Parameter Unit fLSICLK Frequency (VDD =2-3.6V, TA =-40~105℃) 30 40 50 KHz tSU(LSICLK) LSICLK oscillator startup time, (VDD=3.3V, TA=-40~105℃) - - 96 μs IDD(LSICLK) Power consumption of LSICLK oscillator - 0.75 - μA Note: It is obtained from a comprehensive evaluation and is not tested in production. PLL Characteristics 5.5.3 Table 29 PLL Characteristics Numerical Value Symbol Parameter Unit Minimum Typical Maximum value values value PLL input clock 1 8.0 24 MHz PLL input clock duty cycle 40 - 60 % 16 - 48 MHz - - 200 μs fPLL_IN fPLL_OUT PLL frequency doubling output clock, (VDD=3.3V, TA=40~125℃) tLOCK PLL phase locking time Note: It is obtained from a comprehensive evaluation and is not tested in production. 5.6 Reset and power management 5.6.1 Test of Embedded Reset and Power Control Block Characteristics Table 30 Embedded Reset and Power Control Block Characteristics Symbol Parameter Conditions VPOR/PDR Power-on/power-down Falling edge w w w. ge e h y. c o m Minimum Typical Maximum value values value 1.89 1.92 1.95 Unit V P a ge 3 2 Symbol Minimum Typical Maximum value values value Rising edge 1.92 1.95 1.98 V PDR hysteresis - 20.00 30.00 40.00 mV Reset duration - 1.10 1.29 1.52 ms Parameter Conditions reset threshold VPDRhyst TRSTTEMPO Unit Note: It is obtained from a comprehensive evaluation and is not tested in production. 5.7 Power consumption 5.7.1 Power consumption test environment （1） The values are measured by executing Coremark, with the Keil.V5 compilation environment and the L3 compilation optimization level. （2） All I/O pins are configured as analog inputs and are connected to a static level of VDD or VSS (non-loaded) （3） Unless otherwise specified, all peripherals are turned off （4） The relationship between Flash waiting cycle setting and fHCLK : 0~24MHz: 0 waiting cycle 24~48MHz: 1 waiting cycle （5） The instruction prefetch function is enabled (Note: it must be set before clock setting and bus frequency division) （6） When the peripherals are enabled: fPCLK =fHCLK 5.7.2 Power consumption in run mode Table 31 Power Consumption in Run Mode when the Program is Executed in Flash Parameter Conditions HSECLK bypass (2) , enabling all peripherals Power fHCLK Typical value (1) Maximum value (1) TA=25℃，VDD=3.3V TA=105℃，VDD=3.6V IDDA(μA) IDD(mA） IDDA(μA) IDD(mA) 48MHz 103.09 14.51 116.07 15.11 32MHz 71.88 10.05 83.44 10.50 24MHz 58.02 7.93 69.07 8.44 8MHz 2.17 3.17 7.35 3.64 1MHz 2.17 1.94 7.17 2.78 48MHz 103.07 8.99 116.02 9.30 32MHz 71.85 6.23 83.42 6.58 24MHz 58.04 5.07 69.02 5.56 8MHz 2.17 2.25 7.28 2.65 1MHz 2.17 1.82 7.23 2.68 consumption in run mode HSECLK bypass (2) , turning off all peripherals w w w. ge e h y. c o m P a ge 3 3 Parameter Conditions HSICLK (2) , enabling all peripherals HSICLK (2) , turning off all peripherals fHCLK Typical value (1) Maximum value (1) TA=25℃，VDD=3.3V TA=105℃，VDD=3.6V IDDA(μA) IDD(mA） IDDA(μA) IDD(mA) 48MHz 165.36 14.52 182.74 14.78 32MHz 134.37 9.97 150.34 10.28 24MHz 120.54 7.87 135.75 8.13 8MHz 64.98 3.12 76.50 3.36 48MHz 165.40 8.89 182.68 9.01 32MHz 134.36 6.18 150.14 6.44 24MHz 120.55 5.00 135.79 5.25 8MHz 64.99 2.16 76.34 2.44 Note: (1) It is obtained from a comprehensive evaluation and is not tested in production. (2) The external clock is 8MHz, and when fHCLK>8MHz, turn on PLL, otherwise, turn off PLL. Table 32 Power Consumption in Run Mode when the Program is Executed in RAM Parameter Conditions HSECLK bypass (2) , enabling all peripherals Power HSECLK bypass (2) , turning off all consumption peripherals in run mode HSICLK (2) , enabling all peripherals HSICLK (2) , turning off all peripherals w w w. ge e h y. c o m fHCLK Typical value (1) Maximum value (1) TA=25℃，VDD=3.3V TA=105℃，VDD=3.6V IDDA(μA) IDD(mA） IDDA(μA) IDD(mA) 48MHz 103.16 12.36 12.51 12.82 32MHz 71.93 8.52 8.77 8.74 24MHz 58.01 6.62 6.75 6.91 8MHz 2.17 2.70 2.89 2.93 1MHz 2.17 0.98 1.14 1.18 48MHz 102.49 6.75 7.07 6.97 32MHz 71.34 4.79 5.08 4.98 24MHz 57.36 3.72 3.99 4.01 8MHz 2.33 1.77 1.99 1.96 1MHz 2.33 086 1.07 1.07 48MHz 165.37 12.37 12.82 12.86 32MHz 134.37 8.57 8.93 8.90 24MHz 120.52 6.66 6.96 6.84 8MHz 64.98 2.77 3.00 3.04 48MHz 164.62 6.74 7.05 7.03 32MHz 134.35 4.81 5.05 4.99 P a ge 3 4 Parameter Conditions fHCLK Typical value (1) Maximum value (1) TA=25℃，VDD=3.3V TA=105℃，VDD=3.6V IDDA(μA) IDD(mA） IDDA(μA) IDD(mA) 24MHz 120.50 3.76 4.03 4.05 8MHz 64.35 1.84 2.02 2.01 Note: (1) It is obtained from a comprehensive evaluation and is not tested in production. (2) The external clock is 8MHz, and when fHCLK>8MHz, turn on PLL, otherwise, turn off PLL. 5.7.3 Power consumption in sleep mode Table 33 Power Consumption in Sleep Mode when the Program RAM is Executed in Flash Parameter Conditions HSECLK bypass (2) , enabling all peripherals HSECLK bypass (2) , turning off all Sleep mode peripherals Power consumption HSICLK (2) , enabling all peripherals HSICLK (2) , turning off all peripherals fHCLK Typical value (1) Maximum value (1) TA=25℃，VDD=3.3V TA=105℃，VDD=3.6V IDDA(μA) IDD(mA） IDDA(μA) IDD(mA) 48MHz 103.14 9.31 116.13 9.7 32MHz 71.93 6.52 83.37 6.96 24MHz 58.00 5.09 69.03 5.59 8MHz 2.17 2.25 7.23 2.65 1MHz 2.17 1.82 7.22 1.12 48MHz 103.13 2.39 115.96 2.79 32MHz 71.89 1.90 83.17 2.33 24MHz 57.99 1.65 68.91 2.09 8MHz 2.17 1.10 7.13 1.53 1MHz 2.16 0.72 7.12 0.97 48MHz 165.34 9.25 182.73 9.59 32MHz 134.36 6.47 150.16 6.77 24MHz 120.50 5.03 135.52 5.33 8MHz 64.98 2.21 75.37 2.48 48MHz 165.34 2.29 182.58 2.56 32MHz 134.39 1.80 150.09 2.08 24MHz 120.51 1.55 135.39 1.82 8MHz 64.99 1.02 75.68 1.29 Note: (1) It is obtained from a comprehensive evaluation and is not tested in production. (2) The external clock is 8MHz, and when fHCLK>8MHz, turn on PLL, otherwise, turn off PLL. w w w. ge e h y. c o m P a ge 3 5 5.7.4 Power consumption in stop mode and standby mode Table 34 Power Consumption in Stop Mode and Standby Mode Typical value (1), (TA=25℃) Parameter Conditions Regulator in run mode, all Power oscillators OFF consumption in stop mode Power Regulator in low-power mode, all VDD=2.0V VDD=3.3V Maximum value (1), (VDD=3.6V) VDD=3.6V TA=85℃ TA=105℃ IDDA IDD IDDA IDD IDDA IDD IDDA IDD IDDA IDD 2.55 22.78 3.03 23.43 3.25 23.96 4.84 79.63 7.57 165.32 2.50 8.53 3.02 9.24 3.25 9.73 4.80 61.51 7.54 142.50 VDDA oscillators OFF Monitor ON LSICLK and IWDT ON 2.70 1.72 3.40 2.62 3.70 3.18 5.21 7.18 7.65 14.37 LSICLK and IWDT OFF 2.37 1.43 2.90 2.25 3.13 2.69 4.66 6.66 7.11 13.88 Unit consumption in standby mode Regulator in run mode, all Power oscillators OFF consumption in stop mode Power Regulator in low-power mode, all μA 1.35 22.73 1.53 23.62 1.64 24.05 3.16 79.76 5.95 165.3 1.35 8.50 1.52 9.35 1.63 9.77 3.14 61.66 5.88 143.7 VDDA oscillators OFF Monitor OFF LSICLK and IWDT ON 1.55 1.71 1.90 2.75 2.06 3.23 3.54 7.23 6.01 14.46 LSICLK and IWDT OFF 1.22 1.42 1.40 23.00 1.51 2.74 2.99 6.74 5.46 13.89 consumption in standby mode Note: (1) It is obtained from a comprehensive evaluation and is not tested in production. www.geehy.com Page 36 5.7.5 Peripheral power consumption The HSECLK Bypass 1M is adopted as clock source, fPCLK=fHCLK=1M. Peripheral power consumption = current that enables the peripheral clock-current that disables the peripheral clock. Table 35 Peripheral Power Consumption Parameter Peripheral power consumption w w w . g e e h y. c o m Peripheral Typical value (1) TA =25℃, VDD =3.3V BusMatrix 1.12 CRC 0.70 DMA 2.25 FLASH 23.75 GPIOA 2.25 GPIOB 2.12 GPIOC 0.87 GPIOD 0.79 GPIOF 0.71 SRAM 0.25 ALL_AHB 41.04 APB_Bridge 1.00 ADC 3.00 CAN 6.62 DAC 2.46 DBGMCU 0.25 I2C1 7.54 I2C2 1.87 PMU 0.91 SPI1 4.91 SPI2 4.5 SYSCFG 1.08 TMR1 6.95 TMR3 5.20 TMR6 1.41 TMR7 1.33 TMR14 2.70 Unit μA/MHz Page 37 Parameter Peripheral Typical value (1) TA =25℃, VDD =3.3V TMR15 4.20 TMR16 3.20 TMR17 3.58 USART1 9.08 USART2 9.10 USART3 9.04 USART4 3.2 ALL_APB 114.62 Unit Note: It is obtained from a comprehensive evaluation and is not tested in production. 5.8 Wake-up time in low power mode The measurement of wake-up time in low power mode is from the start of wake-up event to the time when the user program reads the first instruction, in which VDD=VDDA. Table 36 Wake Up Time in Low-power Mode Typical value (TA=25℃) Symbol tWUSLEEP Parameter Conditions Wake-up from - sleep mode The voltage regulator is in tWUSTOP Wake up from stop run mode mode The voltage regulator is in Wake up from - standby mode 2V 3.3V 3.6V value 0.15 0.15 0.15 0.17 3..45 3.09 3.02 3.89 Unit μs low power mode tWUSTDBY Maximum 8.15 5.43 5.14 9.72 46.65 37.15 35.93 53.80 Note: It is obtained from a comprehensive evaluation and is not tested in production. 5.9 Pin characteristics 5.9.1 I/O pin characteristics Table 37 DC Characteristics (test condition of VDD =2.7~3.6V, TA =-40~105℃) Symbol VIL Parameter Low level input voltage Conditions Minimum value Typical values Maximum value STD and STDA I/O - - 0.3VDDIOx+0.07 5T and 5Tf I/O - - 0.475VDDIOx -0.2 - - 0.3VDDIOx I/O pins except Boot0 pin w w w. ge e h y. c o m Unit V P a ge 3 8 Symbol VIH Parameter High level input voltage Conditions Minimum value Typical values Maximum value STD and STDA I/O 0.445VDDIOx +0.398 - - 5T and 5Tf I/O 0.5VDDIOx +0.2 - - 0.7VDDIOx - - I/O pins except Boot0 pin Vhys Unit V Schmitt trigger STD and STDA I/O - 300 - hysteresis 5T and 5Tf I/O - 300 - - - +0.1 - - 1 - - 10 VIN=VSS 22 42 46 kΩ VIN=VDDIOx 22 42 46 kΩ mV STD, 5T and 5Tf I/OTTa in digital mode, Ilkg Input leakage current VSS≤VIN≤VDDIOx STDA in digital mode, VDDIOx≤VIN≤VDDA 5T and 5Tf I/O VDDIOx≤VIN≤5V μA Weak pull-up RPU equivalent resistance Weak pull-down RPD equivalent resistance Note: It is obtained from a comprehensive evaluation and is not tested in production. Table 38 AC Characteristics (TA =25℃) OSSELy[1:0] X0(2MHz) Symbol Parameter fmax(IO)out Maximum frequency tf(IO)out Output fall time from high to Conditions CL=50pF, low level Minimum Maximum value value - 2 - 18.16 VDDIOX=2~3.6V tr(IO)out fmax(IO)out 01(10MHz) tf(IO)out Output rise time from low to high level Maximum frequency Output fall time from high to CL=50pF, low level tr(IO)out fmax(IO)out 10(50MHz) tf(IO)out w w w. ge e h y. c o m high level Maximum frequency Output fall time from high to low level CL=30pF, VDD=2.7~3.6V MHz ns - 16.66 - 10 - 11.50 VDDIOX=2~3.6V Output rise time from low to Unit MHz ns - 11.14 - 50 MHz - 3.58 ns P a ge 3 9 OSSELy[1:0] Symbol Parameter Conditions Minimum Maximum value value - 8.06 - 2 - 11 - 33 - 0.5 - 14 - 43 Output rise time from low to tr(IO)out high level fmax(IO)out Maximum frequency Unit MHz CL=50pF， FM+ tf(IO)out configuration Output fall time VDDIOx≥2V tr(IO)out Output rise time fmax(IO)out Maximum frequency ns MHz CL=50pF， FM+ tf(IO)out configuration Output fall time VDDIOx