ES7201

ES7201 High Performance PDM Stereo Audio ADC FEATURES • • • • • • APPLICATIONS High performance advanced deltasigma audio ADC 90 dB dynamic range at 26 dB PGA -85 dB THD+N Low noise PGA 8 to 96 kHz sampling frequency Low power • • • • • • • Mic Array Soundbar Audio Interface Digital TV A/V Receiver DVR NVR ORDERING INFORMATION ES7201 -40°C ~ +85°C QFN-12 BLOCK DIAGRAM AINLP/AINLN AINRP/AINRN PGA Advanced Delta-sigma Modulator Clock Manager Reset RESETb 1 PDM Data Interface DATA CLOCK Everest Semiconductor 1. 2. 3. Confidential ES7201 PIN OUT AND DESCRIPTION ................................................................................................ 3 TYPICAL APPLICATION CIRCUIT.......................................................................................... 4 ELECTRICAL CHARACTERISTICS ....................................................................................... 4 ABSOLUTE MAXIMUM RATINGS.................................................................................................. 4 RECOMMENDED OPERATING CONDITIONS ................................................................................ 4 ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS .......................................... 5 DC CHARACTERISTICS .................................................................................................................. 5 PDM DATA SWITCHING SPECIFICATIONS .................................................................................... 5 4. 5. 6. PACKAGE ................................................................................................................................ 6 CORPORATE INFORMATION ................................................................................................ 7 IMPORTANT NOTICE AND DISCLAIMER.............................................................................. 7 Revision 3.0 2 October 2020 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7201 1. PIN OUT AND DESCRIPTION AINLN AINLP REFQ 10 11 12 RESETb DATA CLOCK 1 2 3 ES7201 9 VDD 8 GND 7 REFP 6 5 4 AINRN AINRP VOLT Pin Name Pin number Input or Output VOLT 4 I AINLP, AINLN AINRP, AINRN VDD, GND REFP REFQ 11,10 5, 6 9, 8 7 12 I I I O O DATA, CLOCK RESETb Revision 3.0 2, 3 1 O, I I Pin Description PDM clock and data Active low reset High: VDD = 3.3V Low: VDD = 1.8V Analog left inputs Analog right inputs Power supply Filtering capacitor connection Filtering capacitor connection 3 October 2020 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7201 2. TYPICAL APPLICATION CIRCUIT The filter capacitors on REFP and REFQ pins must be located as close to ES7201 package as possible. 4.7uF or 10uF capacitor is for better audio performance. U2 OUT+ VDD_MIC VCC 1uF AGND MEMS MIC 1uF OUT- GND 1uF VDD (1.8V TO 3.3V) 13 REFQ AINLP AINLN 1uF PDM_DATA PDM_CLK 1 2 3 33pF AGND One 33pF capacitor is recommended for PDM_CLK 10K 9 8 7 100nF VOLT AINRP AINRN VDD (1.8V TO 3.3V) VDD (1.8V TO 3.3V) VDD GND REFP RESETb DATA CLO CK ES7201 1uF AGND 4 5 6 AGND AGND PAD U1 12 11 10 AGND 10K VOL_SET AGND U3 NC/10K OUT+ VCC 1uF 1uF MEMS MIC OUT- AGND GND For 3.3V VDD, PIN4 VOLT must be high level For 1.8V VDD, PIN4 VOLT must be low level AGND 3. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Continuous operation at or beyond these conditions may permanently damage the device. PARAMETER Supply Voltage Level Analog Input Voltage Range Digital Input Voltage Range Operating Temperature Range Storage Temperature MIN -0.3V GND-0.3V GND-0.3V -40°C -65°C MAX +3.6V VDD+0.3V VDD+0.3V +85°C +150°C RECOMMENDED OPERATING CONDITIONS PARAMETER VDD Revision 3.0 MIN 1.7 TYP 1.8/3.3 MAX 3.6 UNIT V 4 October 2020 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7201 ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: VDD=3.3V, GND=0V, ambient temperature=25°C, CLOCK=6.144 MHz. PARAMETER ADC Performance Dynamic Range (A-weigh, 26 dB PGA) THD+N (26 dB PGA) Channel Separation (1KHz) Interchannel Gain Mismatch Gain Error Analog Input Full Scale Input Level Input Impedance MIN TYP MAX UNIT 87 -88 97 90 -85 100 0.1 93 -82 103 dB dB dB dB % ±5 ±0.0708*VDD/3.3 9.6 (23 dB PGA) Vrms KΩ DC CHARACTERISTICS PARAMETER Normal Operation Mode VDD=3.3V (16 kHz) VDD=1.8V (16 kHz) Power Down Mode Digital Voltage Level Input High-level Voltage Input Low-level Voltage Output High-level Voltage Output Low-level Voltage MIN TYP MAX UNIT 22 4.6 0 0.7*VDD VDD 0 mW uA V V V V 0.5 PDM DATA SWITCHING SPECIFICATIONS PARAMETER CLOCK frequency CLOCK duty cycle Symbol ≤ 3.072 MHz DATA valid VDDD=3.3V VDDD=1.8V VDDD=3.3V VDDD=1.8V DATA hold THOLD TVALID THOLD MIN 0.512 40 45 11 19 10 18 MAX 6.144 60 55 27 61 26 56 UNIT MHz % ns ns THOLD CLOCK TVALID TVALID DATA Figure 1 PDM Data Timing Revision 3.0 5 October 2020 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7201 4. PACKAGE (UNIT: MM) Revision 3.0 6 October 2020 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7201 5. CORPORATE INFORMATION Everest Semiconductor Co., Ltd. No. 1355 Jinjihu Drive, Suzhou Industrial Park, Jiangsu, P.R. China, Zip Code 215021 苏州工业园区金鸡湖大道 1355 号国际科技园, 邮编 215021 Email: info@everest-semi.com 6. IMPORTANT NOTICE AND DISCLAIMER Everest Semiconductor publishes reliable technical information about its products. Information contained herein is subject to change without notice. It may be used by a party at their own discretion and risk. Everest Semiconductor disclaims responsibility for any claims, damages, costs, losses, and liabilities arising out of your use of the information. This publication is not to be taken as a license to operate under any existing patents and intellectual properties. Revision 3.0 7 October 2020 Latest datasheet: www.everest-semi.com or info@everest-semi.com