ES7202

ES7202 High Performance PDM Stereo Audio ADC FEATURES • • • • • • APPLICATIONS High performance advanced deltasigma audio ADC Dynamic range: 95 dB @ 0 dB PGA, 91 dB @ 23 dB PGA, 86 dB @ 32 dB PGA -88 dB THD+N Low noise PGA 8 to 96 kHz sampling frequency Low power • • • • • • • Mic Array Soundbar Audio Interface Digital TV A/V Receiver DVR NVR ORDERING INFORMATION ES7202 -40°C ~ +85°C QFN-16 BLOCK DIAGRAM AINLP/AINLN AINRP/AINRN PGA Advanced Delta-sigma Modulator PDM Data Interface I2C Interface Clock Manager Reset RESETb CCLK CDATA AD0 AD1 AD2 1 DATA CLOCK Everest Semiconductor Confidential ES7202 1. PIN OUT AND DESCRIPTION AINLN AINLP CDATA CCLK 13 14 15 16 RESETb DATA CLOCK AD0 1 2 3 4 ES7202 12 11 10 9 REFQ VDD GND REFP 8 7 6 5 AINRN AINRP AD2 AD1 Pin Name CCLK, CDATA AD0, AD1, AD2 CLOCK, DATA RESETb AINLP, AINLN AINRP, AINRN VDD, GND REFP REFQ Revision 4.1 Pin number 16, 15 4, 5, 6 3, 2 1 14, 13 7, 8 11, 10 9 12 Input or Output I, I/O I I, O I I I I O O Pin Description I2C clock and data I2C addresses PDM clock and data Active low reset Analog left inputs Analog right inputs Power supply Filtering capacitor connection Filtering capacitor connection 2 January 2022 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7202 2. TYPICAL APPLICATION CIRCUIT The filter capacitors on REFP and REFQ pins must be located as close to ES7202 package as possible. 4.7uF or 10uF capacitor is for better audio performance. VDD (1.8V TO 3.3V) U5 OUT+ 2K 1uF VDD_MIC VCC MEMS MIC 1uF 2K OUTI2C SDA I2C SCL GND AGND AGND VDD (1.8V TO 3.3V) AGND 1 2 3 4 33pF VDD (1.8V TO 3.3V) ES7202 17 VDD (1.8V TO 3.3V) 1uF 1uF AGND 5 6 7 8 One 33pF capacitor is recommended for PDM_CLK REFQ VDD GND REFP RESETb DATA CLO CK AD0 1uF 12 11 10 9 AD1 AD2 AINRP AINRN PDM_DATA PDM_CLK CCLK CDATA AINLP AINLN U4 PAD 1uF 16 15 14 13 10K 10K/NC 10K/NC U6 AGND AGND 10K/NC OUT+ VCC 1uF 1uF MEMS MIC OUT- NC/10K NC/10K AGND NC/10K AD2 AD1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 AD0 0 1 0 1 0 1 0 1 GND AGND I2C CHIP ADDRESS 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 (7bit) (7bit) (7bit) (7bit) (7bit) (7bit) (7bit) (7bit) / / / / / / / / 0x60 0x62 0x64 0x66 0x68 0x6a 0x6c 0x6e (8bit) (8bit) (8bit) (8bit) (8bit) (8bit) (8bit) (8bit) 3. MICRO-CONTROLLER CONFIGURATION INTERFACE The device supports standard I2C micro-controller configuration interface. External microcontroller can completely configure the device through writing to internal configuration registers. I2C interface is a bi-directional serial bus that uses a serial data line (CDATA) and a serial clock line (CCLK) for data transfer. The timing diagram for data transfer of this interface is given in Figure 1a and Figure 1b. Data are transmitted synchronously to CCLK clock on the CDATA line on a byte-by-byte basis. Each bit in a byte is sampled during CCLK high with MSB bit being transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull the CDATA low. The transfer rate of this interface can be up to 400 kbps. A master controller initiates the transmission by sending a “start” signal, which is defined as a high-to-low transition at CDATA while CCLK is high. The first byte transferred is the slave address. It is a seven-bit chip address followed by a RW bit. The chip address must be 0110 x, where x equals AD2 AD1 AD0. The RW bit indicates the slave data transfer direction. Once an Revision 4.1 3 January 2022 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7202 acknowledge bit is received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified by the RW bit. The master can terminate the communication by generating a “stop” signal, which is defined as a low-to-high transition at CDATA while CCLK is high. In I2C interface mode, the registers can be written and read. The formats of “write” and “read” instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the register. Table 1 Write Data to Register in I2C Interface Mode start Chip Address 0110 AD2 AD1 AD0 R/W 0 ACK Chip Addr CDATA Register Address RAM Write ACK bit 1 to 7 Reg Addr ACK ACK bit 1 to 8 Data to be written DATA Write Data ACK ACK bit 1 to 8 CCLK START STOP Figure 1a I2C Write Timing Table 2 Read Data from Register in I2C Interface Mode Chip Address 0110 AD2 AD1 AD0 Chip Address 0110 AD2 AD1 AD0 Start Start Chip Addr CDATA bit 1 to 7 Write ACK R/W 0 R/W 1 Reg Addr ACK ACK ACK bit 1 to 8 Register Address RAM Data to be read Data Chip Addr bit 1 to 7 Read ACK ACK NACK Stop Read Data NO ACK bit 1 to 8 CCLK START START STOP Figure 1b I2C Read Timing Revision 4.1 4 January 2022 Latest datasheet: www.everest-semi.com or info@everest-semi.com Stop Everest Semiconductor Confidential ES7202 4. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Continuous operation at or beyond these conditions may permanently damage the device. PARAMETER Supply Voltage Level Analog Input Voltage Range Digital Input Voltage Range Operating Temperature Range Storage Temperature MIN -0.3V GND-0.3V GND-0.3V -40°C -65°C MAX +3.6V VDD+0.3V VDD+0.3V +85°C +150°C RECOMMENDED OPERATING CONDITIONS PARAMETER VDD MIN 1.7 TYP 1.8/3.3 MAX 3.6 UNIT V ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: VDD=3.3V, GND=0V, ambient temperature=25°C, CLOCK=6.144 MHz. PARAMETER ADC Performance Dynamic Range (A-weigh) THD+N (0 dB PGA) Channel Separation (1KHz) Interchannel Gain Mismatch Gain Error Analog Input Full Scale Input Level ES7202 Input Impedance 0 dB PGA 23 dB PGA 26 dB PGA 29 dB PGA 32 dB PGA MIN TYP MAX UNIT 92 88 87 85 83 -85 102 95 91 90 88 86 -88 105 0.1 98 94 93 91 89 -91 108 dB dB dB dB % ±5 ±1.0*VDD/3.3 19.2 (0 dB PGA) ±Vrms KΩ DC CHARACTERISTICS PARAMETER Normal Operation Mode VDD=3.3V (16 kHz) VDD=1.8V (16 kHz) Power Down Mode Digital Voltage Level Input High-level Voltage Input Low-level Voltage Output High-level Voltage Output Low-level Voltage Revision 4.1 MIN TYP MAX 22 4.6 0 0.7*VDD VDD 0 UNIT mW uA 0.5 V V V V 5 January 2022 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7202 I2C SWITCHING SPECIFICATIONS (SLOW SPEED MODE/HIGH SPEED MODE) PARAMETER CCLK Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time Clock Low time Clock High Time Setup Time for Repeated Start Condition CDATA Hold Time from CCLK Falling CDATA Setup time to CCLK Rising Rise Time of CCLK Fall Time CCLK Symbol FCCLK TTWID TTWSTH TTWCL TTWCH TTWSTS TTWDH TTWDS TTWR TTWF MIN 4.7/1.3 4.0/0.6 4.7/1.3 4.0/0.6 4.7/0.6 0.25/0.1 MAX 100/400 UNIT KHz us us us us us us us us us 3.45/0.9 1.0/0.3 1.0/0.3 CDATA TTWSTS TTWSTH TTWDH TTWID TTWDS TTWCL CCLK TTWCH S P TTWF TTWR S Figure 2 I2C Timing PDM DATA SWITCHING SPECIFICATIONS PARAMETER CLOCK frequency CLOCK duty cycle Symbol ≤ 3.072 MHz DATA valid VDDD=3.3V T VDDD=1.8V VALID VDDD=3.3V T VDDD=1.8V HOLD DATA hold THOLD MIN 0.512 40 45 11 19 10 18 MAX 6.144 60 55 27 61 26 56 UNIT MHz % ns ns THOLD CLOCK TVALID DATA TVALID Right Data Left Data Figure 3 PDM Data Timing Revision 4.1 6 January 2022 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7202 5. PACKAGE Revision 4.1 7 January 2022 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7202 6. CORPORATE INFORMATION Everest Semiconductor Co., Ltd. No. 1355 Jinjihu Drive, Suzhou Industrial Park, Jiangsu, P.R. China, Zip Code 215021 苏州工业园区金鸡湖大道 1355 号国际科技园, 邮编 215021 Email: info@everest-semi.com 7. IMPORTANT NOTICE AND DISCLAIMER Everest Semiconductor publishes reliable technical information about its products. Information contained herein is subject to change without notice. It may be used by a party at their own discretion and risk. Everest Semiconductor disclaims responsibility for any claims, damages, costs, losses, and liabilities arising out of your use of the information. This publication is not to be taken as a license to operate under any existing patents and intellectual properties. Revision 4.1 8 January 2022 Latest datasheet: www.everest-semi.com or info@everest-semi.com