GD32F425RET6

GigaDevice Semiconductor Inc. GD32F425xx Arm® Cortex®-M4 32-bit MCU Datasheet GD32F425xx Datasheet Table of Contents Table of Contents ..................................................................................................... 1 List of Figures .......................................................................................................... 4 List of Tables ............................................................................................................ 5 1. General description ........................................................................................... 7 2. Device overview ................................................................................................. 8 2.1. Device information ................................................................................................ 8 2.2. Block diagram ........................................................................................................ 9 2.3. Pinouts and pin assignment ............................................................................... 10 2.4. Memory map ........................................................................................................ 13 2.5. Clock tree ............................................................................................................. 16 2.6. Pin definitions ...................................................................................................... 17 2.6.1. GD32F425Zx LQFP144 pin definitions .......................................................................... 17 2.6.2. GD32F425Vx LQFP100 pin definitions .......................................................................... 25 2.6.3. GD32F425Vx BGA100 pin definitions ............................................................................ 31 2.6.4. GD32F425Rx LQFP64 pin definitions ............................................................................ 38 2.6.5. GD32F425xx pin alternate functions ................................................................................ 0 3. Functional description....................................................................................... 7 3.1. Arm® Cortex®-M4 core ........................................................................................... 7 3.2. On-chip memory .................................................................................................... 7 3.3. Clock, reset and supply management .................................................................. 8 3.4. Boot modes............................................................................................................ 8 3.5. Power saving modes ............................................................................................. 9 3.6. Analog to digital converter (ADC) ........................................................................ 9 3.7. Digital to analog converter (DAC) ....................................................................... 10 3.8. DMA ...................................................................................................................... 10 3.9. General-purpose inputs/outputs (GPIOs) .......................................................... 11 3.10. Timers and PWM generation ........................................................................... 11 3.11. Real time clock (RTC) and backup registers .................................................. 12 3.12. Inter-integrated circuit (I2C) ............................................................................ 13 3.13. Serial peripheral interface (SPI) ...................................................................... 13 3.14. Universal synchronous/asynchronous receiver transmitter (USART/UART) 1 GD32F425xx Datasheet 13 3.15. Inter-IC sound (I2S) .......................................................................................... 14 3.16. Universal serial bus full-speed interface (USBFS) ......................................... 14 3.17. Universal serial bus high-speed interface (USBHS) ...................................... 14 3.18. Controller area network (CAN) ........................................................................ 15 3.19. Secure digital input and output card interface (SDIO) ................................... 15 3.20. Digital camera interface (DCI) ......................................................................... 15 3.21. Debug mode ..................................................................................................... 15 3.22. Package and operation temperature............................................................... 16 4. Electrical characteristics ................................................................................. 17 4.1. Absolute maximum ratings ................................................................................. 17 4.2. Operating conditions characteristics ................................................................. 17 4.3. Power consumption ............................................................................................ 19 4.4. EMC characteristics ............................................................................................ 25 4.5. Power supply supervisor characteristics .......................................................... 25 4.6. Electrical sensitivity ............................................................................................ 27 4.7. External clock characteristics ............................................................................ 27 4.8. Internal clock characteristics ............................................................................. 29 4.9. PLL characteristics.............................................................................................. 30 4.10. Memory characteristics ................................................................................... 32 4.11. NRST pin characteristics ................................................................................. 32 4.12. GPIO characteristics ........................................................................................ 33 4.13. ADC characteristics ......................................................................................... 36 4.14. Temperature sensor characteristics ............................................................... 37 4.15. DAC characteristics ......................................................................................... 37 4.16. I2C characteristics ........................................................................................... 38 4.17. SPI characteristics ........................................................................................... 40 4.18. I2S characteristics ........................................................................................... 42 4.19. USART characteristics..................................................................................... 44 4.20. SDIO characteristics ........................................................................................ 44 4.21. CAN characteristics ......................................................................................... 44 4.22. USBFS characteristics ..................................................................................... 45 2 GD32F425xx Datasheet 4.23. USBHS characteristics .................................................................................... 46 4.24. TIMER characteristics ...................................................................................... 46 4.25. DCI characteristics........................................................................................... 47 4.26. WDGT characteristics ...................................................................................... 47 4.27. Parameter conditions....................................................................................... 47 5. Package information ........................................................................................ 48 5.1. LQFP144 package outline dimensions .............................................................. 48 5.2. BGA100 package outline dimensions ................................................................ 50 5.3. LQFP100 package outline dimensions .............................................................. 52 5.4. LQFP64 package outline dimensions ................................................................ 54 5.5. Thermal characteristics ...................................................................................... 56 6. Ordering information ....................................................................................... 58 7. Revision history ............................................................................................... 59 3 GD32F425xx Datasheet List of Figures Figure 2-1. GD32F425xx block diagram .............................................................................................. 9 Figure 2-2. GD32F425Vx BGA100 pinouts ........................................................................................ 10 Figure 2-3. GD32F425Zx LQFP144 pinouts ...................................................................................... 11 Figure 2-4. GD32F425Vx LQFP100 pinouts ...................................................................................... 12 Figure 2-5. GD32F425Rx LQFP64 pinouts ........................................................................................ 12 Figure 2-6. GD32F425xx clock tree ................................................................................................... 16 Figure 4-1. Recommended power supply decoupling capacitors(1) (2) ........................................... 18 Figure 4-2. Typical supply current consumption in Run mode ...................................................... 24 Figure 4-3. Typical supply current consumption in Sleep mode ................................................... 25 Figure 4-4. Recommended external NRST pin circuit ..................................................................... 33 Figure 4-5. I2C bus timing diagram ................................................................................................... 39 Figure 4-6. SPI timing diagram - master mode ................................................................................ 40 Figure 4-7. SPI timing diagram - slave mode ................................................................................... 41 Figure 4-8. I2S timing diagram - master mode ................................................................................. 43 Figure 4-9. I2S timing diagram - slave mode .................................................................................... 43 Figure 4-10. USBFS timings: definition of data signal rise and fall time ...................................... 45 Figure 5-1. LQFP144 package outline ............................................................................................... 48 Figure 5-2. LQFP144 recommended footprint .................................................................................. 49 Figure 5-3. BGA100 package outline ................................................................................................. 50 Figure 5-4. BGA100 recommended footprint ................................................................................... 51 Figure 5-5. LQFP100 package outline ............................................................................................... 52 Figure 5-6. LQFP100 recommended footprint .................................................................................. 53 4 GD32F425xx Datasheet List of Tables Table 2-1. GD32F425xx devices features and peripheral list ........................................................... 8 Table 2-2. GD32F425xx memory map ............................................................................................... 13 Table 2-3. GD32F425Zx LQFP144 pin definitions ............................................................................ 17 Table 2-4. GD32F425Vx LQFP100 pin definitions ............................................................................ 25 Table 2-5. GD32F425Vx BGA100 pin definitions .............................................................................. 31 Table 2-6. GD32F425Rx LQFP64 pin definitions .............................................................................. 38 Table 2-7. Port A alternate functions summary ................................................................................. 0 Table 2-8. Port B alternate functions summary ................................................................................. 1 Table 2-9. Port C alternate functions summary ................................................................................. 2 Table 2-10. Port D alternate functions summary ............................................................................... 3 Table 2-11. Port E alternate functions summary ............................................................................... 4 Table 2-12. Port F alternate functions summary ................................................................................ 5 Table 2-13. Port G alternate functions summary ............................................................................... 5 Table 2-14. Port H alternate functions summary ............................................................................... 6 Table 4-1. Absolute maximum ratings(1)(4) ........................................................................................ 17 Table 4-2. DC operating conditions ................................................................................................... 17 Table 4-3. Clock frequency(1) .............................................................................................................. 18 Table 4-4. Operating conditions at Power up / Power down(1)........................................................ 18 Table 4-5. Start-up timings of Operating conditions (1)(2)(3) .............................................................. 18 Table 4-6. Power saving mode wakeup timings characteristics(1)(2) .............................................. 19 Table 4-7. Power consumption characteristics(2)(3)(4)(5) .................................................................... 19 Table 4-8. EMS characteristics(1) ....................................................................................................... 25 Table 4-9. Power supply supervisor characteristics ....................................................................... 25 Table 4-10. ESD characteristics(1) ...................................................................................................... 27 Table 4-11. Static latch-up characteristics(1) .................................................................................... 27 Table 4-12. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics ..................................................................................................................................... 27 Table 4-13. High speed external clock characteristics (HXTAL in bypass mode)........................ 28 Table 4-14. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics .............................................................................................................................................................. 28 Table 4-15. Low speed external user clock characteristics (LXTAL in bypass mode) ................ 29 Table 4-16. High speed internal clock (IRC16M) characteristics.................................................... 29 Table 4-17. High speed internal clock (IRC48M) characteristics.................................................... 29 Table 4-18. Low speed internal clock (IRC32K) characteristics ..................................................... 30 Table 4-19. PLL characteristics ......................................................................................................... 30 Table 4-20. PLLI2S characteristics .................................................................................................... 31 Table 4-21. PLLSAI characteristics ................................................................................................... 31 Table 4-22. PLL spread spectrum clock generation (SSCG) characteristics ................................ 31 Table 4-23. Flash memory characteristics........................................................................................ 32 Table 4-24. NRST pin characteristics ................................................................................................ 32 Table 4-25. I/O port DC characteristics(1)(3) ....................................................................................... 33 5 GD32F425xx Datasheet Table 4-26. I/O port AC characteristics(1)(2)(4) .................................................................................... 35 Table 4-27. ADC characteristics ........................................................................................................ 36 Table 4-28. ADC RAIN max for fADC = 40 MHz(2) ................................................................................ 36 Table 4-29. ADC dynamic accuracy at fADC = 40 MHz(1) ................................................................... 37 Table 4-30. ADC static accuracy at fADC = 40 MHz(1)......................................................................... 37 Table 4-31. Temperature sensor characteristics(1) .......................................................................... 37 Table 4-32. DAC characteristics ........................................................................................................ 37 Table 4-33. I2C characteristics(1)(2) ..................................................................................................... 38 Table 4-34. Standard SPI characteristics(1) ....................................................................................... 40 Table 4-35. I2S characteristics(1)(2) ..................................................................................................... 42 Table 4-36. USART characteristics(1) ................................................................................................. 44 Table 4-37. SDIO characteristics(1)(2).................................................................................................. 44 Table 4-38. USBFS start up time ........................................................................................................ 45 Table 4-39. USBFS DC electrical characteristics ............................................................................. 45 Table 4-40. USBFS full speed-electrical characteristics(1) .............................................................. 45 Table 4-41. TIMER characteristics(1) .................................................................................................. 46 Table 4-42. DCI characteristics(1) ....................................................................................................... 47 Table 4-43. FWDGT min/max timeout period at 32 kHz (IRC32K)(1) ................................................ 47 Table 4-44. WWDGT min-max timeout value at 50 MHz (fPCLK1)(1) ................................................... 47 Table 5-1. LQFP144 package dimensions ........................................................................................ 48 Table 5-2. BGA100 package dimensions .......................................................................................... 50 Table 5-3. LQFP100 package dimensions ........................................................................................ 52 Table 5-4. LQFP64 package dimensions .......................................................................................... 54 Table 5-5. Package thermal characteristics(1) .................................................................................. 56 Table 6-1. Part ordering code for GD32F425xx devices .................................................................. 58 Table 7-1. Revision history................................................................................................................. 59 6 GD32F425xx Datasheet 1. General description The GD32F425xx device belongs to the connectivity line of GD32 MCU family. It is a new 32-bit general-purpose microcontroller based on the Arm® Cortex®-M4 RISC core with best cost-performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features a Floating Point Unit (FPU) that accelerates single precision floating point math operations and supports all Arm® single precision instructions and data types. It implements a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a Memory Protection Unit (MPU) and powerful trace technology for enhanced application security and advanced debug support. The GD32F425xx device incorporates the Arm® Cortex®-M4 32-bit processor core operating at 200 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 3072 KB on-chip Flash memory and 256 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit 2.6 MSPS ADCs, two 12-bit DACs, up to eight general 16-bit timers, two 16-bit PWM advanced-control timers, two 32-bit general timers, and two 16-bit basic timers, as well as standard and advanced communication interfaces: up to three SPIs, three I2Cs, four USARTs and two UARTs, two I2Ss, two CANs, a SDIO, USBFS and USBHS. Additional peripherals as Digital camera interface (DCI) is included. The device operates from a 2.6 to 3.6V power supply and available in –40 to +85 °C temperature range. Three power saving modes provide the flexibility for maximum optimization of power consumption, an especially important consideration in low power applications. The above features make GD32F425xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, embedded modules, human machine interface, security and alarm systems, graphic display, automotive navigation, drone, IoT and so on. 7 GD32F425xx Datasheet 2. Device overview 2.1. Device information Table 2-1. GD32F425xx devices features and peripheral list GD32F425xx Flash Part Number RE RG RK VG VK VG VK ZG ZK Code area (KB) 512 512 512 512 512 512 512 512 512 Data area (KB) 0 512 2560 512 2560 512 2560 512 2560 Total (KB) 512 1024 3072 1024 3072 1024 3072 1024 3072 256 256 256 256 256 256 256 256 256 General 8 8 8 8 8 8 8 8 8 timer(16-bit) (2-3,8-13) (2-3,8-13) (2-3,8-13) (2-3,8-13) (2-3,8-13) (2-3,8-13) (2-3,8-13) (2-3,8-13) (2-3,8-13) General timer 2 2 2 2 2 2 2 2 2 (32-bit) (1,4) (1,4) (1,4) (1,4) (1,4) (1,4) (1,4) (1,4) (1,4) Advanced 2 2 2 2 2 2 2 2 2 timer(16-bit) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) Basic timer(16- 2 2 2 2 2 2 2 2 2 bit) (5,6) (5,6) (5,6) (5,6) (5,6) (5,6) (5,6) (5,6) (5,6) SysTick 1 1 1 1 1 1 1 1 1 Watchdog 2 2 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 1 1 USART 4 4 4 4 4 4 4 4 4 UART 2 2 2 2 2 2 2 2 2 I2C 3 3 3 3 3 3 3 3 3 Connectivity Timers SRAM (KB) 3/2 3/2 3/2 3/2 3/2 3/2 3/2 3/2 3/2 (0-2)/(1-2) (0-2)/(1-2) (0-2)/(1-2) (0-2)/(1-2) (0-2)/(1-2) (0-2)/(1-2) (0-2)/(1-2) (0-2)/(1-2) (0-2)/(1-2) SDIO 1 1 1 1 1 1 1 1 1 CAN 2 2 2 2 2 2 2 2 2 SPI/I2S USB FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS 1 1 1 1 1 1 1 1 1 GPIO 51 51 51 82 82 82 82 114 114 ADC(CHs) 3(16) 3(16) 3(16) 3(16) 3(16) 3(16) 3(16) 3(24) 3(24) DAC 2 2 2 2 2 2 2 2 2 DCI Package LQFP64 LQFP100 BGA100 LQFP144 8 GD32F425xx Datasheet Block diagram Figure 2-1. GD32F425xx block diagram Powered By LDO (1.2V) Flash Memory master DBUS SW/JTA G IBUS TPIU master slave FMC slave master M master P master M master P master DMA0 DMA1 USBHS master AHB Interconnect Matrix (Fmax=200MHz) SBUS ARM Cortex-M4 Processor Fmax: 200MHz Powered By V DDA slave TCMSRAM slave SRAM0 slave SRAM1 DAC BKP SRAM CRC LVD PLLs IRC16M IRC32K GPIO RCU slave AHB1 Per ipheral s TRNG DCI USBFS slave AHB2 Per ipheral s slave AHB Interconnect Matrix (Fmax=200MHz) slave 2.2. SPI0 CTC DAC IVREF CAN1 TIMER9 TIMER13 CAN0 TIMER8 TIMER12 TIMER7 TIMER11 TIMER0 TIMER6 USART5 TIMER5 UART3 USART0 TIMER4 USART2 TIMER3 TIMER2 TIMER1 WWDG T SAR ADC Powered By V DDA POR/ PDR USART1 I2C2 I2C1 I2C0 I2S2_add SPI2/I2S2 SPI1/I2S1 LDO FWDG T HXTAL UART4 APB1 (Fmax=50MHz) ADC0~2 APB2 (Fmax=100MHz) EXTI SDIO SYS CFG TIMER10 I2S1_add PMU Powered By V DD LXTAL RTC Powered By V B AT 9 GD32F425xx Datasheet 2.3. Pinouts and pin assignment Figure 2-2. GD32F425Vx BGA100 pinouts 1 2 A PE3 PE1 B PE4 C 3 4 5 6 7 8 PB8 BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11 PC13 PE5 PE0 VDD PB5 PD2 PD0 PC11 NC PA10 D PC14 PE6 VSS PA9 PA8 PC9 E PC15 VBAT NC PC8 PC7 PC6 F PH0 VSS VSS VSS G PH1 VDD VDD VDD H PC0 NRST 9 10 GigaDevice GD32F425Vx BGA100 11 12 PA13 PA12 PDR_ ON PD15 PD14 PD13 PD12 PD11 PD10 PB15 PB14 PB13 J VSSA PC1 PC2 K VREF- PC3 PA2 PA5 PC4 L VREF+ PA0 PA3 PA6 PC5 PB2 PE8 M VDDA PA1 PA4 PA7 PB0 PB1 PE7 PD9 PB11 PE10 PE12 PB10 PE9 NC PB12 PE11 PE13 PE14 PE15 10 GD32F425xx Datasheet Figure 2-3. GD32F425Zx LQFP144 pinouts PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 VSS VDD PD6 PD7 PG9 PG11 PG10 PG12 PG13 PG14 VDD VSS PG15 PB4 PB3 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VDD PDR_ON 144143142141140139138137136135134133 132131130129128127126125124123122121120 119118117116115114113112111110109 PE2 1 108 PE3 PE4 2 107 VSS 3 106 NC PE5 PE6 4 105 PA13 5 104 PA12 VBAT 6 103 PA11 PC13-TAMPER-RTC PC14-OSC32IN 7 102 PA10 8 101 PA9 PC15-OSC32OUT 9 100 PA8 PF0 10 99 PC9 PF1 11 98 PC8 PF2 12 97 PC7 PF3 PF4 13 96 PC6 14 95 VDD PF5 15 94 VSS VSS 16 93 PG8 92 PG7 91 PG6 90 PG5 89 PG4 88 PG3 VDD VDD 17 PF6 18 PF7 19 PF8 20 PF9 21 PF10 22 87 PG2 PH0-OSCIN 23 86 PD15 PH1-OSCOUT 24 85 PD14 NRST 25 84 VDD PC0 26 83 VSS PC1 27 82 PD13 PC2 28 81 PD12 PC3 VDD 29 80 PD11 30 79 PD10 VSSA VREF+ 31 78 PD9 32 77 PD8 VDDA 33 76 PB15 PA0_WKUP 34 75 PB14 PA1 35 74 PB13 PA2 36 73 PB12 GigaDevice GD32F425Zx LQFP144 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 NC VDD PB11 PB10 PE15 PE13 PE14 PE12 PE11 VDD PE10 VSS PE8 PE9 PE7 PG1 PG0 PF15 PF13 PF14 VSS VDD PF12 PB2 PF11 PB1 PC5 PB0 PA7 PC4 PA6 PA5 PA4 VSS VDD PA3 11 GD32F425xx Datasheet Figure 2-4. GD32F425Vx LQFP100 pinouts PA14 PA15 PC10 PC11 PD0 PC12 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PB3 PB4 PB5 PB6 PB7 PB8 BOOT0 PB9 PE0 PE1 VSS VDD PE2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 PE3 PE4 2 74 VSS 3 73 NC PE5 PE6 4 72 PA13 5 71 PA12 VBAT 6 PC13-TAMPER-RTC PC14-OSC32IN 7 70 69 PA10 8 68 PA9 PC15-OSC32OUT 9 67 PA8 VSS 10 66 PC9 VDD 11 65 PC8 64 PC7 63 PC6 PH0-OSCIN 12 PH1-OSCOUT 13 GigaDevice GD32F425Vx LQFP100 VDD PA11 NRST PC0 14 62 PD15 15 61 PD14 PC1 16 60 PD13 PC2 PC3 17 59 PD12 18 58 PD11 VDD 19 57 PD10 VSSA VREF+ 20 56 PD9 21 55 PD8 VDDA 22 54 PB15 PA0-WKUP 23 53 PB14 PA1 24 52 PB13 PA2 25 51 PB12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDD PB11 NC PB10 PE15 PE14 PE13 PE12 PE11 PD2 PC12 PE10 PE8 PE9 PE7 PB2 PB1 PB0 PC5 PC4 PA7 PA6 PA5 PA4 VSS VDD PA3 Figure 2-5. GD32F425Rx LQFP64 pinouts PA14 PA15 PC10 PC11 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VBAT 1 48 PC13-TAMPER-RTC 2 47 VDD_2 NC PC14-OSC32IN 3 46 PA13 PC15-OSC32OUT PH0-OSCIN 4 45 PA12 5 44 PA11 PH1-OSCOUT 6 43 PA10 NRST PC0 7 42 PA9 PC1 9 PC2 PC3 VSSA GigaDevice GD32F425Rx LQFP64 41 PA8 40 PC9 10 39 PC8 11 38 PC7 12 37 PC6 VDDA 13 36 PB15 PA0-WKUP 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 8 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD NC PB11 PB10 PB2 PB1 PC5 PB0 PC4 PA7 PA6 PA5 VDD PA4 VSS PA3 12 GD32F425xx Datasheet 2.4. Memory map Table 2-2. GD32F425xx memory map Pre-defined Regions Bus External Device AHB External RAM AHB2 Peripheral AHB1 Address Peripherals 0xC000 0000 - 0xDFFF FFFF Reserved 0xA000 1000 - 0xBFFF FFFF Reserved 0xA000 0000 - 0xA000 0FFF Reserved 0x9000 0000 - 0x9FFF FFFF Reserved 0x7000 0000 - 0x8FFF FFFF Reserved 0x6000 0000 - 0x6FFF FFFF Reserved 0x5006 0C00 - 0x5FFF FFFF Reserved 0x5006 0800 - 0x5006 0BFF TRNG 0x5005 0400 - 0x5006 07FF Reserved 0x5005 0000 - 0x5005 03FF DCI 0x5004 0000 - 0x5004 FFFF Reserved 0x5000 0000 - 0x5003 FFFF USBFS 0x4008 0000 - 0x4FFF FFFF Reserved 0x4004 0000 - 0x4007 FFFF USBHS 0x4002 BC00 - 0x4003 FFFF Reserved 0x4002 B000 - 0x4002 BBFF Reserved 0x4002 A000 - 0x4002 AFFF Reserved 0x4002 8000 - 0x4002 9FFF Reserved 0x4002 6800 - 0x4002 7FFF Reserved 0x4002 6400 - 0x4002 67FF DMA1 0x4002 6000 - 0x4002 63FF DMA0 0x4002 5000 - 0x4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF BKP SRAM 0x4002 3C00 - 0x4002 3FFF FMC 0x4002 3800 - 0x4002 3BFF RCU 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2400 - 0x4002 2FFF Reserved 0x4002 2000 - 0x4002 23FF GPIOI 0x4002 1C00 - 0x4002 1FFF GPIOH 0x4002 1800 - 0x4002 1BFF GPIOG 0x4002 1400 - 0x4002 17FF GPIOF 0x4002 1000 - 0x4002 13FF GPIOE 0x4002 0C00 - 0x4002 0FFF GPIOD 0x4002 0800 - 0x4002 0BFF GPIOC 0x4002 0400 - 0x4002 07FF GPIOB 0x4002 0000 - 0x4002 03FF GPIOA 13 GD32F425xx Datasheet Pre-defined Regions Bus APB2 APB1 Address Peripherals 0x4001 6C00 - 0x4001 FFFF Reserved 0x4001 6800 - 0x4001 6BFF Reserved 0x4001 5800 - 0x4001 67FF Reserved 0x4001 5400 - 0x4001 57FF Reserved 0x4001 5000 - 0x4001 53FF Reserved 0x4001 4C00 - 0x4001 4FFF Reserved 0x4001 4800 - 0x4001 4BFF TIMER10 0x4001 4400 - 0x4001 47FF TIMER9 0x4001 4000 - 0x4001 43FF TIMER8 0x4001 3C00 - 0x4001 3FFF EXTI 0x4001 3800 - 0x4001 3BFF SYSCFG 0x4001 3400 - 0x4001 37FF Reserved 0x4001 3000 - 0x4001 33FF SPI0 0x4001 2C00 - 0x4001 2FFF SDIO 0x4001 2400 - 0x4001 2BFF Reserved 0x4001 2300 - 0x4001 23FF ADC0(1) 0x4001 2200 - 0x4001 22FF ADC2 0x4001 2100 - 0x4001 21FF ADC1 0x4001 2000 - 0x4001 20FF ADC0 0x4001 1800 - 0x4001 1FFF Reserved 0x4001 1400 - 0x4001 17FF USART5 0x4001 1000 - 0x4001 13FF USART0 0x4001 0800 - 0x4001 0FFF Reserved 0x4001 0400 - 0x4001 07FF TIMER7 0x4001 0000 - 0x4001 03FF TIMER0 0x4000 C800 - 0x4000 FFFF Reserved 0x4000 C400 - 0x4000 C7FF IREF 0x4000 8000 - 0x4000 C3FF Reserved 0x4000 7C00 - 0x4000 7FFF Reserved 0x4000 7800 - 0x4000 7BFF Reserved 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PMU 0x4000 6C00 - 0x4000 6FFF CTC 0x4000 6800 - 0x4000 6BFF CAN1 0x4000 6400 - 0x4000 67FF CAN0 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF I2C2 0x4000 5800 - 0x4000 5BFF I2C1 0x4000 5400 - 0x4000 57FF I2C0 0x4000 5000 - 0x4000 53FF UART4 0x4000 4C00 - 0x4000 4FFF UART3 14 GD32F425xx Datasheet Pre-defined Regions SRAM Code Bus AHB AHB Address Peripherals 0x4000 4800 - 0x4000 4BFF USART2 0x4000 4400 - 0x4000 47FF USART1 0x4000 4000 - 0x4000 43FF I2S2_add 0x4000 3C00 - 0x4000 3FFF SPI2/I2S2 0x4000 3800 - 0x4000 3BFF SPI1/I2S1 0x4000 3400 - 0x4000 37FF I2S1_add 0x4000 3000 - 0x4000 33FF FWDGT 0x4000 2C00 - 0x4000 2FFF WWDGT 0x4000 2800 - 0x4000 2BFF RTC 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIMER13 0x4000 1C00 - 0x4000 1FFF TIMER12 0x4000 1800 - 0x4000 1BFF TIMER11 0x4000 1400 - 0x4000 17FF TIMER6 0x4000 1000 - 0x4000 13FF TIMER5 0x4000 0C00 - 0x4000 0FFF TIMER4 0x4000 0800 - 0x4000 0BFF TIMER3 0x4000 0400 - 0x4000 07FF TIMER2 0x4000 0000 - 0x4000 03FF TIMER1 0x2007 0000 - 0x3FFF FFFF Reserved 0x2003 0000 - 0x2006 FFFF Reserved 0x2002 0000 - 0x2002 FFFF SRAM2(64KB) 0x2001 C000 - 0x2001 FFFF SRAM1(16KB) 0x2000 0000 - 0x2001 BFFF SRAM0(112KB) 0x1FFF C010 - 0x1FFF FFFF Reserved 0x1FFF C000 - 0x1FFF C00F Option bytes(Bank 0) 0x1FFF 7A10 - 0x1FFF BFFF Reserved 0x1FFF 7800 - 0x1FFF 7A0F OTP(512B) 0x1FFF 0000 - 0x1FFF 77FF Boot loader(30KB) 0x1FFE C010 - 0x1FFE FFFF Reserved 0x1FFE C000 - 0x1FFE C00F Option bytes(Bank 1) 0x1001 0000 - 0x1FFE BFFF Reserved 0x1000 0000 - 0x1000 FFFF TCMSRAM(64KB) 0x0830 0000 - 0x0FFF FFFF Reserved 0x0800 0000 - 0x082F FFFF Main Flash(3072KB) 0x0000 0000 - 0x07FF FFFF Aliased to the boot device Note: (1) ADC_SSTAT, ADC_SYNCCTL, ADC_SYNCDATA based on base address of ADC0. 15 GD32F425xx Datasheet 2.5. Clock tree Figure 2-6. GD32F425xx clock tree CK_HXTAL /2 to /31 11 32.768 KHz LXTAL OSC CK_RTC 01 (to RTC) 10 RTCSRC[1:0] CK_FWDGT 32 KHz IRC32K (to FWDGT) CK_OUT1 00 01 10 11 CKOUT1DIV ÷1,2,3,4,5 CK_SYS CK_PLLI2SR CK_HXTAL CK_PLLP CKOUT1SEL[1:0] HCLK (to AHB bus,CortexM4,SRAM,DMA,peripherals) AHB enable CK_OUT0 00 01 10 11 CKOUT0DIV ÷1,2,3,4,5 CK_IRC16M CK_LXTAL CK_HXTAL CK_CST ÷8 (to Cortex-M4 SysTick) FCLK CK_PLLP (free running clock) APB1 Prescaler ÷1,2,4,8,16 CKOUT0SEL[1:0] SCS[1:0] CK_IRC16M 16 MHz IRC16M 01 CK_SYS 200 MHz max AHB Prescaler ÷1,2...512 CK_AHB APB2 Prescaler ÷1,2,4,8,16 10 Clock Monitor CTC 1 VCO ADC Prescaler ÷2,4,6,8 /P /Q xN CK48MSEL PLL48MSEL 0 VCO I2SSEL /P PLLI2S VCO to TIMER1,2,3,4, 5,6,11,12,13 CK_APB2 PCLK2 to APB2 peripherals 100 MHz max 200 MHz max to TIMER0,7, 8,9,10 ADCCK[2] 0 CK_ADCX to ADC0,1,2 40 MHz max ADC Prescaler ÷5,6,10,20 1 1 CK48M 0 Peripheral enable to USBFS USBHS TRNG SDIO 1 /R CK_TIMERx TIMERx enable 1 /Q xN CK_TIMERx TIMERx enable CK_CTC 48 MHz IRC48M /R PLL 200 MHz max Peripheral enable TIMER0,7,8, 9,10 CK_APB2 x1 x2 or x4 PLLSEL 0 TIMER1,2,3,4,5,6, 11,12,13 CK_APB1 x1 x2 or x4 200 MHz max CK_PLLP /PSC PCLK1 to APB1 peripherals Peripheral enable 00 CK_HXTAL 4-32 MHz HXTAL CK_APB1 50 MHz max CK_I2Sx 0 Peripheral enable I2S_CKIN to I2S /P /Q xN /R /DIV PLLSAI CK_TLI Peripheral enable ENET_TX_CLK /2 or /20 0 1 Peripheral enable ENET_PHY_SEL 1 ENET_RX_CLK to TLI CK_ENETTX to ENET TX CK_ENETRX 0 EMBPHY Peripheral enable to ENET RX USB HS PHY clock 24Mhz to 60Mhz 0 CK48M 1 CK_USBHS_ULPI Peripheral enable to USBHS ULPI Legend: HXTAL: High speed crystal oscillator LXTAL: Low speed crystal oscillator IRC16M: Internal 16M RC oscillators IRC32K: Internal 32K RC oscillator IRC48M: Internal 48M RC oscillators 16 GD32F425xx Datasheet 2.6. Pin definitions 2.6.1. GD32F425Zx LQFP144 pin definitions Table 2-3. GD32F425Zx LQFP144 pin definitions Pin I/O Type(1) Level(2) 1 I/O 5VT PE3 2 I/O 5VT PE4 3 I/O 5VT PE5 4 I/O 5VT PE6 5 I/O 5VT VBAT 6 P - Pin Name Pins PE2 PC13TAMPER- OSC32IN 7 I/O 5VT Alternate: TRACECK, EVENTOUT Default: PE3 Alternate:TRACED0, EVENTOUT Default: PE4 Alternate:TRACED1, DCI_D4, EVENTOUT Default: PE5 Alternate:TRACED2,TIMER8_CH0, DCI_D6, EVENTOUT Default: PE6 Alternate:TRACED3,TIMER8_CH1, DCI_D7, EVENTOUT Default: VBAT Alternate: EVENTOUT Additional: RTC_TAMP0, RTC_OUT, RTC_TS Default: PC14 8 I/O 5VT Alternate: EVENTOUT Additional: OSC32IN PC15OSC32OU Default: PE2 Default: PC13 RTC PC14- Functions description Default: PC15 9 I/O 5VT T Alternate: EVENTOUT Additional: OSC32OUT PF0 10 I/O 5VT PF1 11 I/O 5VT PF2 12 I/O 5VT Default: PF0 Alternate:I2C1_SDA, EVENTOUT, CTC_SYNC Default: PF1 Alternate: I2C1_SCL, EVENTOUT Default: PF2 Alternate: I2C1_SMBA, EVENTOUT Default: PF3 PF3 13 I/O 5VT Alternate: EVENTOUT, I2C1_TXFRAME Additional: ADC2_IN9 Default: PF4 PF4 14 I/O 5VT Alternate: EVENTOUT Additional: ADC2_IN14 Default: PF5 PF5 15 I/O 5VT Alternate: EVENTOUT Additional: ADC2_IN15 VSS 16 P - Default: VSS 17 GD32F425xx Datasheet Pin Name Pins VDD 17 Pin I/O Functions description Type(1) Level(2) P - Default: VDD Default: PF6 PF6 18 I/O 5VT Alternate: TIMER9_CH0, EVENTOUT Additional: ADC2_IN4 Default: PF7 PF7 19 I/O 5VT Alternate: TIMER10_CH0, EVENTOUT Additional: ADC2_IN5 Default: PF8 PF8 20 I/O 5VT Alternate: TIMER12_CH0, EVENTOUT Additional: ADC2_IN6 Default: PF9 PF9 21 I/O 5VT Alternate: TIMER13_CH0, EVENTOUT Additional: ADC2_IN7 Default: PF10 PF10 22 I/O 5VT Alternate: DCI_D11, EVENTOUT Additional: ADC2_IN8 Default: PH0, OSCIN PH0 23 I/O 5VT Alternate: EVENTOUT Additional: OSCIN Default: PH1, OSCOUT PH1 24 I/O 5VT Alternate: EVENTOUT Additional: OSCOUT NRST 25 - - Default: NRST Default: PC0 PC0 26 I/O 5VT Alternate: USBHS_ULPI_STP, EVENTOUT Additional: ADC012_IN10 Default: PC1 PC1 27 I/O 5VT Alternate: SPI2_MOSI, I2S2_SD, SPI1_MOSI, I2S1_SD, EVENTOUT Additional: ADC012_IN11 Default: PC2 PC2 28 I/O 5VT Alternate: SPI1_MISO,I2S1_ADD_SD,USBHS_ULPI_DIR, EVENTOUT Additional: ADC012_IN12 Default: PC3 PC3 29 I/O 5VT Alternate: SPI1_MOSI,I2S1_SD,USBHS_ULPI_NXT, EVENTOUT Additional: ADC012_IN13 VDD 30 P - Default: VDD VSSA 31 P - Default: VSSA VREFP 32 P - Default: VREF+ VDDA 33 P - Default: VDDA 18 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Default: PA0 PA0-WKUP 34 I/O 5VT Alternate: TIMER1_CH0,TIMER1_ETI,TIMER4_CH0, TIMER7_ETI,USART1_CTS, UART3_TX, EVENTOUT Additional: ADC012_IN0, WKUP Default: PA1 PA1 35 I/O 5VT Alternate: TIMER1_CH1, TIMER4_CH1, USART1_RTS, UART3_RX, EVENTOUT Additional: ADC012_IN1 Default: PA2 PA2 36 I/O 5VT Alternate: TIMER1_CH2,TIMER4_CH2,TIMER8_CH0, I2S_CKIN, USART1_TX, EVENTOUT Additional: ADC012_IN2 Default: PA3 PA3 37 I/O 5VT Alternate: TIMER1_CH3,TIMER4_CH3,TIMER8_CH1, I2S1_MCK,USART1_RX,USBHS_ULPI_D0, EVENTOUT Additional: ADC012_IN3 VSS 38 P - Default: VSS VDD 39 P - Default: VDD Default: PA4 PA4 40 Alternate: SPI0_NSS,SPI2_NSS, I2S2_WS, USART1_CK, I/O USBHS_SOF, DCI_HSYNC, EVENTOUT Additional: ADC01_IN4, DAC_OUT0 Default: PA5 PA5 41 Alternate: TIMER1_CH0,TIMER1_ETI, TIMER7_CH0_ON, I/O SPI0_SCK, USBHS_ULPI_CK, EVENTOUT Additional: ADC01_IN5, DAC_OUT1 Default: PA6 Alternate: TIMER0_BRKIN, TIMER2_CH0, TIMER7_BRKIN, PA6 42 I/O 5VT SPI0_MISO, I2S1_MCK, TIMER12_CH0, SDIO_CMD, DCI_PIXCLK, EVENTOUT Additional: ADC01_IN6 Default: PA7 PA7 43 I/O 5VT Alternate: TIMER0_CH0_ON, TIMER2_CH1, TIMER7_CH0_ON, SPI0_MOSI, TIMER13_CH0, EVENTOUT Additional: ADC01_IN7 Default: PC4 PC4 44 I/O 5VT Alternate: EVENTOUT Additional: ADC01_IN14 Default: PC5 PC5 45 I/O 5VT Alternate: USART2_RX, EVENTOUT Additional: ADC01_IN15 PB0 46 I/O 5VT Default: PB0 19 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: TIMER0_CH1_ON, TIMER2_CH2, TIMER7_CH1_ON, SPI2_MOSI, I2S2_SD, USBHS_ULPI_D1, SDIO_D1, EVENTOUT Additional: ADC01_IN8, IREF Default: PB1 PB1 47 I/O 5VT Alternate: TIMER0_CH2_ON, TIMER2_CH3, TIMER7_CH2_ON, USBHS_ULPI_D2, SDIO_D2, EVENTOUT Additional: ADC01_IN9 Default: PB2, BOOT1 PB2 48 I/O 5VT Alternate: TIMER1_CH3, SPI2_MOSI, I2S2_SD, USBHS_ULPI_D4, SDIO_CK, EVENTOUT Default: PF11 PF11 49 I/O 5VT PF12 50 I/O 5VT VSS 51 P - Default: VSS VDD 52 P - Default: VDD PF13 53 I/O 5VT PF14 54 I/O 5VT PF15 55 I/O 5VT PG0 56 I/O 5VT PG1 57 I/O 5VT PE7 58 I/O 5VT PE8 59 I/O 5VT PE9 60 I/O 5VT VSS 61 P - Default: VSS VDD 62 P - Default: VDD PE10 63 I/O 5VT PE11 64 I/O 5VT PE12 65 I/O 5VT PE13 66 I/O 5VT Alternate: DCI_D12, EVENTOUT Default: PF12 Alternate: EVENTOUT Default: PF13 Alternate: EVENTOUT Default: PF14 Alternate: EVENTOUT Default: PF15 Alternate: EVENTOUT Default: PG0 Alternate: EVENTOUT Default: PG1 Alternate: EVENTOUT Default: PE7 Alternate: TIMER0_ETI, EVENTOUT Default: PE8 Alternate: TIMER0_CH0_ON, EVENTOUT Default: PE9 Alternate: TIMER0_CH0, EVENTOUT Default: PE10 Alternate: TIMER0_CH1_ON, EVENTOUT Default: PE11 Alternate:TIMER0_CH1, EVENTOUT Default: PE12 Alternate:TIMER0_CH2_ON, EVENTOUT Default: PE13 20 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate:TIMER0_CH2, EVENTOUT PE14 67 I/O 5VT PE15 68 I/O 5VT Default: PE14 Alternate:TIMER0_CH3, EVENTOUT Default: PE15 Alternate: TIMER0_BRKIN, EVENTOUT Default: PB10 PB10 69 I/O 5VT Alternate: TIMER1_CH2,I2C1_SCL, SPI1_SCK, I2S1_CK, I2S2_MCK, USART2_TX, USBHS_ULPI_D3, SDIO_D7, EVENTOUT Default: PB11 PB11 70 I/O 5VT Alternate: TIMER1_CH3, I2C1_SDA, I2S_CKIN, USART2_RX, USBHS_ULPI_D4, EVENTOUT NC 71 - - - VDD 72 P - Default: VDD Default: PB12 PB12 73 I/O 5VT Alternate: TIMER0_BRKIN, I2C1_SMBA, SPI1_NSS, I2S1_WS, USART2_CK, CAN1_RX, USBHS_ULPI_D5, USBHS_ID, EVENTOUT Default: PB13 Alternate: TIMER0_CH0_ON, SPI1_SCK, I2S1_CK, PB13 74 I/O 5VT USART2_CTS, CAN1_TX, USBHS_ULPI_D6, EVENTOUT, I2C1_TXFRAME Additional: USBHS_VBUS Default: PB14 PB14 75 I/O 5VT Alternate: TIMER0_CH1_ON, TIMER7_CH1_ON, SPI1_MISO, I2S1_ADD_SD, USART2_RTS, TIMER11_CH0, USBHS_DM, EVENTOUT Default: PB15 PB15 76 I/O 5VT Alternate: RTC_REFIN, TIMER0_CH2_ON, TIMER7_CH2_ON, SPI1_MOSI, I2S1_SD, TIMER11_CH1, USBHS_DP, EVENTOUT PD8 77 I/O 5VT PD9 78 I/O 5VT PD10 79 I/O 5VT PD11 80 I/O 5VT PD12 81 I/O 5VT PD13 82 I/O 5VT Default: PD8 Alternate: USART2_TX, EVENTOUT Default: PD9 Alternate: USART2_RX, EVENTOUT Default: PD10 Alternate: USART2_CK, EVENTOUT Default: PD11 Alternate: USART2_CTS, EVENTOUT Default: PD12 Alternate: TIMER3_CH0,USART2_RTS , EVENTOUT Default: PD13 21 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: TIMER3_CH1, EVENTOUT VSS 83 P - Default: VSS VDD 84 P - Default: VDD PD14 85 I/O 5VT PD15 86 I/O 5VT PG2 87 I/O 5VT PG3 88 I/O 5VT PG4 89 I/O 5VT PG5 90 I/O 5VT PG6 91 I/O 5VT PG7 92 I/O 5VT PG8 93 I/O 5VT VSS 94 P - Default: VSS VDD 95 P - Default: VDD Default: PD14 Alternate: TIMER3_CH2, EVENTOUT Default: PD15 Alternate: TIMER3_CH3, EVENTOUT, CTC_SYNC Default: PG2 Alternate: EVENTOUT Default: PG3 Alternate: EVENTOUT Default: PG4 Alternate: EVENTOUT Default: PG5 Alternate: EVENTOUT Default: PG6 Alternate: DCI_D12, EVENTOUT Default: PG7 Alternate: USART5_CK, DCI_D13, EVENTOUT Default: PG8 Alternate: USART5_RTS, EVENTOUT Default: PC6 PC6 96 I/O 5VT Alternate: TIMER2_CH0, TIMER7_CH0, I2S1_MCK, USART5_TX, SDIO_D6, DCI_D0, EVENTOUT Default: PC7 PC7 97 I/O 5VT Alternate: TIMER2_CH1, TIMER7_CH1, SPI1_SCK, I2S1_CK, I2S2_MCK, USART5_RX, SDIO_D7, DCI_D1, EVENTOUT Default: PC8 PC8 98 I/O 5VT Alternate: TRACED0, TIMER2_CH2, TIMER7_CH2, USART5_CK, SDIO_D0, DCI_D2, EVENTOUT Default: PC9 PC9 99 I/O 5VT Alternate: CK_OUT1, TIMER2_CH3, TIMER7_CH3, I2C2_SDA, I2S_CKIN, SDIO_D1, DCI_D3, EVENTOUT Default: PA8 PA8 100 I/O 5VT Alternate: CK_OUT0, TIMER0_CH0, I2C2_SCL, USART0_CK, USBFS_SOF, SDIO_D1, EVENTOUT, CTC_SYNC Default: PA9 PA9 101 I/O 5VT Alternate: TIMER0_CH1, I2C2_SMBA, SPI1_SCK, I2S1_CK, USART0_TX, SDIO_D2, DCI_D0, EVENTOUT Additional: USBFS_VBUS 22 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Default: PA10 PA10 102 I/O 5VT Alternate: TIMER0_CH2, I2C2_TXFRAME, USART0_RX, USBFS_ID, DCI_D1, EVENTOUT Default: PA11 PA11 103 I/O 5VT Alternate: TIMER0_CH3, USART0_CTS, USART5_TX, CAN0_RX, USBFS_DM, EVENTOUT Default: PA12 PA12 104 I/O 5VT Alternate: TIMER0_ETI, USART0_RTS, USART5_RX, CAN0_TX, USBFS_DP, EVENTOUT Default: JTMS, SWDIO, PA13 PA13 105 I/O 5VT NC 106 - - - VSS 107 P - Default: VSS VDD 108 P - Default: VDD PA14 109 I/O 5VT Alternate: EVENTOUT Default: JTCK, SWCLK, PA14 Alternate: EVENTOUT Default: JTDI, PA15 PA15 110 I/O 5VT Alternate: TIMER1_CH0, TIMER1_ETI, SPI0_NSS, SPI2_NSS, I2S2_WS, USART0_TX, EVENTOUT Default: PC10 PC10 111 I/O 5VT Alternate: SPI2_SCK, I2S2_CK, USART2_TX, UART3_TX, SDIO_D2, DCI_D8, EVENTOUT Default: PC11 PC11 112 I/O 5VT Alternate: I2S2_ADD_SD, SPI2_MISO, USART2_RX, UART3_RX, SDIO_D3, DCI_D4, EVENTOUT Default: PC12 PC12 113 I/O 5VT Alternate: I2C1_SDA, SPI2_MOSI, I2S2_SD, USART2_CK, UART4_TX, SDIO_CK, DCI_D9, EVENTOUT PD0 114 I/O 5VT PD1 115 I/O 5VT Default: PD0 Alternate: SPI2_MOSI, I2S2_SD, CAN0_RX, EVENTOUT Default: PD1 Alternate: SPI1_NSS, I2S1_WS, CAN0_TX, EVENTOUT Default: PD2 PD2 116 I/O 5VT Alternate: TIMER2_ETI, UART4_RX, SDIO_CMD, DCI_D11, EVENTOUT Default: PD3 PD3 117 I/O 5VT Alternate: TRACED1, SPI1_SCK, I2S1_CK, USART1_CTS, DCI_D5, EVENTOUT PD4 118 I/O 5VT PD5 119 I/O 5VT Default: PD4 Alternate: USART1_RTS, EVENTOUT Default: PD5 Alternate: USART1_TX, EVENTOUT 23 GD32F425xx Datasheet Pin I/O Pin Name Pins Functions description VSS 120 P - Default: VSS VDD 121 P - Default: VDD Type(1) Level(2) Default: PD6 PD6 122 I/O 5VT Alternate: SPI2_MOSI, I2S2_SD, USART1_RX, DCI_D10, EVENTOUT Default: PD7 PD7 123 I/O 5VT PG9 124 I/O 5VT PG10 125 I/O 5VT PG11 126 I/O 5VT PG12 127 I/O 5VT PG13 128 I/O 5VT PG14 129 I/O 5VT VSS 130 P - Default: VSS VDD 131 P - Default: VDD PG15 132 I/O 5VT Alternate: USART1_CK, EVENTOUT Default: PG9 Alternate: USART5_RX, DCI_VSYNC, EVENTOUT Default: PG10 Alternate: DCI_D2, EVENTOUT Default: PG11 Alternate: DCI_D3, EVENTOUT Default: PG12 Alternate: USART5_RTS, EVENTOUT Default: PG13 Alternate: TRACED2, USART5_CTS, EVENTOUT Default: PG14 Alternate:TRACED3, USART5_TX, EVENTOUT Default: PG15 Alternate: USART5_CTS, DCI_D13, EVENTOUT Default: JTDO, PB3 PB3 133 I/O 5VT Alternate: TRACESWO, TIMER1_CH1, SPI0_SCK, SPI2_SCK, I2S2_CK, USART0_RX, I2C1_SDA, EVENTOUT Default: NJTRST, PB4 PB4 134 I/O 5VT Alternate: TIMER2_CH0, I2C0_TXFRAME, SPI0_MISO, SPI2_MISO, I2S2_ADD_SD, I2C2_SDA, SDIO_D0, EVENTOUT Default: PB5 PB5 135 I/O 5VT Alternate: TIMER2_CH1, I2C0_SMBA, SPI0_MOSI, SPI2_MOSI, I2S2_SD, CAN1_RX, USBHS_ULPI_D7, DCI_D10, EVENTOUT Default: PB6 PB6 136 I/O 5VT Alternate: TIMER3_CH0, I2C0_SCL, USART0_TX, CAN1_TX, DCI_D5, EVENTOUT Default: PB7 PB7 137 I/O 5VT Alternate: TIMER3_CH1, I2C0_SDA, USART0_RX, DCI_VSYNC, EVENTOUT BOOT0 138 I/O 5VT Default: BOOT0 PB8 139 I/O 5VT Default: PB8 24 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: TIMER1_CH0, TIMER1_ETI, TIMER3_CH2, TIMER9_CH0, I2C0_SCL, CAN0_RX, SDIO_D4, DCI_D6, EVENTOUT Default: PB9 PB9 140 I/O Alternate: TIMER1_CH1, TIMER3_CH3, TIMER10_CH0, 5VT I2C0_SDA, SPI1_NSS, I2S1_WS, CAN0_TX, SDIO_D5, DCI_D7, EVENTOUT Default: PE0 PE0 141 I/O 5VT PE1 142 I/O 5VT PDR_ON 143 P - Default: PDR_ON VDD 144 P - Default: VDD Alternate: TIMER3_ETI, DCI_D2, EVENTOUT Default: PE1 Alternate: TIMER0_CH1_ON, DCI_D3, EVENTOUT Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. 2.6.2. GD32F425Vx LQFP100 pin definitions Table 2-4. GD32F425Vx LQFP100 pin definitions Pin Name Pins Pin I/O Type(1) Level(2) PE2 1 I/O 5VT PE3 2 I/O 5VT PE4 3 I/O 5VT PE5 4 I/O 5VT PE6 5 I/O 5VT VBAT 6 P - PC13TAMPER- OSC32IN PC15OSC32O Default: PE2 Alternate: TRACECK, EVENTOUT Default: PE3 Alternate: TRACED0, EVENTOUT Default: PE4 Alternate: TRACED1, DCI_D4, EVENTOUT Default: PE5 Alternate: TRACED2, TIMER8_CH0, DCI_D6, EVENTOUT Default: PE6 Alternate: TRACED3, TIMER8_CH1, DCI_D7, EVENTOUT Default: VBAT Default: PC13 7 I/O 5VT RTC PC14- Functions description Alternate: EVENTOUT Additional: RTC_TAMP0, RTC_OUT, RTC_TS Default: PC14 8 I/O 5VT Alternate: EVENTOUT Additional: OSC32IN 9 I/O 5VT Default: PC15 Alternate: EVENTOUT 25 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) UT Additional: OSC32OUT VSS 10 P - Default: VSS VDD 11 P - Default: VDD Default: PH0, OSCIN PH0 12 I/O 5VT Alternate: EVENTOUT Additional: OSCIN Default: PH1, OSCOUT PH1 13 I/O 5VT Alternate: EVENTOUT Additional: OSCOUT NRST 14 - - Default: NRST Default: PC0 PC0 15 I/O 5VT Alternate: USBHS_ULPI_STP, EVENTOUT Additional: ADC012_IN10 Default: PC1 PC1 16 I/O 5VT Alternate: SPI2_MOSI, I2S2_SD, SPI1_MOSI, I2S1_SD, EVENTOUT Additional: ADC012_IN11 Default: PC2 PC2 17 I/O 5VT Alternate: SPI1_MISO, I2S1_ADD_SD, USBHS_ULPI_DIR, EVENTOUT Additional: ADC012_IN12 Default: PC3 PC3 18 I/O 5VT Alternate: SPI1_MOSI, I2S1_SD, USBHS_ULPI_NXT, EVENTOUT Additional: ADC012_IN13 VDD 19 P - Default: VDD VSSA 20 P - Default: VSSA VREF+ 21 P - Default: VREF+ VDDA 22 P - Default: VDDA Default: PA0 PA0WKUP 23 I/O 5VT Alternate: TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI, USART1_CTS, UART3_TX, EVENTOUT Additional: ADC012_IN0, WKUP Default: PA1 PA1 24 I/O 5VT Alternate: TIMER1_CH1, TIMER4_CH1, USART1_RTS, UART3_RX, EVENTOUT Additional: ADC012_IN1 Default: PA2 PA2 25 I/O 5VT Alternate: TIMER1_CH2, TIMER4_CH2, TIMER8_CH0, I2S_CKIN, USART1_TX, EVENTOUT Additional: ADC012_IN2 PA3 26 I/O 5VT Default: PA3 26 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: TIMER1_CH3, TIMER4_CH3, TIMER8_CH1, I2S1_MCK, USART1_RX, USBHS_ULPI_D0, EVENTOUT Additional: ADC012_IN3 VSS 27 P - Default: VSS VDD 28 P - Default: VDD Default: PA4 PA4 29 Alternate: SPI0_NSS, SPI2_NSS, I2S2_WS, USART1_CK, I/O USBHS_SOF, DCI_HSYNC, EVENTOUT Additional: ADC01_IN4, DAC_OUT0 Default: PA5 PA5 30 Alternate: TIMER1_CH0, TIMER1_ETI, TIMER7_CH0_ON, I/O SPI0_SCK, USBHS_ULPI_CK, EVENTOUT Additional: ADC01_IN5, DAC_OUT1 Default: PA6 Alternate: TIMER0_BRKIN, TIMER2_CH0, TIMER7_BRKIN, PA6 31 I/O 5VT SPI0_MISO, I2S1_MCK, TIMER12_CH0, SDIO_CMD, DCI_PIXCLK, EVENTOUT Additional: ADC01_IN6 Default: PA7 PA7 32 I/O 5VT Alternate: TIMER0_CH0_ON, TIMER2_CH1, TIMER7_CH0_ON, SPI0_MOSI, TIMER13_CH0, EVENTOUT Additional: ADC01_IN7 Default: PC4 PC4 33 I/O 5VT Alternate: EVENTOUT Additional: ADC01_IN14 Default: PC5 PC5 34 I/O 5VT Alternate: USART2_RX, EVENTOUT Additional: ADC01_IN15 Default: PB0 Alternate: TIMER0_CH1_ON, TIMER2_CH2, TIMER7_CH1_ON, PB0 35 I/O 5VT SPI2_MOSI, I2S2_SD, USBHS_ULPI_D1, SDIO_D1, EVENTOUT Additional: ADC01_IN8, IREF Default: PB1 PB1 36 I/O 5VT Alternate: TIMER0_CH2_ON, TIMER2_CH3, TIMER7_CH2_ON, USBHS_ULPI_D2, SDIO_D2, EVENTOUT Additional: ADC01_IN9 Default: PB2, BOOT1 PB2 37 I/O 5VT Alternate: TIMER1_CH3, SPI2_MOSI, I2S2_SD, USBHS_ULPI_D4, SDIO_CK, EVENTOUT PE7 38 I/O 5VT Default: PE7 Alternate: TIMER0_ETI, EVENTOUT 27 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) PE8 39 I/O 5VT PE9 40 I/O 5VT PE10 41 I/O 5VT PE11 42 I/O 5VT PE12 43 I/O 5VT PE13 44 I/O 5VT PE14 45 I/O 5VT PE15 46 I/O 5VT Default: PE8 Alternate: TIMER0_CH0_ON, EVENTOUT Default: PE9 Alternate: TIMER0_CH0, EVENTOUT Default: PE10 Alternate: TIMER0_CH1_ON, EVENTOUT Default: PE11 Alternate: TIMER0_CH1, EVENTOUT Default: PE12 Alternate:TIMER0_CH2_ON, EVENTOUT Default: PE13 Alternate: TIMER0_CH2, EVENTOUT Default: PE14 Alternate: TIMER0_CH3, EVENTOUT Default: PE15 Alternate: TIMER0_BRKIN, EVENTOUT Default: PB10 PB10 47 I/O 5VT Alternate: TIMER1_CH2, I2C1_SCL, SPI1_SCK, I2S1_CK, I2S2_MCK, USART2_TX, USBHS_ULPI_D3, SDIO_D7, EVENTOUT Default: PB11 PB11 48 I/O 5VT Alternate: TIMER1_CH3, I2C1_SDA, I2S_CKIN, USART2_RX, USBHS_ULPI_D4, EVENTOUT NC 49 - - - VDD 50 P - Default: VDD Default: PB12 PB12 51 I/O 5VT Alternate: TIMER0_BRKIN, I2C1_SMBA, SPI1_NSS, I2S1_WS, USART2_CK, CAN1_RX, USBHS_ULPI_D5, USBHS_ID, EVENTOUT Default: PB13 Alternate: TIMER0_CH0_ON, SPI1_SCK, I2S1_CK, PB13 52 I/O 5VT USART2_CTS, CAN1_TX, USBHS_ULPI_D6, EVENTOUT, I2C1_TXFRAME Additional: USBHS_VBUS Default: PB14 PB14 53 I/O 5VT Alternate: TIMER0_CH1_ON, TIMER7_CH1_ON, SPI1_MISO, I2S1_ADD_SD, USART2_RTS, TIMER11_CH0, USBHS_DM, EVENTOUT Default: PB15 PB15 54 I/O 5VT Alternate: RTC_REFIN, TIMER0_CH2_ON, TIMER7_CH2_ON, SPI1_MOSI, I2S1_SD, TIMER11_CH1, USBHS_DP, EVENTOUT 28 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) PD8 55 I/O 5VT PD9 56 I/O 5VT PD10 57 I/O 5VT PD11 58 I/O 5VT PD12 59 I/O 5VT PD13 60 I/O 5VT PD14 61 I/O 5VT PD15 62 I/O 5VT Default: PD8 Alternate: USART2_TX, EVENTOUT Default: PD9 Alternate: USART2_RX, EVENTOUT Default: PD10 Alternate: USART2_CK, EVENTOUT Default: PD11 Alternate: USART2_CTS, EVENTOUT Default: PD12 Alternate: TIMER3_CH0, USART2_RTS, EVENTOUT Default: PD13 Alternate: TIMER3_CH1, EVENTOUT Default: PD14 Alternate: TIMER3_CH2, EVENTOUT Default: PD15 Alternate:TIMER3_CH3, EVENTOUT, CTC_SYNC Default: PC6 PC6 63 I/O 5VT Alternate: TIMER2_CH0, TIMER7_CH0, I2S1_MCK, USART5_TX, SDIO_D6, DCI_D0, EVENTOUT Default: PC7 PC7 64 I/O 5VT Alternate: TIMER2_CH1, TIMER7_CH1, SPI1_SCK, I2S1_CK, I2S2_MCK, USART5_RX, SDIO_D7, DCI_D1, EVENTOUT Default: PC8 PC8 65 I/O 5VT Alternate: TRACED0, TIMER2_CH2, TIMER7_CH2, USART5_CK, SDIO_D0, DCI_D2, EVENTOUT Default: PC9 PC9 66 I/O 5VT Alternate: CK_OUT1, TIMER2_CH3, TIMER7_CH3, I2C2_SDA, I2S_CKIN, SDIO_D1, DCI_D3, EVENTOUT Default: PA8 PA8 67 I/O 5VT Alternate: CK_OUT0, TIMER0_CH0, I2C2_SCL, USART0_CK, USBFS_SOF, SDIO_D1, EVENTOUT, CTC_SYNC Default: PA9 PA9 68 I/O 5VT Alternate: TIMER0_CH1, I2C2_SMBA, SPI1_SCK, I2S1_CK, USART0_TX, SDIO_D2, DCI_D0, EVENTOUT Additional: USBFS_VBUS Default: PA10 PA10 69 I/O 5VT Alternate: TIMER0_CH2, USART0_RX, USBFS_ID, DCI_D1, EVENTOUT, I2C2_TXFRAME Default: PA11 PA11 70 I/O 5VT Alternate: TIMER0_CH3, USART0_CTS, USART5_TX, CAN0_RX, USBFS_DM, EVENTOUT PA12 71 I/O 5VT Default: PA12 29 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: TIMER0_ETI, USART0_RTS, USART5_RX, CAN0_TX, USBFS_DP, EVENTOUT Default: JTMS, SWDIO, PA13 PA13 72 I/O 5VT NC 73 - - - VSS 74 P - Default: VSS VDD 75 P - Default: VDD PA14 76 I/O 5VT Alternate: EVENTOUT Default: JTCK, SWCLK, PA14 Alternate: EVENTOUT Default: JTDI, PA15 PA15 77 I/O 5VT Alternate: TIMER1_CH0, TIMER1_ETI, SPI0_NSS, SPI2_NSS, I2S2_WS, USART0_TX, EVENTOUT Default: PC10 PC10 78 I/O 5VT Alternate: SPI2_SCK, I2S2_CK, USART2_TX, UART3_TX, SDIO_D2, DCI_D8, EVENTOUT Default: PC11 PC11 79 I/O 5VT Alternate: I2S2_ADD_SD, SPI2_MISO, USART2_RX, UART3_RX, SDIO_D3, DCI_D4, EVENTOUT Default: PC12 PC12 80 I/O 5VT Alternate: I2C1_SDA, SPI2_MOSI, I2S2_SD, USART2_CK, UART4_TX, SDIO_CK, DCI_D9, EVENTOUT PD0 81 I/O 5VT PD1 82 I/O 5VT Default: PD0 Alternate: SPI2_MOSI, I2S2_SD, CAN0_RX, EVENTOUT Default: PD1 Alternate: SPI1_NSS, I2S1_WS, CAN0_TX, EVENTOUT Default: PD2 PD2 83 I/O 5VT Alternate: TIMER2_ETI, UART4_RX, SDIO_CMD, DCI_D11, EVENTOUT Default: PD3 PD3 84 I/O 5VT Alternate: TRACED1, SPI1_SCK, I2S1_CK, USART1_CTS, DCI_D5, EVENTOUT PD4 85 I/O 5VT PD5 86 I/O 5VT Default: PD4 Alternate: USART1_RTS, EVENTOUT Default: PD5 Alternate: USART1_TX, EVENTOUT Default: PD6 PD6 87 I/O 5VT Alternate: SPI2_MOSI, I2S2_SD, USART1_RX, DCI_D10, EVENTOUT PD7 88 I/O 5VT PB3 89 I/O 5VT Default: PD7 Alternate: USART1_CK, EVENTOUT Default: JTDO, PB3 Alternate: TRACESWO, TIMER1_CH1, SPI0_SCK, SPI2_SCK, 30 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) I2S2_CK, USART0_RX, I2C1_SDA, EVENTOUT Default: NJTRST, PB4 PB4 90 I/O 5VT Alternate: TIMER2_CH0, SPI0_MISO, SPI2_MISO, I2S2_ADD_SD, I2C2_SDA, SDIO_D0, EVENTOUT, I2C0_TXFRAME Default: PB5 PB5 91 I/O 5VT Alternate: TIMER2_CH1, I2C0_SMBA, SPI0_MOSI, SPI2_MOSI, I2S2_SD, CAN1_RX, USBHS_ULPI_D7, DCI_D10, EVENTOUT Default: PB6 PB6 92 I/O 5VT Alternate: TIMER3_CH0, I2C0_SCL, USART0_TX, CAN1_TX, DCI_D5, EVENTOUT Default: PB7 PB7 93 I/O 5VT Alternate: TIMER3_CH1, I2C0_SDA, USART0_RX, DCI_VSYNC, EVENTOUT BOOT0 94 I/O 5VT Default: BOOT0 Default: PB8 PB8 95 I/O 5VT Alternate: TIMER1_CH0, TIMER1_ETI, TIMER3_CH2, TIMER9_CH0, I2C0_SCL, CAN0_RX, SDIO_D4, DCI_D6, EVENTOUT Default: PB9 PB9 96 I/O 5VT Alternate: TIMER1_CH1, TIMER3_CH3, TIMER10_CH0, I2C0_SDA, SPI1_NSS, I2S1_WS, CAN0_TX, SDIO_D5, DCI_D7, EVENTOUT Default: PE0 PE0 97 I/O 5VT PE1 98 I/O 5VT VSS 99 P - Default: VSS VDD 100 P - Default: VDD Alternate: TIMER3_ETI, DCI_D2, EVENTOUT Default: PE1 Alternate: TIMER0_CH1_ON, DCI_D3, EVENTOUT Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. 2.6.3. GD32F425Vx BGA100 pin definitions Table 2-5. GD32F425Vx BGA100 pin definitions Pin I/O Type(1) Level(2) B2 I/O 5VT A1 I/O 5VT Pin Name Pins PE2 PE3 Functions description Default: PE2 Alternate: TRACECK, EVENTOUT Default: PE3 31 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate:TRACED0, EVENTOUT PE4 B1 I/O 5VT PE5 C2 I/O 5VT PE6 D2 I/O 5VT VBAT E2 P - PC13TAMPER- OSC32IN C1 I/O 5VT Default: PE5 Alternate: TRACED2, TIMER8_CH0, DCI_D6, EVENTOUT Default: PE6 Alternate: TRACED3, TIMER8_CH1, DCI_D7, EVENTOUT Default: VBAT Alternate: EVENTOUT Additional: RTC_TAMP0, RTC_OUT, RTC_TS Default: PC14 D1 I/O 5VT Alternate: EVENTOUT Additional: OSC32IN PC15OSC32OU Alternate: TRACED1, DCI_D4, EVENTOUT Default: PC13 RTC PC14- Default: PE4 Default: PC15 E1 I/O 5VT T Alternate: EVENTOUT Additional: OSC32OUT VSS F2 P - Default: VSS VDD G2 P - Default: VDD Default: PH0, OSCIN PH0 F1 I/O 5VT Alternate: EVENTOUT Additional: OSCIN Default: PH1, OSCOUT PH1 G1 I/O 5VT Alternate: EVENTOUT Additional: OSCOUT NRST H2 - - Default: NRST Default: PC0 PC0 H1 I/O 5VT Alternate: USBHS_ULPI_STP, EVENTOUT Additional: ADC012_IN10 Default: PC1 PC1 J2 I/O 5VT Alternate: SPI2_MOSI, I2S2_SD, SPI1_MOSI, I2S1_SD, EVENTOUT Additional: ADC012_IN11 Default: PC2 PC2 J3 I/O 5VT Alternate: SPI1_MISO, I2S1_ADD_SD, USBHS_ULPI_DIR, EVENTOUT Additional: ADC012_IN12 Default: PC3 PC3 K2 I/O 5VT Alternate: SPI1_MOSI, I2S1_SD, USBHS_ULPI_NXT, EVENTOUT Additional: ADC012_IN13 VSSA J1 P - Default: VSSA 32 GD32F425xx Datasheet Pin I/O Pin Name Pins Functions description VREFN K1 P - Default: VREF- VREFP L1 P - Default: VREF+ VDDA M1 P - Default: VDDA Type(1) Level(2) Default: PA0 PA0WKUP L2 I/O 5VT Alternate: TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI, USART1_CTS, UART3_TX, EVENTOUT Additional: ADC012_IN0, WKUP Default: PA1 PA1 M2 I/O 5VT Alternate: TIMER1_CH1, TIMER4_CH1, USART1_RTS, UART3_RX, EVENTOUT Additional: ADC012_IN1 Default: PA2 PA2 K3 I/O 5VT Alternate: TIMER1_CH2, TIMER4_CH2, TIMER8_CH0, I2S_CKIN, USART1_TX, EVENTOUT Additional: ADC012_IN2 Default: PA3 PA3 L3 I/O 5VT Alternate: TIMER1_CH3, TIMER4_CH3, TIMER8_CH1, I2S1_MCK, USART1_RX, USBHS_ULPI_D0, EVENTOUT Additional: ADC012_IN3 NC E3 - - Default: PA4 PA4 M3 Alternate: SPI0_NSS, SPI2_NSS, I2S2_WS, USART1_CK, I/O USBHS_SOF, DCI_HSYNC, EVENTOUT Additional: ADC01_IN4, DAC_OUT0 Default: PA5 PA5 K4 Alternate: TIMER1_CH0, TIMER1_ETI, TIMER7_CH0_ON, I/O SPI0_SCK, USBHS_ULPI_CK, EVENTOUT Additional: ADC01_IN5, DAC_OUT1 Default: PA6 Alternate: TIMER0_BRKIN, TIMER2_CH0, TIMER7_BRKIN, PA6 L4 I/O 5VT SPI0_MISO, I2S1_MCK, TIMER12_CH0, SDIO_CMD, DCI_PIXCLK, EVENTOUT Additional: ADC01_IN6 Default: PA7 PA7 M4 I/O 5VT Alternate: TIMER0_CH0_ON, TIMER2_CH1, TIMER7_CH0_ON, SPI0_MOSI, TIMER13_CH0, EVENTOUT Additional: ADC01_IN7 Default: PC4 PC4 K5 I/O 5VT Alternate: EVENTOUT Additional: ADC01_IN14 PC5 L5 I/O 5VT Default: PC5 Alternate: USART2_RX, EVENTOUT 33 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Additional: ADC01_IN15 Default: PB0 Alternate: TIMER0_CH1_ON, TIMER2_CH2, PB0 M5 I/O 5VT TIMER7_CH1_ON, SPI2_MOSI, I2S2_SD, USBHS_ULPI_D1, SDIO_D1, EVENTOUT Additional: ADC01_IN8, IREF Default: PB1 PB1 M6 I/O 5VT Alternate: TIMER0_CH2_ON, TIMER2_CH3, TIMER7_CH2_ON, USBHS_ULPI_D2, SDIO_D2, EVENTOUT Additional: ADC01_IN9 Default: PB2, BOOT1 PB2 L6 I/O 5VT Alternate: TIMER1_CH3, SPI2_MOSI, I2S2_SD, USBHS_ULPI_D4, SDIO_CK, EVENTOUT PE7 M7 I/O 5VT PE8 L7 I/O 5VT PE9 M8 I/O 5VT PE10 L8 I/O 5VT PE11 M9 I/O 5VT PE12 L9 I/O 5VT PE13 M10 I/O 5VT PE14 M11 I/O 5VT PE15 M12 I/O 5VT Default: PE7 Alternate: TIMER0_ETI, EVENTOUT Default: PE8 Alternate: TIMER0_CH0_ON, EVENTOUT Default: PE9 Alternate: TIMER0_CH0, EVENTOUT Default: PE10 Alternate: TIMER0_CH1_ON, EVENTOUT Default: PE11 Alternate: TIMER0_CH1, EVENTOUT Default: PE12 Alternate: TIMER0_CH2_ON, EVENTOUT Default: PE13 Alternate: TIMER0_CH2, EVENTOUT Default: PE14 Alternate: TIMER0_CH3, EVENTOUT Default: PE15 Alternate: TIMER0_BRKIN, EVENTOUT Default: PB10 PB10 L10 I/O 5VT Alternate: TIMER1_CH2, I2C1_SCL, SPI1_SCK, I2S1_CK, I2S2_MCK, USART2_TX, USBHS_ULPI_D3, SDIO_D7, EVENTOUT Default: PB11 PB11 K9 I/O 5VT Alternate: TIMER1_CH3, I2C1_SDA, I2S_CKIN, USART2_RX, USBHS_ULPI_D4, EVENTOUT NC L11 - - - VSS F12 P - Default: VSS VDD G12 P - Default: VDD PB12 L12 I/O 5VT Default: PB12 34 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: TIMER0_BRKIN, I2C1_SMBA, SPI1_NSS, I2S1_WS, USART2_CK, CAN1_RX, USBHS_ULPI_D5, USBHS_ID, EVENTOUT Default: PB13 Alternate: TIMER0_CH0_ON, SPI1_SCK, I2S1_CK, PB13 K12 I/O 5VT USART2_CTS, CAN1_TX, USBHS_ULPI_D6, EVENTOUT, I2C1_TXFRAME Additional: USBHS_VBUS Default: PB14 PB14 K11 I/O 5VT Alternate: TIMER0_CH1_ON, TIMER7_CH1_ON, SPI1_MISO, I2S1_ADD_SD, USART2_RTS, TIMER11_CH0, USBHS_DM, EVENTOUT Default: PB15 PB15 K10 I/O 5VT Alternate: RTC_REFIN, TIMER0_CH2_ON, TIMER7_CH2_ON, SPI1_MOSI, I2S1_SD, TIMER11_CH1, USBHS_DP, EVENTOUT PD9 K8 I/O 5VT PD10 J12 I/O 5VT PD11 J11 I/O 5VT PD12 J10 I/O 5VT PD13 H12 I/O 5VT PD14 H11 I/O 5VT PD15 H10 I/O 5VT Default: PD9 Alternate: USART2_RX, EVENTOUT Default: PD10 Alternate: USART2_CK, EVENTOUT Default: PD11 Alternate: USART2_CTS, EVENTOUT Default: PD12 Alternate: TIMER3_CH0, USART2_RTS, EVENTOUT Default: PD13 Alternate: TIMER3_CH1, EVENTOUT Default: PD14 Alternate: TIMER3_CH2, EVENTOUT Default: PD15 Alternate: TIMER3_CH3, EVENTOUT, CTC_SYNC Default: PC6 PC6 E12 I/O 5VT Alternate: TIMER2_CH0, TIMER7_CH0, I2S1_MCK, USART5_TX, SDIO_D6, DCI_D0, EVENTOUT Default: PC7 PC7 E11 I/O 5VT Alternate: TIMER2_CH1, TIMER7_CH1, SPI1_SCK, I2S1_CK, I2S2_MCK, USART5_RX, SDIO_D7, DCI_D1, EVENTOUT Default: PC8 PC8 E10 I/O 5VT Alternate: TRACED0, TIMER2_CH2, TIMER7_CH2, USART5_CK, SDIO_D0, DCI_D2, EVENTOUT Default: PC9 PC9 D12 I/O 5VT Alternate: CK_OUT1, TIMER2_CH3, TIMER7_CH3, I2C2_SDA, I2S_CKIN, SDIO_D1, DCI_D3, EVENTOUT 35 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Default: PA8 PA8 D11 I/O 5VT Alternate: CK_OUT0, TIMER0_CH0, I2C2_SCL, USART0_CK, USBFS_SOF, SDIO_D1, EVENTOUT, CTC_SYNC Default: PA9 PA9 D10 I/O 5VT Alternate: TIMER0_CH1, I2C2_SMBA, SPI1_SCK, I2S1_CK, USART0_TX, SDIO_D2, DCI_D0, EVENTOUT Additional: USBFS_VBUS Default: PA10 PA10 C12 I/O 5VT Alternate: TIMER0_CH2, USART0_RX, USBFS_ID, DCI_D1, EVENTOUT, I2C2_TXFRAME Default: PA11 PA11 B12 I/O 5VT Alternate: TIMER0_CH3, USART0_CTS, USART5_TX, CAN0_RX, USBFS_DM, EVENTOUT Default: PA12 PA12 A12 I/O 5VT Alternate: TIMER0_ETI, USART0_RTS, USART5_RX, CAN0_TX, USBFS_DP, EVENTOUT Default: JTMS, SWDIO, PA13 PA13 A11 I/O 5VT NC C11 - - - VSS F11 P - Default: VSS VDD G11 P - Default: VDD PA14 A10 I/O 5VT Alternate: EVENTOUT Default: JTCK, SWCLK, PA14 Alternate: EVENTOUT Default: JTDI, PA15 PA15 A9 I/O 5VT Alternate: TIMER1_CH0, TIMER1_ETI, SPI0_NSS, SPI2_NSS, I2S2_WS, USART0_TX, EVENTOUT Default: PC10 PC10 B11 I/O 5VT Alternate: SPI2_SCK, I2S2_CK, USART2_TX, UART3_TX, SDIO_D2, DCI_D8, EVENTOUT Default: PC11 PC11 C10 I/O 5VT Alternate: I2S2_ADD_SD, SPI2_MISO, USART2_RX, UART3_RX, SDIO_D3, DCI_D4, EVENTOUT Default: PC12 PC12 B10 I/O 5VT Alternate: I2C1_SDA, SPI2_MOSI, I2S2_SD, USART2_CK, UART4_TX, SDIO_CK, DCI_D9, EVENTOUT PD0 C9 I/O 5VT PD1 B9 I/O 5VT PD2 C8 I/O 5VT Default: PD0 Alternate: SPI2_MOSI, I2S2_SD, CAN0_RX, EVENTOUT Default: PD1 Alternate: SPI1_NSS, I2S1_WS, CAN0_TX, EVENTOUT Default: PD2 Alternate: TIMER2_ETI, UART4_RX, SDIO_CMD, DCI_D11, EVENTOUT 36 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Default: PD3 PD3 B8 I/O 5VT Alternate: TRACED1, SPI1_SCK, I2S1_CK, USART1_CTS, DCI_D5, EVENTOUT PD4 B7 I/O 5VT PD5 A6 I/O 5VT Default: PD4 Alternate: USART1_RTS, EVENTOUT Default: PD5 Alternate: USART1_TX, EVENTOUT Default: PD6 PD6 B6 I/O 5VT Alternate: SPI2_MOSI, I2S2_SD, USART1_RX, DCI_D10, EVENTOUT PD7 A5 I/O 5VT Default: PD7 Alternate: USART1_CK, EVENTOUT Default: JTDO, PB3 PB3 A8 I/O 5VT Alternate: TRACESWO, TIMER1_CH1, SPI0_SCK, SPI2_SCK, I2S2_CK, USART0_RX, I2C1_SDA, EVENTOUT Default: NJTRST, PB4 PB4 A7 I/O 5VT Alternate: TIMER2_CH0, SPI0_MISO, SPI2_MISO, I2S2_ADD_SD, I2C2_SDA, SDIO_D0, EVENTOUT, I2C0_TXFRAME Default: PB5 PB5 C5 I/O 5VT Alternate: TIMER2_CH1, I2C0_SMBA, SPI0_MOSI, SPI2_MOSI, I2S2_SD, CAN1_RX, USBHS_ULPI_D7, DCI_D10, EVENTOUT Default: PB6 PB6 B5 I/O 5VT Alternate: TIMER3_CH0, I2C0_SCL, USART0_TX, CAN1_TX, DCI_D5, EVENTOUT Default: PB7 PB7 B4 I/O 5VT Alternate: TIMER3_CH1, I2C0_SDA, USART0_RX, DCI_VSYNC, EVENTOUT BOOT0 A4 I/O 5VT Default: BOOT0 Default: PB8 PB8 A3 I/O 5VT Alternate: TIMER1_CH0, TIMER1_ETI, TIMER3_CH2, TIMER9_CH0, I2C0_SCL, CAN0_RX, SDIO_D4, DCI_D6, EVENTOUT Default: PB9 PB9 B3 I/O 5VT Alternate: TIMER1_CH1, TIMER3_CH3, TIMER10_CH0, I2C0_SDA, SPI1_NSS, I2S1_WS, CAN0_TX, SDIO_D5, DCI_D7, EVENTOUT PE0 C3 I/O 5VT PE1 A2 I/O 5VT Default: PE0 Alternate: TIMER3_ETI, DCI_D2, EVENTOUT Default: PE1 Alternate: TIMER0_CH1_ON, DCI_D3, EVENTOUT 37 GD32F425xx Datasheet Pin I/O Pin Name Pins Functions description VSS D3 P - Default: VSS PDR_ON H3 P - Default: PDR_ON VDD C4 P - Default: VDD Type(1) Level(2) Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. 2.6.4. GD32F425Rx LQFP64 pin definitions Table 2-6. GD32F425Rx LQFP64 pin definitions Pin Name Pins VBAT 1 Pin I/O Type(1) Level(2) P - PC13TAMPER- OSC32IN 2 I/O 5VT Alternate: EVENTOUT Additional: RTC_TAMP0, RTC_OUT, RTC_TS Default: PC14 3 I/O 5VT Alternate: EVENTOUT Additional: OSC32IN PC15OSC32OU Default: VBAT Default: PC13 RTC PC14- Functions description Default: PC15 4 I/O 5VT T Alternate: EVENTOUT Additional: OSC32OUT Default: PH0, OSCIN PH0 5 I/O 5VT Alternate: EVENTOUT Additional: OSCIN Default: PH1, OSCOUT PH1 6 I/O 5VT Alternate: EVENTOUT Additional: OSCOUT NRST 7 - - Default: NRST Default: PC0 PC0 8 I/O 5VT Alternate: USBHS_ULPI_STP, EVENTOUT Additional: ADC012_IN10 Default: PC1 PC1 9 I/O 5VT Alternate: SPI2_MOSI, I2S2_SD, SPI1_MOSI, I2S1_SD, EVENTOUT Additional: ADC012_IN11 Default: PC2 PC2 10 I/O 5VT Alternate: SPI1_MISO, I2S1_ADD_SD, USBHS_ULPI_DIR, EVENTOUT Additional: ADC012_IN12 PC3 11 I/O 5VT Default: PC3 38 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: SPI1_MOSI, I2S1_SD, USBHS_ULPI_NXT, EVENTOUT Additional: ADC012_IN13 VSSA 12 P - Default: VSSA VDDA 13 P - Default: VDDA Default: PA0 PA0WKUP 14 I/O 5VT Alternate: TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI, USART1_CTS, UART3_TX, EVENTOUT Additional: ADC012_IN0, WKUP Default: PA1 PA1 15 I/O 5VT Alternate: TIMER1_CH1, TIMER4_CH1, USART1_RTS, UART3_RX, EVENTOUT Additional: ADC012_IN1 Default: PA2 PA2 16 I/O 5VT Alternate: TIMER1_CH2, TIMER4_CH2, TIMER8_CH0, I2S_CKIN, USART1_TX, EVENTOUT Additional: ADC012_IN2 Default: PA3 PA3 17 I/O 5VT Alternate: TIMER1_CH3, TIMER4_CH3, TIMER8_CH1, I2S1_MCK, USART1_RX, USBHS_ULPI_D0, EVENTOUT Additional: ADC012_IN3 VSS 18 P - Default: VSS VDD 19 P - Default: VDD Default: PA4 PA4 20 Alternate: SPI0_NSS, SPI2_NSS, I2S2_WS, USART1_CK, I/O USBHS_SOF, DCI_HSYNC, EVENTOUT Additional: ADC01_IN4, DAC_OUT0 Default: PA5 PA5 21 Alternate: TIMER1_CH0, TIMER1_ETI, TIMER7_CH0_ON, I/O SPI0_SCK, USBHS_ULPI_CK, EVENTOUT Additional: ADC01_IN5, DAC_OUT1 Default: PA6 Alternate: TIMER0_BRKIN, TIMER2_CH0, TIMER7_BRKIN, PA6 22 I/O 5VT SPI0_MISO, I2S1_MCK, TIMER12_CH0, SDIO_CMD, DCI_PIXCLK, EVENTOUT Additional: ADC01_IN6 Default: PA7 PA7 23 I/O 5VT Alternate: TIMER0_CH0_ON, TIMER2_CH1, TIMER7_CH0_ON, SPI0_MOSI, TIMER13_CH0, EVENTOUT Additional: ADC01_IN7 PC4 24 I/O 5VT Default: PC4 Alternate: EVENTOUT 39 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Additional: ADC01_IN14 Default: PC5 PC5 25 I/O 5VT Alternate: USART2_RX, EVENTOUT Additional: ADC01_IN15 Default: PB0 Alternate: TIMER0_CH1_ON, TIMER2_CH2, TIMER7_CH1_ON, PB0 26 I/O 5VT SPI2_MOSI, I2S2_SD, USBHS_ULPI_D1, SDIO_D1, EVENTOUT Additional: ADC01_IN8, IREF Default: PB1 PB1 27 I/O 5VT Alternate: TIMER0_CH2_ON, TIMER2_CH3, TIMER7_CH2_ON, USBHS_ULPI_D2, SDIO_D2, EVENTOUT Additional: ADC01_IN9 Default: PB2, BOOT1 PB2 28 I/O 5VT Alternate: TIMER1_CH3, SPI2_MOSI, I2S2_SD, USBHS_ULPI_D4, SDIO_CK, EVENTOUT Default: PB10 PB10 29 I/O 5VT Alternate: TIMER1_CH2, I2C1_SCL, SPI1_SCK, I2S1_CK, I2S2_MCK, USART2_TX, USBHS_ULPI_D3, SDIO_D7, EVENTOUT Default: PB11 PB11 30 I/O 5VT Alternate: TIMER1_CH3, I2C1_SDA, I2S_CKIN, USART2_RX, USBHS_ULPI_D4, EVENTOUT NC 31 - - - VDD 32 P - Default: VDD Default: PB12 PB12 33 I/O 5VT Alternate: TIMER0_BRKIN, I2C1_SMBA, SPI1_NSS, I2S1_WS, USART2_CK, CAN1_RX, USBHS_ULPI_D5, USBHS_ID, EVENTOUT Default: PB13 Alternate: TIMER0_CH0_ON, SPI1_SCK, I2S1_CK, PB13 34 I/O 5VT USART2_CTS, CAN1_TX, USBHS_ULPI_D6, EVENTOUT, I2C1_TXFRAME Additional: USBHS_VBUS Default: PB14 PB14 35 I/O 5VT Alternate: TIMER0_CH1_ON, TIMER7_CH1_ON, SPI1_MISO, I2S1_ADD_SD, USART2_RTS, TIMER11_CH0, USBHS_DM, EVENTOUT Default: PB15 PB15 36 I/O 5VT Alternate: RTC_REFIN, TIMER0_CH2_ON, TIMER7_CH2_ON, SPI1_MOSI, I2S1_SD, TIMER11_CH1, USBHS_DP, EVENTOUT PC6 37 I/O 5VT Default: PC6 40 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: TIMER2_CH0, TIMER7_CH0, I2S1_MCK, USART5_TX, SDIO_D6, DCI_D0, EVENTOUT Default: PC7 PC7 38 I/O 5VT Alternate: TIMER2_CH1, TIMER7_CH1, SPI1_SCK, I2S1_CK, I2S2_MCK, USART5_RX, SDIO_D7, DCI_D1, EVENTOUT Default: PC8 PC8 39 I/O 5VT Alternate: TRACED0, TIMER2_CH2, TIMER7_CH2, USART5_CK, SDIO_D0, DCI_D2, EVENTOUT Default: PC9 PC9 40 I/O 5VT Alternate: CK_OUT1, TIMER2_CH3, TIMER7_CH3, I2C2_SDA, I2S_CKIN, SDIO_D1, DCI_D3, EVENTOUT Default: PA8 PA8 41 I/O 5VT Alternate: CK_OUT0, TIMER0_CH0, I2C2_SCL, USART0_CK, USBFS_SOF, SDIO_D1, EVENTOUT, CTC_SYNC Default: PA9 PA9 42 I/O 5VT Alternate: TIMER0_CH1, I2C2_SMBA, SPI1_SCK, I2S1_CK, USART0_TX, SDIO_D2, DCI_D0, EVENTOUT Additional: USBFS_VBUS Default: PA10 PA10 43 I/O 5VT Alternate: TIMER0_CH2, USART0_RX, USBFS_ID, DCI_D1, EVENTOUT, I2C2_TXFRAME Default: PA11 PA11 44 I/O 5VT Alternate: TIMER0_CH3, USART0_CTS, USART5_TX, CAN0_RX, USBFS_DM, EVENTOUT Default: PA12 PA12 45 I/O 5VT Alternate: TIMER0_ETI, USART0_RTS, USART5_RX, CAN0_TX, USBFS_DP, EVENTOUT Default: JTMS, SWDIO, PA13 PA13 46 I/O 5VT NC 47 - - - VSS - P - Default: VSS VDD 48 P - Default: VDD PA14 49 I/O 5VT Alternate: EVENTOUT Default: JTCK, SWCLK, PA14 Alternate: EVENTOUT Default: JTDI, PA15 PA15 50 I/O 5VT Alternate: TIMER1_CH0, TIMER1_ETI, SPI0_NSS, SPI2_NSS, I2S2_WS, USART0_TX, EVENTOUT Default: PC10 PC10 51 I/O 5VT Alternate: SPI2_SCK, I2S2_CK, USART2_TX, UART3_TX, SDIO_D2, DCI_D8, EVENTOUT PC11 52 I/O 5VT Default: PC11 Alternate: I2S2_ADD_SD, SPI2_MISO, USART2_RX, 41 GD32F425xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) UART3_RX, SDIO_D3, DCI_D4, EVENTOUT Default: PC12 PC12 53 I/O 5VT Alternate: I2C1_SDA, SPI2_MOSI, I2S2_SD, USART2_CK, UART4_TX, SDIO_CK, DCI_D9, EVENTOUT Default: PD2 PD2 54 I/O 5VT Alternate: TIMER2_ETI, UART4_RX, SDIO_CMD, DCI_D11, EVENTOUT Default: JTDO, PB3 PB3 55 I/O 5VT Alternate: TRACESWO, TIMER1_CH1, SPI0_SCK, SPI2_SCK, I2S2_CK, USART0_RX, I2C1_SDA, EVENTOUT Default: NJTRST, PB4 PB4 56 I/O 5VT Alternate: TIMER2_CH0, SPI0_MISO, SPI2_MISO, I2S2_ADD_SD, I2C2_SDA, SDIO_D0, EVENTOUT, I2C0_TXFRAME Default: PB5 PB5 57 I/O 5VT Alternate: TIMER2_CH1, I2C0_SMBA, SPI0_MOSI, SPI2_MOSI, I2S2_SD, CAN1_RX, USBHS_ULPI_D7, DCI_D10, EVENTOUT Default: PB6 PB6 58 I/O 5VT Alternate: TIMER3_CH0, I2C0_SCL, USART0_TX, CAN1_TX, DCI_D5, EVENTOUT Default: PB7 PB7 59 I/O 5VT Alternate: TIMER3_CH1, I2C0_SDA, USART0_RX, DCI_VSYNC, EVENTOUT BOOT0 60 I/O 5VT Default: BOOT0 Default: PB8 PB8 61 I/O 5VT Alternate: TIMER1_CH0, TIMER1_ETI, TIMER3_CH2, TIMER9_CH0, I2C0_SCL, CAN0_RX, SDIO_D4, DCI_D6, EVENTOUT Default: PB9 PB9 62 I/O 5VT Alternate: TIMER1_CH1, TIMER3_CH3, TIMER10_CH0, I2C0_SDA, SPI1_NSS, I2S1_WS, CAN0_TX, SDIO_D5, DCI_D7, EVENTOUT VSS 63 P - Default: VSS VDD 64 P - Default: VDD Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. 42 GD32F425xx pin alternate functions 2.6.5. Table 2-7. Port A alternate functions summary Pin Name PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 AF0 AF1 TIMER1_C H0/TIMER 1_ETI TIMER1_C H1 TIMER1_C H2 TIMER1_C H3 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 TIMER4_C TIMER7_E H0 TI USART1_ UART3_T CTS X EVENTOU T TIMER4_C H1 TIMER4_C TIMER8_C H2 H0 TIMER4_C TIMER8_C H3 H1 USART1_ UART3_R RTS X USART1_ I2S_CKIN TX USART1_ I2S1_MCK RX SPI2_NSS USART1_ SPI0_NSS /I2S2_WS CK EVENTOU T EVENTOU T EVENTOU T EVENTOU T USBHS_U LPI_D0 TIMER1_C TIMER7_C USBHS_U H0/TIMER SPI0_SCK H0_ON LPI_CK 1_ETI TIMER0_B TIMER2_C TIMER7_B SPI0_MIS TIMER12_ I2S1_MCK RKIN H0 RKIN O CH0 TIMER0_C TIMER2_C TIMER7_C SPI0_MO TIMER13_ H0_ON H1 H0_ON SI CH0 TIMER0_C USART0_ CTC_SYN USBFS_S CK_OUT0 I2C2_SCL H0 CK C OF TIMER0_C I2C2_SMB SPI1_SCK USART0_ H1 A /I2S1_CK TX TIMER0_C I2C2_TXF USART0_ USBFS_ID H2 RAME RX TIMER0_C USART0_ USART5_ USBFS_D CAN0_RX H3 CTS TX M TIMER0_E USART0_ USART5_ USBFS_D CAN0_TX TI RTS RX P JTMS/SW DIO JTCK/SW CLK TIMER1_C SPI2_NSS USART0_ JTDI H0/TIMER SPI0_NSS /I2S2_WS TX 1_ETI USBHS_S DCI_HSY OF NC EVENTOU T SDIO_CM DCI_PIXC D LK SDIO_D1 SDIO_D2 DCI_D0 DCI_D1 EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T GD32F425xx Table 2-8. Port B alternate functions summary Pin Name AF0 AF1 AF2 AF3 PB0 TIMER0_C TIMER2_C TIMER7_C H1_ON H2 H1_ON PB1 TIMER0_C TIMER2_C TIMER7_C H2_ON H3 H2_ON PB2 TIMER1_C H3 PB3 JTDO/TRA TIMER1_C CESWO H1 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 NJTRST TIMER2_C H0 TIMER2_C H1 TIMER3_C H0 TIMER3_C H1 AF4 AF5 AF6 AF7 AF8 AF9 SPI2_MO SI/I2S2_S D SPI2_MO SI/I2S2_S D SPI2_SCK USART0_ SPI0_SCK /I2S2_CK RX I2C0_TXF SPI0_MIS SPI2_MIS I2S2_ADD RAME O O _SD SPI2_MO I2C0_SMB SPI0_MO SI/I2S2_S A SI D USART0_ I2C0_SCL TX USART0_ I2C0_SDA RX TIMER1_C TIMER3_C TIMER9_C H0/TIMER I2C0_SCL H2 H0 1_ETI TIMER1_C TIMER3_C TIMER10_ SPI1_NSS I2C0_SDA H1 H3 CH0 /I2S1_WS TIMER1_C SPI1_SCK USART2_ I2C1_SCL I2S2_MCK H2 /I2S1_CK TX TIMER1_C USART2_ I2C1_SDA I2S_CKIN H3 RX TIMER0_B I2C1_SMB SPI1_NSS USART2_ RKIN A /I2S1_WS CK TIMER0_C I2C1_TXF SPI1_SCK USART2_ H0_ON RAME /I2S1_CK CTS TIMER0_C TIMER7_C SPI1_MIS I2S1_ADD USART2_ H1_ON H1_ON O _SD RTS SPI1_MO RTC_REFI TIMER0_C TIMER7_C SI/I2S1_S N H2_ON H2_ON D AF10 AF11 AF12 AF13 AF15 USBHS_U LPI_D1 SDIO_D1 EVENTOU T USBHS_U LPI_D2 SDIO_D2 EVENTOU T USBHS_U LPI_D4 SDIO_CK EVENTOU T EVENTOU T EVENTOU T I2C1_SDA I2C2_SDA CAN1_RX AF14 SDIO_D0 USBHS_U LPI_D7 DCI_D10 CAN1_TX DCI_D5 DCI_VSY NC CAN0_RX SDIO_D4 DCI_D6 CAN0_TX SDIO_D5 DCI_D7 EVENTOU T EVENTOU T EVENTOU T EVENTOU T USBHS_U LPI_D3 USBHS_U LPI_D4 USBHS_U CAN1_RX LPI_D5 USBHS_U CAN1_TX LPI_D6 TIMER11_ CH0 USBHS_D M EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T TIMER11_ CH1 USBHS_D P EVENTOU T SDIO_D7 USBHS_I D GD32F425xx Datasheet Table 2-9. Port C alternate functions summary Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 USBHS_U LPI_STP PC0 SPI2_MO SPI1_MO SI/I2S2_S SI/I2S1_S D D SPI1_MIS I2S1_ADD O _SD SPI1_MO SI/I2S1_S D PC1 PC2 PC3 EVENTOU T USBHS_U LPI_DIR EVENTOU T USBHS_U LPI_NXT EVENTOU T USART2_ RX PC6 PC7 PC8 TRACED0 PC9 CK_OUT1 PC10 PC11 PC12 PC13 PC14 PC15 TIMER2_C H0 TIMER2_C H1 TIMER2_C H2 TIMER2_C H3 TIMER7_C H0 TIMER7_C H1 TIMER7_C H2 TIMER7_C I2C2_SDA H3 I2S1_MCK SPI1_SCK I2S2_MCK /I2S1_CK AF15 EVENTOU T PC4 PC5 AF14 USART5_ TX USART5_ RX USART5_ CK I2S_CKIN SPI2_SCK USART2_ UART3_T /I2S2_CK TX X I2S2_ADD SPI2_MIS USART2_ UART3_R _SD O RX X SPI2_MO USART2_ UART4_T I2C1_SDA SI/I2S2_S CK X D SDIO_D6 DCI_D0 SDIO_D7 DCI_D1 SDIO_D0 DCI_D2 SDIO_D1 DCI_D3 SDIO_D2 DCI_D8 SDIO_D3 DCI_D4 SDIO_CK DCI_D9 EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T 2 GD32F425xx Datasheet Table 2-10. Port D alternate functions summary Pin Name AF0 AF1 AF2 AF3 AF4 AF5 PD0 AF7 AF8 SPI1_NSS /I2S1_WS PD1 TIMER2_E TI PD2 PD3 AF6 SPI2_MO SI/I2S2_S D UART4_R X SPI1_SCK /I2S1_CK TRACED1 USART1_ CTS AF9 AF10 AF11 AF12 AF13 AF14 AF15 CAN0_RX EVENTOU T CAN0_TX EVENTOU T SDIO_CM D DCI_D11 EVENTOU T DCI_D5 EVENTOU T PD4 USART1_ RTS EVENTOU T PD5 USART1_ TX EVENTOU T SPI2_MO SI/I2S2_S D PD6 USART1_ RX DCI_D10 EVENTOU T PD7 USART1_ CK EVENTOU T PD8 USART2_ TX EVENTOU T PD9 USART2_ RX EVENTOU T PD10 USART2_ CK EVENTOU T PD11 USART2_ CTS EVENTOU T USART2_ RTS EVENTOU T PD12 TIMER3_C H0 PD13 TIMER3_C H1 EVENTOU T PD14 TIMER3_C H2 EVENTOU T TIMER3_C H3 EVENTOU T PD15 CTC_SYN C 3 GD32F425xx Datasheet Table 2-11. Port E alternate functions summary Pin Name AF0 AF1 AF2 AF3 TIMER3_E TI PE0 TIMER0_C H1_ON PE1 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 DCI_D2 EVENTOU T DCI_D3 EVENTOU T PE2 TRACECK EVENTOU T PE3 TRACED0 EVENTOU T PE4 TRACED1 PE5 TRACED2 PE6 TRACED3 DCI_D4 EVENTOU T TIMER8_C H0 DCI_D6 EVENTOU T TIMER8_C H1 DCI_D7 EVENTOU T PE7 TIMER0_E TI EVENTOU T PE8 TIMER0_C H0_ON EVENTOU T PE9 TIMER0_C H0 EVENTOU T PE10 TIMER0_C H1_ON EVENTOU T PE11 TIMER0_C H1 EVENTOU T PE12 TIMER0_C H2_ON EVENTOU T PE13 TIMER0_C H2 EVENTOU T PE14 TIMER0_C H3 EVENTOU T PE15 TIMER0_B RKIN EVENTOU T 4 GD32F425xx Datasheet Table 2-12. Port F alternate functions summary Pin Name AF0 PF0 CTC_SYN C AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T I2C1_SDA PF1 I2C1_SCL I2C1_SMB A I2C1_TXF RAME PF2 PF3 PF4 PF5 TIMER9_C H0 TIMER10_ CH0 PF6 PF7 TIMER12_ CH0 TIMER13_ CH0 PF8 PF9 PF10 DCI_D11 PF11 DCI_D12 AF15 PF12 PF13 PF14 PF15 Table 2-13. Port G alternate functions summary Pin Name PG0 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 EVENTOU T 5 GD32F425xx Datasheet Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 PG1 PG2 PG3 PG4 PG5 PG6 DCI_D12 USART5_ CK USART5_ RTS USART5_ RX PG7 PG8 PG9 DCI_D13 DCI_VSY NC PG10 DCI_D2 PG11 DCI_D3 USART5_ RTS USART5_ CTS USART5_ TX USART5_ CTS PG12 PG13 TRACED2 PG14 TRACED3 PG15 AF15 EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T DCI_D13 Table 2-14. Port H alternate functions summary Pin Name PH0 PH1 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 EVENTOU T EVENTOU T 6 GD32F425xx 3. Functional description 3.1. Arm® Cortex®-M4 core The Arm® Cortex®-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring floating point operations, memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts. 32-bit Arm® Cortex®-M4 processor core  Up to 200 MHz operation frequency  Single-cycle multiplication and hardware divider  Floating Point Unit (FPU)  Integrated DSP instructions  Integrated Nested Vectored Interrupt Controller (NVIC)  24-bit SysTick timer The Cortex®-M4 processor is based on the Armv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M4:  Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP) 3.2.  Nested Vectored Interrupt Controller (NVIC)  Flash Patch and Breakpoint (FPB)  Data Watchpoint and Trace (DWT)  Instrument Trace Macrocell (ITM)  Memory Protection Unit (MPU)  Serial Wire JTAG Debug Port (SWJ-DP)  Trace Port Interface Unit (TPIU) On-chip memory  Up to 3072 Kbytes of Flash memory, including code Flash and data Flash  256 KB of SRAM The Arm® Cortex®-M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 3072 Kbytes of inner Flash at most, which includes code Flash and data Flash is available for storing programs and data, and accessed (R/W) at CPU clock speed with zero wait states. Up to 256 Kbytes of inner SRAM is composed GD32F425xx Datasheet of SRAM0 (112KB), SRAM1 (16KB) and SRAM2 (64KB) that can be accessed at same time, and including 64 KB of TCM (tightly-coupled memory) data RAM that can be accessed only by the data bus of the Cortex®-M4 core. The additional 4KB of backup SRAM (BKP SRAM) is implemented in the backup domain, which can keep its content even when the VDD power supply is down. Table 2-2. GD32F425xx memory map shows the memory map of the GD32F425xx series of devices, including Flash, SRAM, peripheral, and other pre-defined regions. 3.3. Clock, reset and supply management  Internal 16 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator  Internal 48 MHz RC oscillator  Internal 32 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator  Integrated system clock PLL  2.6 to 3.6 V application supply and I/Os  Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD) The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the two AHB domains are 200 MHz. The maximum frequency of the two APB domains including APB1 is 50 MHz and APB2 is 100 MHz. See Figure 2-6. GD32F425xx clock tree for details on the clock tree. The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.4 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security. Power supply schemes:  VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.  VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.  VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and backup registers (through power switch) when VDD is not present. 3.4. Boot modes At startup, boot pins are used to select one of three boot options:  Boot from main Flash memory (default) 8 GD32F425xx Datasheet  Boot from system memory  Boot from on-chip SRAM The boot loader is located in the internal 30KB of information blocks for the boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10), USART2 (PB10 and PB11, or PC10 and PC11), and USBFS (PA9, PA10, PA11 and PA12) in device mode. It also can be used to transfer and update the Flash memory code, the data and the vector table sections. In default condition, boot from bank0 of Flash memory is selected. It also supports to boot from bank1 of Flash memory by setting a bit in option bytes. 3.5. Power saving modes The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.  Sleep mode In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.  Deep-sleep mode In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC16M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, RTC Tamper and TimeStamp event, the LVD output, RTC wakeup and USB wakeup. When exiting the deep-sleep mode, the IRC16M is selected as the system clock.  Standby mode In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC16M, HXTAL and PLL are disabled. The contents of SRAM and registers (except backup registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC, the FWDGT reset, and the rising edge on WKUP pin. 3.6. Analog to digital converter (ADC)  12-bit SAR ADC's conversion rate is up to 2.6 MSPS  12-bit, 10-bit, 8-bit or 6-bit configurable resolution  Hardware oversampling ratio adjustable from 2x to 256x improves resolution to 16-bit  Input voltage range: VSSA to VDDA (2.6V ≤ VDDA ≤ 3.6V)  Temperature sensor Up to three 12-bit 2.6 MSPS multi-channel ADCs are integrated in the device. It has a total of 9 GD32F425xx Datasheet 19 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor (VSENSE), 1 channel for internal reference voltage (VREFINT) and 1 channel for external battery power supply (VBAT). The input voltage range is between 2.6 V and 3.6 V. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use. The ADC can be triggered from the events generated by the general level 0 timers (TIMERx) and the advanced-control timers (TIMER0 and TIMER7) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value. 3.7. Digital to analog converter (DAC)  Two 12-bit DAC converter of independent output channel  8-bit or 12-bit mode in conjunction with the DMA controller The 12-bit buffered DAC channel is used to generate variable analog outputs. The DACs are designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. The maximum output value of the DAC is VREF+. 3.8. DMA  16 channels DMA controller and each channel are configurable (8 for DMA0 and 8 for DMA1)  Support independent 8, 16, 32-bit memory and peripheral transfer  Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, UARTs, DAC, I2S, SDIO and DCI The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory. Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable. 10 GD32F425xx Datasheet 3.9. General-purpose inputs/outputs (GPIOs)  Up to 114 fast GPIOs, all mappable on 16 external interrupt lines  Analog input/output configurable  Alternate function input/output configurable There are up to 114 general purpose I/O pins (GPIO) in GD32F425xx, named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15, PG0 ~ PG15 and PH0 ~ PH1 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pullup or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs. 3.10. Timers and PWM generation  Two 16-bit advanced-control timer (TIMER0 & TIMER7), eight 16-bit general timers (TIMER2, TIMER3, TIMER8 ~ TIMER13), two 32-bit general timers (TIMER1 & TIMER4) and two 16-bit basic timer (TIMER5 & TIMER6)  Up to 4 independent channels of PWM, output compare or input capture for each general timer and external trigger input  16-bit, motor control PWM advanced-control timer with programmable dead-time generation for output match  Encoder interface controller with two inputs using quadrature decoder  24-bit SysTick timer down counter  2 watchdog timers (free watchdog timer and window watchdog timer) The advanced-control timer (TIMER0 & TIMER7) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable deadtime generation. It can also be used as a complete general timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center-aligned counting modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features. The general timer, can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TIMER1 & TIMER4 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER2 & 11 GD32F425xx Datasheet TIMER3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER8 ~ TIMER13 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The general timer also supports an encoder interface with two inputs using quadrature decoder. The basic timer, known as TIMER5 & TIMER6, are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base. The GD32F425xx have two watchdog peripherals, free watchdog timer and window watchdog timer. They offer a combination of high safety level, flexibility of use and timing accuracy. The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler. It is clocked from an independent 32 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. The window watchdog timer is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in debug mode. The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It features: 3.11.  A 24-bit down counter  Auto reload capability  Maskable system interrupt generation when the counter reaches 0  Programmable clock source Real time clock (RTC) and backup registers  Independent binary-coded decimal (BCD) format timer/counter with twenty 32-bit backup registers.  Calendar with sub-second, seconds, minutes, hours, week day, date, year and month automatically correction.  Alarm function with wake up from deep-sleep and standby mode capability.  On-the-fly correction for synchronization with master clock. Digital calibration with 1 ppm resolution for compensation of quartz crystal inaccuracy. The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. A prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 KHz from external crystal oscillator. 12 GD32F425xx Datasheet 3.12. Inter-integrated circuit (I2C)  Up to three I2C bus interfaces can support both master and slave mode with a frequency up to 400 KHz (Fast mode).  Provide arbitration function, optional PEC (packet error checking) generation and checking.  Supports 7-bit and 10-bit addressing mode and general call addressing mode. The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides two data transfer rates: 100 KHz of standard mode or 400 KHz of the fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data. 3.13. Serial peripheral interface (SPI)  Up to three SPI interfaces with a frequency of up to 30 MHz  Support both master and slave mode  Hardware CRC calculation and transmit automatic CRC error checking The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. 3.14. Universal synchronous/asynchronous receiver transmitter (USART/UART)  Up to four USARTs and two UARTs with operating frequency up to 12.5 MHz  Supports both asynchronous and clocked synchronous serial communication modes  IrDA SIR encoder and decoder support  LIN break generation and detection  ISO 7816-3 compliant smart card interface The USART (USART0, USART1, USART2, USART5) and UART (UART3, UART4) are used to transfer data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART/UART includes a programmable baud rate generator 13 GD32F425xx Datasheet which is capable of dividing the system clock to produce a dedicated clock for the USART/UART transmitter and receiver. The USART/UART also supports DMA function for high speed data communication. 3.15. Inter-IC sound (I2S)  Two I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz, multiplexed with SPI1 and SPI2  Support either master or slave mode Audio  Sampling frequencies from 8 KHz up to 192 KHz are supported The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 4-wire serial lines. GD32F425xx contain an I2S-bus interface that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and SPI2. The audio sampling frequencies from 8 KHz to 192 KHz is supported. 3.16. Universal serial bus full-speed interface (USBFS)  One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s  Internal 48 MHz oscillator support crystal-less operation  Internal main PLL for USB CLK compliantly  Internal USBFS PHY support The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction formatting is performed by the hardware, including CRC generation and checking. It supports both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The controller contains a full-speed USB PHY internal. For full-speed or low-speed operation, no more external PHY chip is needed. It supports all the four types of transfer (control, bulk, Interrupt and isochronous) defined in USB 2.0 protocol. The required precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use an HXTAL crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode that allows crystal-less operation. 3.17. Universal serial bus high-speed interface (USBHS)  One USB device/host/OTG high-speed Interface with frequency up to 480 Mbit/s  An external PHY device connected to the ULPI is required when using in HS mode USBHS supports both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The controller provides ULPI interface for external USB PHY integration and it also contains a full-speed USB PHY internal. For fullspeed or low-speed operation, no more external PHY chip is needed. It supports all the four 14 GD32F425xx Datasheet types of transfer (control, bulk, Interrupt and isochronous) defined in USB 2.0 protocol. HUB connection is supported when USBHS operates at high-speed in host mode. There is also a DMA engine operating as an AHB bus master in USBHS to speed up the data transfer between USBHS and system. 3.18. Controller area network (CAN)  Two CAN2.0B interface with communication frequency up to 1 Mbit/s  Internal main PLL for CAN CLK compliantly Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 28 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others. 3.19. Secure digital input and output card interface (SDIO)  Support SD2.0/SDIO2.0/MMC4.2 host interface The Secure Digital Input and Output Card Interface (SDIO) provides access to external SD memory cards specifications version 2.0, SDIO card specification version 2.0 and multi-media card system specification version 4.2 with DMA supported. In addition, this interface is also compliant with CE-ATA digital protocol rev1.1. 3.20. Digital camera interface (DCI)  Digital video/picture capture  8/10/12/14 data width supported  High transfer efficiency with DMA interface  Video/picture crop supported  Various pixel formats supported including JPEG/YCrCb/RGB  Hard/embedded synchronous signals supported DCI is an 8-bit to 14-bit parallel interface that able to capture video or picture from a camera via Digital Camera Interface. It supports 8/10/12/14 bits data width through DMA operation. 3.21. Debug mode  Serial wire JTAG debug port (SWJ-DP) The Arm® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug 15 GD32F425xx Datasheet port that enables either a serial wire debug or a JTAG probe to be connected to the target. 3.22. Package and operation temperature  BGA100 (GDF425VxH), LQFP144 (GD32F425Zx), LQFP100 (GD32F425VxT) and LQFP64 (GD32F425Rx)  Operation temperature range: -40°C to +85°C (industrial level) 16 GD32F425xx Datasheet 4. Electrical characteristics 4.1. Absolute maximum ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Table 4-1. Absolute maximum ratings(1)(4) Symbol VDD External voltage range(2) Min Max Unit VSS - 0.3 VSS + 3.6 V VDDA External analog supply voltage VSSA - 0.3 VSSA + 3.6 V VBAT External battery supply voltage VSS - 0.3 VSS + 3.6 V VSS - 0.3 VDD + 3.6 V Input voltage on other I/O VSS - 0.3 3.6 V |ΔVDDX| Variations between different VDD power pins — 50 mV |VSSX −VSS| Variations between different ground pins — 50 mV IIO Maximum current for GPIO pins — 25 mA TA Operating temperature range -40 +85 °C Power dissipation at TA = 85°C of LQFP144 — 820 Power dissipation at TA = 85°C of BGA100 — 511 Power dissipation at TA = 85°C of LQFP100 — 697 Power dissipation at TA = 85°C of LQFP64 — 772 TSTG Storage temperature range -65 +150 °C TJ Maximum junction temperature — 125 °C VIN PD (1) (2) (3) (4) 4.2. Parameter Input voltage on 5V tolerant pin (3) mW Guaranteed by design, not tested in production. All main power and ground pins should be connected to an external power source within the allowable range. VIN maximum value cannot exceed 5.5 V. It is recommended that VDD and VDDA are powered by the same source. The maximum difference between VDD and VDDA does not exceed 300 mV during power-up and operation. Operating conditions characteristics Table 4-2. DC operating conditions Min(1) Typ Max(1) Unit Symbol Parameter Conditions VDD Supply voltage — 2.6 3.3 3.6 V VDDA Analog supply voltage Same as VDD 2.6 3.3 3.6 V VBAT Battery supply voltage — 1.8 — 3.6 V (1) Based on characterization, not tested in production. 17 GD32F425xx Datasheet Figure 4-1. Recommended power supply decoupling capacitors(1) (2) VBAT 100 nF VSS N * VDD 4.7 μF + N * 100 nF VSS VDDA 1 μF VSSA 10 nF VREF+ 1 μF (1) (2) VREF- 10 nF The VREF+ and VREF- pins are only available on no less than 100-pin packages, or else the VREF+ and VREF- pins are not available and internally connected to VDDA and VSSA pins. All decoupling capacitors need to be as close as possible to the pins on the PCB board. Table 4-3. Clock frequency(1) Symbol Parameter Conditions Min Max Unit fHCLK AHB clock frequency — — 200 MHz fAPB1 APB1 clock frequency — — 50 MHz fAPB2 APB2 clock frequency — — 100 MHz Min Max Unit 0 ∞ 20 ∞ (1) Guaranteed by design, not tested in production. Table 4-4. Operating conditions at Power up / Power down(1) Symbol tVDD (1) Parameter Conditions VDD rise time rate — VDD fall time rate μs/ V Guaranteed by design, not tested in production. Table 4-5. Start-up timings of Operating conditions (1)(2)(3) Symbol Parameter tstart-up Start-up time (1) (2) (3) Conditions Typ Clock source from HXTAL 140.6 Clock source from IRC16M 140.2 Unit ms Based on characterization, not tested in production. After power-up, the start-up time is the time between the rising edge of NRST high and the main function. PLL is off. 18 GD32F425xx Datasheet Table 4-6. Power saving mode wakeup timings characteristics(1)(2) Symbol Parameter Typ tSleep Wakeup from Sleep mode 0.623 Wakeup from Deep-sleep mode（LDO On） 1.57 tDeep-sleep Wakeup from Deep-sleep mode （LDO in low power mode） tStandby (1) (2) 4.3. Wakeup from Standby mode Unit μs 1.57 140 ms Based on characterization, not tested in production. The wakeup time is measured from the wakeup event to the point at which the application code reads the first instruction under the below conditions: VDD = VDDA = 3.3 V, IRC16M = System clock = 16 MHz. Power consumption The power measurements specified in the tables represent that code with data executing from on-chip Flash with the following specifications. Table 4-7. Power consumption characteristics(2)(3)(4)(5) Symbol Parameter Conditions Min Typ(1) Max Unit VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 200 MHz, All peripherals — 61.5 — mA — 37.1 — mA — 55.9 — mA — 33.9 — mA — 52.6 — mA — 32.0 — mA — 38.6 — mA — 23.9 — mA — 35.2 — mA enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 200 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 180 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 180 MHz, All peripherals disabled IDD+IDDA Supply current (Run mode) VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 168 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 168 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 120 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 120 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 108 MHz, All peripherals enabled 19 GD32F425xx Datasheet Symbol Parameter Conditions Min Typ(1) Max Unit VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 108 MHz, All peripherals — 22.0 — mA — 29.9 — mA — 19.0 — mA — 21.2 — mA — 13.9 — mA — 13.3 — mA — 9.5 — mA — 11.7 — mA — 8.5 — mA — 8.9 — mA — 6.9 — mA — 6.4 — mA — 5.3 — mA — 5.0 — mA disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 90 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 90 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 60 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 60 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 30 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 30 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 25 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 25 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 16 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 16 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 8 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 8 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 4 MHz, All peripherals enabled 20 GD32F425xx Datasheet Symbol Parameter Conditions Min Typ(1) Max Unit VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 4 MHz, All peripherals — 4.5 — mA — 42.2 — mA — 18.7 — mA — 38.5 — mA — 17.2 — mA disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 200 MHz,CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 200 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 180 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 180 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 168 MHz, CPU clock off, 36.2 mA 16.4 mA All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 168 MHz, CPU clock off, All peripherals disabled Supply current (Sleep mode) VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 120 MHz, CPU clock off, — 27.0 — mA — 12.8 — mA — 24.7 — mA — 11.9 — mA — 21.2 — mA — 10.5 — mA — 15.5 — mA All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 120 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 108 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 108 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 90 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 90 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 60 MHz, CPU clock off, All peripherals enabled 21 GD32F425xx Datasheet Symbol Parameter Conditions Min Typ(1) Max Unit VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 60 MHz, CPU clock off, All — 8.4 — mA — 10.5 — mA — 6.7 — mA — 9.4 — mA — 6.2 — mA — 7.4 — mA — 5.4 — mA — 5.7 — mA — 4.7 — mA — 4.8 — mA — 4.3 — mA — 1.39 — mA — 1.36 11 mA — 1.33 — mA peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 30 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 30 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 25 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 25 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 16 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 16 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 8 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 8 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 4 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 4 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, LDO in run mode and normal driver mode, IRC32K off, RTC off, All GPIOs analog mode Supply current VDD = VDDA = 3.3 V, LDO in low power (Deep-Sleep mode and normal driver mode, IRC32K off, mode) RTC off, All GPIOs analog mode VDD = VDDA = 3.3 V, LDO in run mode and low driver mode, IRC32K off, RTC off, All GPIOs analog mode 22 GD32F425xx Datasheet Symbol Parameter Conditions Min Typ(1) Max Unit VDD = VDDA = 3.3 V, LDO in low power mode and low driver mode, IRC32K off, — 1.30 — mA — 9.90 — μA — 9.67 — μA — 9.19 — μA — 3.26 — μA — 9.09 — μA — 8.93 — μA — 8.74 — μA — 7.47 — μA — 2.23 — μA — 2.13 — μA — 2 — μA — 1.89 — μA — 8.16 — μA — 8 — μA RTC off, All GPIOs analog mode VDD = VDDA = 3.3 V, LXTAL off, IRC32K on, RTC on, backup SARM LDO ON VDD = VDDA = 3.3 V, LXTAL off, IRC32K on, Supply current RTC off, backup SARM LDO ON (Standby mode) VDD = VDDA = 3.3 V, LXTAL off, IRC32K off, RTC off, backup SARM LDO ON VDD = VDDA = 3.3 V, LXTAL off, IRC32K off, RTC off, backup SARM LDO OFF VDD off, VDDA off, VBAT=3.6V, LXTAL on with external crystal, RTC on, LXTAL High driving, backup SARM LDO ON VDD off, VDDA off, VBAT=3.3V, LXTAL on with external crystal, RTC on, LXTAL High driving, backup SARM LDO ON VDD off, VDDA off, VBAT=2.6V, LXTAL on with external crystal, RTC on, LXTAL High driving, backup SARM LDO ON VDD off, VDDA off, VBAT=1.8V, LXTAL on with external crystal, RTC on, LXTAL High driving, backup SARM LDO ON VDD off, VDDA off, VBAT =3.6V, LXTAL on Battery supply IBAT current (Backup mode) with external crystal, RTC on, LXTAL High driving, backup SARM LDO OFF VDD off, VDDA off, VBAT =3.3V, LXTAL on with external crystal, RTC on, LXTAL High driving, backup SARM LDO OFF VDD off, VDDA off, VBAT =2.6V, LXTAL on with external crystal, RTC on, LXTAL High driving, backup SARM LDO OFF VDD off, VDDA off, VBAT =1.8V, LXTAL on with external crystal, RTC on, LXTAL High driving, backup SARM LDO OFF VDD off, VDDA off, VBAT =3.6V, LXTAL on with external crystal, RTC on, LXTAL Low driving, backup SARM LDO ON VDD off, VDDA off, VBAT =3.3V, LXTAL on with external crystal, RTC on, LXTAL Low driving, backup SARM LDO ON 23 GD32F425xx Datasheet Symbol Parameter Conditions Min Typ(1) Max Unit VDD off, VDDA off, VBAT =2.6V, LXTAL on with external crystal, RTC on, LXTAL Low — 7.8 — μA — 6.7 — μA — 1.27 — μA — 1.18 — μA — 1.06 — μA — 0.96 — μA driving, backup SARM LDO ON VDD off, VDDA off, VBAT =1.8V, LXTAL on with external crystal, RTC on, LXTAL Low driving, backup SARM LDO ON VDD off, VDDA off, VBAT =3.6V, LXTAL on with external crystal, RTC on, LXTAL Low driving, backup SARM LDO OFF VDD off, VDDA off, VBAT =3.3V, LXTAL on with external crystal, RTC on, LXTAL Low driving, backup SARM LDO OFF VDD off, VDDA off, VBAT =2.6V, LXTAL on with external crystal, RTC on, LXTAL Low driving, backup SARM LDO OFF VDD off, VDDA off, VBAT =1.8V, LXTAL on with external crystal, RTC on, LXTAL Low driving, backup SARM LDO OFF (1) (2) (3) (4) (5) Based on characterization, not tested in production. Unless otherwise specified, all values given for TA = 25 ℃ and test result is mean value. When System Clock is less than 4 MHz, an external source is used, and the HXTAL bypass function is needed, no PLL. When System Clock is greater than 8 MHz, a crystal 8 MHz is used, and the HXTAL bypass function is closed, using PLL. When analog peripheral blocks such as ADCs, DACs, HXTAL, LXTAL, IRC16M, or IRC32K are ON, an additional power consumption should be considered. Figure 4-2. Typical supply current consumption in Run mode 24 GD32F425xx Datasheet Figure 4-3. Typical supply current consumption in Sleep mode 4.4. EMC characteristics EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is given in Table 4-8. EMS characteristics, based on the EMS levels and classes compliant with IEC 61000 series standard. Table 4-8. EMS characteristics(1) Symbol VESD VFTB (1) 4.5. Parameter Conditions Voltage applied to all device pins to induce a functional disturbance Level/Class VDD = 3.3 V, TA = 25 °C LQFP144, fHCLK = 200 MHz 3A conforms to IEC 61000-4-2 Fast transient voltage burst applied to VDD = 3.3 V, TA = 25 °C induce a functional disturbance through LQFP144, fHCLK = 200 MHz 100 pF on VDD and VSS pins conforms to IEC 61000-4-4 3A Based on characterization, not tested in production. Power supply supervisor characteristics Table 4-9. Power supply supervisor characteristics Symbol VLVD(1) Parameter Conditions Min Typ Max Low voltage LVDT = 000(rising edge) — 2.1 — Detector level selection LVDT = 000(falling edge) — 1.98 — Unit V 25 GD32F425xx Datasheet Symbol Parameter Conditions Min Typ Max LVDT = 001(rising edge) — 2.23 — LVDT = 001(falling edge) — 2.12 — LVDT = 010(rising edge) — 2.36 — LVDT = 010(falling edge) — 2.25 — LVDT = 011(rising edge) — 2.50 — LVDT = 011(falling edge) — 2.38 — LVDT = 100(rising edge) — 2.62 — LVDT = 100(falling edge) — 2.52 — LVDT = 101(rising edge) — 2.74 — LVDT = 101(falling edge) — 2.66 — LVDT = 110(rising edge) — 2.90 — LVDT = 110(falling edge) — 2.80 — LVDT = 111(rising edge) — 3.03 — LVDT = 111(falling edge) — 2.93 — Unit VLVDhyst(2) LVD hystersis — — 100 — mV VPOR(1) Power on reset threshold — — 2.45 — V — — 1.82 — V — — 600 — mV Falling edge — 2.80 — V Rising edge — 2.89 — V Falling edge — 2.51 — V Rising edge — 2.59 — V Falling edge — 2.20 — V Rising edge — 2.30 — V VPDR(1) Power down reset threshold VPDRhyst(2) PDR hysteresis VBOR3(1) Brownout level 3 threshold VBOR2(1) VBOR1(1) Brownout level 2 threshold Brownout level 1 threshold VBORhyst(2) BOR hysteresis — — 100 — mV tRSTTEMPO(2) Reset temporization — — 2 — ms (1) (2) Based on characterization, not tested in production. Guaranteed by design, not tested in production. 26 GD32F425xx Datasheet 4.6. Electrical sensitivity The device is strained in order to determine its performance in terms of electrical sensitivity. Electrostatic discharges (ESD) are applied directly to the pins of the sample. Static latch-up (LU) test is based on the two measurement methods. Table 4-10. ESD characteristics(1) Symbol VESD(HBM) VESD(CDM) (1) Parameter Conditions Electrostatic discharge TA=25 °C; voltage (human body model) JS-001-2017 Electrostatic discharge TA=25 °C; voltage (charge device model) JS-002-2018 Min Typ Max Unit — — 2000 V — — 500 V Min Typ Max Unit — — ±200 mA — — 5.4 V Based on characterization, not tested in production. Table 4-11. Static latch-up characteristics(1) Symbol Parameter I-test LU Vsupply over voltage (1) 4.7. Conditions TA=105 °C; JESD78 Based on characterization, not tested in production. External clock characteristics Table 4-12. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics Symbol fHXTAL RF (1) (2) Parameter Conditions Min Typ Max Unit Crystal or ceramic frequency 2.6 V ≤ VDD ≤ 3.6 V 4 25 32 MHz Feedback resistor VDD = 3.3 V — 400 — kΩ — — 20 30 pF Crystal or ceramic duty cycle — 30 50 70 % Oscillator transconductance Startup — 25 — mA/V VDD = 3.3 V — 1.2 — mA VDD = 3.3 V — 0.42 — ms Recommended matching CHXTAL (2) (3) capacitance on OSCIN and OSCOUT Ducy(HXTAL) (2) gm(2) IDDHXTAL(1) tSUHXTAL(1) (1) (2) (3) Crystal or ceramic operating current Crystal or ceramic startup time Based on characterization, not tested in production. Guaranteed by design, not tested in production. CHXTAL1 = CHXTAL2 = 2*(CLOAD - CS), For CHXTAL1 and CHXTAL2, it is recommended matching capacitance on OSCIN and OSCOUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic manufacturer. For CS, it is PCB and MCU pin stray capacitance. 27 GD32F425xx Datasheet Table 4-13. High speed external clock characteristics (HXTAL in bypass mode) Symbol fHXTAL_ext(1) Parameter Conditions External clock source or oscillator 2.6 V ≤ VDD ≤ frequency 3.6 V OSCIN input pin high level VHXTALH(2) voltage VDD = 3.3 V Min Typ Max Unit 1 — 50 MHz 0.7 VDD — VDD V VSS — 0.3 VDD V VHXTALL(2) OSCIN input pin low level voltage tH/L(HXTAL) (2) OSCIN high or low time — 5 — — ns tR/F(HXTAL) (2) OSCIN rise or fall time — — — 10 ns CIN(2) OSCIN input capacitance — — 5 — pF Ducy(HXTAL) (2) Duty cycle — 40 — 60 % (1) (2) Based on characterization, not tested in production. Guaranteed by design, not tested in production. Table 4-14. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics Symbol fLXTAL(1) Parameter Conditions Min Typ Max Unit VDD = 3.3 V — 32.768 — kHz — — 15 — pF — 30 — 70 % Oscillator Medium low driving capability — 6 — transconductance Higher driving capability — 18 — Crystal or ceramic LXTALDRI= 0 — 0.8 — operating current LXTALDRI= 1 — 1.6 — Crystal or ceramic LXTALDRI= 0 — 369 — ms startup time LXTALDRI= 1 — 175 — ms Crystal or ceramic frequency Recommended CLXTAL(2) (3) matching capacitance on OSC32IN and OSC32OUT Ducy(LXTAL)(2) gm(2) IDDLXTAL (1) tSULXTAL(1) (4) (1) (2) (3) (4) Crystal or ceramic duty cycle μA/V μA Based on characterization, not tested in production. Guaranteed by design, not tested in production. CLXTAL1 = CLXTAL2 = 2*(CLOAD - CS), For CLXTAL1 and CLXTAL2, it is recommended matching capacitance on OSC32IN and OSC32OUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic manufacturer. For CS, it is PCB and MCU pin stray capacitance. tSULXTAL is the startup time measured from the moment it is enabled (by software) to the 32.768 kHz oscillator stabilization flags is SET. This value varies significantly with the crystal manufacturer. 28 GD32F425xx Datasheet Table 4-15. Low speed external user clock characteristics (LXTAL in bypass mode) Symbol fLXTAL_ext(1) External clock source or oscillator frequency Conditions Min Typ Max Unit VDD = 3.3 V — 32.768 1000 kHz VLXTALH(2) OSC32IN input pin high level voltage — 0.7 VDD — VDD VLXTALL(2) OSC32IN input pin low level voltage — VSS — 0.3 VDD tH/L(LXTAL) (2) OSC32IN high or low time — 450 — — tR/F(LXTAL) (2) OSC32IN rise or fall time — — — 50 CIN(2) OSC32IN input capacitance — — 5 — pF Ducy(LXTAL) (2) Duty cycle — 30 50 70 % (1) (2) 4.8. Parameter V ns Based on characterization, not tested in production. Guaranteed by design, not tested in production. Internal clock characteristics Table 4-16. High speed internal clock (IRC16M) characteristics Symbol Parameter Conditions Min Typ Max Unit VDD = VDDA = 3.3 V — 16 — MHz High Speed Internal fIRC16M Oscillator (IRC16M) frequency VDD = VDDA = 3.3 V, IRC16M oscillator Frequency TA = -40 °C ~ +85 °C accuracy, Factory-trimmed VDD = VDDA = 3.3 V, TA = — — 0.5 — % VDD = VDDA = 3.3 V 45 50 55 % — 47 — μA — 1.18 — μs accuracy, User trimming step I DDIRC16M IRC16M oscillator operating VDD = VDDA = 3.3 V, (1) +IDDAIRC16M current fHCLK =fHXTAL = 25 MHz IRC16M oscillator startup VDD = VDDA = 3.3 V, time fHCLK =fHXTAL_PLL = 200 MHz (1) (2) % — 25 °C IRC16M oscillator Frequency tSUIRC16M(1) — +1.1 (1) -1.0 ACCIRC16M DucyIRC16M(2) IRC16M oscillator duty cycle -1.73 to — +1.0 % Based on characterization, not tested in production. Guaranteed by design, not tested in production. Table 4-17. High speed internal clock (IRC48M) characteristics Symbol Parameter Conditions Min Typ Max Unit VDD = 3.3 V — 48 — MHz — % +2.0 % High Speed Internal fIRC48M Oscillator (IRC48M) frequency IRC48M oscillator ACCIRC48M Frequency accuracy, Factory-trimmed VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C VDD = VDDA = 3.3 V, TA = 25 °C — -2.0 -1.31 to -0.39 (1) — 29 GD32F425xx Datasheet Symbol Parameter Conditions Min Typ Max Unit — — 0.12 — % VDD = VDDA = 3.3 V 45 50 55 % — 358 — μA — 1.23 — μs IRC48M oscillator Frequency accuracy, User trimming step DucyIRC48M(2) IRC48M oscillator duty cycle IDDIRC48M IRC48M oscillator VDD = VDDA = 3.3 V, +IDDAIRC48M(1) operating current fHCLK = fIRC16M = 16 MHz IRC48M oscillator startup VDD = VDDA = 3.3 V, time fHCLK = fHXTAL_PLL = 200 MHz tSUIRC48M(1) (1) (2) Based on characterization, not tested in production. Guaranteed by design, not tested in production. Table 4-18. Low speed internal clock (IRC32K) characteristics Symbol fIRC32K(1) IDDAIRC32K(2) tSUIRC32K(2) (1) (2) 4.9. Parameter Conditions Low Speed Internal oscillator VDD = VDDA = 3.3 V, (IRC32K) frequency TA = -40 °C ~ +85 °C IRC32K oscillator operating VDD = VDDA = 3.3 V, current fHCLK = fIRC16M = 16 MHz, IRC32K oscillator startup VDD = VDDA = 3.3 V, fHCLK = time fHXTAL_PLL = 200 MHz, Min Typ Max Unit — 32 — kHz — 0.43 — μA — 22.1 — μs Guaranteed by design, not tested in production. Based on characterization, not tested in production. PLL characteristics Table 4-19. PLL characteristics Symbol Parameter Conditions Min Typ Max Unit fPLLIN(1) PLL input clock frequency — 1 — 4 MHz fPLLOUT(2) PLL output clock frequency — 100 — 500 MHz — 32 — 344 MHz — — — 400 μs VCO freq = 400 MHz — 797 — μA — 40 — — 400 — fVCO(2) tLOCK(2) IDDA(1)(3) PLL VCO output clock frequency PLL lock time Current consumption on VDDA Cycle to cycle Jitter(rms) JitterPLL Cycle to cycle Jitter （peak to peak） (1) (2) (3) (4) System clock ps Based on characterization, not tested in production. Guaranteed by design, not tested in production. System clock = HXTAL = 25 MHz, PLL clock source = HXTAL/25 = 1 MHz, fPLLOUT = 100 MHz. Value given with main PLL running. 30 GD32F425xx Datasheet Table 4-20. PLLI2S characteristics Symbol Parameter Min Typ Max Unit — 1 — 4 MHz — 100 — 500 MHz — 32 — 344 MHz — — — 400 μs VCO freq = 400 MHz — 814 — μA — 40 — — 400 — PLLI2S input clock fPLLIN(1) frequency PLLI2S output clock fPLLOUT(2) fVCO(2) Conditions frequency PLLI2S VCO output clock frequency tLOCK(2) PLLI2S lock time Current consumption on IDDA(1)(3) VDDA Cycle to cycle Jitter(rms) JitterPLL Cycle to cycle Jitter System clock （peak to peak） (1) (2) (3) (4) ps Based on characterization, not tested in production. Guaranteed by design, not tested in production. System clock = HXTAL = 25 MHz, PLL clock source = HXTAL/25 = 1 MHz, fPLLOUT = 100 MHz. Value given with main PLLI2S running. Table 4-21. PLLSAI characteristics Symbol Parameter Min Typ Max Unit — 1 — 4 MHz — 100 — 500 MHz — 32 — 344 MHz — — — 400 μs VCO freq = 400 MHz — 796 — μA — 40 — — 400 — PLLSAI input clock fPLLIN(1) frequency PLLSAI output clock fPLLOUT(2) fVCO(2) Conditions frequency PLLSAI VCO output clock frequency tLOCK(2) PLLSAI lock time Current consumption on IDDA(1)(3) VDDA Cycle to cycle Jitter(rms) JitterPLL Cycle to cycle Jitter System clock （peak to peak） (1) (2) (3) (4) ps Based on characterization, not tested in production. Guaranteed by design, not tested in production. System clock = HXTAL = 25 MHz, PLL clock source = HXTAL/25 = 1 MHz, fPLLOUT = 100 MHz. Value given with main PLLSAI running. Table 4-22. PLL spread spectrum clock generation (SSCG) characteristics Symbol Parameter Conditions Min Typ Max Unit fmod Modulation frequency — — — 10 KHz mdamp Peak modulation amplitude — — — 2 % — — — — 215-1 — MODCNT* MODSTEP (1) (2) Based on characterization, not tested in production. Guaranteed by design, not tested in production. 31 GD32F425xx Datasheet Equation 1: SSCG configuration equation: MODCNT = round(fPLLIN /4/fmod ) MODSTEP = round(mdamp ∗ PLLN ∗ 214 /(MODCNT ∗ 100)) The formula above (Equation 1) is SSCG configuration equation. 4.10. Memory characteristics Table 4-23. Flash memory characteristics Symbol Parameter PECYC program /erase cycles before Conditions Min(1) Typ(1) Max(2) Unit Number of guaranteed TA = -40 °C ~ +85 °C 100 — — kcycles failure (Endurance) tRET Data retention time — — 20 — years tPROG Word programming time TA = -40°C ~ +85 °C — 37.5 180 μs tERASE16kB Sector(16kB) erase time — 200 2000 tERASE64kB Sector(64kB) erase time — 300 4000 ms tERASE128kB Sector(128kB) erase time — 600 8000 tMERASE(512K) Mass erase time TA = -40°C ~ +85 °C — 2.4 32 s tMERASE(1MB) Mass erase time TA = -40°C ~ +85 °C — 4.8 64 s tMERASE(2MB) Mass erase time TA = -40°C ~ +85 °C — 9.6 128 s tMERASE(3MB) Mass erase time TA = -40°C ~ +85 °C — 14.4 192 s Min Typ Max Unit -0.3 — 0.3 VDD (1) (2) 4.11. TA = -40°C ~ +85 °C Based on characterization, not tested in production. Guaranteed by design, not tested in production. NRST pin characteristics Table 4-24. NRST pin characteristics Symbol Parameter VIL(NRST)(1) NRST Input low level voltage (1) NRST Input high level voltage VIH(NRST) Vhyst(1) VIL(NRST) — 440 — NRST Input low level voltage -0.3 — 0.3 VDD (1) NRST Input high level voltage NRST Input low level voltage VIH(NRST)(1) NRST Input high level voltage Vhyst(1) Schmidt trigger Voltage hysteresis Rpu VDD = VDDA = 3.3 V 0.7 VDD — Schmidt trigger Voltage hysteresis (1) (1) (2) VDD + 0.3 Schmidt trigger Voltage hysteresis Vhyst(1) (2) VDD = VDDA = 2.6 V 0.7 VDD — (1) VIH(NRST) VIL(NRST) Conditions — 490 -0.3 — VDD = VDDA = 3.6 V 0.7 VDD — Pull-up equivalent resistor — VDD + 0.3 — 0.3 VDD VDD + 0.3 V mV V mV V — 510 — mV — 40 — kΩ Based on characterization, not tested in production. Guaranteed by design, not tested in production. 32 GD32F425xx Datasheet Figure 4-4. Recommended external NRST pin circuit VDD VDD External reset circuit 10 kΩ RPU NRST K 100 nF GND 4.12. GPIO characteristics Table 4-25. I/O port DC characteristics(1)(3) Symbol Parameter Standard IO Low level VIL input voltage 5V-tolerant IO Low level input voltage Standard IO Low level VIH input voltage 5V-tolerant IO Low level input voltage RPU(2) RPD(2) Conditions Min Typ Max Unit 2.6 V ≤ VDD = VDDA ≤ 3.6 V — — 0.3 VDD V 2.6 V ≤ VDD = VDDA ≤ 3.6 V — — 0.3 VDD V 2.6 V ≤ VDD = VDDA ≤ 3.6 V 0.7 VDD — — V 2.6 V ≤ VDD = VDDA ≤ 3.6 V 0.7 VDD — — V Internal pull- All pins VIN = VSS — 40 — up resistor PA10 — — 10 — Internal pull- All pins VIN = VDD — 40 — down resistor PA10 — — 10 — VDD = 2.6 V — — 0.11 VDD = 3.3 V — — 0.10 (IIO = +8 mA) VDD = 3.6 V — — 0.10 Low level output VDD = 2.6 V — — 0.29 VDD = 3.3 V — — 0.27 (IIO = +20 mA) VDD = 3.6 V — — 0.26 High level output VDD = 2.6 V 2.46 — — voltage for an IO Pin VDD = 3.3 V 3.18 — — (IIO = +8 mA) VDD = 3.6 V 3.48 — — High level output VDD = 2.6 V 2.22 — — voltage for an IO Pin VDD = 3.3 V 2.98 — — kΩ kΩ IO_Speed:level 3 Low level output voltage for an IO Pin VOL voltage VOH for an IO Pin V 33 GD32F425xx Datasheet Symbol Parameter Conditions Min Typ Max (IIO = +20 mA) VDD = 3.6 V 3.29 — — VDD = 2.6 V — — 0.16 VDD = 3.3 V — — 0.14 (IIO = +8 mA) VDD = 3.6 V — — 0.14 Low level output VDD = 2.6 V — — 0.43 VDD = 3.3 V — — 0.37 (IIO = +20 mA) VDD = 3.6 V — — 0.36 High level output VDD = 2.6 V 2.40 — — voltage for an IO Pin VDD = 3.3 V 3.12 — — (IIO = +8 mA) VDD = 3.6 V 3.44 — — High level output VDD = 2.6 V 2.05 — — voltage for an IO Pin VDD = 3.3 V 2.84 — — (IIO = +20 mA) VDD = 3.6 V 3.17 — — VDD = 2.6 V — — 0.28 VDD = 3.3 V — — 0.28 (IIO = +8 mA) VDD = 3.6 V — — 0.24 (IIO = +15 mA) VDD = 2.6 V — — 0.57 Low level output VDD = 3.3 V — — 0.66 VDD = 3.6 V — — 0.64 High level output VDD = 2.6 V 2.23 — — voltage for an IO Pin VDD = 3.3 V 3.00 — — (IIO = +8 mA) VDD = 3.6 V 3.31 — — (IIO = +15 mA) VDD = 2.6 V 1.83 — — High level output VDD = 3.3 V 2.45 — — VDD = 3.6 V 2.81 — — VDD = 2.6 V — — 0.17 VDD = 3.3 V — — 0.15 (IIO = +1 mA) VDD = 3.6 V — — 0.15 Low level output VDD = 2.6 V — — 0.80 VDD = 3.3 V — — 0.63 (IIO = +4 mA) VDD = 3.6 V — — 0.60 High level output VDD = 2.6 V 2.38 — — voltage for an IO Pin VDD = 3.3 V 3.12 — — (IIO = +1 mA) VDD = 3.6 V 3.42 — — High level output VDD = 2.6 V 1.45 — — voltage for an IO Pin VDD = 3.3 V 2.48 — — Unit IO_Speed:level 2 Low level output voltage for an IO Pin VOL voltage for an IO Pin VOH V IO_Speed:level 1 Low level output voltage VOL voltage for an IO Pin for an IO Pin (IIO = +20 mA) VOH V voltage for an IO Pin (IIO = +20 mA) IO_Speed:level 0 Low level output voltage for an IO Pin VOL voltage VOH for an IO Pin V 34 GD32F425xx Datasheet Symbol (1) (2) (3) Parameter Conditions Min Typ Max (IIO = +4 mA) VDD = 3.6 V 2.83 — — Unit Based on characterization, not tested in production. Guaranteed by design, not tested in production. All pins except PC13 / PC14 / PC15 / PI8. Since PC13 to PC15 and PI8 are supplied through the Power Switch, which can only be obtained by a small current, the speed of GPIOs PC13 to PC15 and PI8 should not exceed 2 MHz when they are in output mode(maximum load: 30 pF). Table 4-26. I/O port AC characteristics(1)(2)(4) GPIOx_OSPD[1:0] bit value(3) Parameter Conditions 2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF GPIOx_OSPD0->OSPDy[1:0] = 00 （IO_Speed:level 0） GPIOx_OSPD0->OSPDy[1:0] = 01 （IO_Speed:level 1） GPIOx_OSPD0->OSPDy[1:0] = 10 （IO_Speed: level 2） GPIOx_OSPD0->OSPDy[1:0] = 11 （IO_Speed:level 3） (1) (2) (3) (4) (5) TRise/TFall Max Unit 51 2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF 63.2 ns 2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF 74.2 TRise/TFall 2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF 3.6 2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF 9.6 ns 2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF 12.2 TRise/TFall TRise/TFall 2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF 2.2 2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF 3 2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF 3.8 2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF 2 2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF 2.8 2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF 3.4 ns ns Based on characterization, not tested in production. Unless otherwise specified, all test results given for TA = 25 °C. The I/O speed is configured using the GPIOx_OSPD -> OSPDy[1:0] bits. Only for reference, Depending on user’s design. Max frequency is defined when the sum of rise time plus the fall time is less than 2/3 cycle. 35 GD32F425xx Datasheet 4.13. ADC characteristics Table 4-27. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA(1) Operating voltage — 2.6 3.3 3.6 V VIN(1) ADC input voltage range — 0 — VREF+ V VREF+(2) Positive Reference Voltage — 2.6 — VDDA V Negative Reference Voltage — — VSSA — V ADC clock — 0.1 — 40 MHz 12-bit 0.007 — 2.6 10-bit 0.008 — 3.1 MS 8-bit 0.01 — 3.6 PS 6-bit 0.011 — 4.4 VREF- (2) fADC(1) fS(1) Sampling rate (1) Analog input voltage 16 external;3 internal 0 — VREF+ V (2) External input impedance See Equation 2 — — 308.6 kΩ — — — 0.55 kΩ — — 4.0 pF VAIN RAIN Input sampling switch RADC(2) resistance Input sampling capacitance tCAL(2) Calibration time fADC = 40 MHz — 3.275 — μs Sampling time fADC = 40 MHz 0.075 — 12 μs 12-bit — 15 — Total conversion time (including 10-bit — 13 — 1/ sampling time) 8-bit — 11 — fADC 6-bit — 9 — — — — 1 (2) ts tCONV(2) tSU(2) (1) (2) No pin/pad capacitance CADC(2) included Startup time μs Based on characterization, not tested in production. Guaranteed by design, not tested in production. Equation 2: RAIN max formula R AIN < Ts fADC ∗CADC ∗ln(2N+2 ) − R ADC The formula above (Equation 2) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 4-28. ADC RAIN max for fADC = 40 MHz(2) Ts (cycles) ts (us) RAIN max (KΩ) 3 0.075 1.3 15 0.375 9.1 28 0.7 17.4 55 1.375 34.8 84 2.1 53.5 112 2.8 71.5 144 3.6 92.1 480 12 308.6 36 GD32F425xx Datasheet (1) (2) Based on characterization, not tested in production. Guaranteed by design, not tested in production. Table 4-29. ADC dynamic accuracy at fADC = 40 MHz(1) Symbol Parameter Test conditions Min Typ Max Unit ENOB Effective number of bits fADC = 40 MHz — 10.9 — bits SNDR Signal-to-noise and distortion ratio VDDA = VREF+ = 3.3 V — 67.3 — SNR Signal-to-noise ratio Input Frequency = 110 — 67.7 — — -75 — Typ Max ±1 — ±1 — ±1.5 — THD (1) kHz Total harmonic distortion Temperature = 25 ℃ dB Based on characterization, not tested in production. Table 4-30. ADC static accuracy at fADC = 40 MHz(1) Symbol Parameter Offset Offset error DNL Differential linearity error INL Integral linearity error (1) 4.14. Test conditions fADC = 40 MHz VDDA = VREF+ = 3.3 V Unit LSB Based on characterization, not tested in production. Temperature sensor characteristics Table 4-31. Temperature sensor characteristics(1) Symbol Parameter Min Typ Max Unit TL VSENSE linearity with temperature — ±1.5 — ℃ Avg_Slope Average slope — 4.4 — mV/℃ V25 Voltage at 25 °C — 1.4 — V ADC sampling time when reading the temperature — 17.1 — μs tS_temp (1) (2) 4.15. (2) Based on characterization, not tested in production. Shortest sampling time can be determined in the application by multiple iterations. DAC characteristics Table 4-32. DAC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA(1) Operating voltage — 2.6 3.3 3.6 V VREF+(2) Positive Reference Voltage — 2.6 — VDDA V — — VSSA — V Resistive load with buffer ON 5 — — kΩ — — 15 kΩ — — 50 pF 0.2 — — V VREF-(2) Negative Reference Voltage RLOAD(2) Resistive load Ro(2) Impedance output CLOAD(2) Capacitive load DAC_OUT min(2) Lower DAC_OUT voltage Impedance output with buffer OFF Capacitive load with buffer ON Lower DAC_OUT voltage with buffer ON 37 GD32F425xx Datasheet Symbol Parameter Conditions Lower DAC_OUT voltage with buffer OFF DAC_OUT max (2) Higher DAC_OUT voltage with buffer ON Higher DAC_OUT voltage Higher DAC_OUT voltage with buffer OFF Min Typ Max Unit 0.5 — — mV — — — — — 350 VDDA0.2 VDDA1LSB V V With no load, middle code(0x800) on the input, IDDA(1) DAC current consumption VREF+ = 3.6 V in quiescent mode With no load, worst — μA code(0xF1C) on the input, — 430 — — 115 — VREF+ = 3.6 V With no load, middle code(0x800) on the input, IDDVREF+(1) DAC current consumption in quiescent mode VREF+ = 3.6 V μA With no load, worst code(0xF1C) on the input, — 298 — 10-bit configuration — — ±0.75 12-bit configuration — — ±3 10-bit configuration — — ±1.25 12-bit configuration — — ±5 VREF+ = 3.6 V DNL(1) Differential non linearity INL(1) Integral non linearity Offset(1) Offset error DAC in 12-bit mode — — ±24 LSB GE(1) Gain error DAC in 12-bit mode — — ±1.5 % Settling time CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ — 0.5 1 μs Wakeup from off state — — 5 10 μs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ — — 4 MS/s No RLoad, CLOAD=50 pF — -90 — dB Tsetting (1) Twakeup (2) Update rate(2) PSRR(2) (1) (2) 4.16. LSB LSB Max frequency for a correct DAC_OUT change from code i to i±1LSB Power supply rejection ratio(to VDDA) Based on characterization, not tested in production. Guaranteed by design, not tested in production. I2C characteristics Table 4-33. I2C characteristics(1)(2) Symbol Parameter Conditions tSCL(H) SCL clock high time tSCL(L) tsu(SDA) Standard mode Fast mode Unit Min Max Min Max — 4.0 — 0.6 — μs SCL clock low time — 4.7 — 1.3 — μs SDA setup time — 2 — 0.8 — μs 38 GD32F425xx Datasheet Symbol Parameter Conditions th(SDA) SDA data hold time tr(SDA/SCL) Standard mode Fast mode Unit Min Max Min Max — 250 — 250 — ns SDA and SCL rise time — — 1000 20 300 ns tf(SDA/SCL) SDA and SCL fall time — — 300 — 300 ns th(STA) Start condition hold time — 4.0 — 0.6 — μs — 4.7 — 0.6 — μs — 4.0 — 0.6 — μs — 4.7 — 1.3 — μs Repeated Start condition setup ts(STA) time Stop condition setup time ts(STO) tbuff (1) (2) Stop to Start condition time (bus free) Guaranteed by design, not tested in production. Test condition: GPIO_SPEED set 2 MHz and external pull-up resistor value is 1 kΩ when operate EEPROM with I2C. Figure 4-5. I2C bus timing diagram tsu(STA) SDA 70% 30% tf(SDA) tr(SDA) tSCL(H) th(STA) SCL tbuff th(SDA) tsu(SDA) 70% 30% tSCL(L) tr(SCL) tf(SCL) tsu(STO) 39 GD32F425xx Datasheet 4.17. SPI characteristics Table 4-34. Standard SPI characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fSCK SCK clock frequency — — — 30 MHz tSCK(H) SCK clock high time tSCK(L) SCK clock low time Master mode, fPCLKx = 120 MHz, presc = 4 Master mode, fPCLKx = 120 MHz, presc = 4 14.67 16.67 18.67 ns 14.67 16.67 18.67 ns SPI master mode tV(MO) Data output valid time — — — 8 ns tSU(MI) Data input setup time — 1 — — ns tH(MI) Data input hold time — 0 — — ns SPI slave mode (1) tSU(NSS) NSS enable setup time — 0 — — ns tH(NSS) NSS enable hold time — 1 — — ns tA(SO) Data output access time — — 9 — ns tDIS(SO) Data output disable time — — 10 — ns tV(SO) Data output valid time — — 11 — ns tSU(SI) Data input setup time — 0 — — ns tH(SI) Data input hold time — 2 — — ns Based on characterization, not tested in production. Figure 4-6. SPI timing diagram - master mode tSCK SCK (CKPH=0 CKPL=0) SCK (CKPH=0 CKPL=1) SCK (CKPH=1 CKPL=0) tSCK(H) tSCK(L) SCK (CKPH=1 CKPL=1) tSU(MI) MISO D[0] LF=1,FF16=0 D[7] tH(MI) MOSI D[0] D[7] tV(MO) tH(MO) 40 GD32F425xx Datasheet Figure 4-7. SPI timing diagram - slave mode NSS tSCK tSU(NSS) SCK (CKPH=0 CKPL=0) tSCK(H) SCK (CKPH=0 CKPL=1) tSCK(L) tH(NSS) tH(SO) tDIS(SO) tV(SO) tA(SO) MISO D[0] D[7] tSU(SI) MOSI D[0] D[7] tH(SI) 41 GD32F425xx Datasheet 4.18. I2S characteristics Table 4-35. I2S characteristics(1)(2) Symbol Parameter fCK Clock frequency Conditions Master mode (data: 32 bits, Audio frequency = 96 kHz) Slave mode Min Typ Max Unit — 6.25 — — — 12.5 — 80 — ns — 80 — ns MHz tH Clock high time tL Clock low time tV(WS) WS valid time Master mode — 3 — ns tH(WS) WS hold time Master mode — 3 — ns tSU(WS) WS setup time Slave mode 0 — — ns tH(WS) WS hold time Slave mode 3 — — ns Slave mode — 50 — % Ducy(SCK) I2S slave input clock duty cycle — tSU(SD_MR) Data input setup time Master mode 0 — — ns tsu(SD_SR) Data input setup time Slave mode 0 — — ns Master receiver 1 — — ns Slave receiver 3 — — ns — — 9 ns 6 — — ns — — 6 ns 0 — — ns tH(SD_MR) tH(SD_SR) Data input hold time tV(SD_ST) Data output valid time tH(SD_ST) Data output hold time tV(SD_MT) Data output valid time tH(SD_MT) Data output hold time (1) (2) Slave transmitter (after enable edge) Slave transmitter (after enable edge) Master transmitter (after enable edge) Master transmitter (after enable edge) Guaranteed by design, not tested in production. Based on characterization, not tested in production. 42 GD32F425xx Datasheet Figure 4-8. I2S timing diagram - master mode tCK CPOL=0 tL CPOL=1 tV(WS) tH tH(WS) WS output tH(SD_MT) tV(SD_MT) SD transmit D[0] SD receive D[0] tSU(SD_MR) tH(SD_MR) Figure 4-9. I2S timing diagram - slave mode tCK CPOL=0 tL CPOL=1 tH tH(WS) WS input tSU(WS) SD transmit SD receive tV(SD_ST) tH(SD_ST) D[0] D[0] tSU(SD_SR) tH(SD_SR) 43 GD32F425xx Datasheet 4.19. USART characteristics Table 4-36. USART characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fSCK SCK clock frequency fPCLKx =100MHz — — 12.5 MHz tSCK(H) SCK clock high time fPCLKx =100MHz 40 — — ns tSCK(L) SCK clock low time fPCLKx =100MHz 40 — — ns (1) 4.20. Guaranteed by design, not tested in production. SDIO characteristics Table 4-37. SDIO characteristics(1)(2) Symbol Parameter fPP(3) Conditions Min Typ Max Unit Clock frequency in data transfer mode — 0 — 48 MHz tW(CKL) (3) Clock low time fpp = 48 MHz 9.5 10.5 — ns tW(CKH) (3) Clock high time fpp = 48 MHz 9.3 10.3 — ns CMD, D inputs (referenced to CK) in MMC and SD HS mode tISU(4) Input setup time HS fpp = 48 MHz 4 — — ns tIH(4) Input hold time HS fpp = 48 MHz 3 — — ns CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV(3) Output valid time HS fpp = 48 MHz — — 13.8 ns tOH(3) Output hold time HS fpp = 48 MHz 12 — — ns CMD, D inputs (referenced to CK) in SD default mode tISUD(4) Input setup time SD fpp = 24 MHz 3 — — ns tIHD(4) Input hold time SD fpp = 24 MHz 3 — — ns CMD, D outputs (referenced to CK) in SD default mode tOVD(3) Output valid default time SD fpp = 24 MHz — 2.4 2.8 ns tOHD(3) Output hold default time SD fpp = 24 MHz 2 — — ns (1) (2) (3) (4) 4.21. CLK timing is measured at 50% of VDD. Capacitive load CL = 30 pF. Based on characterization, not tested in production. Guaranteed by design, not tested in production. CAN characteristics Refer to Table 4-25. for more details on the input/output alternate function characteristics (CANTX and CANRX). 44 GD32F425xx Datasheet 4.22. USBFS characteristics Table 4-38. USBFS start up time Symbol Parameter Max Unit tSTARTUP(1) USBFS startup time 1 μs (1) Guaranteed by design, not tested in production. Table 4-39. USBFS DC electrical characteristics Symbol Parameter Conditions Min Typ VDD USBFS operating voltage — 3 — 3.6 Input VDI Differential input sensitivity — 0.2 — — levels(1) VCM Differential common mode range Includes VDI range 0.8 — 2.5 VSE Single ended receiver threshold — 1.3 — 2.0 Output VOL Static output level low RL of 1.0 kΩ to 3.6 V — 0.06 0.3 levels (2) VOH Static output level high RL of 15 kΩ to VSS 2.8 3.3 3.6 17 21 25 0.72 0.9 1.1 PA11, PA12(USBFS_DM/DP) PB14, PB15(USBHS_ DM/DP) RPD(2) PA9(USBFS_VBUS) PA9(USBFS_VBUS) V 1.2 1.5 1.8 0.24 0.3 0.33 VIN = VSS PB13(USBHS_VBUS) (1) (2) V kΩ PA11, PA12(USBFS_DM/DP) PB14, PB15(USBHS_ DM/DP) V VIN = VDD PB13(USBHS_VBUS) RPU(2) Max Unit Guaranteed by design, not tested in production. Based on characterization, not tested in production. Table 4-40. USBFS full speed-electrical characteristics(1) (1) Symbol Parameter Conditions Min Typ Max Unit tR Rise time CL = 50 pF 4 — 20 ns tF Fall time CL = 50 pF 4 — 20 ns tRFM Rise / fall time matching tR / tF 90 — 110 % vCRS Output signal crossover voltage — 1.3 — 2.0 V Guaranteed by design, not tested in production. Figure 4-10. USBFS timings: definition of data signal rise and fall time Crossover points Differential data lines VCRS VSS tf tr 45 GD32F425xx Datasheet 4.23. USBHS characteristics Table 61. USBHS clock timing parameters(1) Symbol Parameter Min Typ Max Unit VDD USBHS operating voltage 3.0 — 3.6 V 30 — — MHz fHCLK value to guarantee proper fHCLK operation of USBHS interface FSTART_8BIT Frequency (first transition) 8-bit ± 10% 54 60 66 MHz FSTEADY Frequency (steady state) ±500 ppm 59.97 60 60.63 MHz DSTART_8BIT Duty cycle (first transition) 8-bit ± 10% 40 50 60 % DSTEADY Duty cycle (steady state) ±500 ppm 49.975 50 50.025 % (1) Guaranteed by design, not tested in production. Table 62. USB-ULPI Dynammic characteristics Symbol Parameter Min Typ Max Unit tSC Control in (ULPI_DIR, ULPI_NXT) setup time — — 2 ns tHC Control in (ULPI_DIR, ULPI_NXT) hold time 0.5 — — ns tSD Data in setup time — — 2 ns tHD Data in hold time 0 — — ns (1) 4.24. Guaranteed by design, not tested in production. TIMER characteristics Table 4-41. TIMER characteristics(1) Symbol Parameter tres Timer resolution time fEXT Timer external clock frequency Conditions Min Max Unit — 1 — tTIMERxCLK fTIMERxCLK = 200 MHz 5 — ns — 0 fTIMERxCLK/2 MHz fTIMERxCLK = 200 MHz 0 100 MHz — 16 bit TIMER1 & TIMER4 — 32 bit — 1 65536 tTIMERxCLK 327.68 μs TIMERx (except RES tCOUNTER tMAX_COUNT (1) TIMER1 & TIMER4) Timer resolution 16-bit counter clock period when internal clock is selected Maximum possible count fTIMERxCLK = 200 MHz 0.005 — — fTIMERxCLK = 200 MHz — 65536x65536 tTIMERxCLK 21.47 s Guaranteed by design, not tested in production. 46 GD32F425xx Datasheet 4.25. DCI characteristics Table 4-42. DCI characteristics(1) Symbol Parameter Min Max Unit Frequency ratio DCI_PIXCLK /fHCLK — 0.4 — DCI_PIXCLK Pixel clock input — 80 MHz DPixel Pixel clock input duty cycle 30 70 % tsu(DATA) Data input setup time 2.5 — ns th(DATA) Data output valid time 1 — ns tsu(HS) DCI_HS input setup time 2 — ns tsu(VS) DCI_VS input setup time 2 — ns th(HS) DCI_HS input hold time 0.5 — ns th(VS) DCI_VS input hold time 0.5 — ns (1) 4.26. Guaranteed by design, not tested in production. WDGT characteristics Table 4-43. FWDGT min/max timeout period at 32 kHz (IRC32K)(1) Prescaler divider PSC[2:0] bits 1/4 (1) Min timeout RLD[11:0] = Max timeout RLD[11:0] 0x000 = 0xFFF 000 0.03125 511.90625 1/8 001 0.03125 1023.7812 1/16 010 0.03125 2047.53125 1/32 011 0.03125 4095.03125 1/64 100 0.03125 8190.03125 1/128 101 0.03125 16380.03125 1/256 110 or 111 0.03125 32760.03125 Unit ms Guaranteed by design, not tested in production. Table 4-44. WWDGT min-max timeout value at 50 MHz (fPCLK1)(1) PSC[1:0] 1/1 00 81.92 1/2 01 163.84 1/4 10 327.68 1/8 11 655.36 (1) 4.27. Min timeout value Prescaler divider CNT[6:0] = 0x40 Unit Max timeout value CNT[6:0] = 0x7F Unit 5.24 μs 10.48 20.96 ms 41.92 Guaranteed by design, not tested in production. Parameter conditions Unless otherwise specified, all values given for VDD = VDDA = 3.3 V, TA = 25 °C. 47 GD32F425xx Datasheet 5. Package information 5.1. LQFP144 package outline dimensions Figure 5-1. LQFP144 package outline A3 c F θ A2A A1 D D1 108 73 109 72 0.25 L L1 DETAIL: F E1 E b b1 c1 c 37 144 BASE METAL WITH PLATING 1 e b BB SECTION B-B 36 Table 5-1. LQFP144 package dimensions Symbol Min Typ Max A — — 1.60 A1 0.05 — 0.15 A2 1.35 1.40 1.45 A3 0.59 0.64 0.69 b 0.18 — 0.26 b1 0.17 0.20 0.23 c 0.13 — 0.17 c1 0.12 0.13 0.14 D 21.80 22.00 22.20 D1 19.90 20.00 20.10 E 21.80 22.00 22.20 E1 19.90 20.00 20.10 e — 0.50 — L 0.45 — 0.75 L1 — 1.00 — θ 0° — 7° (Original dimensions are in millimeters) 48 GD32F425xx Datasheet Figure 5-2. LQFP144 recommended footprint 22.70 109 144 20.30 108 36 73 72 37 17.80 22.70 0.30 1 1.20 0.50 (Original dimensions are in millimeters 49 GD32F425xx Datasheet 5.2. BGA100 package outline dimensions Figure 5-3. BGA100 package outline aaa B E 2X eee fff E1 B A PIN 1 CORNER e 1 2 3 4 5 6 7 8 12 11 10 9 9 10 11 12 8 7 6 b 5 4 3 PIN 1 CORNER 2 1 A A B C A B C LASER MARK PIN 1 B C C D D E E F F D G G H H J J L K e D1 K L L M M aaa A L 2X TOP VIEW BOTTOM VIEW A2 DETAIL A A3 ccc C A SEATING PLANE c 100X ddd C A1 SEATING PLANE C SIDE VIEW C DETAIL A(3:1) Table 5-2. BGA100 package dimensions Symbol Min Typ Max A — — 0.84 A1 0.13 0.18 0.23 A2 0.53 0.58 0.63 A3 — 0.40 — b 0.20 0.25 0.30 c 0.15 0.18 0.21 D 6.90 7.00 7.10 D1 — 5.50 — E 6.90 7.00 7.10 E1 — 5.50 — e — 0.50 — L — 0.625 — aaa — 0.10 — ccc — 0.20 — ddd — 0.08 — eee — 0.15 — fff — 0.08 — (Original dimensions are in millimeters) 50 GD32F425xx Datasheet Figure 5-4. BGA100 recommended footprint Dimension Pitch Dpad Dsm Recommended values 0.50 mm 0.28 mm 0.38 mm Dpad Dsm (Original dimensions are in millimeters) 51 GD32F425xx Datasheet 5.3. LQFP100 package outline dimensions Figure 5-5. LQFP100 package outline A3 A2 A c θ A1 F eB D D1 51 75 0.25 50 76 L L1 DETAIL: F E1 E b b1 100 c1 c 26 BASE METAL 1 25 b e WITH PLATING B B SECTION B-B Table 5-3. LQFP100 package dimensions Symbol Min Typ Max A — — 1.60 A1 0.05 — 0.15 A2 1.35 1.40 1.45 A3 0.59 0.64 0.69 b 0.18 — 0.26 b1 0.17 0.20 0.23 c 0.13 — 0.17 c1 0.12 0.13 0.14 D 15.80 16.00 16.20 D1 13.90 14.00 14.10 E 15.80 16.00 16.20 E1 13.90 14.00 14.10 e — 0.50 — eB 15.05 — 15.35 L 0.45 — 0.75 L1 — 1.00 — θ 0° — 7° (Original dimensions are in millimeters) 52 GD32F425xx Datasheet Figure 5-6. LQFP100 recommended footprint 16.70 76 100 14.30 75 25 51 50 26 12.30 16.70 0.30 1 1.20 0.50 (Original dimensions are in millimeters) 53 GD32F425xx Datasheet 5.4. LQFP64 package outline dimensions Figure 5-7. LQFP64 package outline A3 A2 A θ c A1 F eB D D1 33 48 0.25 32 37 L L1 DETAIL: F E1 E b b1 c1 c BASE METAL 64 17 WITH PLATING 1 e b SECTION B-B 16 B B Table 5-4. LQFP64 package dimensions Symbol Min Typ Max A — — 1.60 A1 0.05 — 0.15 A2 1.35 1.40 1.45 A3 0.59 0.64 0.69 b 0.18 — 0.26 b1 0.17 0.20 0.23 c 0.13 — 0.17 c1 0.12 0.13 0.14 D 11.80 12.00 12.20 D1 9.90 10.00 10.10 E 11.80 12.00 12.20 E1 9.90 10.00 10.10 e — 0.50 — eB 11.25 — 11.45 L 0.45 — 0.75 L1 — 1.00 — θ 0° — 7° (Original dimensions are in millimeters) 54 GD32F425xx Datasheet Figure 5-8. LQFP64 recommended footprint 12.70 64 49 10.30 48 16 33 17 32 7.80 12.70 0.30 1 1.20 0.50 (Original dimensions are in millimeters) 55 GD32F425xx Datasheet 5.5. Thermal characteristics Thermal resistance is used to characterize the thermal performance of the package device, which is represented by the Greek letter “θ”. For semiconductor devices, thermal resistance represents the steady-state temperature rise of the chip junction due to the heat dissipated on the chip surface. θJA: Thermal resistance, junction-to-ambient. θJB: Thermal resistance, junction-to-board. θJC: Thermal resistance, junction-to-case. ᴪJB: Thermal characterization parameter, junction-to-board. ᴪJT: Thermal characterization parameter, junction-to-top center. θJA =(TJ -TA )/PD (5-1) θJB =(TJ -TB )/PD (5-2) θJC =(TJ -TC )/PD (5-3) Where, TJ = Junction temperature. TA = Ambient temperature TB = Board temperature TC = Case temperature which is monitoring on package surface PD = Total power dissipation θJA represents the resistance of the heat flows from the heating junction to ambient air. It is an indicator of package heat dissipation capability. Lower θJA can be considerate as better overall thermal performance. θJA is generally used to estimate junction temperature. θJB is used to measure the heat flow resistance between the chip surface and the PCB board. θJC represents the thermal resistance between the chip surface and the package top case. θJC is mainly used to estimate the heat dissipation of the system (using heat sink or other heat dissipation methods outside the device package). Table 5-5. Package thermal characteristics(1) Symbol θJA θJB Condition Natural convection, 2S2P PCB Cold plate, 2S2P PCB Package Value LQFP144 48.76 BGA100 78.32 LQFP100 57.42 LQFP64 51.81 LQFP144 35.00 BGA100 55.27 LQFP100 31.68 Unit °C/W °C/W 56 GD32F425xx Datasheet Symbol θJC ᴪJB ᴪJT (1) Condition Cold plate, 2S2P PCB Natural convection, 2S2P PCB Natural convection, 2S2P PCB Package Value LQFP64 33.36 LQFP144 12.03 BGA100 20.15 LQFP100 13.85 LQFP64 11.25 LQFP144 35.32 BGA100 55.74 LQFP100 41.28 LQFP64 33.53 LQFP144 1.86 BGA100 1.74 LQFP100 0.75 LQFP64 0.49 Unit °C/W °C/W °C/W Thermal characteristics are based on simulation, and meet JEDEC specification. 57 GD32F425xx Datasheet 6. Ordering information Table 6-1. Part ordering code for GD32F425xx devices Ordering code Flash (KB) Package Package type GD32F425ZKT6 3072 LQFP144 Green GD32F425ZGT6 1024 LQFP144 Green GD32F425VKH6 3072 BGA100 Green GD32F425VGH6 1024 BGA100 Green GD32F425VKT6 3072 LQFP100 Green GD32F425VGT6 1024 LQFP100 Green GD32F425RKT6 3072 LQFP64 Green GD32F425RGT6 1024 LQFP64 Green GD32F425RET6 512 LQFP64 Green Temperature operating range Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C 58 GD32F425xx Datasheet 7. Revision history Table 7-1. Revision history Revision No. Description Date 1.0 Initial Release Feb. 22, 2022 59 GD32F425xx Datasheet Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). 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