PSMNR51-25YLHX

PSMNR51-25YLH N-channel 25 V, 0.57 mΩ, 380 A logic level MOSFET in LFPAK56E using NextPowerS3 technology 30 September 2019 Product data sheet 1. General description Logic level gate drive N-channel enhancement mode MOSFET in LFPAK56E package optimized for low RDSon, low IDSS leakage even when hot, high efficiency and high current. Rated to 380 A, optimized for DC load switch and hot-swap applications. 2. Features and benefits • • • • • • • • 100% avalanche tested at I(AS) = 190 A Optimized for low RDSon Low leakage < 1 μA at 25 °C Low spiking and ringing for low EMI designs Optimized for 4.5 V gate drive Copper-clip for low parasitic inductance and resistance High reliability LFPAK package, qualified to 175 °C Wave solderable; exposed leads for optimal solder coverage and visual solder inspection 3. Applications • • • • • • • Hot swap e-Fuse Power OR-ing DC switch / Load switch Battery protection Brushed and BLDC (brushless) motor control Synchronous rectification in AC-DC and DC-DC applications 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 25 V ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 - - 380 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 333 W Tj junction temperature -55 - 175 °C VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 0.49 0.57 mΩ VGS = 4.5 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 0.65 0.82 mΩ ID = 25 A; VDS = 12 V; VGS = 4.5 V; Fig. 12; Fig. 13 3.1 17 34 nC 24 53 87 nC [1] Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD gate-drain charge QG(tot) total gate charge PSMNR51-25YLH Nexperia N-channel 25 V, 0.57 mΩ, 380 A logic level MOSFET in LFPAK56E using NextPowerS3 technology Symbol Parameter Conditions Min Typ Max IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 12 V; Fig. 16 - 0.89 - Unit Source-drain diode S [1] softness factor 380A Continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 S source 2 S source 3 S source G 4 G gate mbb076 mb D mounting base; connected to drain D 1 2 3 S 4 LFPAK56E; PowerSO8 (SOT1023) 6. Ordering information Table 3. Ordering information Type number Package PSMNR51-25YLH Name Description Version LFPAK56E; Power-SO8 plastic, single-ended surface-mounted package (LFPAK56); 4 leads; 1.27 mm pitch SOT1023 7. Marking Table 4. Marking codes Type number Marking code PSMNR51-25YLH H5125L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 25 V VDGR drain-gate voltage 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ - 25 V VGS gate-source voltage -20 20 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 333 W ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 - 380 A VGS = 10 V; Tmb = 100 °C; Fig. 2 - 380 A pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 - 2174 A IDM PSMNR51-25YLH Product data sheet peak drain current All information provided in this document is subject to legal disclaimers. 30 September 2019 [1] © Nexperia B.V. 2019. All rights reserved 2 / 12 PSMNR51-25YLH Nexperia N-channel 25 V, 0.57 mΩ, 380 A logic level MOSFET in LFPAK56E using NextPowerS3 technology Symbol Parameter Tstg Conditions Min Max Unit storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C Source-drain diode IS source current Tmb = 25 °C - 333 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 2174 A Avalanche ruggedness EDS(AL)S non-repetitive drainID = 25 A; Vsup ≤ 25 V; RGS = 50 Ω; source avalanche energy VGS = 10 V; Tj(init) = 25 °C; unclamped; tp = 15.5 ms [2] - 6.3 J IAS non-repetitive avalanche Vsup ≤ 25 V; VGS = 10 V; Tj(init) = 25 °C; current RGS = 50 Ω [2] - 190 A [1] [2] 380A Continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. Protected by 100% test 03aa16 120 Pder (%) 80 aaa-028834 600 ID (A) 500 400 (1) 300 40 200 100 0 Fig. 1. 0 50 100 150 Tmb (°C) 0 200 Fig. 2. Product data sheet 25 50 75 100 125 150 175 Tmb (°C) 200 VGS ≥ 10 V (1) 380A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. Normalized total power dissipation as a function of mounting base temperature PSMNR51-25YLH 0 Continuous drain current as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. 30 September 2019 © Nexperia B.V. 2019. All rights reserved 3 / 12 PSMNR51-25YLH Nexperia N-channel 25 V, 0.57 mΩ, 380 A logic level MOSFET in LFPAK56E using NextPowerS3 technology ID (A) aaa-028822 104 Limit RDSon = VDS / ID 103 tp = 10 µs 100 µs 102 DC 1 ms 10 ms 10 100 ms 1 10-1 1 10 102 VDS (V) Tmb = 25 °C; IDM is a single pulse Fig. 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Min Typ Max Unit Rth(j-mb) thermal resistance from Fig. 4 junction to mounting base Conditions - 0.33 0.45 K/W Rth(j-a) thermal resistance from Fig. 5 junction to ambient Fig. 6 - 42 - K/W - 85 - K/W aaa-028225 1 Zth(j-mb) (K/W) δ = 0.5 10-1 0.2 0.1 0.05 10-2 0.02 P single shot δ= Fig. 4. 10-5 10-4 10-3 10-2 T t tp 10-3 10-6 tp T 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration PSMNR51-25YLH Product data sheet All information provided in this document is subject to legal disclaimers. 30 September 2019 © Nexperia B.V. 2019. All rights reserved 4 / 12 PSMNR51-25YLH Nexperia N-channel 25 V, 0.57 mΩ, 380 A logic level MOSFET in LFPAK56E using NextPowerS3 technology aaa-027935 aaa-027933 Copper square 25.4 mm x 25.4 mm; 70 µm thick on FR4 board Fig. 5. PCB layout for thermal resistance from junction to ambient 70 µm thick copper on FR4 board Fig. 6. PCB layout with minimum footprint for thermal resistance from junction to ambient 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 25 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 22.5 - - V VGS(th) gate-source threshold voltage ID = 2 mA; VDS=VGS; Tj = 25 °C 1.2 1.55 2.2 V ΔVGS(th)/ΔT gate-source threshold voltage variation with temperature 25 °C ≤ Tj ≤ 150 °C - -4.8 - mV/K IDSS drain leakage current VDS = 20 V; VGS = 0 V; Tj = 25 °C - - 1 µA VDS = 20 V; VGS = 0 V; Tj = 125 °C - 8.3 - µA VGS = 16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 0.49 0.57 mΩ VGS = 10 V; ID = 25 A; Tj = 150 °C; Fig. 11 - - 1.01 mΩ VGS = 4.5 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 0.65 0.82 mΩ VGS = 4.5 V; ID = 25 A; Tj = 150 °C; Fig. 11 - - 1.46 mΩ f = 1 MHz; Tj = 25 °C 0.64 1.6 4 Ω ID = 25 A; VDS = 12 V; VGS = 4.5 V; Fig. 12; Fig. 13 24 53 87 nC ID = 25 A; VDS = 12 V; VGS = 10 V; Fig. 12; Fig. 13 51 113 186 nC ID = 0 A; VDS = 0 V; VGS = 10 V - 57 - nC Static characteristics V(BR)DSS IGSS RDSon RG gate leakage current drain-source on-state resistance gate resistance Dynamic characteristics QG(tot) total gate charge PSMNR51-25YLH Product data sheet All information provided in this document is subject to legal disclaimers. 30 September 2019 © Nexperia B.V. 2019. All rights reserved 5 / 12 PSMNR51-25YLH Nexperia N-channel 25 V, 0.57 mΩ, 380 A logic level MOSFET in LFPAK56E using NextPowerS3 technology Symbol Parameter Conditions Min Typ Max Unit QGS gate-source charge 4.1 15 29 nC QGS(th) pre-threshold gatesource charge ID = 25 A; VDS = 12 V; VGS = 4.5 V; Fig. 12; Fig. 13 2.7 10 19 nC QGS(th-pl) post-threshold gatesource charge 1.5 5.5 10.5 nC QGD gate-drain charge 3.1 17 34 nC VGS(pl) gate-source plateau voltage ID = 25 A; VDS = 12 V; Fig. 12; Fig. 13 - 2.6 - V Ciss input capacitance 4195 6991 10487 pF Coss output capacitance VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; Fig. 14 2317 3861 5792 pF Crss reverse transfer capacitance 174 645 1548 pF td(on) turn-on delay time - 39 - ns tr rise time - 65 - ns td(off) turn-off delay time - 63 - ns tf fall time Qoss output charge VDS = 12 V; RL = 0.4 Ω; VGS = 4.5 V; RG(ext) = 5 Ω - 49 - ns VGS = 0 V; VDS = 12 V; f = 1 MHz; Tj = 25 °C - 67 - nC Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 15 - 0.75 1 V trr reverse recovery time 51 - ns recovered charge IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 12 V; Fig. 16 [1] - Qr - 61 - nC ta reverse recovery rise time - 27 - ns tb reverse recovery fall time - 24 - ns S softness factor - 0.89 - [1] includes capacitive recovery aaa-028823 300 ID (A) 250 10 V VGS = 3 V 4.5 V aaa-028824 3 RDSon (mΩ) 2.5 200 2 2.8 V 150 1.5 100 1 2.6 V 50 0 Fig. 7. 0.5 2.2 V 0 1 2 3 VDS (V) 0 4 0 2 4 6 8 10 12 14 VGS (V) 16 Tj = 25 °C Tj = 25 °C; ID = 25 A Output characteristics; drain current as a Fig. 8. function of drain-source voltage; typical values Drain-source on-state resistance as a function of gate-source voltage; typical values PSMNR51-25YLH Product data sheet All information provided in this document is subject to legal disclaimers. 30 September 2019 © Nexperia B.V. 2019. All rights reserved 6 / 12 PSMNR51-25YLH Nexperia N-channel 25 V, 0.57 mΩ, 380 A logic level MOSFET in LFPAK56E using NextPowerS3 technology aaa-028825 360 ID (A) 300 aaa-028826 3 RDSon (mΩ) 2.5 240 2 180 1.5 2.8 V 3V 3.5 V 120 1 150°C 60 Tj = 25°C 4.5 V 0.5 VGS = 10 V 0 0 0.5 1 1.5 2 2.5 3 3.5 VGS (V) 0 4 VDS = 8 V Fig. 9. a 0 50 100 150 200 250 ID (A) 300 Tj = 25 °C Transfer characteristics; drain current as a function of gate-source voltage; typical values Fig. 10. Drain-source on-state resistance as a function of drain current; typical values aaa-028835 2.2 VGS (V) aaa-028827 10 8 1.8 6 20 V 1.4 12 V 4 VDS = 5 V 1 0.6 -60 2 -30 0 30 60 90 120 150 Tj (°C) 0 180 0 25 50 75 100 QG (nC) 125 Tj = 25 °C; ID = 25 A Fig. 11. Normalized drain-source on-state resistance factor as a function of junction temperature PSMNR51-25YLH Product data sheet Fig. 12. Gate-source voltage as a function of gate charge; typical values All information provided in this document is subject to legal disclaimers. 30 September 2019 © Nexperia B.V. 2019. All rights reserved 7 / 12 PSMNR51-25YLH Nexperia N-channel 25 V, 0.57 mΩ, 380 A logic level MOSFET in LFPAK56E using NextPowerS3 technology aaa-028828 105 C (pF) VDS ID 104 VGS(pl) Ciss Coss VGS(th) VGS QGS2 103 Crss QGS1 QGS QGD QG(tot) 003aaa508 102 10-1 Fig. 13. Gate charge waveform definitions 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig. 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values IS (A) 003aal160 aaa-028829 103 ID (A) trr 102 ta tb 0 10 0.25 IRM 150°C 1 0 0.2 0.4 Tj = 25°C 0.6 0.8 1 VSD (V) IRM t (s) 1.2 Fig. 16. Reverse recovery timing definition VGS = 0 V Fig. 15. Source-drain (diode forward) current as a function of source-drain (diode forward) voltage; typical values PSMNR51-25YLH Product data sheet All information provided in this document is subject to legal disclaimers. 30 September 2019 © Nexperia B.V. 2019. All rights reserved 8 / 12 PSMNR51-25YLH Nexperia N-channel 25 V, 0.57 mΩ, 380 A logic level MOSFET in LFPAK56E using NextPowerS3 technology 11. Package outline Plastic single-ended surface-mounted package (LFPAK56E); 4 leads A E SOT1023 E1 A b1 b2 (3x) c1 mounting base H D1 D L 1 2 3 4 b e A1 w A X c C θ Lp detail X 0 2.5 mm 5 mm scale Dimensions Unit y C A A1 b b1 b2 c c1 D(1) D1(1) E(1) E1(1) max 1.10 0.15 0.50 4.41 0.25 0.30 4.70 4.45 5.30 nom 0.85 min 0.95 0.00 0.35 3.62 0.19 0.24 4.45 4.95 3.7 3.5 e 1.27 H L Lp 6.2 1.3 0.85 5.9 0.8 0.40 w y 0.25 0.1 θ 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm per side are not included. Outline version sot1023_po References IEC JEDEC JEITA European projection Issue date 13-03-05 17-07-31 SOT1023 Fig. 17. Package outline LFPAK56E; Power-SO8 (SOT1023) PSMNR51-25YLH Product data sheet All information provided in this document is subject to legal disclaimers. 30 September 2019 © Nexperia B.V. 2019. All rights reserved 9 / 12 PSMNR51-25YLH Nexperia N-channel 25 V, 0.57 mΩ, 380 A logic level MOSFET in LFPAK56E using NextPowerS3 technology 12. Soldering 4.7 4.2 0.25 (2×) 0.9 (3×) 0.25 (2×) 0.6 (4×) 3.45 0.6 (3×) 2 3.5 2.55 0.25 (2×) SR opening = Cu + 0.075 1.1 2.15 3.3 SP opening = Cu - 0.050 0.7 (4×) 1.27 3.81 solder lands solder paste 125 µm stencil solder resist occupied area sot1023_fr Fig. 18. Reflow soldering footprint for LFPAK56E; Power-SO8 (SOT1023) PSMNR51-25YLH Product data sheet All information provided in this document is subject to legal disclaimers. 30 September 2019 © Nexperia B.V. 2019. All rights reserved 10 / 12 PSMNR51-25YLH Nexperia N-channel 25 V, 0.57 mΩ, 380 A logic level MOSFET in LFPAK56E using NextPowerS3 technology 13. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. 30 September 2019 © Nexperia B.V. 2019. All rights reserved 11 / 12 PSMNR51-25YLH Nexperia N-channel 25 V, 0.57 mΩ, 380 A logic level MOSFET in LFPAK56E using NextPowerS3 technology Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Quick reference data....................................................1 5. Pinning information......................................................2 6. Ordering information....................................................2 7. Marking.......................................................................... 2 8. Limiting values............................................................. 2 9. Thermal characteristics............................................... 4 10. Characteristics............................................................ 5 11. Package outline.......................................................... 9 12. Soldering................................................................... 10 13. Legal information......................................................11 © Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 30 September 2019 PSMNR51-25YLH Product data sheet All information provided in this document is subject to legal disclaimers. 30 September 2019 © Nexperia B.V. 2019. All rights reserved 12 / 12