CM1213-04SO

CM1213-04SO LOW CAPACITANCE TVS DIODE ARRAY Features ● ● ● ● ● ● Ultra low leakage: nA level Operating voltage: 5V Low clamping voltage Complies with following standards: – IEC 61000-4-2 (ESD) immunity test Air discharge: ±20kV Contact discharge: ±20kV – IEC61000-4-4 (EFT) 40A (5/50ns) – IEC61000-4-5 (Lightning) 5A (8/20 μs) RoHS Compliant Dimensions SOT-26 AEC -Q101 qualified. Pin Configuration Applications ● ● ● ● ● ● USB 2.0 power and data line Set-top box and digital TV Digital video interface (DVI) Notebook Computers SIM Ports 10/100/1000 Ethernet Mechanical Characteristics ● Package: SOT-26 ● Lead Finish: Lead Free ● UL Flammability Classification Rating 94V-0 ● Quantity Per Reel:3,000pcs ● Reel Size:7inch ● Device Marking: V05 Absolute Maximum Ratings(Tamb=25°C unless otherwise specified) Parameter Symbol Peak Pulse Power (8/20µs) Ppp Value Unit 350 W ±20 ESD per IEC 61000−4−2 (Air) Kv VESD ±20 ESD per IEC 61000−4−2 (Contact) Operating Temperature Range TJ -55 to +125 ℃ Storage Temperature Range TSTJ -55 to +150 ℃ Rev : 01.06.2014 1/7 www.leiditech.com CM1213-04SO Electrical Characteristics(TA=25°C unless otherwise specified) Parameter Symbol Test Condition Min Typ VRWM Reverse Working Voltage Breakdown Voltage VBR Max Unit 5 V 6 IT = 1mA V Reverse Leakage Current IR VRWM = 5V 1 µA Clamping Voltage VC IPP = 1A (8 x 20 μs pulse) 15 V Clamping Voltage VC IPP = 5A (8 x 20 μs pulse) 28 V Junction Capacitance CJ VR = 0V, f = 1MHz 0.5 pF Characteristic Curves Fig2. ESD Pulse Waveform (according to IEC 61000-4-2) Fig1. 8/20µ s Pulse Waveform 120 IPP - Peak Pulse Current - % of IPP 100 100% TEST WAVEFORM PARAMETERS tr=8 s td=20 s Peak Value IPP 80 Percent of Peak Pulse Current % tr 60 40 td=t IPP/2 20 0 0 5 10 15 20 25 30 10% tr = 0.7~1ns Time (ns) 30ns 60ns t - Time ( s) Fig3. 90% Power Derating Curve % of Rated Power 110 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 150 Ambient Temperature –TA (ºC) Rev : 01.06.2014 2/7 www.leiditech.com CM1213-04SO Applications Information Figure 1. Data Line and Power Supply Protection Using VCC as reference Figure 2. Data Line Protection with Bias and Power Supply Isolation Resistor Device Connection Options for Protection of Four High-Speed Data Lines The C M 1 2 1 3 - 0 4 S O is designed to protect four data lines from transient over-voltages by clamping them to a fixed reference. When the voltage on the protected line exceeds the reference voltage (plus diode VF) the steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. Data lines are connected at pins 1, 3, 4 and 6. The negative reference (REF1) is connected at pin 2. This pin should be connected directly to a ground plane on the board for best results. The path length is kept as short as possible to minimize parasitic inductance. The positive reference (REF2) is connected at pin 5. The options for connecting the positive reference are as follows: 1. To protect data lines and the power line, connect pin 5 directly to the positive supply rail (VCC). In this configuration the data lines are referenced to the supply voltage. The internal TVS diode prevents over-voltage on the supply rail (See Figure1). 2. The CM1213-04SO can be isolated from the power supply by adding a series resistor between pin 5 and VCC. A value of 100kΩ is recommended. The internal TVS and steering diodes remain biased, providing the advantage of lower capacitance (See Figure2). Figure 3. Data Line Protection Using Internal TVS Diode as Reference Rev : 01.06.2014 3/7 3. In applications where no positive supply reference is available, or complete supply isolation is desired, the internal TVS may be used as the reference. In this case, pin 5 is not connected. The steering diodes will begin to conduct when the voltage on the protected line exceeds the working voltage of the TVS (plus one diode drop) (See Figure3). www.leiditech.com CM1213-04SO Applications Information (Continue) Applications Information Video Interface Protection Figure 4．Video Interface Protection Video interfaces are susceptible to transient voltages resulting from electrostatic discharge (ESD) and “hot plugging” cables. If left unprotected, the video interface IC may be damaged or even destroyed. Protecting a high-speed video port presents some unique challenges. SRV05-4 First, any added protection device must have extremely low capacitance and low leakage current so that the integrity of the video signal is not compromised. Second, the protection component must be able to absorb high voltage transients without damage or degradation. As a minimum, the device should be rated to handle ESD voltages per IEC61000-4-2, level 4 (±15kV air, ±8kV contact). The clamping voltage of the device (when conducting high current ESD pulses) must be sufficiently SRV05-4 low enough to protect the sensitive CMOS IC. If the Figure 5 - Dual USB Port Protection clamping voltage is too high, the “protected” device may latch-up or be destroyed. Finally, the device must take up a relatively small amount of board space, particularly in portable applications such as notebooks and handhelds. The CM1213-04SO is designed to meet or exceed all of the above criteria. A typical video interface protection circuit is shown in Figure 4. All exposed lines are SRV05-4 protected including R, G, B, H-Sync, V-Sync, and the ID lines for plug and play monitors. Universal Serial Bus ESD Protection The CM1213-04SO may also be used to protect the USB ports on monitors, computers, peripherals or portable systems. Each device will protect up to two Figure 6 - SIM Port USB ports (Figure5). When the voltage on the data lines exceed the bus voltage (plus one diode drop), the internal rectifiers are forward biased conducting the transient current away from the protected controller chip. The TVS diode directs the surge to ground. The TVS diode also acts to suppress ESD strikes SRV05-4 directly on the voltage bus. Thus, both power and data pins are protected with a single device. Rev : 01.06.2014 4/7 www.leiditech.com CM1213-04SO Applications Information (Continue) Applications Information DVI Protection The small geometry of a typical digital-visual interface (DVI) graphic chip will make it more susceptible to electrostatic discharges (ESD) and cable discharge events (CDE). Transient protection of a DVI port can be challenging. Digital-visual interfaces can often transmit and receive at a rate equal to or above 1Gbps. The high-speed data transmission requires the protection device to have low capacitance to maintain signal integrity and low clamping voltage to reduce stress on the protected IC. The CM1213-04SO has a low typical insertion loss of 1.5kV. If more common mode protection is needed, figure 9 shows how to design the CM1213-04SO on the IC side of the 10/100. www.leiditech.com CM1213-04SO Applications Information (Continue) Applications Information Figure 8 - 10/100 Ethernet Differential Protection Figure 9 - 10/100 Ethernet Differential and Common Mode Protection Rev : 01.06.2014 6/7 www.leiditech.com CM1213-04SO SOT-26 Package Outline & Dimensions Inches Symbol Min. A θ Nom. Max. Min. Nom. Max. 0.035 - 0.057 0.90 - 1.45 A1 0.000 - 0.006 0.00 - 0.15 A2 0.035 0.045 0.051 0.90 1.15 1.30 b 0.010 - 0.020 0.25 - 0.50 - 0.009 0.08 - 0.22 c 0.003 D 0.110 0.114 0.122 2.80 2.90 3.10 E1 0.060 0.063 0.069 1.50 1.60 1.75 E 0.110 BSC 2.80 BSC e 0.037 BSC 0.95 BSC e1 0.075 BSC 1.90 BSC L 0.012 0.018 0.024 0.30 0.45 0.60 L1 θ Soldering Footprint Millimeters (0.024) 0° - (0.60) 10° 0° - 10° aaa 0.004 0.10 bbb 0.008 0.20 ccc 0.008 0.20 Symbol Inches Millimeters C (0.098) (2.50) G 0.055 1.40 P 0.037 0.95 X 0.024 0.60 Y 0.043 1.10 Z 0.141 3.60 Shanghai Leiditech Electronic Co.,Ltd Email: sale1@leiditech.com Tel : +86- 021 50828806 Fax : +86- 021 50477059 Rev : 01.06.2014 7/7 www.leiditech.com