NCT5655Y/W
Nuvoton
NCT5655Y/W
16-bit I2C-bus and SMBus GPIO
controller with interrupt
Revision: 1.0
Date: May, 2016
- I -
Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
NCT5655Y/W Datasheet Revision History
PAGES
1
DATES
VERSION
18 , May, 2016
1.0
th
MAIN CONTENTS
Public release for MP
2.
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
Table of Contents1.
GENERAL DESCRIPTION ............................................................................................................................. 1
2.
FEATURES ................................................................................................................................................. 1
2.1
2.2
GENERAL FEATURES ...................................................................................................................................... 1
KEY SPECIFICATIONS...................................................................................................................................... 1
3.
PIN CONFIGURATION ................................................................................................................................ 2
4.
PIN DESCRIPTION ...................................................................................................................................... 3
5.
BLOCK DIAGRAM ...................................................................................................................................... 4
6.
FUNCTION DESCRIPTIONS ......................................................................................................................... 5
6.1
6.1
6.2
6.3
7.
ACCESS INTERFACE ....................................................................................................................................... 5
POWER-ON RESET........................................................................................................................................ 6
I/O PORT ................................................................................................................................................... 7
INTERRUPT OUTPUT ...................................................................................................................................... 8
REGISTER DESCRIPTION .......................................................................................................................... 10
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
8.
REGISTER 00H – GPIO0X INPUT PORT REGISTER .............................................................................................. 10
REGISTER 01H – GPIO1X INPUT PORT REGISTER .............................................................................................. 10
REGISTER 02H – GPIO0X OUTPUT PORT REGISTER ........................................................................................... 10
REGISTER 03H – GPIO1X OUTPUT PORT REGISTER ........................................................................................... 10
REGISTER 04H – GPIO0X POLARITY INVERSION REGISTER .................................................................................. 11
REGISTER 05H – GPIO1X POLARITY INVERSION REGISTER .................................................................................. 11
REGISTER 06H – GPIO0X CONFIGURATION REGISTER........................................................................................ 11
REGISTER 07H – GPIO1X CONFIGURATION REGISTER........................................................................................ 11
REGISTER 10H – INT#/LED/BEEP CONFIGURATION REGISTER ........................................................................... 12
REGISTER 12H – GPIO0X OUTPUT TYPE REGISTER ............................................................................................ 12
REGISTER 13H – GPIO1X OUTPUT TYPE REGISTER ............................................................................................ 13
REGISTER 14H – LED CONFIGURATION REGISTER ............................................................................................. 13
REGISTER 15H – BEEP CONFIGURATION REGISTER ........................................................................................... 14
REGISTER 18H – REGISTER ON/OFF CONFIGURATION REGISTER ......................................................................... 14
REGISTER 1DH – CHIP ID HIGH BYTE REGISTER ................................................................................................. 14
REGISTER 1EH – CHIP ID LOW BYTE REGISTER .................................................................................................. 14
DC AND AC SPECIFICATION ..................................................................................................................... 15
8.1
8.2
8.3
9.
10.
ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 15
DC CHARACTERISTICS .................................................................................................................................. 15
AC CHARACTERISTICS .................................................................................................................................. 17
ORDERING INFORMATION ...................................................................................................................... 19
TOP MARKING SPECIFICATION ............................................................................................................ 19
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
11.
11.1
11.2
PACKAGE DIMENSION OUTLINE .......................................................................................................... 20
QFN 24L 4X4MM2, THICKNESS: 0.8MM, PITCH:0.50MM................................................................................ 20
2
TSSOP 24L 4.4X7.8 MM .......................................................................................................................... 21
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
1. GENERAL DESCRIPTION
2
The NCT5655Y/W is a general purpose input/output IC with I C-bus/SMBus that provides 16 bits of
General Purpose Input/Output (GPIO) expansion. The GPIO expanders provide a simple solution
when additional I/O is needed for push buttons, flashing LED output, BEEP functions, sensors and so
on. It also provides an interrupt to inform the system master when a transistion occurs on general
purpose input pins.
2
The NCT5655Y/W provides I C-bus/SMBus address setting pins to set the address during power-on
2
reset or from external reset, allowing up to eight devices to share the same I C-bus/SMBus.
2. FEATURES
2.1
General Features
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant I/Os
Polarity inversion register
General purpose output setting for level or pulse mode
Interrupt output setting for level or pulse mode
Interrupt notification support for system event occurs
Low standby current
Noise filter on SCL/SDA inputs
No glitch on power-up
Internal power-on reset
16 I/O pins which default to 16 inputs with push-pull or open-drain selection
Flashing LED output
PC beep output
0 Hz to 400 kHz clock frequency
Halogen free packages (RoHS Compliable) offered: QFN24 and TSSOP24
2.2
Key Specifications
Supply Voltage is 2.3 V to 5.5 V
Standby Current is 1uA max.
Operating Temperature is from -40 °C to 85 °C
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
A2
A1
INT#/LED/BEEP
VDD
SDA
SCL
3. PIN CONFIGURATION
QFN24
24 23 22 21 20 19
GPIO00
GPIO01
GPIO02
GPIO03
GPIO04
GPIO05
1
2
3
4
5
6
NCT5655Y
18
17
16
15
14
13
A0
GPIO17
GPIO16
GPIO15
GPIO14/BEEP
GPIO13/LED3
24
23
22
21
20
19
18
17
16
15
14
13
VDD
SDA
SCL
A0
GPIO17
GPIO16
GPIO15
GPIO14/BEEP
GPIO13/LED3
GPIO12/LED2
GPIO11/LED1
GPIO10/LED0
GPIO06
GPIO07
VSS
GPIO10/LED0
GPIO11/LED1
GPIO12/LED2
7 8 9 10 11 12
TSSOP24
INT#/LED/BEEP
A1
A2
GPIO00
GPIO01
GPIO02
GPIO03
GPIO04
GPIO05
GPIO06
GPIO07
VSS
1
2
3
4
5
6
7
8
9
10
11
12
NCT5655W
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
4. PIN DESCRIPTION
Symbol
Pin
Description
TSSOP24
QFN24
INT#/LED/BEEP
1
22
Interrupt output (open-drain), or LED or BEEP output (push-pull)
A1
2
23
Address input 1 (Connect directly to VDD or VSS)
A2
3
24
Address input 2 (Connect directly to VDD or VSS)
GPIO00
4
1
General purpose input/output (GPIO00)
GPIO01
5
2
General purpose input/output (GPIO01)
GPIO02
6
3
General purpose input/output (GPIO02)
GPIO03
7
4
General purpose input/output (GPIO03)
GPIO04
8
5
General purpose input/output (GPIO04)
GPIO05
9
6
General purpose input/output (GPIO05)
GPIO06
10
7
General purpose input/output (GPIO06)
GPIO07
11
8
General purpose input/output (GPIO07)
VSS
12
9
Supply ground
GPIO10/LED0
13
10
General purpose input/output (GPIO10) and LED signal output
(LED0)
GPIO11/LED1
14
11
General purpose input/output (GPIO11) and LED signal output
(LED1)
GPIO12/LED2
15
12
General purpose input/output (GPIO12) and LED signal output
(LED2)
GPIO13/LED3
16
13
General purpose input/output (GPIO13) and LED signal output
(LED3)
GPIO14/BEEP
17
14
General purpose input/output (GPIO14) and BEEP signal output
(BEEP)
GPIO15
18
15
General purpose input/output (GPIO15)
GPIO16
19
16
General purpose input/output (GPIO16)
GPIO17
20
17
General purpose input/output (GPIO17)
A0
21
18
Address input 0 (Connect directly to VDD or VSS)
SCL
22
19
Serial clock line (Connect to VDD through a pull-up resistor)
SDA
23
20
Serial data line (Connect to VDD through a pull-up resistor)
VDD
24
21
Supply voltage
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
5. BLOCK DIAGRAM
GPIO00
NCT5655Y/W
GPIO01
A0
8-bit
GPIO02
Input/
Output
Ports
A1
A2
GPIO03
GPIO04
GPIO05
write pulse
GPIO06
SCL
SDA
Input
Filter
I2C-BUS/SMBus
Control
&
LED/BEEP
Control
read pulse
GPIO07
GPIO10/LED0
GPIO11/LED1
8-bit
GPIO12/LED2
Input/
Output
Ports
GPIO13/LED3
GPIO14/BEEP
GPIO15
write pulse
GPIO16
VDD
read pulse
Power-On
Reset
GPIO17
VSS
VDD
LP
Filter
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INT#/LED/BEEP
Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
6. FUNCTION DESCRIPTIONS
6.1
Access Interface
2
NCT5655Y/W provides a two-wired serial interface which is compliant with I C-bus/SMBus Write Byte
and Read Byte protocol.
NCT5655Y/W I2C-bus/SMBus Address is:
2
Inputs
6.1.1
I C-bus/SMBus slave address
A2
A1
A0
(0, 1, 0, 0, A2, A1, A0, R/W)
L
L
L
40h
L
L
H
42h
L
H
L
44h
L
H
H
46h
H
L
L
48h
H
L
H
4Ah
H
H
L
4Ch
H
H
H
4Eh
Write to output port registers
Write to output port registers
slave address
command byte
(cont.)
SCL
SDA
A2
A1
A0
D7
R/W
START
data to port 0
D6
D5
ACK
(slave)
D4
D3
D2
D1
D0
ACK
(slave)
data to port 1
(cont.)
D7
D6
D5
D4
D3
D2
D1
D0
D7
ACK
(slave)
D6
D5
D4
D3
D2
D1
D0
ACK
(slave)
STOP
Data is transmitted to the NCT5655Y/W by sending the device address and setting the least significant
bit to a logic 0. The command byte is sent after the address and determines which register will receive
the data following the command byte.
The eight registers within the NCT5655Y/W are configured to operate as four registers pairs. The four
pairs are Input Ports, Output Ports, Polarity Inversion Ports, and Configuration Ports. After sending
data to one register, the next data byte will be sent to the other register in the pair. For example, if the
first byte is sent to Output Port 1 (register 3), then the next byte will be stored in Output Port 0 (register
2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each
8-bit register may be updated independently of the other registers.
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
6.1.2
Read from output port registers
Read from output port registers
slave address
command byte
(cont.)
SCL
SDA
A2
A1
A0
D7
R/W
START
slave address
D6
D5
D4
D3
D2
D1
D0
ACK
(slave)
(cont.)
ACK
(slave)
(cont.)
A2
START
(repeated)
A1
A0
R/W
data to port 0
ACK
(slave)
data to port 1
(cont.)
D7
D6
D5
D4
D3
D2
D1
D0
D7
ACK
(master)
D6
D5
D4
D3
D2
D1
D0
NACK
(master)
STOP
In order to read data from the NCT5655Y/W, the bus master must first send the NCT5655Y/W
address with the least significant bit set to a logic 0. The command byte is sent after the address and
determines which register will be accessed. After a restart, the device address is sent again, but this
time the least significant bit is set to a logic 1. Data from the register defined by the command byte will
then be sent by the NCT5655Y/W. Data is clocked into the register on the falling edge of the
acknowledge clock pulse. After the first byte is read, additional bytes may be read out the data will
now reflect the information in the other register in the pair. For example, if you read Input Port 1, then
the next byte read would be Input Port 0. There is no limitation on the number of data bytes received
in one read transmission but the final byte received, the bus master must not acknowledge the data.
6.1
Power-On Reset
When power is applied to VDD, an internal power-on reset holds the NCT5655Y/W in a reset condition
until VDD has reached VPOR. At that point, the reset condition is released and the NCT5655Y/W
2
registers and I C-bus/SMBus state machine will initialize to their default states. The power-on reset
typically completes the reset and enables the part by the time the power supply is above VPOR.
However, when it is required to reset the part by lowering the power supply, it is necessary to lower it
below 0.2 V.
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
6.2
I/O Port
data from
shift register
D
SET
Q
write pulse
CLR
output port
register data
Q
output type
register
data from
shift register
VDD
configuration
register
data from
shift register
D
write
configuration
pulse
SET
CLR
0
Q
1
Q1
100 kΩ
Q
D
SET
Q
write pulse
CLR
Q
I/O pin
output port
register
Q2
input port
register
D
SET
VSS
Q
read pulse
CLR
input port
register
Q
to INT#
polarity inversion
register
data from
shift register
D
write
polarity
pulse
SET
CLR
polarity
inversion
register data
Q
Q
When an I/O is configured as an input (default), FETs Q1 and Q2 are off, creating a high-impedance
input with a weak pull-up to VDD. The input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of the Output
Port register. Care should be exercised if an external voltage is applied to an I/O configured as an
output because of the low-impedance path that exists between the pin and either VDD or VSS.
*GPIO Output Table:
GPIO CONFIGURATION
REGISTER
OUTPUT PORT
REGISTER
OUTPUT VALUE AT PIN
0
0
1
1
WAVE
0
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
6.3
Interrupt Output
The open-drain interrupt output is activated when one of the port pins changes state and the pin is
configured as an input. The interrupt is deactivated when the input returns to its previous state or the
Input Port register is read. A pin configured as an output cannot cause an interrupt. Since each 8-bit
port is read independently, the interrupt caused by Port 0 will not be cleared by a read of Port 1 or the
other way around.
Example 1: GPIO00 input; polarity register set ‘0’; level output (Input Port register is read)
GPIO00
Input Port 0
register (bit 0)
INT#/LED/BEEP
input low SMBus read
(read pulse)
input high SMBus read
(read pulse)
Example 2: GPIO00 input; polarity register set ‘0’; level output (input returns to its previous state)
GPIO00
Input Port 0
register (bit 0)
INT#/LED/BEEP
input low
input returns its previous state
Example 3: GPIO00 input; polarity register set ‘0’; pulse output (Input Port register is read)
tp=250us
tp=250us
GPIO00
Input Port 0
register (bit 0)
INT#/LED/BEEP
input low
SMBus read
(read pulse)
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input high
SMBus read
(read pulse)
Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
Example 4: GPIO00 input; polarity register set ‘0’; pulse output (input returns to its previous state)
tp=250us
GPIO00
Input Port 0
register (bit 0)
INT#/LED/BEEP
input low
input returns to its previous state
*INT#/LED/BEEP output LED signal during low period when it is configured to LED output.
*INT#/LED/BEEP output BEEP signal during low period when it is configured to BEEP output.
INT# Output Mode Table:
INT OUTPUT MODE
POLARITY
OUTPUT
0
0
1
1
0
Low Pulse
1
High Pulse
WAVE
Level
Pulse
*In level mode, if INT# is activated, it will be de-activated when Input Port register is read or when
input returns to its previous state. (Example 1~2)
*In pulse mode, interrupt will be activated again unless Input Port register is read or unless input
returns to its previous state and changes again. (Example 3~4)
*The INT# pulse mode output waveform width is 250uS.
* The control register is Register 10h.
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Revision 1.0
NCT5655Y/W
7. REGISTER DESCRIPTION
7.1
Register 00h – GPIO0x Input port register
This register is an input-only port. It reflects the incoming logic levels of the pins, regardless of whether the
pin is defined as an input or an output by Register 06h. This register is read only.
BIT
7
6
5
4
3
2
1
0
R/W
RO
RO
RO
RO
RO
RO
RO
RO
Default
X
X
X
X
X
X
X
X
*This register reflects the respective GPIO0 pins level.
*The default value ‘X’ is determined by the externally applied logic level.
7.2
Register 01h – GPIO1x Input port register
This register is an input-only port. It reflects the incoming logic levels of the pins, regardless of whether the
pin is defined as an input or an output by Register 07h. This register is read only.
BIT
7
6
5
4
3
2
1
0
R/W
RO
RO
RO
RO
RO
RO
RO
RO
Default
X
X
X
X
X
X
X
X
*This register reflects the respective GPIO1 pins level.
*The default value ‘X’ is determined by the externally applied logic level.
7.3
Register 02h – GPIO0x Output port register
This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by
Register 06h. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
BIT
7
6
5
4
3
2
1
0
R/W
RW
RW
RW
RW
RW
RW
RW
RW
Default
1
1
1
1
1
1
1
1
7.4
Register 03h – GPIO1x Output port register
This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by
Register 07h. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
BIT
7
6
5
4
3
2
1
0
R/W
RW
RW
RW
RW
RW
RW
RW
RW
Default
1
1
1
1
1
1
1
1
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
7.5
Register 04h – GPIO0x Polarity Inversion register
This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set
(written with ‘1’), the Input port data polarity is inverted. If a bit in this register is cleared (written with ‘0’),
the Input port data polarity is retained.
BIT
7
6
5
4
3
2
1
0
R/W
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
7.6
Register 05h – GPIO1x Polarity Inversion register
This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set
(written with ‘1’), the Input port data polarity is inverted. If a bit in this register is cleared (written with ‘0’),
the Input port data polarity is retained.
BIT
7
6
5
4
3
2
1
0
R/W
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
7.7
Register 06h – GPIO0x Configuration register
This register configures the directions of the I/O pins. If a bit in this register is set (written with ‘1’), the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is
cleared (written with ‘0’), the corresponding port pin is enabled as an output. Note that there is a high value
resistor tied to VDD at each pin. At reset, the device’s ports are inputs with a pull-up to VDD.
BIT
7
6
5
4
3
2
1
0
R/W
RW
RW
RW
RW
RW
RW
RW
RW
Default
1
1
1
1
1
1
1
1
*This register configures the respective GPIO0 pins as input mode (‘1’) or output mode (‘0’).
7.8
Register 07h – GPIO1x Configuration register
This register configures the directions of the I/O pins. If a bit in this register is set (written with ‘1’), the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is
cleared (written with ‘0’), the corresponding port pin is enabled as an output. Note that there is a high value
resistor tied to VDD at each pin. At reset, the device’s ports are inputs with a pull-up to VDD.
BIT
7
6
5
4
3
2
1
0
R/W
RW
RW
RW
RW
RW
RW
RW
RW
Default
1
1
1
1
1
1
1
1
*This register configures the respective GPIO1 pins as input mode (‘1’) or output mode (‘0’).
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
7.9
Register 10h – INT#/LED/BEEP Configuration register
More INT#/LED/BEEP function description is in 6.3 Interrupt Output section.
BIT
7
6
5
4
3
2
1
0
R/W
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
Bit1-Bit0: INT# output select register
= 11, Reserved
= 10, BEEP output
= 01, LED output
= 00, INT# output
Bit2: INT# output type register
= 1, Pulse mode
= 0, Level mode
Bit3: INT# polarity select register
= 1, Inverted
= 0, Non-inverted
Bit5-4: LED configuration register
=11, LED frequency = 2 Hz; duty-cycle 50%
=10, LED frequency = 1 Hz; duty-cycle 50%
=01, LED frequency = 0.5 Hz; duty-cycle 50%
=00, LED function is disabled
Bit7-6: BEEP configuration register
=11, BEEP frequency = 4K Hz; tone = 250 Hz
=10, BEEP frequency = 2K Hz; tone = 10 Hz
=01, BEEP frequency = 1K Hz / 500 Hz; tone= 1 Hz
=00, BEEP function is disabled
7.10 Register 12h – GPIO0x Output type register
This register configures the output type of the GPIO0 I/O pins. If a bit in this register is set (written with ‘1’),
the corresponding output port is enabled as a push-pull output driver. If a bit in this register is cleared
(written with ‘0’), the corresponding output port is enabled as an open-drain output driver. Note that there is
a high value resistor tied to VDD at each pin.
BIT
7
6
5
4
3
2
1
0
R/W
RW
RW
RW
RW
RW
RW
RW
RW
Default
1
1
1
1
1
1
1
1
*This register configures the respective GPIO0 pins as push-pull mode (‘1’) or open-drain mode (‘0’).
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
7.11 Register 13h – GPIO1x Output type register
This register configures the output type of the GPIO1 I/O pins. If a bit in this register is set (written with ‘1’),
the corresponding output port is enabled as a push-pull output driver. If a bit in this register is cleared
(written with ‘0’), the corresponding output port is enabled as an open-drain output driver. Note that there is
a high value resistor tied to VDD at each pin.
BIT
7
6
5
4
3
2
1
0
R/W
RW
RW
RW
RW
RW
RW
RW
RW
Default
1
1
1
1
1
1
1
1
*This register configures the respective GPIO1 pins as push-pull mode (‘1’) or open-drain mode (‘0’).
7.12 Register 14h – LED Configuration register
This register configures the output signal of the GPIO10/LED0~GPIO13/LED3 I/O pins. When output LED
signal, the pin must define as an output by Register 07h. For GPIO function use, the corresponding
register must set to “00”.
BIT
7
6
5
4
3
2
1
0
R/W
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
Bit1-Bit0: GPIO10/LED0 configuration register
=11, LED frequency = 2 Hz; duty-cycle 50%
=10, LED frequency = 1 Hz; duty-cycle 50%
=01, LED frequency = 0.5 Hz; duty-cycle 50%
=00, LED function is disabled
Bit3-Bit2: GPIO11/LED1 configuration register
=11, LED frequency = 2 Hz; duty-cycle 50%
=10, LED frequency = 1 Hz; duty-cycle 50%
=01, LED frequency = 0.5 Hz; duty-cycle 50%
=00, LED function is disabled
Bit5-Bit4: GPIO12/LED2 configuration register
=11, LED frequency = 2 Hz; duty-cycle 50%
=10, LED frequency = 1 Hz; duty-cycle 50%
=01, LED frequency = 0.5 Hz; duty-cycle 50%
=00, LED function is disabled
Bit7-Bit6: GPIO13/LED3 configuration register
=11, LED frequency = 2 Hz; duty-cycle 50%
=10, LED frequency = 1 Hz; duty-cycle 50%
=01, LED frequency = 0.5 Hz; duty-cycle 50%
=00, LED function is disabled
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
7.13 Register 15h – BEEP Configuration register
This register configures the output signal of the GPIO14/BEEP I/O pins. When output BEEP signal, the pin
must define as an output by Register 07h. For GPIO function use, the corresponding register must set to
“00”.
BIT
7
6
5
4
3
2
1
0
R/W
RO
RO
RO
RO
RO
RO
RW
RW
Default
0
0
0
0
0
0
0
0
Bit1-0: GPIO14/BEEP configuration register
=11, BEEP frequency = 4K Hz; tone = 250 Hz
=10, BEEP frequency = 2K Hz; tone = 10 Hz
=01, BEEP frequency = 1K Hz / 500 Hz; tone= 1 Hz
=00, BEEP function is disabled
7.14 Register 18h – Register ON/OFF Configuration register
This register configures the register 10h~1Fh on/off for this chip.
BIT
7
6
5
4
3
2
1
0
R/W
RO
RO
RO
RO
RO
RO
RO
RW
Default
0
0
0
0
0
0
0
1
Bit0: Register 10h~1Fh ON/OFF configuration register
=1, registers 10h~1Fh will be off.
=0, registers 10h~1Fh will be on.
Bit7-1: Reserved.
7.15 Register 1Dh – Chip ID high byte register
This register indicates the high byte of the Chip ID.
BIT
7
6
5
4
3
2
1
0
R/W
RO
RO
RO
RO
RO
RO
RO
RO
Default
1
1
0
1
0
0
0
1
7.16 Register 1Eh – Chip ID low byte register
This register indicates the low byte of the Chip ID.
BIT
7
6
5
4
3
2
1
0
R/W
RO
RO
RO
RO
RO
RO
RO
RO
Default
0
1
0
0
X
X
X
X
Bit3-0: XXXX=0000~1111
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
8. DC AND AC SPECIFICATION
8.1
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Power Supply Voltage
2.3 to 5.5
V
Input Voltage
2.3 to 5.5
V
Operating Temperature
-40 to +85
C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life
and reliability of the device.
8.2
DC Characteristics
DC characteristics at VDD=2.3V to 5.5V; VSS=0V; Tamb=-40℃ to +85℃; unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
2.3
-
5.5
V
-
135
200
uA
-
1.1
1.5
mA
-
0.25
1
uA
-
1.5
1.65
V
Supply
VDD
Supply Voltage
IDD
Supply Current
Operating mode; VDD=5.5V;
no load; fSCL=100KHz
Standby mode; VDD=5.5V;
no load; VI=VSS; fSCL=0KHz;
Istb
Standby Current
I/O=inputs
Standby mode; VDD=5.5V;
no load; VI=VDD; fSCL=0KHz;
I/O=inputs
VPOR
Power-on reset voltage
No load; VI=VDD or VSS
Input SCL; input/output SDA
VIL
LOW-level input voltage
-0.5
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
IOL
LOW-level output current
VOL=0.4V
3
-
-
mA
IL
leakage current
VI=VDD or VSS
-1
-
+1
uA
Ci
input capacitance
VI=VSS
-
6
10
pF
-0.5
-
+0.3VDD
V
I/Os
VIL
LOW-level input voltage
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
Symbol
Parameter
VIH
HIGH-level input voltage
IOL
LOW-level output current
VOH
HIGH-level output
voltage
Conditions
Min.
Typ.
Max.
Unit
0.7VDD
-
5.5
V
VDD=2.3V to 5.5V; VOL=0.5V
8
(8 to 20)
-
mA
VDD=2.3V to 5.5V; VOL=0.7V
10
(10 to 24)
-
mA
IOH=-8mA; VDD=2.3V
1.8
-
-
V
IOH=-10mA; VDD=2.3V
1.7
-
-
V
IOH=-8mA; VDD=3.0V
2.6
-
-
V
IOH=-10mA; VDD=3.0V
2.5
-
-
V
IOH=-8mA; VDD=4.75V
4.1
-
-
V
IOH=-10mA; VDD=4.75V
4.0
-
-
V
ILIH
HIGH-level input leakage
current
VDD=5.5V; VI=VDD
-
-
1
uA
ILIL
LOW-level input leakage
current
VDD=5.5V; VI=VDD
-
-
-100
uA
Ci
input capacitance
-
3.7
5
pF
Co
output capacitance
-
3.7
5
pF
3
-
-
mA
Interrupt INT_N
IOL
LOW-level output current
VOL=0.4V
Select Inputs A0, A1, A2
VIL
LOW-level input voltage
-0.5
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
ILI
input leakage current
-1
-
+1
uA
pin at VDD or VSS
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
8.3
AC Characteristics
Symbol
Parameter
Conditions
Standard-mode
Fast-mode
Unit
Min.
Max.
Min.
Max.
0
100
0
400
kHz
fSCL
SCL clock frequency
tBUF
Bus free time between a STOP
and START condition
4.7
-
1.3
-
us
tHD;STA
Hold time (repeated) START
condition
4.0
-
0.6
-
us
tSU;STA
Set-up time for a repeated
START condition
4.7
-
0.6
-
us
tSU;STO
Set-up time for STOP condition
4.0
-
0.6
-
us
tVD;ACK
Data valid acknowledge time
0.3
3.45
0.1
0.9
us
tHD;DAT
Data hold time
0
-
0
-
us
tVD;DAT
Data valid time
300
-
50
-
ns
tSU;DAT
Data set-up time
250
-
100
-
ns
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
us
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
-
us
tf
Fall time of both SDA and SCL
signals
-
300
20+0.1Cb
300
ns
tr
Rise time of both SDA and SCL
signals
-
1000
20+0.1Cb
300
ns
Cb
Capacitive load for each bus line
-
400
-
400
pF
tSP
Pulse width of spikes that must
be suppressed by the input filter
-
50
-
50
ns
tv(Q)
Data output valid time
-
200
-
200
ns
tsu(D)
Data input set-up time
150
-
150
-
ns
th(D)
Data input hold time
1
-
1
-
us
tv(INT_N)
Valid time on pin INT_N
-
4
-
4
us
trst(INT_N)
Reset time on pin INT_N
-
4
-
4
us
Port timing
INT_N
[1] tVD;ACK = Time for acknowledgement signal from SCL low to SDA out low.
[2] tVD;DAT = Minimum time for SDA data out to be valid following SCL low.
[3] Cb = Total capacitance of one bus line in pF.
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
2
Definition of timing on the I C-bus/SMBus
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
9. ORDERING INFORMATION
PART NUMBER
PACKAGE TYPE
REMARK
NCT5655Y
QFN24
Green Package (Halogen-free)
NCT5655W
TSSOP24
Green Package (Halogen-free)
10. TOP MARKING SPECIFICATION
st
NCT5655Y
618
GA E41700
03-xx
1 line: Part number NCT5655Y
nd
th
2 ~ 4 line: Tracking code
618: Packages assembled in Year 2016, week 18
G: Assembly house ID
A: IC version
E4170003-xx: Lot number
st
1 line: Nuvoton Logo
nd
2 line: Part number: NCT5655W
NCT5655W
618GASA
rd
3 line: Tracking code: 618 GA SA
618: Packages assembled in Year 2015, week 18
G: Assembly house ID
A: IC version
SA: Internal use code
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
11. PACKAGE DIMENSION OUTLINE
11.1 QFN 24L 4x4mm2, Thickness: 0.8mm, Pitch:0.50mm
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
11.2 TSSOP 24L 4.4x7.8 mm2
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Publication Release Date: May, 2016
Revision 1.0
NCT5655Y/W
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
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Publication Release Date: May, 2016
Revision 1.0
