S-8265C Series
www.ablic.com
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION
FOR 3-SERIAL TO 5-SERIAL CELL PACK
(SECONDARY PROTECTION)
© ABLIC Inc., 2019-2021
Rev.1.5_00
The S-8265C Series is a secondary protection IC with cell balancing function for lithium-ion rechargeable batteries, which
includes high-accuracy voltage detection circuits, delay circuits, and FETs for cell balancing discharge. The cell balancing
function is effective for balancing the voltage of serially connected batteries. Short-circuiting between cells enables cell
balancing for serial connection of three cells to five cells.
Features
•
•
•
•
•
•
•
•
•
•
High-accuracy voltage detection circuit for each cell
Cell balancing detection voltage n (n = 1 to 5):
2.700 V to 4.650 V (5 mV step)
Accuracy ±20 mV (Ta = +25°C)
Accuracy ±25 mV (Ta = −10°C to +60°C)
Cell balancing release voltage n (n = 1 to 5)*1:
2.700 V to 4.650 V
Accuracy ±50 mV (Ta = +25°C)
Overcharge detection voltage n (n = 1 to 5)*2:
2.750 V to 4.700 V (5 mV step)
Accuracy ±20 mV (Ta = +25°C)
Accuracy ±25 mV (Ta = −10°C to +60°C)
Overcharge release voltage n (n = 1 to 5)*3, *4:
2.750 V to 4.700 V
Accuracy ±50 mV (Ta = +25°C)
Built-in cell balancing discharging FET for each cell
Output form:
CMOS output, Nch open-drain output
Output logic:
Active "H", active "L"
Built-in test mode function to check cell balancing detection voltage and overcharge detection voltage with shortened delay time
High-withstand voltage:
Absolute maximum rating 28 V
Wide operation voltage range:
3.6 V to 26 V
Wide operation temperature range:
Ta = −40°C to +85°C
Low current consumption
During operation:
0.3 μA typ., 0.7 μA max. (Ta = +25°C)
Lead-free (Sn 100%), halogen-free
*1.
*2.
*3.
*4.
Cell balancing release voltage = Cell balancing detection voltage + Cell balancing hysteresis voltage
(Cell balancing hysteresis voltage can be selected from a range of 0 mV to −400 mV in 50 mV step.)
Satisfy Overcharge detection voltage ≥ Cell balancing detection voltage + 50 mV when selecting them.
Overcharge release voltage = Overcharge detection voltage + Overcharge hysteresis voltage
(Overcharge hysteresis voltage can be selected from a range of 0 mV to −400 mV in 50 mV step.)
Satisfy Overcharge release voltage ≥ Cell balancing release voltage + 50 mV when selecting them.
Application
•
Lithium-ion rechargeable battery pack
Packages
•
•
TMSOP-8
SNT-8A
1
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8265C Series
Rev.1.5_00
Block Diagram
1. CMOS output product
VDD
VC1
Cell balancing
detection
comparator 1
Overcharge
detection
comparator 1
SW1
VC2
Cell balancing
detection
comparator 2
Overcharge
detection
comparator 2
SW2
Control logic
VC3
Cell balancing
detection
comparator 3
Overcharge
detection
comparator 3
SW3
VC4
Cell balancing
detection
comparator 4
Overcharge
detection
comparator 4
SW4
VC5
Cell balancing
detection
comparator 5
Overcharge
detection
comparator 5
SW5
VSS
Remark
2
Figure 1
The diodes in the figure are parasitic diodes.
Delay circuit
Oscillator
CO
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.5_00
S-8265C Series
2. Nch open-drain output product
VDD
VC1
Cell balancing
detection
comparator 1
Overcharge
detection
comparator 1
SW1
VC2
Cell balancing
detection
comparator 2
Overcharge
detection
comparator 2
SW2
Control logic
VC3
Cell balancing
detection
comparator 3
Delay circuit
CO
Oscillator
Overcharge
detection
comparator 3
SW3
VC4
Cell balancing
detection
comparator 4
Overcharge
detection
comparator 4
SW4
VC5
Cell balancing
detection
comparator 5
Overcharge
detection
comparator 5
SW5
VSS
Remark
Figure 2
The diodes in the figure are parasitic diodes.
3
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8265C Series
Rev.1.5_00
Product Name Structure
1. Product name
S-8265C
xx
-
xxxx
U
7
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
K8T2: TMSOP-8, Tape
I8T1: SNT-8A, Tape
Serial code*2
Sequentially set from AA to ZZ
*1. Refer to the tape drawing.
*2. Refer to "3. Product name list".
2. Packages
Table 1 Package Drawing Codes
Package Name
TMSOP-8
SNT-8A
4
Dimension
FM008-A-P-SD
PH008-A-P-SD
Tape
FM008-A-C-SD
PH008-A-C-SD
Reel
FM008-A-R-SD
PH008-A-R-SD
Land
−
PH008-A-L-SD
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.5_00
S-8265C Series
3. Product name list
3. 1 TMSOP-8
Table 2
Cell Balancing Cell Balancing Overcharge Overcharge
Detection
Release
Detection
Release
Output Form
Product Name
Voltage
Voltage
Voltage
Voltage
[VBU]
[VBL]
[VCU]
[VCL]
S-8265CAA-K8T2U7
4.145 V
4.145 V
4.275 V
4.275 V CMOS output
S-8265CAB-K8T2U7
3.900 V
3.850 V
4.130 V
3.880 V Nch open-drain output
S-8265CAC-K8T2U7
4.200 V
4.150 V
4.250 V
4.200 V Nch open-drain output
Remark Please contact our sales representatives for products other than the above.
Output Logic
Active "H"
Active "L"
Active "L"
3. 2 SNT-8A
Table 3
Product Name
Cell Balancing
Detection
Voltage
[VBU]
Cell Balancing
Release
Voltage
[VBL]
Overcharge
Detection
Voltage
[VCU]
Overcharge
Release
Voltage
[VCL]
Output Form
S-8265CAA-I8T1U7
4.145 V
4.145 V
4.275 V
4.275 V CMOS output
Remark
Please contact our sales representatives for products other than the above.
Output Logic
Active "H"
5
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8265C Series
Rev.1.5_00
Pin Configurations
1. TMSOP-8
Table 4
Pin No. Symbol
1
VDD
2
VC1
Top view
1
2
3
4
8
7
6
5
Figure 3
3
VC2
4
VC3
5
VC4
6
VC5
7
VSS
8
CO
Description
Input pin for positive power supply
Positive voltage connection pin of battery 1
Negative voltage connection pin of battery 1,
Positive voltage connection pin of battery 2
Negative voltage connection pin of battery 2,
Positive voltage connection pin of battery 3
Negative voltage connection pin of battery 3,
Positive voltage connection pin of battery 4
Negative voltage connection pin of battery 4,
Positive voltage connection pin of battery 5
Input pin for negative power supply,
Negative voltage connection pin of battery 5
Overcharge detection output pin
2. SNT-8A
Table 5
Pin No.
Top view
1
2
3
4
8
7
6
5
Figure 4
6
Symbol
1
2
VDD
VC1
3
VC2
4
VC3
5
VC4
6
VC5
7
VSS
8
CO
Description
Input pin for positive power supply
Positive voltage connection pin of battery 1
Negative voltage connection pin of battery 1,
Positive voltage connection pin of battery 2
Negative voltage connection pin of battery 2,
Positive voltage connection pin of battery 3
Negative voltage connection pin of battery 3,
Positive voltage connection pin of battery 4
Negative voltage connection pin of battery 4,
Positive voltage connection pin of battery 5
Input pin for negative power supply,
Negative voltage connection pin of battery 5
Overcharge detection output pin
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.5_00
S-8265C Series
Absolute Maximum Ratings
Table 6
(Ta = +25°C unless otherwise specified)
Item
Symbol
Input voltage between VDD pin and VSS pin
Input pin voltage
VDS
VDD
VIN
VC1
VC2
VC3
VC4
VC5
CMOS output product
CO pin
VCO
output voltage Nch open-drain output product
Operation ambient temperature
Topr
Storage temperature
Caution
Applied Pin
Unit
−
Absolute Maximum Rating
VSS − 0.3 to VSS + 28,
VC1 − 0.3 to VC1 + 5.6
VC2 − 0.3 to VC2 + 5.6
VC3 − 0.3 to VC3 + 5.6
VC4 − 0.3 to VC4 + 5.6
VC5 − 0.3 to VC5 + 5.6
VSS − 0.3 to VSS + 5.6
VSS − 0.3 to VDD + 0.3
VSS − 0.3 to VSS + 28
−40 to +85
−
−40 to +125
°C
CO
Tstg
V
V
V
V
V
V
V
V
°C
The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Thermal Resistance Value
Table 7
Item
Junction-to-ambient thermal resistance*1
Symbol
θJA
Condition
Board A
Board B
Board C
TMSOP-8
Board D
Board E
Board A
Board B
SNT-8A
Board C
Board D
Board E
Min.
−
−
−
−
−
−
−
−
−
−
Typ.
160
133
−
−
−
211
173
−
−
−
Max.
−
−
−
−
−
−
−
−
−
−
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
*1. Test environment: compliance with JEDEC STANDARD JESD51-2A
Remark Refer to " Power Dissipation" and "Test Board" for details.
7
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8265C Series
Rev.1.5_00
Electrical Characteristics
Table 8
Item
Symbol
Condition
(Ta = +25°C unless otherwise specified)
Test
Min.
Typ.
Max.
Unit
Circuit
Detection voltage
Ta = +25°C
Cell balancing detection voltage n
(n = 1, 2, 3, 4, 5)
VBUn
Cell balancing release voltage n
(n = 1, 2, 3, 4, 5)
VBLn
Overcharge detection voltage n
(n = 1, 2, 3, 4, 5)
VCUn
Overcharge release voltage n
(n = 1, 2, 3, 4, 5)
Input voltage
Operation voltage between VDD pin
and VSS pin
Input current
Ta = −10°C to +60°C*1
Ta = +25°C
Ta = −10°C to +60°C*1
VCLn
−
VDSOP
−
Current consumption during operation IOPE
Current consumption during
overdischarge
IOPED
VC1 pin input current
IVC1
VCn pin input current
(n = 2, 3, 4, 5)
Output current
CO pin source current
CO pin sink current
CO pin leakage current
Delay time
Cell balancing detection delay time
Overcharge detection delay time
Overcharge timer reset delay time
Cell balancing ON time
Cell balancing OFF time
Transition time to test mode
Internal resistance
Resistance between pins during cell
balancing discharge 1
Resistance between pins during cell
balancing discharge n (n = 2, 3, 4, 5)
−
IVCn
ICOH
ICOL
ICOLL
V1 = V2 = V3 = V4 = V5
= VBU × 0.75 V
V1 = V2 = V3 = V4 = V5
= VBU × 0.4 V
V1 = V2 = V3 = V4 = V5
= VBU × 0.75 V
V1 = V2 = V3 = V4 = V5
= VBU × 0.75 V
−
CMOS output product
Nch open-drain output product
−
−
−
−
−
−
tBU
tCU
tTR
tCBON
tCBOFF
tTST
RVC1
RVCn
VBL < 3.8V
VBL ≥ 3.8V
VBL < 3.8V
VBL ≥ 3.8V
VBU
− 0.020
VBU
− 0.025
VBL
− 0.050
VCU
− 0.020
VCU
− 0.025
VCL
− 0.050
VBU
VBU
VBL
VCU
VCU
VCL
VBU
+ 0.020
VBU
+ 0.025
VBL
+ 0.050
VCU
+ 0.020
VCU
+ 0.025
VCL
+ 0.050
V
1
V
1
V
1
V
1
V
1
V
1
3.6
−
26
V
−
−
0.3
0.7
μA
2
−
0.05
0.30
μA
2
−
−
0.3
μA
3
−0.3
0.0
0.3
μA
3
−
0.4
−
−
−
−
−20
−
0.1
μA
mA
μA
4
4
4
200
200
6
5.7
0.8
−
256
256
12
7.2
1.0
−
310
310
20
8.7
1.2
10
ms
ms
ms
s
s
ms
−
−
−
−
−
1
0.15
0.15
0.20
0.20
0.35
0.30
0.35
0.30
0.55
0.45
0.55
0.45
kΩ
kΩ
kΩ
kΩ
5
5
5
5
*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
8
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.5_00
S-8265C Series
Test Circuits
S-8265C Series transitions to the test mode when V0 is increased up to 4 V and the conditions continue for 10 ms or longer
after setting V0 = 0 V, V1 to V5 = 2.6 V.
1. Detection voltage
(Test circuit 1)
1. 1 Cell balancing detection voltage n (VBUn), cell balancing release voltage n (VBLn)
After transitioning to the test mode and then setting V0 = 4 V, V1 to V5 = VBU − 0.05 V, V1 is gradually increased.
When the CO pin output inverts, the voltage V1 is defined as VBU1.
V0 is then returned to 0 V. After setting V1 = VBU + 0.05 V, V2 to V5 = VBL − 0.05 V, V1 is gradually decreased.
When the CO pin output inverts again, the voltage V1 is defined as VBL1.
VBUn and VBLn (n = 2 to 5) can be defined in the same way as when n =1.
1. 2 Overcharge detection voltage n (VCUn), overcharge release voltage n (VCLn)
After transitioning to the test mode and then setting V0 = 0 V, V1 to V5 = VCU − 0.05 V, V1 is gradually increased.
When the CO pin output inverts, the voltage V1 is defined as VCU1.
V0 is then returned to 0 V. After setting V1 = VCU + 0.05 V, V2 to V5 = VCL − 0.05 V, V1 is gradually decreased.
When the CO pin output inverts again, the voltage V1 is defined as VCL1.
VCUn and VCLn (n = 2 to 5) can be defined in the same way as when n = 1.
2. Output current
(Test circuit 4)
2. 1 CMOS output product
SW6 and SW7 are set to OFF.
2. 1. 1 Active "H"
(1) CO pin source current (ICOH)
After transitioning to the test mode and then setting V0 = 0 V, V1 = 4.8 V, V2 to V5 = 2.05 V and V6 = 0.5 V,
SW6 is turned on. I6 is then defined as ICOH.
(2) CO pin sink current (ICOL)
After setting V0 = 0 V, V1 to V5 = 2.6 V and V7 = 0.5 V, SW7 is turned on. I7 is then defined as ICOL.
2. 1. 2 Active "L"
(1) CO pin source current (ICOH)
After setting V0 = 0 V, V1 to V5 = 2.6 V and V6 = 0.5 V, SW6 is turned on. I6 is then defined as ICOH.
(2) CO pin sink current (ICOL)
After transitioning to the test mode and then setting V0 = 0 V, V1 = 4.8 V, V2 to V5 = 2.05 V and V7 = 0.5 V,
SW7 is turned on. I7 is then defined as ICOL.
9
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8265C Series
Rev.1.5_00
2. 2 Nch open-drain output product
SW6 and SW7 are set to OFF.
2. 2. 1 Active "H"
(1) CO pin leakage current "L" (ICOLL)
After transitioning to the test mode and then setting V0 = 0 V, V1 = 4.8 V, V2 to V5 = 2.05 V and V7 = 28 V,
SW7 is turned on. I7 is then defined as ICOLL.
(2) CO pin sink current (ICOL)
After setting V0 = 0 V, V1 to V5 = 2.6 V and V7 = 0.5 V, SW7 is turned on. I7 is then defined as ICOL.
2. 2. 2 Active "L"
(1) CO pin leakage current "L" (ICOLL)
After setting V0 = 0 V, V1 to V5 = 2.6 V, V7 = 28 V, SW7 is turned on. I7 is then defined as ICOLL.
(2) CO pin sink current (ICOL)
After transitioning to the test mode and then setting V0 = 0 V, V1 = 4.8 V, V2 to V5 = 2.05 V and V7 = 0.5 V,
SW7 is turned on. I7 is then defined as ICOL.
3. Transition time to test mode (tTST)
(Test circuit 1)
After setting V0 = 0 V, V1 to V5 = 2.6 V, V0 is increased to 4.0 V and decreased to 0 V again.
When the time interval from when V0 is increased until it is decreased is long, if V1 is then increased to 4.8 V, the CO
pin output inverts within 40 ms. However, when the time interval from when V0 is increased until it is decreased is short,
if V1 is then increased to 4.8 V, it takes more than 40 ms for the CO pin output to invert. tTST is the minimum value of the
time interval from V0 rise until V0 fall under the condition that the CO pin output inverts within 40 ms.
4. Resistance between pins during cell balancing discharge n (RVCn)
(Test circuit 5)
After setting V1 to V5 = VBL − 0.05 V, V1 is increased to VBU + 0.05 V, and then decreased to VBL + 0.05 V after the
cell balancing detection delay time (tBU). When tBU + cell balancing OFF time (tCBOFF) have elapsed after the first rise of
V1, cell balancing discharge starts. VI1 / I1 at that moment is defined as RVC1. RVCn (n = 2 to 5) can be defined in the
same way as when n = 1.
10
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.5_00
S-8265C Series
IOPE
IOPED
S-8265C Series
VDD
CO
V0
V
VC1
S-8265C Series
VSS
V1
VC2
VC5
V2
VC3
VDD
CO
VC1
VSS
A
V5
V1
V4
V2
V5
VC4
VC2
VC5
VC3
VC4
V4
V3
V3
Figure 5 Test Circuit 1
Figure 6 Test Circuit 2
V6
A I6
S-8265C Series
IVC1
A
V1
CO
V0
VC1
VSS
IVC2
A
V2
VDD
VC2
VC5
IVC3
A
IVC5
A
IVC4
VC3
VC4
SW6
S-8265C Series
V5
VDD
CO
VC1
VSS
VC2
VC5
VC3
VC4
V1
V4
V5
V2
A
V3
SW7
V4
V3
Figure 7 Test Circuit 3
V
A I7
V7
Figure 8 Test Circuit 4
S-8265C Series
I1 1kΩ
A
V1
VC1
VSS
VI5 V 1kΩ I5
VC2
A
VC5
I3 1kΩ V VI2
A
V3
CO
I2 1kΩ V VI1
A
V2
VDD
VI4 V 1kΩ I4
VC3
VC4
V5
V4
A
V VI3
Figure 9 Test Circuit 5
11
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8265C Series
Rev.1.5_00
Operation
Remark Refer to " Battery Protection IC Connection Examples".
1. Normal status
When the voltage of all batteries is lower than cell balancing release voltage n (VBLn), "L" (Active "H") or "H" (Active "L")
is output from the CO pin. This is the normal status.
2. Cell balancing status
When the voltage of any of all batteries exceeds the cell balancing detection voltage n (VBUn) in the normal status and
the conditions continue for the cell balancing detection delay time (tBU) or longer, S-8265C Series changes to the cell
balancing status. In the cell balancing status, the cell balancing OFF time (tCBOFF) and cell balancing ON time (tCBON) are
repeated. S-8265C Series monitors VBLn and overcharge detection voltage (VCUn) during tCBOFF. In addition, every cell
balancing discharging FET (SWn) between pins is off during tCBOFF, and cell balancing current does not flow. S-8265C
Series returns to the normal status when the voltage of all batteries falls to VBLn or lower during VBLn monitoring time of
tCBOFF.
S-8265C Series turns on SWn with which a battery exceeding VBLn is connected during tCBON, and the cell balancing
current flows. Note that the voltage of each battery is not monitored during tCBON.
Every SWn is turned off during tCBON when the voltage of all batteries exceeds VBLn in the cell balancing status.
Rn
VCn
Cell balancing current
BATn (≥ VBLn)
SWn
+
−
R(n + 1) VC(n + 1)
Control
logic
Cell balancing detection
comparator
BAT(n + 1)
Figure 10
3. Overcharge cell balancing status
During the cell balancing status and VCUn monitoring time of tCBOFF, when the voltage of any of all batteries exceeds VCUn
and the conditions continue for the overcharge detection delay time (tCU) or longer, the CO pin output inverts. S-8265C
Series then changes to the overcharge cell balancing status.
In the cell balancing status, even when the voltage of any of all batteries exceeds VCUn during tCBON, the cell balancing
status is retained. During VCUn monitoring time of the following tCBOFF, when the voltage of any of all batteries exceeds
VCUn and the conditions continue for the overcharge detection delay time (tCU) or longer, the CO pin output inverts and
S-8265C Series then changes to the overcharge cell balancing status.
In the overcharge cell balancing status, tCBOFF and tCBON are repeated. S-8265C Series monitors VBLn and overcharge
release voltage (VCLn) during tCBOFF. In addition, every SWn is off during tCBOFF, and cell balancing current does not flow.
The CO pin output inverts and S-8265C Series returns to the cell balancing status when the voltage of all batteries falls
to VCLn or lower during VCLn monitoring time of tCBOFF.
S-8265C Series turns on SWn with which a battery exceeding VBLn is connected during tCBON, and the cell balancing
current flows. Note that the voltage of each battery is not monitored during tCBON.
Every SWn is turned off during tCBON when the voltage of all batteries exceeds VBLn in the overcharge cell balancing
status.
Remark n = 1 to 5
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BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.5_00
S-8265C Series
Battery voltage
VCUn
VBUn
VCLn
VBLn
(n
= 1 to 5)
SWn = ON
tBU tCBOFF tCBON
tCU tCBOFF tCBON tCBOFF tCBON Shorter tCBOFF tCBON Shorter
than
than
Shorter
tCBOFF
tCBOFF
than
tCBOFF
CO pin
(Active "H")
CO pin
(Active "L")
Status*1
(1)
(2)
(3)
(2)
(1)
*1. (1) : Normal status
(2) : Cell balancing status
(3) : Overcharge cell balancing status
Figure 11
13
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8265C Series
Rev.1.5_00
4. Overcharge timer reset function
During the overcharge detection voltage monitoring time of tCBOFF and additionally, the time interval of tCU from when the
voltage of any of the batteries exceeds VCUn until the CO pin output inverts, S-8265C Series has the following
operations.
Even if an overcharge release noise, which temporarily forces the battery voltage below VCUn, is input, tCU is
continuously counted as long as the overcharge release noise time is shorter than the overcharge timer reset delay time
(tTR). Under the same conditions, if the overcharge release noise time is tTR or longer, counting of tCU is reset. After that,
tCBOFF resumes.
Battery voltage
tTR or longer
VCUn
VCLn
(n = 1 to 5)
Shorter than tTR
tCBON
Shorter than
tCBOFF
tTR
Shorter than
tCU
Shorter than tTR
Shorter than
tCBOFF
tCU
tCBOFF
tCBON
Timer reset
CO pin
(Active "H")
CO pin
(Active "L")
Status*1
(2)
(1)
*1. (1) : Cell balancing status
(2) : Overcharge cell balancing status
Figure 12
14
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.5_00
S-8265C Series
5. Test mode
Transition to the test mode enables S-8265C Series to check cell balancing detection voltage (VBUn) and overcharge
detection voltage (VCUn) in a short time.
S-8265C Series transitions to the test mode by retaining the VDD pin voltage at 4.0 V above the VC1 pin voltage or
higher for at least 10 ms. The status is retained by test mode retaining latch, and the test mode is retained even if the
VDD pin voltage is returned to the same voltage as the VC1 pin voltage again.
In the test mode, when a battery voltage exceeds VBUn while the VDD pin voltage is held at 4.0 V above the VC1 pin
voltage or higher, the CO pin output inverts and S-8265C Series switches to the detection status. When the VDD pin
voltage is then returned to the same voltage as VC1 pin voltage and the battery voltage falls to VBLn or lower, the CO pin
output inverts again and S-8265C Series switches to the release status.
When the CO pin output switches from the detection status to the release status, the test mode retaining latch is reset
and S-8265C Series is released from the test mode. Make sure that the battery voltage does not fall to VBLn or lower
before returning the VDD pin voltage to the same voltage as the VC1 pin voltage.
After setting the VDD pin voltage to 4.0 V above the VC1 pin voltage or higher and transitioning to the test mode, the
VDD pin voltage is returned to the same voltage as the VC1 pin voltage. When a battery voltage then exceeds VCUn, the
CO pin output inverts and S-8265C Series switches to the detection status. When the battery voltage then falls to VCLn
or lower, the CO pin output inverts again and switches to the release status. When the CO pin output switches from the
detection status to the release status, the test mode retaining latch is reset and S-8265C Series is released from the test
mode.
Note that cell balancing current does not flow in the test mode.
VDD pin voltage
Pin voltage
VC1 pin voltage
VDD pin voltage
VC1 pin voltage
4.0 V or higher
VCUn
VBUn
Battery voltage
VCLn
VBLn
(n = 1 to 5)
tTST = 10 ms max.
tTST
Test mode
CO pin
(Active "H")
CO pin
(Active "L")
32 ms typ.
Caution
32 ms typ.
1. Transition to test mode when the voltage of all batteries is lower than VBUn.
2. The overcharge timer reset delay time (tTR) is not shortened in the test mode.
Figure 13
15
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8265C Series
Rev.1.5_00
Battery Protection IC Connection Examples
1. 5-serial cell (CMOS output product)
EB+
VDD
RVDD
CVDD
VC1
R1
BAT1
C1
OC
VC2
R2
BAT2
S-8265C
Series
C2
VC3
R3
BAT3
VC4
R4
BAT4
FET
C3
CO
DP
C4
VC5
R5
BAT5
C5
VSS
EB−
Figure 14
Table 9 Constants for External Components
No.
1
2
3
Caution
16
Symbol
R1 to R5
C1 to C5, CVDD
RVDD
Min.
100
0.1
100
Typ.
100
0.1
100
Max.
1000
0.1
1000
Unit
Ω
μF
Ω
1. The constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the
connection example. In addition, the connection example and the constants do not guarantee
proper operation. Perform thorough evaluation using the actual application to set the constants.
3. R1 to R5 should be the same constant. C1 to C5 and CVDD should be the same constant.
4. Set values for R1 to R5 so that the loss of the IC does not exceed the power dissipation by the
cell balancing current.
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.5_00
S-8265C Series
2. 4-serial cell (CMOS output product)
EB+
VDD
RVDD
CVDD
VC1
R1
BAT1
C1
OC
VC2
R2
BAT2
S-8265C
Series
C2
VC3
R3
BAT3
C3
VC4
R4
BAT4
FET
CO
DP
C4
VC5
VSS
EB−
Figure 15
Table 10 Constants for External Components
No.
1
2
3
Caution
Symbol
R1 to R4
C1 to C4, CVDD
RVDD
Min.
100
0.1
100
Typ.
100
0.1
100
Max.
1000
0.1
1000
Unit
Ω
μF
Ω
1. The constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the
connection example. In addition, the connection example and the constants do not guarantee
proper operation. Perform thorough evaluation using the actual application to set the constants.
3. R1 to R4 should be the same constant. C1 to C4 and CVDD should be the same constant.
4. Set values for R1 to R4 so that the loss of the IC does not exceed the power dissipation by the
cell balancing current.
17
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8265C Series
Rev.1.5_00
3. 3-serial cell (CMOS output product)
EB+
VDD
RVDD
CVDD
VC1
R1
BAT1
C1
OC
VC2
R2
BAT2
S-8265C
Series
C2
VC3
R3
BAT3
FET
C3
VC4
CO
DP
VC5
VSS
EB−
Figure 16
Table 11 Constants for External Components
No.
1
2
3
Caution
18
Symbol
R1 to R3
C1 to C3, CVDD
RVDD
Min.
100
0.1
100
Typ.
100
0.1
100
Max.
1000
0.1
1000
Unit
Ω
μF
Ω
1. The constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the
connection example. In addition, the connection example and the constants do not guarantee
proper operation. Perform thorough evaluation using the actual application to set the constants.
3. R1 to R3 should be the same constant. C1 to C3 and CVDD should be the same constant.
4. Set values for R1 to R3 so that the loss of the IC does not exceed the power dissipation by the
cell balancing current.
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.5_00
S-8265C Series
Precautions
•
Do not connect batteries charged with VCLn or higher. If the connected batteries include a battery charged with VCLn or
higher, the S-8265C Series may become overcharge status after all pins are connected.
•
In some application circuits, even if an overcharged battery is not included, the order of connecting batteries may be
restricted to prevent transient output of CO detection pulses when the batteries are connected. Perform thorough
evaluation with the actual application circuit.
•
Before the battery connection, short-circuit the battery side pins RVDD and R1, shown in the figure in " Battery
Protection IC Connection Examples".
•
The application conditions for the input voltage, output voltage, and load current should not exceed the power
dissipation.
•
Do not apply to this IC an electrostatic discharge that exceeds the performance ratings of the built-in electrostatic
protection circuit.
•
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement of patents
owned by a third party by products including this IC.
19
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8265C Series
Rev.1.5_00
Characteristics (Typical Data)
1. Current consumption
1. 1 IOPE vs. Ta
S-8265CAA
1.0
VDD = 15.5 V
1. 2 IOPED vs. Ta
S-8265CAA
0.5
0.4
IOPED [μA]
IOPE [μA]
0.8
0.6
0.4
0.2
0.0
−40 −25
0.2
0.0
0
25
Ta [°C]
50
75 85
Ta = +25°C
12
IOPE [μA]
0.3
0.1
1. 3 IOPE vs. VDD
S-8265CAA
15
9
6
3
0
0
20
VDD = 8.3 V
5
10
15
20
VDD [V]
25
30
−40 −25
0
25
Ta [°C]
50
75 85
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.5_00
S-8265C Series
2. Detection voltage
2. 1 VBU vs. Ta
2. 2 VBL vs. Ta
VBU = 4.145 V
4.195
4.170
VBL [V]
VBU [V]
4.170
4.145
4.120
4.095
VBL = 4.145 V
4.195
4.145
4.120
−
4.095
−
−
−
Ta [°C]
Ta [°C]
2. 3 VCU vs. Ta
2. 4 VCL vs. Ta
VCL = 4.275 V
4.325
4.300
4.300
VCL [V]
VCU [V]
VCU = 4.275 V
4.325
4.275
4.250
4.225
4.275
4.250
−
4.225
−
Ta [°C]
−
−
Ta [°C]
21
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8265C Series
Rev.1.5_00
3. Delay time
3. 2 tCU vs. Ta
350
350
300
300
tCU [ms]
tBU [ms]
3. 1 tBU vs. Ta
250
200
150
200
−40 −25
150
0
25
Ta [°C]
50
75 85
9
1.30
8
1.15
7
6
5
−40 −25
−40 −25
0
25
Ta [°C]
50
75 85
0
25
Ta [°C]
50
75 85
3. 4 tCBOFF vs. Ta
tCBOFF [s]
tCBON [s]
3. 3 tCBON vs. Ta
22
250
1.00
0.85
0.70
0
25
Ta [°C]
50
75 85
−40 −25
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.5_00
S-8265C Series
4. Output current
4. 1 ICOL vs. Ta
4. 2 ICOL vs. VDD
5
5
4
ICOL [mA]
ICOL [mA]
4
3
2
1
0
−40 −25
0
25
Ta [°C]
2
50
0
75 85
0
5
10
30
ICOH [μA]
−200
−400
−600
−800
−400
−600
−800
−40 −25
0
25
Ta [°C]
50
75 85
4. 5 ICOLL vs. Ta
−1000
0
5
10
15
20
VDD [V]
25
30
4. 6 ICOLL vs. VDD
Ta = +25°C
VDD = 13.0 V
0.10
0.10
0.08
0.08
ICOLL [μA]
ICOLL [μA]
25
Ta = +25°C
0
−200
0.06
0.04
0.02
0.00
15
20
VDD [V]
4. 4 ICOH vs. VDD
VDD = 13.0 V
0
ICOH [μA]
3
1
4. 3 ICOH vs. Ta
−1000
Ta = +25°C
VDD = 13.0 V
0.06
0.04
0.02
−40 −25
0
25
Ta [°C]
50
75 85
0.00
0
5
10
15
20
VDD [V]
25
30
23
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8265C Series
Rev.1.5_00
5. Internal resistance
5. 2 RVC2 vs. Ta
0.6
0.6
0.5
0.5
RVC2 [kΩ]
RVC1 [kΩ]
5. 1 RVC1 vs. Ta
0.4
0.3
0.2
0.1
0.0
0.4
0.3
0.2
0.1
−
0.0
−
−
−
Ta [°C]
0.6
0.6
0.5
0.5
0.4
0.3
0.2
0.1
0.0
−
0.6
0.5
RVC5 [kΩ]
0.3
0.2
0.0
−
5. 5 RVC5 vs. Ta
0.4
0.3
0.2
0.1
0.0
0.4
0.1
Ta [°C]
−
−
Ta [°C]
24
Ta [°C]
5. 4 RVC4 vs. Ta
RVC4 [kΩ]
RVC3 [kΩ]
5. 3 RVC3 vs. Ta
−
−
Ta [°C]
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.5_00
S-8265C Series
Marking Specifications
1. TMSOP-8
Top view
8
7
6
5
(1):
(2) to (4):
(5):
(6) to (8):
Blank
Product code (Refer to Product name vs. Product code)
Blank
Lot number
(1) (2) (3) (4)
(5) (6) (7) (8)
1
2
3
4
Product name vs. Product code
Product Code
(2)
(3)
(4)
8
J
A
8
J
B
8
J
C
Product Name
S-8265CAA-K8T2U7
S-8265CAB-K8T2U7
S-8265CAC-K8T2U7
2. SNT-8A
Top view
8
7
6
5
(1):
(2) to (4):
(5), (6):
(7) to (11):
(1) (2) (3) (4)
Blank
Product code (Refer to Product name vs. Product code)
Blank
Lot number
(5) (6) (7) (8)
(9) (10) (11)
1
2
3
4
Product name vs. Product code
Product Name
S-8265CAA-I8T1U7
Product Code
(2)
(3)
(4)
8
J
A
25
BATTERY PROTECTION IC WITH CELL BALANCING FUNCTION FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8265C Series
Rev.1.5_00
Power Dissipation
TMSOP-8
SNT-8A
Tj = +125°C max.
B
0.8
A
0.6
0.4
0.2
0.0
0
25
50
75
100
125
150
175
Tj = +125°C max.
1.0
Power dissipation (PD) [W]
Power dissipation (PD) [W]
1.0
0.8
B
0.6
A
0.4
0.2
0.0
0
25
Ambient temperature (Ta) [°C]
Board
A
B
C
D
E
26
Power Dissipation (PD)
0.63 W
0.75 W
−
−
−
50
75
100
125
150
Ambient temperature (Ta) [°C]
Board
A
B
C
D
E
Power Dissipation (PD)
0.47 W
0.58 W
−
−
−
175
TMSOP-8 Test Board
(1) Board A
IC Mount Area
Item
Size [mm]
Material
Number of copper foil layer
Copper foil layer [mm]
1
2
3
4
Thermal via
Specification
114.3 x 76.2 x t1.6
FR-4
2
Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.070
-
(2) Board B
Item
Size [mm]
Material
Number of copper foil layer
Copper foil layer [mm]
Thermal via
1
2
3
4
Specification
114.3 x 76.2 x t1.6
FR-4
4
Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070
-
No. TMSOP8-A-Board-SD-1.0
ABLIC Inc.
SNT-8A Test Board
IC Mount Area
(1) Board A
Item
Size [mm]
Material
Number of copper foil layer
Copper foil layer [mm]
1
2
3
4
Thermal via
Specification
114.3 x 76.2 x t1.6
FR-4
2
Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.070
-
(2) Board B
Item
Size [mm]
Material
Number of copper foil layer
Copper foil layer [mm]
Thermal via
1
2
3
4
Specification
114.3 x 76.2 x t1.6
FR-4
4
Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070
-
No. SNT8A-A-Board-SD-1.0
ABLIC Inc.
2.90±0.2
8
5
1
4
0.13±0.1
0.2±0.1
0.65±0.1
No. FM008-A-P-SD-1.2
TITLE
TMSOP8-A-PKG Dimensions
No.
FM008-A-P-SD-1.2
ANGLE
UNIT
mm
ABLIC Inc.
2.00±0.05
4.00±0.1
4.00±0.1
1.5
1.00±0.1
+0.1
-0
1.05±0.05
0.30±0.05
3.25±0.05
4
1
5
8
Feed direction
No. FM008-A-C-SD-2.0
TITLE
TMSOP8-A-Carrier Tape
FM008-A-C-SD-2.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
13.0
+1.0
- 0.0
15.4±1.0
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. FM008-A-R-SD-2.0
TITLE
TMSOP8-A-Reel
No.
FM008-A-R-SD-2.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
1.97±0.03
8
7
6
5
3
4
+0.05
1
0.5
2
0.08 -0.02
0.48±0.02
0.2±0.05
No. PH008-A-P-SD-2.1
TITLE
SNT-8A-A-PKG Dimensions
No.
PH008-A-P-SD-2.1
ANGLE
UNIT
mm
ABLIC Inc.
ø1.5
2.25±0.05
+0.1
-0
4.0±0.1
2.0±0.05
ø0.5±0.1
0.25±0.05
0.65±0.05
4.0±0.1
4321
5 6 78
Feed direction
No. PH008-A-C-SD-2.0
TITLE
SNT-8A-A-Carrier Tape
No.
PH008-A-C-SD-2.0
ANGLE
UNIT
mm
ABLIC Inc.
9.0
+1.0
- 0.0
11.4±1.0
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. PH008-A-R-SD-2.0
TITLE
SNT-8A-A-Reel
No.
PH008-A-R-SD-2.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
5,000
0.52
2.01
2
0.52
0.2 0.3
1.
2.
1
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
1.
2.
3.
4.
0.03 mm
SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm).
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1.
2.
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
TITLE
No. PH008-A-L-SD-4.1
SNT-8A-A
-Land Recommendation
No.
PH008-A-L-SD-4.1
ANGLE
UNIT
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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