GPX2-EVA-KIT

This product, formerly sold by ams AG, and before that optionally by either Applied Sensors GmbH, acam-messelectronic GmbH or Cambridge CMOS Sensors, is now owned and sold by ScioSense The technical content of this document under ams / Applied Sensors / acammesselectronic / Cambridge CMOS Sensors is still valid. Contact information Headquarters: ScioSense B.V. High Tech Campus 10 5656 AE Eindhoven The Netherlands info@sciosense.com www.sciosense.com TDC-GPX2 4-Channel Time-to-Digital Converter General Description The GPX2 is a high performance time-to-digital converter (TDC) frontend device. Highest measurement performance and highest data throughput is achieved with LVDS stop inputs and LVDS serial outputs for each channel. Current saving operation is also possible with CMOS inputs and SPI readout. High configuration flexibility and unlimited measurement range cover many applications. They range from portable handheld laser range equipment to ambitious time-of-flight measurements of highest performance, as e.g. done in medical imaging applications. GPX2 operates without any locked loop technologies. GPX2 calculates all stop measurements inside, proportional to the applied reference clock. Combinations of best single shot accuracy of 10ps with lowest pulse-to-pulse spacing SV@ Figure 19: STOP2 – STOP1, HIGHRES 4x, Histogram 100000 Values +LVWRJUDP6723 6723 +LJK5HVROXWLRQ[W6723W6723 QVVWGGHY SV      FWHM§SV   Page 18 Document Feedback                  >SV@ ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Converter Characteristics Figure 20: STOP2 – REFCLK, HIGHRES 0, Histogram 100000 Values +LVWRJUDP6723 +LJK5HVROXWLRQRIIW6723 SVVWGGHYSV                        >SV@ Figure 21: STOP2 – STOP1, HIGHRES 0, Histogram 100000 Values +LVWRJUDP6723 6723 +LJK5HVROXWLRQRIIW6723W6723 QVVWGGHYSV      4XDQWL]DWLRQHIIHFWV JHWREYLRXV  §SV     ams Datasheet [v1-03] 2017-Dec-18                  >SV@ Page 19 Document Feedback TDC-GPX2 − Converter Characteristics Integral Non-Linearity Difference betweeen two measured time / ps Figure 22: Integral Non-Linearity Integral Non Linearity < 4ps 50ns time steps counted from a 20MHz quartz. Reference Clock 800ns (16 Periods of 20MHz) 50003 50002 50001 50000 49999 49998 49997 Page 20 Document Feedback 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 Time generated by Quartz / ns ams Datasheet [v1-03] 2017-Dec-18 T D C - G PX 2 − Register Description Register Description Configuration Register Overview The configuration registers are organized in 17 addresses of one byte. All configuration registers are accessible via the SPI interface. They can be read and written individually or with an incremental access. For monitoring the chip it is possible to observe at the PARITY pin whether the sum of all set bits is even or odd. Figure 23: Configuration Register Overview Addr 0 PIN_ENA_RSTIDX PIN_ENA_DISABLE PIN_ENA_LVDS_OUT PIN_ENA_REFCLK PIN_ENA_STOP4 PIN_ENA_STOP3 PIN_ENA_STOP2 PIN_ENA_STOP1 1 HIGH_RESOLUTION HIT_ENA_STOP4 HIT_ENA_STOP3 HIT_ENA_STOP2 HIT_ENA_STOP1 2 BLOCKWISE_ FIFO_READ 3 REFCLK_DIVISIONS (Lower byte) 4 REFCLK_DIVISIONS (Middle byte) 5 Fixed value*: (0000b) 6 Fixed value*: (110b) 7 REFCLK_BY _ XOSC 8 Fixed value*: (10100001b) 9 Fixed value*: (00010011b) 10 Fixed value*: (00000000b) 11 Fixed value*: (00001010b) ams Datasheet [v1-03] 2017-Dec-18 CHANNEL_COMBINE COMMON_FIFO_ READ LVS_DOUBLE_DATA_ RATE STOP_DATA_BITWIDTH REFCLK_DIVISIONS (Upper bits) LVDS_ TEST_ PATTERN Fixed value*: (1b) REF_INDEX_BITWIDTH LVDS_DATA_VALID_ ADJUST Fixed value*: (0000b) Fixed Value*: (0011b) Page 21 Document Feedback T D C - G P X 2 − Register Description Addr 12 Fixed value*: (11001100b) 13 Fixed value*: (11001100b) 14 Fixed value*: (11110001b) 15 Fixed value*: (01111101b) 16 Fixed value*: (00000b) CMOS_ INPUT Fixed value*: (00b) The fixed values are assigned by ams: Unless otherwise suggested, they should be set as shown in this table. Page 22 Document Feedback ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Register Description Detailed Configuration Register Description All registers are read/write with 0 as default value, besides registers 13, 14 with 5 as default value. Figure 24: Configuration Register 0 Addr: 0 Bit Pin Enable Register Bit Name Bit Description The PIN_ENA registers activate the LVDS input or output drivers of the related pins. Main purpose of PIN_ENA is cutting of current consumption of differential LVDS buffers to nearly zero. But also with CMOS input levels the pins have to be activated accordingly. Unused inputs has to be tied to VDD33. Activation on stop event input pins STOP1 to STOP4 0: Stop input pins not active 1: Stop input pins active 0 to 3 PIN_ENA1 to PIN_ENA4 4 PIN_ENA_ REFCLK 0: REFCLK input pins not active 1: REFCLK input pins active 5 PIN_ENA_ LVDS_OUT 0: All LDVS output pins disabled 1: Activation of LCLK and LCLKOUT pins. Activation of SDO1…4 and FRAME1…4, depends further on CHANNEL_COMBINE and PIN_ENA 6 PIN_ENA_ DISABLE 0: Stop disable pin is not active. The stop measurement on all channels is always active according to configuration. 1: Stop disable pin is active. The stop measurements are disabled if the DISABLE pin on the PCB is set to HIGH 7 PIN_ENA_ RSTIDX 0: Deactivation of reference clock index counter reset pin 1: Activation of reference clock index counter reset pin ams Datasheet [v1-03] 2017-Dec-18 Page 23 Document Feedback TDC-GPX2 − Register Description Figure 25: Configuration Register 1 Addr: 1 Bit Bit Name 0 to 3 HIT_ENA1 to HIT_ENA4 4, 5 6, 7 CHANNEL_ COMBINE HIGH_ RESOLUTION Page 24 Document Feedback Content Bit Description 0: Stop events are internally rejected. The pin enabling of STOP1…4 is not affected. 1: Stop events are internally accepted and processed. Normal working condition The four stop channels may be combined for improved pulse pair resolution or higher conversion rate. 00b: Normal operation with four independent stop channels 01b: “Pulse distance” Stop events at STOP1 are measured alternatingly by stop channels 1 & 3 Stop events at STOP2 are measured alternatingly by stop channels 2 & 4 10b: “Pulse width” The rising edges at STOP1 are measured by stop channel 1 The falling edges at STOP1 are measured by stop channel 3 The rising edges at STOP2 are measured by stop channel 2 The falling edges at STOP2 are measured by stop channel 4 A stop event is internally delayed, measured several times and summed up in order to one result to increase the time resolution. = 0 (off ): Off, standard resolution with minimal pulse-to-pulse spacing. = 1 (2x): A stop event is measured twice = 2 (4x): A stop event is measured four times ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Register Description Figure 26: Configuration Register 2 Addr: 2 Bit 0 to 2 3, 4 5 6 7 Data Output Bit Name Bit Description REF_INDEX_ BITWIDTH Bit width of reference clock index in LVDS output (not applicable to SPI data readout) 000b: 0Bit, no data out 001b: 2Bits 010b: 4Bits 011b: 8Bits 100b: 16Bits 101b: 24Bits 110b: 6Bits 111b: 12Bits STOP_DATA_ BITWIDTH Bit width of the stop result in LVDS output. Bit width should be sufficient to represent the REFCLK_DIVISIONS configuration value (not applicable to SPI data readout) 00b: 14Bits → max of REFCLK_DIVISIONS = 214-1 01b: 16Bits → max of REFCLK_DIVISIONS = 216-1 10b: 18Bits → max of REFCLK_DIVISIONS = 218-1 11b: 20Bits → max of REFCLK_DIVISIONS = 220-1 LVDS_ DOUBLE _ DATA_RATE 0: Single Data Read (SDR): The LVDS data clocked out on rising edges of LCLK-OUT 1: Double Data Read (DDR): The LVDS data are clocked on both edges of LCLK-OUT COMMON_ FIFO_READ 0: LVDS: Operation with four independent stop channels SPI: INTERUPT pin is set to zero, as soon as one FIFOs does have a value. OFF, operation with four independent stop channels 1: LVDS: All active frame pins are set simultaneous as soon as all related FIFOs have values. SPI: INTERUPT pin is set to zero, as soon as all active FIFOs have value. In combination with BLOCKWISE_READ this option guaranties successive measurements in parallel on all stop channels BLOCKWISE_ FIFO_READ 0: OFF, Operation with standard FIFO function 1: Data output (LVDS or SPI) is not started before a channel FIFO is full. Once FIFO is full, measurement is not restarted before FIFO is completely read-out. This option guaranties successive measurements at high stop event rate or slow read-out speeds (e.g. SPI) ams Datasheet [v1-03] 2017-Dec-18 Page 25 Document Feedback TDC-GPX2 − Register Description Figure 27: Configuration Register 3, 4, 5 Addr: 3, 4, 5 Bit 0 to 7 0 to 7 0 to 3 Reference Clock Divider Bit Name Bit Description REFCLK_ DIVISIONS Defines a LSB at the output interface as fraction of the reference clock period. The most convenient way is applying a LSB of 1ps by configuring REFCLK_DIVISIONS to the picosecond value of the reference clock period address 3 lower 8bits, address 4 middle 8bits, address 5 upper 4bits Figure 28: Configuration Register 6 Addr: 6 Bit Content Bit Name Bit Description 4 LVDS_TEST_ PATTERN 0: Normal operation of LVDS outputs 1: LVDS interface continuously outputs the following test patterns. All stop events are ignored. Reference index = 111100001100110010101010bin (=15781034dec) Stop result = 000010101010110011110000bin (=699632dec) Depending on the configuration of the output format width (REF_INDEX_BITWIDTH, STOP_DATA_BITWIDTH) only the corresponding lower bits are transmitted 5 to 7 Fixed value 110b: Defined by ams Figure 29: Configuration Register 7 Addr: 7 Pin Enable Register Bit Bit Name 0 to 3 Fixed value 4, 5 LVDS_DATA_ VALID_ ADJUST 6 Fixed value 1b: Defined by ams 7 REFCLK_BY_ XOSC 0: Reference pulses have to be applied at REFCLK pins. The circuit for driving the external quartz is not in use. 1: The reference clock is generated by a quartz which is connected to the GPX2; REFCLK pins are not in use and should be disabled with PIN_ENA_REFCLK. Page 26 Document Feedback Bit Description 0011b: Defined by ams Adjustment of the data valid time at the LVDS output interface. 000b: - 160ps 001b: 0ps 010b: +160ps 011b: +320ps ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Register Description For registers 8 to 15 use the default fixed values as shown in the register overview. Figure 30: Configuration Register 16 Addr: 16 Bit Bit Name 0 to 1 Fixed value 2 CMOS_INPUT 3 to 7 Fixed value ams Datasheet [v1-03] 2017-Dec-18 Pin Enable Register Bit Description 00b: Defined by ams Input voltage levels of STOP1 to STOP4, REFCLK, RSTIDX and DISABLE are selected as CMOS or LVDS 0: Differential LVDS input level. 1: Single ended CMOS input level Also with CMOS input level the pins have to be activated with according PIN_ENA-configuration 00000b: Defined by ams Page 27 Document Feedback TDC-GPX2 − Register Description Read Register Overview All read registers are accessible via SPI Interface. Incremental read may start at any register address. Figure 31: Read Register Overview Addr Name 0 n.c. 1 n.c. 2 n.c. 3 n.c. Status 4 n.c. 5 n.c. 6 n.c. 7 n.c. 8 REFERENCE INDEX CH1 BYTE #3 9 REFERENCE INDEX CH1 BYTE #2 10 REFERENCE INDEX CH1 BYTE #1 Channel1 11 STOP RESULT CH1 BYTE #3 12 STOP RESULT CH1 BYTE #2 13 STOP RESULT CH1 BYTE #1 14 REFERENCE INDEX CH2 BYTE #3 15 REFERENCE INDEX CH2 BYTE #2 16 REFERENCE INDEX CH2 BYTE #1 Channel2 17 STOP RESULT CH2 BYTE #3 18 STOP RESULT CH2 BYTE #2 19 STOP RESULT CH2 BYTE #1 20 REFERENCE INDEX CH3 BYTE #3 21 REFERENCE INDEX CH3 BYTE #2 22 REFERENCE INDEX CH3 BYTE#1 Channel3 23 STOP RESULT CH3 BYTE #3 24 STOP RESULT CH3 BYTE #2 25 STOP RESULT CH3 BYTE #1 Page 28 Document Feedback ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Register Description Addr Name 26 REFERENCE INDEX CH4 BYTE #3 27 REFERENCE INDEX CH4 BYTE #2 28 REFERENCE INDEX CH4 BYTE #1 Channel4 29 STOP RESULT CH4 BYTE #3 30 STOP RESULT CH4 BYTE #2 31 STOP RESULT CH4 BYTE #1 ams Datasheet [v1-03] 2017-Dec-18 Page 29 Document Feedback TDC-GPX2 − Detailed Description Detailed Description Time Measurements and Results Measurements of TDC-GPX2 The reference clock is the framework for all time measurements. The clock pulses are measured continuously by the TDC as time reference point for stop pulses and as internal reference period. The measurement of the stop events always refers to the preceding reference clock. Additionally, the reference clock is counted continuously and the actual count is assigned as reference index to a stop pulse. • t REF is the internal TDC measurement of the reference clock period • t STOP is the internal TDC measurement of a stop to the preceding reference clock • REFID is the index of reference period where the measured stop occurred Figure 32: TDC-GPX2 Time Measurement REFID N N+1 REFCLK STOP tSTOP REFID = N tREF Output Results Each stop generates a dataset which consists of two values TSTOP and REFID: REFID is the reference index of the preceding reference clock pulse to TSTOP. The reference index is necessary to indicate the relationship of stop pulses which belong to different reference clock periods. The maximum length of the reference index is 24 bits. TSTOP is the ratio of the internal measured times of t STOP over t REF scaled by the configured REFCLK_DIVISONS. The readout result TSTOP is always less than configured REFCLK_DIVISONS. The resulting LSB at the output interface has to be chosen much lower than the single shot resolution of GPX2. For details see chapter “Coding of Results”. Suitable values are e.g. 1ps, 5ps or 10ps. Page 30 Document Feedback ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Detailed Description Figure 33: tSTOP Calculation tSTOP = TSTOP × tSTOP × REFCLK_DIVISIONS tREF Ratio of internal time measurements Internal calculated result for read-out LSB tREFC LK-PER IOD REFCLK_DIVISIONS LSB resulting by the period of the applied reference clock and by the configured REFCLK_DIVISIONS Calculation of Time Differences The results of the GPX2 are the time intervals from stop event pulses to the preceding reference clock pulses. In many applications the time difference between stop event pulses is desired. This happens e.g. in case of a quartz as a reference clock. Depending on the application and the measurement setup, several approaches are possible to calculate the time between two stops in the connected microprocessor or FPGA. Figure 34: Calculating Time Differences tREF REFID N N+1 REFCLK Δt13 Δt12 Δt23 STOP tSTOP1 tSTOP3 REFID1=N REFID3=N+1 tSTOP2 REFID2=N ams Datasheet [v1-03] 2017-Dec-18 Page 31 Document Feedback TDC-GPX2 − Detailed Description General Approach On the output interface, either SPI or LVDS, both data REFID and TSTOP are available. With these data it is possible to calculate time differences between stops. The maximum time difference depends on the bit width of the reference index (see also chapter “Maximum Time Differences” between stops depending on the reference index bit width) Δt 13 = (TSTOP3 - TSTOP1) + (REFID3 - REFID1) * REFCLK_DIVISIONS In two special cases it is not necessary to readout the REFID: Stops in the Same Reference Clock Period In applications where stops occur always in the same reference period (e.g. STOP1 & STOP2), it is not necessary to read out the reference index. It is sufficient just read out the stop results and to calculate the difference: Δt 12 = TSTOP2 - TSTOP1; REFID2 = REFID1 Time Difference Smaller Than Reference Clock In applications where the measured time difference Δt is always smaller than the reference clock period T REF but not necessarily in the same reference clock period (e.g. STOP2 & STOP3), it is often sufficient to read out just the stop results without the reference index by distinguishing positive and negative time difference: If TSTOP3 - TSTOP2 > 0 • Δt 23 = (TSTOP3 – TSTOP2) If TSTOP3 - TSTOP2 < 0 and ΔT < REFCLK_DIVISIONS • Δt 23 = (TSTOP3 – TSTOP2) + REFCLK_DIVISIONS Page 32 Document Feedback ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Detailed Description Resolution RMS-Resolution Versus Effective Resolution The RMS resolution of a TDC is the root-mean-square-value of a set of single shot time measurements. TDC do not have an obvious full scale definition, as the time they are measuring is unlimited. Therefore, the definition of an effective resolution in number of bits likewise in ADC is not feasible. High Resolution For achieving best single-shot RMS resolution, GPX2 offers a complete integrated solution. During the initial sampling the stop event is internally delayed and sampled again, after the first sample was stored in the FIFO. All samples of one stop event are averaged inside of the GPX2 and occur as one result with lower conversion noise at the output interface. With HIGH_ RESOLUTION it is possible to configure internal 2 or 4 samples of one event. Due of the internal delay and the multiple samples the conversion latency t conv and the pulse-to-pulse spacing tPPS increase as well as the maximum FIFO_DEPTH decreases. In order to compensate these drawbacks, it is possible to use HIGH_RESOLUTION with both CHANNEL_COMBINATION modes and to achieve the excellent pulse-to-pulse spacing of channel combination mode, doubled FIFO depth per stop input and higher resolution. ams Datasheet [v1-03] 2017-Dec-18 Page 33 Document Feedback TDC-GPX2 − Detailed Description Combining Two Stop Channels Channel Combination for Low Pulse-to-Pulse Spacing With CHANNEL_COMBINE set to “PULSE_SPACING”, two stop channels 1 & 3 (and 2 & 4) are connected to one input pin STOP1 (and STOP2). The stop events at the input pin are distributed alternatingly between the combined channels. Readout is indicated via FRAME or INTERRUPT pins when both channels have results in their FIFO. The advantage of combining channels lies in improved pulse-to-pulse spacing • Excellent pulse-to-pulse spacing • Doubled FIFO depth per stop input pin • Higher burst storage capability • Doubled LVDS readout rate per stop input pin • HIGH_RESOLUTION is applicable Figure 35: Channel Combination Low Pulse-to-Pulse Spacing HIT_ENA_STOP 1 CHANNEL_COMBINE = 1 STOP1 STOP1P PIN_ENA_STOP1 CMOS_INPUT 1 + STOP 1N 1 2 HIT_ENA_STOP 3 0 STOP3 - HIT_ENA_STOP 2 CHANNEL_COMBINE = 1 STOP2 STOP2P PIN_ENA_STOP2 + STOP 2N CMOS_INPUT 1 PIN_ENA _DISABLE + DISABLEN Page 34 Document Feedback 2 HIT_ENA_STOP 4 0 STOP4 - DISABLEP 1 CMOS_INPUT 1 0 - ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Detailed Description The outstanding low pulse-to-pulse spacing t PPS,CCH is achievable only for a single pulse pair. After a pulse pair, the regular pulse-to-pulse spacing t PPS must be awaited, before capturing the next pulse becomes possible. Measurements with HIGH_RESOLUTION will increase the regular pulse-to-pulse spacing but the low pulse-to-pulse spacing t PPS,CCH is not affected. Figure 36: Channel Combination Low Pulse-to-Pulse Spacing STOP1 #1 #2 #3 tPPS ,CCH #4 tPPS ,CCH tPPS INTERRUPT FRAME1 #1 #3 FRAME3 #2 #4 Note(s): • With LVDS outputs the FRAME pins of combined channels are active together • SPI readout of combined channel pairs is permitted only pairwise like ch1-ch3-ch1-ch3-… or ch2-ch4-ch2-ch4-… . Also incremental readout like ch1-ch2-ch3-ch4… is possible. But it is not permitted to read one channel twice like ch1-ch1-ch3-ch3-.. or ch2-ch2-ch4-ch4…. ams Datasheet [v1-03] 2017-Dec-18 Page 35 Document Feedback TDC-GPX2 − Detailed Description Channel Combination for Pulse Width Measurement With CHANNEL_COMBINE set to “PULSE_WIDTH” two internal stop channels 1&3 (and 2&4) are connected to one input pin STOP1 (and STOP2). The rising edges are measured by channel 1 (2), falling edges are measured by channel 3 (4). Readout starts on both channels simultaneous when a rising and falling edge was measured. • HIGH_RESOLUTION or COMMON_FIFO_READ is fully applicable Figure 37: Channel Combination for Pulse Width Measurement HIT_ENA_STOP 1 CHANNEL _COMBINE = 2 STOP1 STOP1P PIN_ENA_STOP1 CMOS_INPUT 1 + STOP 1N 1 2 HIT_ENA_STOP 3 0 STOP3 - HIT_ENA_STOP 2 CHANNEL _COMBINE = 2 STOP2 STOP2P PIN_ENA_STOP2 + STOP 2N CMOS_INPUT 1 PIN_ENA _DISABLE + DISABLEN 2 HIT_ENA_STOP 4 0 STOP4 - DISABLEP 1 CMOS_INPUT 1 0 - Note(s): 1. For internal processing reasons, after the conversion latency t PPS must be waited before capturing the next pulse. Measurements with HIGH_RESOLUTION will increase the conversion latency but minimum pulse width t PWH,STOP is not affected. Page 36 Document Feedback ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Detailed Description Figure 38: Channel Combination Pulse Width Measurement STOP 1 #1 #2 #3 tPWH ,ST OP #4 tPWH ,ST OP tPP S INTERRUPT FRAME 1 # 1 # 3 FRAME 3 # 2 # 4 Note(s): • With LVDS output the FRAME pins of combined channels are active together • SPI readout of combined channel pairs is permitted only pairwise like ch1-ch3-ch1-ch3-… or ch2-ch4-ch2-ch4-…. Also incremental readout like ch1-ch2-ch3-ch4… is possible. But it is not permitted to read one channel twice like ch1-ch1-ch3-ch3-.. or ch2-ch2-ch4-ch4…. ams Datasheet [v1-03] 2017-Dec-18 Page 37 Document Feedback TDC-GPX2 − Detailed Description Input Pins for Time Measurement The following diagram show the relevant input pins for the reference and the stops. Figure 39: Input Circuitry REFOSCO STOP4P REFOSCI REFCLKP PIN_ENA_REF RES + REFCLKN REFRESP + 1 1 0 START PIN_ENA_REF RES - STOP4N STOP3P PIN_ENA_ STOP3 CMOS_ INPUT + 1 0 START_ RESET STOP3N STOP2P STOP1P PIN_ENA_ STOP2 DISABLEP PIN_ENA_ STOP1 CMOS_IN PUT HIT_ENA_STOP3 1 STOP3 0 CMOS_IN PUT HIT_ENA_STOP2 1 STOP2 0 CMOS_IN PUT 1 HIT_ENA_STOP1 STOP1 0 - PIN_ENA_DIS ABLE + DISABLEN STOP4 0 - + STOP1N HIT_ENA_STOP4 1 - + STOP2N CMOS_IN PUT - 0 - + REFRESN CMOS_ INPUT REFCLK_BY_ XOSC PIN_ENA_ STOP4 CMOS_IN PUT 1 0 - REFCLKP/N: Reference Clock Input The reference clock serves as universal time base. Due to internal averaging, the phase jitter of the reference clock is non-critical. The accuracy and drift of the reference clock also does not affect the proper working of GPX2 itself. But it will directly affect the quality of the time measurement results. REFOSCI/O: Quartz Driver as Reference Clock Note(s): The quartz is not mandatory for operation of GPX2. The quartz is just an optional source for the reference clock. It can be used instead of a clock signal at the reference clock pin. Therefore REFCLK pins should be disabled. With a quartz as reference clock usually the time difference between stops channels is relevant (see chapter “Calculation of Time Differences”). The use of COMMON_FIFO_READ and BLOCKWISE_FIFO_READ can help to measure and read out associated stop results together. Page 38 Document Feedback ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Detailed Description RSTIDXP/N: Reference Index Counter Reset With pin RSTIDX the internal counter for the reference index is set back to zero. This option may simply the overview on the reference index in the output data stream. RSTIDX is applied synchronously to the reference clock for a single period. Therefore one reference clock cycle passes, before stop events are assigned with zero as reference index. The pin has to be activated with PIN_ENA_RSTIDX. Figure 40: Reference Index Counter Reset Reference Index REFCLK N-2 N-2 N-2 N-1 N-1 0 0 1 1 2 2 3 RSTIDX STOP1…STOP4P/N: Stop Channels Inputs for the stop signals. The positive edges of the stop signals are measured versus the preceding reference clock edge. The chip has four independent stop channels. With CHANNEL_ COMBINE variations of this normal operation mode can be achieved. DISABLE/N: Stop Disable With setting stop disable pin to HIGH, the measurement on all four stops is disabled. The reference clock is not affected and internal reference measurements are continued. The DISABLE should meet the timing requirement with regards to a stop event. The pin has to be activated by configuring PIN_ENA_ DISABLE to 1. Input Levels, CMOS or LVDS All input pins, STOP1 to STOP4, REFCLK, RSTIDX and DISABLE, can be switched in common to CMOS input levels with CMOS_ INPUT configuration. Tie the unused negative inputs to TVDD33. ams Datasheet [v1-03] 2017-Dec-18 Page 39 Document Feedback TDC-GPX2 − Detailed Description Figure 41: CMOS-LVDS General Circuit STOP1P PIN_ENA _STOP1 + STOP1N - CMOS_IN PUT 1 LVDS (CMOS_INPUT=0): CMOS (CMOS_INPUT=1): STOP1P STOP1 STOP1P PIN_ENA_STOP1 + 0 STOP1N - TVDD33 STOP1 STOP1N Termination of Differential LVDS Input Pin Integrated termination is not provided. It is necessary to place termination resistors on the PCB near to the input pins. The default termination for LVDS signals is to have single 100Ω resistors between the differential lines. Connection of Unused LVDS Inputs Any kind of unused LVDS inputs (e.g. STOP1 to STOP4, REFCLK, RSTIDX, DISABLE, LCLKIN) have to be pulled up to VDD33 and disabled by setting PIN_ENA to zero. Unused channels should also be switched off with HIT_ENA_STOP1…4. Figure 42: Unused LVDS VDD33 PIN_ENA_STOPx=0 + - Software Enable (HIT_ENA_STOP1…4) Setting the configuration bits HIT_ENA_STOP1 to HIT_ENA_ STOP4 applies a software enable for stop channels 1 to 4. Pin Enable (PIN_ENA_xxx) The pin enable registers PIN_ENA_STOP1 to PIN_ENA_STOP4, PIN_ENA_REFCLK, PIN_ENA_RSTIDX and PIN_ENA_DISABLE activate the LVDS input or output drivers of the related pins. Main purpose of PIN_ENA is cutting of current consumption of unused differential LVDS buffer to nearly zero. But also with CMOS_INPUTs the pin need to be activated. In case of the LVDS output interface, PIN_ENA_STOP1 to PIN_ENA_STOP4 enable also the according LVDS output drivers. Page 40 Document Feedback ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Detailed Description LVDS Output Interface Digital Output Interface Each stop channel has its own serial interface with a data output SDO pin and a FRAME pin to indicate the MSB. Data output is supported on falling edges (SDR, single data read) or rising and falling edges (DDR, double data read). The operating clock is looped from LCLKIN through the chip to LCLKOUT pin. The data at SDO and FRAME pins have stable timing relation a t DV,LVDS to LCLKOUT. The FRAME indicate the first 8bits of an output sequence. On the SDO pin the reference index is output first, and the stop result follows that. The bit width of both results is configurable by STOP_DATA_BITWIDTH and REF_INDEX_ BITWIDTH. With careful configuration data overhead can be avoided in favor of higher conversion rates. Output Setup and Configuration: LVDS output interface is activated configuring LVDS_ENA_ LVDSOUT =1. The clock at the input LCLKIN is looped through the chip to pins LCLKOUT. The phase of SDO and FRAME pins are in stable relation to LCLKOUT. The SDO and FRAME pins needed for output are activated according to the configuration of PAD_ENA_STOP1 to PAD_ENA_STOP4 and CHANNEL_ COMBINE. Figure 43: LVDS Outputs PIN_ENA_STOP4/ PIN_ENA_STOP2 (CH-COMB) FRAME4P SDO4P + - SDO4 PIN_ENA_STOP 2 FRAME4 + FRAME4N SDO4N FRAME2P SDO2P SDO2 + - FRAME2 FRAME2N SDO2N PIN_ENA_STOP3/ PIN_ENA_STOP1 (CH-COMB) FRAME3 SDO3N PIN_ENA_STOP1 FRAME3P SDO3P + - SDO3 + - FRAME1P SDO1P SDO1 FRAME3N + - + - FRAME1 + FRAME1N SDO1N PIN_ENA_LVDSOUT LCLKI NP + LCLKI NN - ams Datasheet [v1-03] 2017-Dec-18 LCLKOUTP + LCLKOUTN Page 41 Document Feedback TDC-GPX2 − Detailed Description LVDS Output Buffers The LVDS output buffers SDO1 to SDO4, FRAME1 to FRAME4, and LCLKOUT are designed for 200mV voltage swing with external 100Ω termination. Unused LVDS output buffers can be left open. Differential LCLKIN Input Termination: No integrated termination resistors are provided. A termination resistor of 100Ω should be placed near the input pin. Connection of unused LCLKIN input: LCLKIN input has to be pulled up to VDD33 and disabled by configuring PIN_ENA_LVDS to zero. Figure 44: LCLIN Input DVDD33 PIN_ENA_LVDSOUT=0 + LCLKI N - LVDS Single Data Read Output Interface (SDR) In single data read mode (LVDS_DOUBLE_DATA_RATE = 0) the data and frame bits are clocked on the falling edge of LVDS output clock LCLKOUT. The data bits are stable during the following rising edge of LCLKOUT. Figure 45: LVDS Outputs Single Data Read (SDR) LCLK#N LCLK#P FRAME#N 2 nd frame 1 st frame FRAME#P 8 LCLK periods SDO#N i23 SDO #P i22 i21 i20 i19 i18 MSB Index (0 – 24 Bits) i17 i16 i0 s19 LSB MSB s18 s1 s0 i23 i22 LSB Stop (14 – 20 Bits) Note(s): 1. Bit width of the reference index and the stop result is configured by STOP_DATA_BITWIDTH and REF_INDEX_BITWIDTH Page 42 Document Feedback ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Detailed Description LVDS Double Data Read Output Interface (DDR) With double data read mode the readout rate is doubled or alternatively the LVDS clock frequency can be halved with constant readout rate. The data and frame bits are clocked on rising and falling edges of LCLKOUT. Both bits, data and frame, are delayed by t DV,LVDS to LCLKOUT in order to grant sufficient hold time for the receiving device. With configuration parameter LVDS_DATA_VALID_ADJUST the delay can be adjusted for all LVDS outputs in common. Figure 46: LVDS Outputs Double Data Read (DDR) LCLK#N LCLK#P FRAME#N st nd 1 frame 2 frame FRAME#P 4 LCLK periods SDO #N i23 i22 i21 i20 i19 i18 i17 i16 i15 SDO#P i1 i0 s1 s1 s1 9 8 7 s3 s2 s1 s0 i23 i22 i21 i20 i19 i18 i17 i16 i15 i14 i13 i12 i11 i10 LSB MSB MSB Index (0 – 24 Bits) LSB Stop (14 – 20 Bits) Note(s): 1. Bit width of the reference index and the stop result is configured by STOP_DATA_BITWIDTH and REF_INDEX_BITWIDTH LVDS Output Test Pattern Setting LVDS_TEST_PATTERN = 1 the interface continuously outputs the following fixed test patterns. All stop events are ignored. Reference index = 111100001100110010101010bin (=15781034dec) Stop result = 000010101010110011110000bin (=699632dec) Depending on the configuration of the output format width (REF_INDEX_BITWIDTH, STOP_DATA_BITWIDTH) only the corresponding lower bits of the reference index and the stop result are transmitted. ams Datasheet [v1-03] 2017-Dec-18 Page 43 Document Feedback TDC-GPX2 − Detailed Description SPI Communication Interface General The SPI interface is implemented to • Reset the chip to power on state • Write configuration registers • Verify configuration or status registers • Initialize and restart measurements • Byte-wise readout of results from the read registers (see Figure 31) via SPI instead via serial LVDS outputs The serial interface is compatible with the 4-wire SPI standard in Motorola specification: • Clock Phase Bit = 1 • Clock Polarity Bit = 0 Detailed Pin Description Pin SSN The ‘Slave Select Not’ line is the HIGH-active reset for the serial interface. When set to LOW, the interface is ready for serial shift of data into or out of the device. Each access POR, INIT, READ or WRITE has to start with a positive pulse on SSN. Pin SCK The ‘Serial Clock’ line is the driving clock which starts at LOW level and expects HIGH active pulses. Pin MOSI The ‘Master Out Slave In’ line is the serial data input of the device. Data takeover is done with the falling edge of SCK. The MSB is sent first. Pin MISO At ‘Master In Slave Out’ line, the serial data are clocked out of the chip with the rising edge of SCK. When SSN is set to HIGH, then the data output pin MISO is in high-Z state. The MSB is sent first. Pin INTERRUPT A low level at the interrupt pin indicates to the receiving device that data are available. Pin PARITY Monitoring the chip is possible by observing the PARITY pin. It indicates whether the sum of all configuration bits is even (Parity = 0) or odd (Parity = 1). Page 44 Document Feedback ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Detailed Description Communication Commands (Opcodes) Figure 47: Opcodes Overview Opcode HEX / BIN Description spiopc_power 0x30 = 0b00110000 Power on reset and stop measurement spiopc_init 0x18 = 0b00011000 Initializes Chip and starts measurement spiopc_write_config 0x80 = 0b100XXXXX Write to configuration register X=0..17 spiopc_read_results 0x60 = 0b011XXXXX Read opcode for result and status register X=8..31 spiopc_read_config 0x40 = 0b010XXXXX Readout of configuration register X=0..17 Detailed Command Description Power-ON Reset After stabilization of all VDD33 and VDD18 the device expects the opcode spiopc_power = 0x30 to be sent via the SPI interface for power on reset. After the last bit of the opcode the reset remains active during t HD,SSN before the device is ready for the next read or write access. After the reset, the measurement is stopped and the configuration registers are set to internal defaults of the chip. Figure 48: Power-On Reset Opcode SSN SCK MOSI 0 0 1 1 0 0 0 0 Opcode 0x30 ams Datasheet [v1-03] 2017-Dec-18 Page 45 Document Feedback TDC-GPX2 − Detailed Description Initialization Reset After the configuration, the initialization opcode spiopc_init=0x18 resets again the chip to power on state, but preserves the configuration and starts the measurement. The initialization reset can be send while the reference clock or stops are applied. It takes 16 pulses of the reference clock before the stop channels are opened internally. After the initialization reset the delay t POR has to be waited before next communication. The initialization reset can be applied also during measurements to restart the chip, but preserves measured data in FIFOs. Figure 49: Initialization Reset Opcode SSN SCK MOSI 0 0 0 1 1 0 0 0 Opcode 0x18 Write / Incremental Write Write access is permitted to the configuration registers exclusively. The access starts by sending the opcode spiopc_ write_config = 0x80 after a positive SSN pulse. The register address is just added to spiopc_write_config. The data are sent after the opcode. Incremental write access to the successive registers is possible by sending the next data bytes. A complete configuration starts normally at register 0, followed by all register data bytes. Figure 50: SPI Incremental Write SSN SCK MOSI 1 0 0 Opcode Page 46 Document Feedback A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Register addr ess Data byte of addressed register Data byte of next register ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Detailed Description Read / Incremental Read The read access to registers starts by sending the opcodes spiopc_read_results =0x60 or spiopc_read_config = 0x40 after a positive SSN pulse. The register address is just added to the opcode. After the opcode the data are clocked out at the MISO line. Incremental read access to following registers is possible by continuously reading bytes. Each register is suitable as start address for incremental access. Figure 51: SPI Incremental Read SSN SCK MOSI 0 1 0 Opcode MISO A4 A3 A2 A1 A0 Register addr ess D7 D6 D5 D4 D3 D2 D1 D0 Result byte from addressed register D7 D6 D5 D4 D3 D2 D1 D0 Result byte from next register Using SPI Interface for Read-Out of Stop Results Reading results byte-wise from TDC-GPX2 e.g. by an external microcontroller is fully supported. While using the SPI interface, data read by LVDS has to be suppressed by setting PIN_ENA_ LVDS_OUT to zero or at least by not applying a clock at LCLKIN. When reading an empty channel the results of REFINDEX and STOPRESULT are marked with 0xFFFFFF. Typically, the measurement rate of TDC-GPX2 is much higher than the readout rate possible with SPI. In this case using COMMON_ FIFO_READ and BLOCKWISE_FIFO_READ is helpful to get sequential results which were measured in parallel in TDC-GPX2. REF_INDEX_BITWIDTH and STOP_DATA_BITWIDTH are not relevant for reading via SPI. ams Datasheet [v1-03] 2017-Dec-18 Page 47 Document Feedback TDC-GPX2 − Detailed Description Coding of Results Configuration of LSB by REFCLK_DIVISIONS The reference clock period is divided into subdivisions by REFCLK_DIVISIONS for the definition of the LSB of the stop results at the output interface. One subdivision corresponds to the LSB and the stop results are scaled into multiples of this LSB. In order to avoid quantization artefacts of the output interface, the resulting LSB has to be much smaller than the single shot resolution of GPX2. The most convenient way is choosing an LSB of 1ps by configuring REFCLK_DIVISIONS to the picosecond value of the reference clock period. Other LSB settings are possible as well, like LSB of 5ps or 10ps. Figure 52: LSB Configuration Reference Clock Period Reference Clock Frequency REFCLK_ DIVISIONS LSB = 1ps REFCLK_ DIVISIONS LSB = 5ps REFCLK_ DIVISIONS LSB = 10ps 500ns 2MHz 500000 100000 50000 250ns 4MHz 250000 50000 25000 200ns 5MHz 200000 40000 20000 100ns 10MHz 100000 20000 10000 50ns 20MHz 50000 10000 5000 Note(s): 1. For LVDS output, REFCLK_DIVISIONS must not exceed the result bit width defined by STOP_DATA_BITWIDTH Page 48 Document Feedback ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Detailed Description Examples for Codes of Time Measurements Results Figure 53: LSB Configuration Readout of Stop Result Resulting Stop Time with An Assumed LSB of Note Hexadecimal Decimal LSB = 1ps LSB = 5ps LSB = 10ps 0x0 0 0ps 0ps 0ps 0x1 1 1ps 5ps 10ps 0x2 2 2ps 10ps 20ps 0xA 10 10ps 50ps 100ps 0x64 100 100ps 500ps 1000ps 0x3E8 1000 1000ps 5000ps 10000ps 0x2710 10000 10000ps 50000ps 100000ps 0x61A7 24999 24999ps 124995ps 249990ps 0xC34F 49999 49999ps 249995ps (2) See note (1) 0x3D08F 249999 249999ps (2) See note (1) See note (1) 0x1869F 99999 99999ps 499995ps See note (1) 0x30D3F 199999 199999ps See note (1) See note (1) 0xF423F 999999 See note (1) See note (1) See note (1) 0x3FFF 16383 16383ps 81915ps 163830ps 0xFFFF 65335 65335ps 326675ps 653350ps 0x3FFFF 262143 262143ps See note (1) See note (1) 0xFFFFF 1048575 1048575ps See note (1) See note (1) 20Bit 0x0FFFFF 1048575 1048575ps See note (1) See note (1) SPI: Max readout with 20Bit (3) refclk-period tREFCLK =250ns refclk-period tREFCLK =500ns 14Bit LVDS: Max readout with stop_data_ bitwidth= 16Bit 18Bit Note(s): 1. Time difference exceed GPX2 specification for reference clock period 2. REFCLK_DIVISIONS decreased by one is the highest possible readout value 3. With SPI read-out the four upper bits are unused ams Datasheet [v1-03] 2017-Dec-18 Page 49 Document Feedback TDC-GPX2 − Detailed Description Maximum Time Differences The following table shows the maximum possible time differences between stops, depending on the reference index bit width. Figure 54: LSB Configuration REF_ INDEX_ BITWIDTH Mode Maximum Readout Hexadecimal 0Bit LVDS/SPI No read-out 2Bit LVDS 4Bit Maximum Readout Decimal Max Time Difference with Reference Clock fREFCLK = 2MHz fREFCLK = 5MHz fREFCLK = 10MHz No read-out 0.5μs 200ns 100ns 0x3 3 2μs 800ns 400ns LVDS 0xF 15 8μs 3.2μs 1.6μs 8Bit LVDS/SPI 0xFF 255 128μs 51.2μs 25.6μs 16Bit LVDS/SPI 0xFFFF 65335 32ms 13.0ms 6.5ms 24Bit LVDS/SPI 0xFFFFFF 16777215 8s 3.2s 1.6s 6Bit LVDS 0x3F 63 31μs 12.6μs 6.3μs 12Bit LVDS 0xFFF 4095 2ms 800μs 400μs Page 50 Document Feedback ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Detailed Description Conversion Latency and Conversion Rate The conversion latency t conv is the time need when an event at a stop input pin occurs until it is processed and ready for output through the interface. With LVDS instead of SPI output an additional synchronization latency to the LCLK is applied. Figure 55: Conversion Latency STOP 1 2 3 INTERRUPT Interrupt for STOP#3 LCLKOUT SDO STOP#1 FRAME STOP#2 FRAME2 FRAME1 tCONV tSYNC tCONV tSYNC remaining time The conversion and synchronization latency is only applied to single events. During an output sequence of several events the conversion latency is processed in parallel during the remaining time. Converter Latency The conversion latency t CONV is the time needed when an event at a stop input pin occurs until it is processed. Once a stop event is recognized, it has to be converted into the results of TSTOP and REFID. The basic conversion latency tCONV is the same for SPI or LVDS readout. After the conversion latency has passed, the INTERRUPT pin is set to zero (if not already zero from a previous stop) and the stop result is ready for readout via the SPI interface. The conversion latency depends also on the HIGH_RESOLUTION configuration. ams Datasheet [v1-03] 2017-Dec-18 Page 51 Document Feedback TDC-GPX2 − Detailed Description LVDS Synchronization Latency For both LVDS output modes, DDR+SDR, an additional synchronization latency t SYNC has to be processed before the output sequence starts. With LVDS reading an additional latency t SYNC for synchronization to the LCLK is applied. tSYNC is counted in LVDS clock cycles and the output is indicated by setting the frame output pin. Conversion Rate Conversion rate is the rate where stop events can be measured. It is determined or limited by the peak input conversion rate or the read-out rate. The conversion rate of the stop events at the input can be higher or also lower than the read-out rate output interface. In any case, the FIFO will adapt a variable peak stop event rate and to the read-out rate. Peak Conversion Rate The peak input conversion rate is limited by the ability of GPX2 to sample, convert and store stop events in the FIFOs. The maximum peak conversion rate is limited minimal pulse-to-pulse-spacing t PPS of the chosen measuring mode. The number of conversions at peak conversion rate is given by the FIFO depth and to a certain extent by the read out rate of the interface. Read-Out Rate The maximum read-out rate is reached when the output interface (either SPI or LVDS) is continuously in use for outputting the measurement results. The configured code length (LVDS: STOP_DATA_BITWIDTH and REF_INDEX_ BITWIDTH, SPI: readout bytes) and the frequency define the readout capabilities. Average Conversion Rate The average conversion rate is determined either by the • Peak Input Conversion Rate: If the read-out rate is higher than peak input conversion rate no time event is getting lost because of a full FIFO. This is typically the case when reading out with LVDS. • Read-Out Rate: If read-out rate is always slower than the input conversion rate then time measurements necessarily are getting lost because the FIFO may be full. This is typically the case when reading out via SPI. In this case the configuration of BLOCKWISE_FIFO_READ and COMMON_FIFO_READ is an option even to get measured a sequence of successive stops Page 52 Document Feedback ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Detailed Description Examples for Read-Out Rate with LVDS The conversion rate of measured stop events can be calculated by dividing the bus frequency by the number of bits, which are readout reference index and stop result. The number of bits is configured by STOP_DATA_BITWIDTH and REF_INDEX_ BITWIDTH. Figure 56: Example Data Average Conversion Rate STOP_DATA_ BITWIDTH REF_INDEX_ BITWIDTH Sum of Bits LCLK SDR Throughput Rate DDR Throughput Rate 00 (14Bit) 000 (0Bit) 14 300MHz 21MSPS 42MSPS 00 (14Bit) 010 (4Bit) 18 300MHz 16MSPS 32MSPS 01 (16Bit) 000 (0Bit) 16 300MHz 18MSPS 37MSPS 01 (16Bit) 011 (8Bit) 24 300MHz 12MSPS 25MSPS 10 (18Bit) 000 (0Bit) 18 200MHz 11MSPS 22MSPS 10 (18Bit) 100 (16Bit) 32 200MHz 6MSPS 12MSPS 11 (20Bit) 000 (0Bit) 20 100MHz 5MSPS 10MSPS 11 (20Bit) 101 (24Bit) 44 100MHz 2MSPS 4MSPS Note(s): 1. Maximal throughput rate is only reached when the stop event rate at input is high enough 2. With CHANNEL_COMBINE = 1 (”Pulse Distance”) the throughput rate per stop input pin is doubled, as the stop events of one input pin are alternatively measured and readout by two channels. ams Datasheet [v1-03] 2017-Dec-18 Page 53 Document Feedback TDC-GPX2 − Detailed Description FIFOs for Adapting Peak and Average Conversion Rate Each channel of GPX2 has a First-In-First-Out data buffer (FIFO). Generally, GPX2 is capable of measuring the incoming stops faster than the length of an output sequence. The FIFO is capable of storing up to data of 16 stop events until the data are read out. Up to a certain degree, the FIFO prevents rejection of stop events for a short time when the input stop event rate is higher than the read-out rate. But when the input data rate is constantly higher than the read-out rate, then the FIFO gets full and stop events are rejected. After a full FIFO was read out and empty space is available for stop measurement further two stops are needed to restart the FIFO (t FIFO_RESTART ). The maximum FIFO depth is 16, 8 or 4 stages, depending on the HIGH_RESOLUTION configuration (off, 2x, 4x). The following figures illustrate the typical dependencies between stop event rate and the read out rate. They are applicable for both SPI and LVDS readout. The INTERRUPT pin indicates that the result is available for read-out through the SPI interface. For SPI a continuous readout is assumed as long as the interrupt is on low level. For LVDS output the FRAME indicates the beginning of data output at SDO line. The interrupt goes back to HIGH when all FIFOs are empty even if output is LVDS. In the figures FIFO_DEPTH = 4 is assumed. The FIFO LEVEL indicates the stop event buffered in the FIFO. A stop event will increase FIFO LEVEL by one, reading out will decrease the FIFO LEVEL. Figure 57: Input Stop Event Rate is Lower than the Readout Rate STOP #1 FIFO LEVEL 0 #2 1 0 #3 0 1 0 1 INTERRUPT FRAME #1 SDO #2 Stop#1 #3 Stop#2 Stop #3 • Enough time for complete readout of first stop before the next stop event arises • Interrupt goes back to high because the FIFO is empty after read-out • In this example, no stop events are rejected. All stops are measured and read out Page 54 Document Feedback ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Detailed Description Figure 58: Average Stop Event Rate is Lower, but Peak Stop Event Rate is Higher than the Readout Rate STOP #1 #2 FIFO LEVEL 0 1 2 #4 #3 1 2 #5 #6 1 2 1 #7 2 3 2 #8 3 2 3 2 1 0 INTERRUPT FRAME #1 SDO #2 Stop #1 #3 Stop#2 #4 Stop #3 #5 Stop#4 #6 Stop #5 #7 Stop#6 #8 Stop #7 Stop#8 • Stop events during read-out are stored in FIFO • Stop events buffer up to FIFO LEVEL 3 • In this example, no stop events are rejected. All stops are measured and read out. • Interrupt goes back to high when all data are readout and the FIFO is empty. • Maximal FIFO_DEPTH and HIGH_RESOLUTION limits the peak event storage Figure 59: Stop Event Rate is Higher than the Readout Rate STOP #1 #2 #3 #4 #5 FIFO LEVEL 0 1 2 1 2 3 #10 4 3 #14 4 3 #18 4 3 #23 4 3 #27 4 3 #31 4 3 4 INTERRUPT FRAME #1 SDO #2 Stop #1 #3 Stop#2 #4 Stop#3 #5 Stop #4 #10 Stop #5 #14 Stop#10 Stop #14 • During read-out stop events (dots) are ignored when FIFO full at FIFO LEVEL 4. • After reading a result from a full FIFO the next two stops events (dashed) are still ignored but used to restart the FIFO • Interrupt is always zero because the FIFO never gets empty. ams Datasheet [v1-03] 2017-Dec-18 Page 55 Document Feedback TDC-GPX2 − Detailed Description Figure 60: Stops on All Four Channels STOP1 1 2 3 STOP2 1 2 3 STOP3 1 2 3 STOP4 1 2 3 INTERRUPT FRAME1 1 FRAME2 2 1 FRAME3 3 2 1 3 2 FRAME4 3 1 2 3 • All four channels are completely independent from each other (COMMON_FIFO_READ=0) • In this example no stop events are rejected, because FIFOs never get full • Interrupt remains zero as long as at least one FIFO has a valid data, interrupt gets high when all FIFO are empty Figure 61: BLOCKWISE_FIFO_READ STOP #1 #2 #3 #4 FIFO LEVEL 0 1 2 3 #20 #21 #22 #23 4 3 2 1 0 1 2 3 4 3 2 INTERRUPT FRAME #1 SDO Page 56 Document Feedback #2 Stop#1 #3 Stop #2 #4 Stop #3 #22 Stop #4 #26 Stop #20 ... ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Detailed Description • A block of successive stop events are measured in a block before readout • Readout of FIFO starts not before the FIFO is full. • During read-out stop events (dots) are ignored when FIFO full at FIFO level 4…1. • After reading all result from the FIFO the next two stops events (dashed) are still ignored but used to restart the FIFO • Measurement starts not before the FIFO is empty. • COMMON_FIFO_READ is applicable. Figure 62: COMMON_FIFO_READ STOP1 2 1 3 STOP2 1 2 3 STOP3 1 2 3 STOP4 1 2 3 INTERRUPT FRAME1 1 2 3 FRAME2 1 2 3 FRAME3 1 2 3 FRAME4 1 2 3 • All active FRAME pins are set simultaneously, as soon as all active FIFOs have value (COMMON_FIFO_READ = 1) • As long as one FIFO has no valid data, no readout is done • Interrupt doesn’t fall to low before all active FIFOs have valid data • In this example no stop events are rejected, because FIFOs never get full. • BLOCKWISE_FIFO_READ is fully applicable • SPI readout only successively of all active FIFOs (1, 2, 3, 4 …). It is not permitted to read one channel twice (e.g 1 & 1, 2 & 2 …) ams Datasheet [v1-03] 2017-Dec-18 Page 57 Document Feedback TDC-GPX2 − Application Information Application Information Configuration Examples Typical Configuration for LVDS org ROM_ADD_CFG; config_default.cfg saved on 19.09.2016 11:58 equal 0x401F0131; Register 3, 2, 1, 0 equal 0x53C0030D; Register 7, 6, 5, 4 equal 0x0A0013A1; Register 11, 10, 9, 8 equal 0x7DF1CCCC; Register 15, 14, 13, 12 equal 0x00000004; Register 19, 18, 17, 16 equal 0x00000000; Register 23, 22, 21, 20 Example C++ Code The following C++ code is provided to give an overview about how to organize the initial steps of a microprocessor, to be able to conduct a typical time measurement task with GPX2. #include // This is an imaginary header file // defined to support this example code // --------------------------------------------------------------------------------------------// *** uProcessor.h *** // --------------------------------------------------------------------------------------------// Almost every microprocessor has a specific C++ libraries (header files) that introduce // specific commands for data readout. // Therefore, this imaginary header data is given to support this example code. // The intention of each virtual function on this header is clearly explained as follows. // In real projects, instead of these functions, // the user should use the similar functions of the micro-processor which is used with GPX2. // // Virtual functions: // send_byte_to_SPI( Var1 ); : send Var1 (8 Bits) through the SPI // // read_byte_from_SPI( Var1 ); : read 1 Byte data from SPI and write it to Var1 // // Virtual pin variables: // GPIO_SSN : // Variable (1 Bit) to control the output pin which is supposed to be connected the SSN pin of the GPX2 // // GPIO_INTERRUPT : // Variable (1 Bit) to monitor the input pin which is supposed to be connected INTERRUPT pin of the GPX2 // --------------------------------------------------------------------------------------------// *** Configuration Registers *** // --------------------------------------------------------------------------------------------const char config_register[16] = { 0x31, 0x01, 0x1F, 0x40, 0x0D, 0x03, 0xC0, 0x53, 0xA1, 0x13, 0x00, 0x0A, 0xCC, 0xCC, 0x31, 0x8E, 0x04 }; // A typical config settings = { config00, config01, … , config16 } Page 58 Document Feedback ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Application Information // --------------------------------------------------------------------------------------------// *** SPI Opcodes *** // --------------------------------------------------------------------------------------------const char spiopc_power = 0x30; // opcode for "Power on Reset" const char spiopc_init = 0x18; // opcode for "Initialize Chip and Start Measurement" const char spiopc_write_config = 0x80; // opcode for "Write Configuration" const char spiopc_read_config = 0x40; // opcode for "Read Configuration" const char spiopc_read_results = 0x60; // opcode for "Read Measurement Results" // --------------------------------------------------------------------------------------------// *** SPI Addresses *** // --------------------------------------------------------------------------------------------const char reference_index_ch1_byte3 = 8; // const char reference_index_ch1_byte2 = 9; const char reference_index_ch1_byte1 = 10; const char stopresult_ch1_byte3 = 11; const char stopresult_ch1_byte2 = 12; const char stopresult_ch1_byte1 = 13; // . . . . const char stopresult_ch4_byte3 = 29; const char stopresult_ch4_byte2 = 30; const char stopresult_ch4_byte1 = 31; // --------------------------------------------------------------------------------------------// *** Other Variables *** // -------------------------------------------------------------------------------------------int Buffer = 0; // buffer variable used to copy the SPI data char i = 0; // counter for for-loops int reference_index[4] = 0; // reference index data array {Ch1, Ch2, Ch3, Ch4} int stopresult[4] = 0; // stop result data array {Ch1, Ch2, Ch3, Ch4} bool config_error = false; // flag that indicates if the config registers // are not written correctly // --------------------------------------------------------------------------------------------// *** Main body of the software *** // --------------------------------------------------------------------------------------------int main(void) { // ----------------------------------------------------------------------------------------// *** Power on reset *** // ----------------------------------------------------------------------------------------GPIO_SSN = 1; // Reset the SPI interface and select the slave device GPIO_SSN = 0; send_byte_to_SPI( spiopc_power ); ams Datasheet [v1-03] 2017-Dec-18 // Opcode for "Power On Reset" is sent over SPI Page 59 Document Feedback TDC-GPX2 − Application Information // ----------------------------------------------------------------------------------------// *** Writing the configuration registers *** // ----------------------------------------------------------------------------------------GPIO_SSN = 1; // Reset the SPI interface and select the slave device GPIO_SSN = 0; config_error = false; send_byte_to_SPI( spiopc_write_config + 00 ); // Opcode for "Write Configuration" // and config address (00) are sent over SPI for ( i = 0; i < 17; i++) // Send all 17 config registers via SPI send_byte_to_SPI( config_register[i] ); // ----------------------------------------------------------------------------------------// *** Verification of config registers *** // ----------------------------------------------------------------------------------------GPIO_SSN = 1; // Reset the SPI interface and select the slave device GPIO_SSN = 0; send_byte_to_SPI( spiopc_read_config + 00 ); // Opcode for "Read Configuration" // and config address (00) are sent over SPI for ( i = 0; i < 17; i++) { read_byte_from_SPI( Buffer ); // read one byte from SPI to Buffer variable if ( config_register[i] != Buffer ) config_error = true; // if there was a failure in writing the config // registers, then the config_error flag is raised. } // // ----------------------------------------------------------------------------------------// *** Initialize and start the measurement *** // ----------------------------------------------------------------------------------------if (config_error == false ) { GPIO_SSN = 1; // Reset the SPI interface and select the slave device GPIO_SSN = 0; send_byte_to_SPI( spiopc_init ); // Opcode for "Initialize" is sent over SPI // This is required to start measuring process // ************************************************************************************* // End of the configuration settings. After now the time measurement will start. // This code is designed to use SPI to read the measurement data from GPX2. // Using LVDS as a output interface requires additional hardware and code. // ************************************************************************************* Page 60 Document Feedback ams Datasheet [v1-03] 2017-Dec-18 TDC-GPX2 − Application Information // ----------------------------------------------------------------------------------------// *** Readout of measurement data via SPI *** // ----------------------------------------------------------------------------------------while( GPIO_INTERRUPT != 0 ); // wait till the Interrupt pin is low GPIO_SSN = 1; // Reset the SPI interface and select the slave device GPIO_SSN = 0; send_byte_to_SPI( spiopc_read_results + reference_index_ch1_byte3 ); // Opcode for "Read Result" and data address are sent for ( i = 0; i < 4; i++) { read_byte_from_SPI( Buffer ); // read one byte from SPI to Buffer reference_index[i] = reference_index[i] // Data is shifted 16 Bits to the left + ( Buffer