Internal
TABLE OF SPECIFICATION
CONTENTS
PRODUCT
Prepared (also subject responsible if other)
No.
jidkzhou Kevin
JID/Kevin
ZhouZhou
Approved
BMR481
series
JID/Kevin
jidkzhou
Kevin
Zhou
ZhouDirect
Checked
1 (2)
(5)
1/1301-BMR481
00152-BMR481
Technical Specification
Date
Rev
Conversion
2021-5-10
3/16/2021
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Reference
28701-BMR481 revF
D
PA1
May 2022
© Flex
Key Features
•
•
•
•
•
•
•
•
Direct Conversion 48V to 1V single stage
High efficiency – 92% @ 1V multi-phase
Multi-phase design – up to 6 phases @ 70A each
Small footprint
o Main – 27.7mm x 12mm x 14mm
(1.1” x 0.47” x 0.55”)
o Satellite – 27.7mm x 12mm x 12.6mm
(1.1” x 0.47” x 0.5”)
Fast transient response
Meets safety requirements per IEC/EN/UL 62368-1
PMBus 1.3 Compliant
MTBF
o Main – 8.7 million hours
o Satellite – 9.7 million hours
General Characteristics
•
•
•
•
Configurable with PMBus
Full configuration support with Flex Power Designer
Full featured input/output telemetry
Configurable protections
o OV/UV
o Overcurrent
o Over temperature
• Differential remote sense
• ISO 9001/14001 certified supplier
• Highly automated manufacturing ensures quality
Safety Approvals
Design for Environment
Meets requirements in hightemperature lead-free soldering
processes.
Contents
Ordering Information
General Information
Safety Specification
Application Overview
Connections
Absolute Maximum Ratings
............................................................. 2
............................................................. 2
............................................................. 3
............................................................. 5
............................................................. 7
........................................................... 13
Electrical Specification
Main
Main/Satellite
BMR481 0021..................................... 13
BMR481 002x ..................................... 16
Parametric Information
EMC Considerations
PMBus Interface
Operating Information
Thermal Information
PCB Layout
Mechanical Information
Soldering Information
Delivery Information
Product Qualification Specification
PMBus Command Appendix
........................................................... 19
........................................................... 24
........................................................... 26
........................................................... 30
........................................................... 36
........................................................... 37
........................................................... 38
........................................................... 40
........................................................... 41
........................................................... 43
........................................................... 44
PRODUCT SPECIFICATION
Prepared (also subject responsible if other)
No.
jidkzhou Kevin Zhou
Approved
Checked
BMR481
series
jidkzhou
Kevin
ZhouDirect
2 (5)
1/1301-BMR481
Technical Specification
Date
Rev
Conversion
2021-5-10
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Reference
28701-BMR481 revF
D
2
May 2022
© Flex
Ordering Information
Product program
BMR4810021/002C
BMR4810022C
Function
Main
Satellite
Product number and Packaging
BMR481 n1n2n3n4/n5n6n7n8
/
Options
n1
n2 n 3 n4
Mounting
x
/
xx
Output Config
n 5n 6n 7
/
Package information
/
Compatibility with RoHS requirements
xxx
0
0
Main – Open Frame, LGA
Satellite – Open Frame, Box Pin
n2n3
00
Vout = 1.0V, Iout = 70 A
Vadjust range = 0.5 V to 1.35 V
1
2
n5n6n7
n8
x
Description
n1
n4
n8
/
Config File (Main only)
Options
Satellite
MTBF (mean value) for BMR481 series = 10.7 Mh
MTBF at 90% confidence level = 9.7 Mh
/
x
Functional
Main
MTBF (mean value) for BMR481 series = 9.6 Mh
MTBF at 90% confidence level = 8.7 Mh
Output
1 V / 70 A
1 V / 70 A
Main
Satellite
002
Single Main, AVSBus Vout Control
C
Antistatic tape and reel packaging
The products are compatible with the relevant clauses and
requirements of the RoHS directive 2011/65/EU and
2015/863 and have a maximum concentration value of 0.1%
by weight in homogeneous materials for lead, mercury,
hexavalent chromium, PBB, PBDE, DEHP, BBP, DBP, DIBP
and of 0.01% by weight in homogeneous materials for
cadmium.
Exemptions in the RoHS directive utilized in Flex Power
products are found in the Statement of Compliance
document.
Flex Power fulfills and will continuously fulfill all its obligations
under regulation (EC) No 1907/2006 concerning the
registration, evaluation, authorization and restriction of
chemicals (REACH) as they enter into force and is through
product materials declarations preparing for the obligations to
communicate information on substances in the products.
Quality Statement
Example: An open frame Main with LGA and Vout setpoint at 1.0V configured
for single module operation would be BMR481 0021/002C
1) The “Main” configuration sets all PMBus registers for proper module
operation. Application specific registers can be modified to customize the
configuration to meet a wide variety of performance objectives. The
configuration can be changed using the PMBus communication and stored in
non-volatile memory. Customized configurations can be created as orderable
parts and would be defined with an individual value for n5n6n7. The “002” part
is configured for single phase operation with PMBus output voltage control.
Please refer to additional details in this document for further definition of the
“002” configuration.
General Information
Reliability
The failure rate () and mean time between failures (MTBF=
1/) is calculated at max output power and an operating
ambient temperature (TA) of +40°C. Flex Power uses
Telcordia SR-332 Issue 4 Method 1 to calculate the mean
steady-state failure rate and standard deviation ().
Telcordia SR-332 Issue 4 also provides techniques to
estimate the upper confidence levels of failure rates based on
the mean and standard deviation.
Mean steady-state
failure rate, (
nFailures/h)
Main - 104
Satellite - 93
Std. deviation,
( nFailures/h)
Main – 7.8
Satellite – 7.4
The products are designed and manufactured in an industrial
environment where quality systems and methods like ISO
9000, Six Sigma, and SPC are intensively in use to boost the
continuous improvements strategy. Infant mortality or early
failures in the products are screened out and they are
subjected to an ATE-based final test. Conservative design
rules, design reviews and product qualifications, plus the high
competence of an engaged work force, contribute to the high
quality of the products.
PRODUCT SPECIFICATION
Prepared (also subject responsible if other)
No.
jidkzhou Kevin Zhou
Approved
BMR481
series
jidkzhou
Kevin
ZhouDirect
Checked
1/1301-BMR481
Technical Specification
Date
Rev
Conversion
2021-5-10
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Warranty
Warranty period and conditions are defined in Flex Power
General Terms and Conditions of Sale.
Limitation of Liability
Flex Power does not make any other warranties, expressed
or implied including any warranty of merchantability or fitness
for a particular purpose (including, but not limited to, use in
life support applications, where malfunctions of product can
cause injury to a person’s health or life).
© Flex Power 2021
The information and specifications in this technical
specification is believed to be correct at the time of
publication. However, no liability is accepted for
inaccuracies, printing errors or for any consequences
thereof. Flex Power reserves the right to change the
contents of this technical specification at any time without
prior notice.
3 (5)
Reference
28701-BMR481 revF
D
© Flex
3
May 2022
PRODUCT SPECIFICATION
Prepared (also subject responsible if other)
No.
jidkzhou Kevin Zhou
Approved
BMR481
series
jidkzhou
Kevin
ZhouDirect
Checked
1/1301-BMR481
Technical Specification
Date
Rev
Conversion
2021-5-10
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Safety Specification
General information
Flex Power DC/DC converters and DC/DC regulators are
designed in accordance with the safety standards
IEC 62368-1, EN 62368-1 and UL 62368-1 Audio/video,
information and communication technology equipment Part 1: Safety requirements
IEC/EN/UL 62368-1 contains requirements to prevent injury
or damage due to the following hazards:
•
•
•
•
•
•
Electrical shock
Electrically-caused fire
Injury caused by hazardous substances
Mechanically-caused injury
Skin burn
Radiation-caused injury
On-board DC/DC converters, Power interface modules and
DC/DC regulators are defined as component power
supplies. As components they cannot fully comply with the
provisions of any safety requirements without “conditions of
acceptability”. Clearance between conductors and between
conductive parts of the component power supply and
conductors on the board in the final product must meet the
applicable safety requirements. Certain conditions of
acceptability apply for component power supplies with
limited stand-off (see Mechanical Information for further
information). It is the responsibility of the installer to ensure
that the final product housing these components complies
with the requirements of all applicable safety standards and
regulations for the final product.
Component power supplies for general use shall comply
with the requirements in IEC/EN/UL 62368-1. Product
related standards, e.g. IEEE 802.3af Power over Ethernet,
and ETS-300132-2 Power interface at the input to telecom
equipment, operated by direct current (dc) are based on
IEC/EN/UL 60950-1 with regards to safety.
Flex Power DC/DC converters, Power interface modules
and DC/DC regulators are UL 62368-1 recognized and
certified in accordance with EN 62368-1. The flammability
rating for all construction parts of the products meet
requirements for V-0 class material according to
IEC 60695-11-10, Fire hazard testing, test flames – 50 W
horizontal and vertical flame test methods.
Isolated DC/DC converters & Power interface modules
The product may provide basic or functional insulation
between input and output according to IEC/EN/UL 62368-1
(see Safety Certificate), different conditions shall be met if
the output of a basic or a functional insulated product shall
be considered as ES1 energy source.
For basic insulated products (see Safety Certificate) the
output is considered as ES1 energy source if one of the
4 (5)
Reference
28701-BMR481 revF
D
4
May 2022
© Flex
following conditions is met:
• The input source provides supplementary or double or
reinforced insulation from the AC mains according to
IEC/EN/UL 62368-1.
• The input source provides functional or basic insulation
from the AC mains and the product’s output is reliably
connected to protective earth according to
IEC/EN/UL 62368-1.
For functional insulated products (see Safety Certificate)
the output is considered as ES1 energy source if one of the
following conditions is met:
• The input source provides double or reinforced
insulation from the AC mains according to
IEC/EN/UL 62368-1.
• The input source provides basic or supplementary
insulation from the AC mains and the product’s output is
reliably connected to protective earth according to
IEC/EN/UL 62368-1.
• The input source is reliably connected to protective
earth and provides basic or supplementary insulation
according to IEC/EN/UL 62368-1 and the maximum
input source voltage is 60 Vdc.
Galvanic isolation between input and output is verified in an
electric strength test and the isolation voltage (Viso) meets
the voltage strength requirement for basic insulation
according to IEC/EN/UL 62368-1.
It is recommended to use a slow blow fuse at the input of
each DC/DC converter. If an input filter is used in the circuit
the fuse should be placed in front of the input filter. In the
rare event of a component problem that imposes a short
circuit on the input source, this fuse will provide the
following functions:
• Isolate the fault from the input power source so as not
to affect the operation of other parts of the system.
• Protect the distribution wiring from excessive current
and power loss thus preventing hazardous overheating.
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
No.
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
1 (21)
Specification
Rev
28701-BMR481 revF
E
© Flex
Application Overview
Power supply system including one Main product and 0-5 Satellite products (in total 1-6 phases). Non-isolated solution.
Complete isolated solution with included supplies for driver and controller voltages.
5
May 2022
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
No.
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Fundamental Circuit Diagram - Main
Fundamental Circuit Diagram – Satellite
Rev
2 (21)
Specification
28701-BMR481 revF
E
© Flex
6
May 2022
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
No.
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
3 (21)
Specification
Rev
28701-BMR481 revF
E
7
May 2022
© Flex
Pin-Out Description Satellite
Pin layout, top view.
Pin
Designation
Type
Function
1, 17
+IN
Power
Input voltage positive.
2, 16
-IN
Power
Input voltage negative.
3
START
Input
4, 5, 13, 14
GND
Power
Power ground and digital ground.
6
TMN
Output
Temperature sense ground. Connect to common temperature sense ground
TMN of Main.
7
TMP
Output
Temperature sense output. Connect to TMPx* input of Main.
8, 9, 10
VOUT
Power
Output voltage.
11
CSN
Output
Output current sense negative. Connect to CSNx* input of Main.
12
CSP
Output
Output current sense positive. Connect to CSPx* input of Main.
15
VCC
Power
Secondary side driver voltage supply.
18
PWMX
Input
19
VDD
Power
20
PWMY
Input
Secondary side synchronization input. Connect to STARTx* output of Main.
Primary side PWM signal. Connect to PWMXx* output of Main (through
digital isolator if isolation needed).
Primary side driver voltage supply. References to -IN.
Primary side PWM signal. Connect to PWMYx* output of Main (through
digital isolator if isolation needed).
________________________________
Note 1. x = 2, 3, 4, 5 or 6 depending on satellite number in application.
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
No.
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
4 (21)
Specification
Rev
28701-BMR481 revF
E
8
May 2022
© Flex
Pin-Out Description Main
Pin layout, top view.
Pin
Designation
Type
Function
1, 2, 41, 42
+IN
Power
Input voltage positive.
3-8, 35-40
-IN
Power
Input voltage negative.
9-16, 27-34
GND
Power
Output voltage ground and digital ground.
17
Reserved
-
18
TMP1
Input
19-24
VOUT
Power
25
CSN1
Input
26
CSP1
Input
43
PWMX
Input
44
VDD
Power
45
PWMY
Input
46
Reserved
-
A1
PFAULT_IN
Output
A2
CSP6
Input
Do not connect.
Temperature sense input for Phase 1. Internally routed to Phase 1 power
train in Main. For test purpose only. Do not connect.
Output voltage.
Output current sense negative for Phase 1. Internally routed to Phase 1
power train in Main. For test purpose only. Do not connect.
Output current sense positive for Phase 1. Internally routed to Phase 1
power train in Main. For test purpose only. Do not connect.
Primary side PWM signal to Phase 1 power train in Main. Connect to
PWMX1 pin (through digital isolator if isolated application).
Primary side driver voltage supply to Phase 1 power train in Main.
References to -IN.
Primary side PWM signal to Phase 1 power train in Main. Connect to
PWMY1 pin (through digital isolator if isolated application).
Do not connect.
Analog signal output for internal testing. Connect to test point or leave
floating.
Output current sense input positive for Phase 6. Connect to CSP output of
Satellite 5. If no Satellite 5, terminate CSP6 and CSN6 to a VOUT pin.
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
No.
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
5 (21)
Specification
Rev
28701-BMR481 revF
E
9
May 2022
© Flex
Pin
Designation
Type
Function
A3
CSP5
Input
Output current sense input positive for Phase 5. Connect to CSP output of
Satellite 4. If no Satellite 4, terminate CSP5 and CSP5 to a VOUT pin.
A4
CSP4
Input
Output current sense input positive for Phase 4. Connect to CSP output of
Satellite 3. If no Satellite 3, terminate CSP4 and CSN4 to a VOUT pin.
A5
CSP3
Input
Output current sense input positive for Phase 3. Connect to CSP output of
Satellite 2. If no Satellite 2, terminate CSP3 and CSN3 to a VOUT pin.
A6
CSP2
Input
Output current sense input positive for Phase 2. Connect to CSP output of
Satellite 1. If no Satellite 1, terminate CSP2 and CSN2 to a VOUT pin.
A7
FAULT
A8
+S
A9
-S
B1
VSRMON
Input
B2
CSN6
Input
B3
CSN5
Input
B4
CSN4
Input
B5
CSN3
Input
B6
CSN2
Input
B7
RST
Input
B8
SALERT
B9
SADDR
Input
Address setting. Connect a resistor divider to VCC5/GND in order to define
PMBus and VR12.5 / VR13 addresses (if applicable). See section PMBus
Interface.
C1
TMN
Input
Temperature sense input ground common for Main and Satellites. Connect
to TMN of Satellites. If no Satellites, leave unconnected.
C2
TMP6
Input
Temperature sense input for Phase 6. Connect to TMP output of Satellite 5.
If no Satellite 5, leave unconnected.
C3
TMP5
Input
Temperature sense input for Phase 5. Connect to TMP output of Satellite 4.
If no Satellite 4, leave unconnected.
C4
TMP4
Input
Temperature sense input for Phase 4. Connect to TMP output of Satellite 3.
If no Satellite 3, leave unconnected.
Programmable fault indicator, active low. It is pulled low when any of the
Output
selected fault conditions are triggered. Pull-up to any external voltage
Open drain
equal or lower than VS. If not used leave floating.
Output voltage positive sense. Connect to the positive side of the
Input
load to perform remote sense compensating for copper losses on the PCB.
Route differentially with -S.
Output voltage negative sense. Connect to the negative side of the
Input
load to perform remote sense compensating for copper losses on the PCB.
Route differentially with +S.
Input voltage monitoring and feed forward input. See section Input Voltage
Sense.
Output current sense input negative for Phase 5. Connect to CSN output of
Satellite 4. If no Satellite 4, terminate CSPx and CSNx together to VOUT
pins. Note 1, 2
Output current sense input negative for Phase 3. Connect to CSN output of
Satellite 2. If no Satellite 2, terminate CSPx and CSNx together to VOUT
pins. Note 1, 2
Output current sense input negative for Phase 2. Connect to CSN output of
Satellite 1. If no Satellite 1, terminate CSPx and CSNx together to VOUT
pins. Note 1, 2
Output current sense input negative for Phase 4. Connect to CSN output of
Satellite 3. If no Satellite 3, terminate CSPx and CSNx together to VOUT
pins. Note 1, 2
Output current sense input negative for Phase 6. Connect to CSN output of
Satellite 5. If no Satellite 5, terminate CSPx and CSNx together to VOUT
pins. Note 1, 2
Reset, active low. Puts the controller in the lowest power consumption state.
Internally pulled high. Leave unconnected if unused.
Output
PMBus Alert. Asserted low when any of the configured protection
Open drain mechanisms indicate a fault. If not used leave floating.
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
No.
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
6 (21)
Specification 10
Rev
28701-BMR481 revF
E
May 2022
© Flex
Pin
Designation
Type
Function
C5
TMP3
Input
Temperature sense input for Phase 3. Connect to TMP output of Satellite 2.
If no Satellite 2, leave unconnected.
C6
TMP2
Input
Temperature sense input for Phase 2. Connect to TMP output of Satellite 1.
If no Satellite 1, leave unconnected.
C7
EN
Input
Output voltage enable/CTRL pin. Can be left open if unused due to internal
pull-up. See section Remote Control.
C8
SCL
Input
PMBus Clock. Clock for PMBus communication. Requires a pull-up resistor,
also when unused. See section PMBus Interface.
C9
SDA
D1
PUCDTI
Input
Optional microcontroller interface chip select. 5 V compatible. Connect to
GND if unused. See section PuC Interface.
D2
PUCCK
Input
Optional microcontroller interface clock. 5 V compatible. Connect to GND if
unused. See section PuC Interface.
D3
START2
Output
Secondary side synchronization output for Phase 2/Satellite 1. If no Satellite
1 leave floating.
D4
START3
Output
Secondary side synchronization output for Phase 3/Satellite 2. If no Satellite
2 leave floating.
D5
START4
Output
Secondary side synchronization output for Phase 4/Satellite 3. If no Satellite
3 leave floating.
D6
START5
Output
Secondary side synchronization output for Phase 5/Satellite 4. If no Satellite
4 leave floating.
D7
START6
Output
Secondary side synchronization output for Phase 6/Satellite 5. If no Satellite
5 leave floating.
D8
VR_RDY
D9
SVCLK_AVSCLK
Input
Optional Intel domain VR1x serial bus clock or AVSBus clock. Connect to
GND if unused. See sections SVID Interface and AVSBus Interface.
E1
PUCDTO
Output
Optional microcontroller interface data output. 5 V compatible. If not used
leave floating. See section PuC Interface.
E2
PWM1Y
Output
Primary side PWMY output to Phase 1. Connect to PWMY pin (through
digital isolator if isolated application).
E3
PWM2Y
Output
Primary side PWMY output to Phase 2. Connect to PWMY pin of Satellite 1
(through digital isolator if isolated application). If no Satellite 1 leave floating.
E4
PWM3Y
Output
Primary side PWMY output to Phase 3. Connect to PWMY pin of Satellite 2
(through digital isolator if isolated application). If no Satellite 2 leave floating.
E5
PWM4Y
Output
Primary side PWMY output to Phase 4. Connect to PWMY pin of Satellite 3
(through digital isolator if isolated application). If no Satellite 3 leave floating.
E6
PWM5Y
Output
Primary side PWMY output to Phase 5. Connect to PWMY pin of Satellite 4
(through digital isolator if isolated application). If no Satellite 4 leave floating.
E7
PWM6Y
Output
Primary side PWMY output to Phase 6. Connect to PWMY pin of Satellite 5
(through digital isolator if isolated application). If no Satellite 5 leave floating.
Input/
PMBus Data. Data signal for PMBus communication. Requires a pull-up
Output
resistor, also when unused. See section PMBus Interface.
Open drain
Output
Power good or VR ready output. Pull-up to any external voltage
Open drain equal or lower than VCTRL. If not used leave floating.
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
No.
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
7 (21)
Specification 11
Rev
28701-BMR481 revF
E
May 2022
© Flex
Pin
Designation
Type
Function
Input/
Optional Intel domain VR1x serial bus data or AVSBus master data. Connect
Output
to GND if unused. See sections SVID Interface and AVSBus Interface.
Open drain
E8
SVDAT_AVSMDAT
E9
SVALRT_AVSSDAT
F1
PUCCS
Input
F2
PWM1X
Output
Primary side PWMX output to Phase 1. Connect to PWMX pin (through
digital isolator if isolated application).
F3
PWM2X
Output
Primary side PWMX output to Phase 2. Connect to PWMX pin of Satellite 1
(through digital isolator if isolated application). If no Satellite 1 leave floating.
F4
PWM3X
Output
Primary side PWMX output to Phase 3. Connect to PWMX pin of Satellite 2
(through digital isolator if isolated application). If no Satellite 2 leave floating.
F5
PWM4X
Output
Primary side PWMX output to Phase 4. Connect to PWMX pin of Satellite 3
(through digital isolator if isolated application). If no Satellite 3 leave floating.
F6
PWM5X
Output
Primary side PWMX output to Phase 5. Connect to PWMX pin of Satellite 4
(through digital isolator if isolated application). If no Satellite 4 leave floating.
F7
PWM6X
Output
Primary side PWMX output to Phase 6. Connect to PWMX pin of Satellite 5
(through digital isolator if isolated application). If no Satellite 5 leave floating.
F8
VR_HOT
F9
PAD_ALERT
G4
START1
Output
Secondary side synchronization output to Phase 1. Internally routed to
Phase 1 in Main. For test purpose only. Do not connect.
G5
VCC
Power
Secondary side driver voltage supply to Phase 1 in Main.
G6
VCTRL
Power
Controller supply.
Output
Optional Intel domain VR1x serial bus alert or AVSBus slave data. If not
Open drain used leave floating. See sections SVID Interface and AVSBus Interface.
Optional microcontroller interface chip select. 5 V compatible. Connect to
GND if unused. See section PuC Interface.
Input/
Intel Domain Voltage Regulator Hot, active low. Alarm signal being
Output
asserted when the temperature of one of the sensed Phases exceed the
Open drain maximum programmed (TMAX). If not used leave floating.
Input power sensor alert pin (pin_alert), active low. Can only be used if input
Output
power information is provided through the PuC interface. The threshold is set
Open drain
by command MFR_SVID_PIN_ALERT_THR. If not used leave floating.
________________________________
Note 1. x = 2, 3, 4, 5 or 6 depending on satellite number in application.
Note 2. In the layout for the termination of CSP and CSN, pay special attention and terminate at the exact same point in order to
eliminate any potential voltage drop. Keep termination lines as short as possible.
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
No.
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Rev
8 (21)
Specification 12
28701-BMR481 revF
E
May 2022
© Flex
Application Example
Non-isolated application with one Main and one Satellite (2 phase system).
________________________________
Note 1. The optional use of SVID or AVSBus is dependent on the variant of product used and the specifications of the load.
See section Additional Interfaces for more information.
Note 2. Value of output capacitance will depend on the applicaion and load transient requirements. See section External
Output Capacitors.
Note 3. For PMBus pull-up resistor values, see section SMBus Interface.
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
No.
9 (21)
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
Checked
Date
Specification 13
Rev
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
28701-BMR481 revF
May 2022
E
© Flex
Absolute Maximum Ratings
Characteristics
min
TP1
Operating temperature (see Thermal Consideration section)
TS
Storage temperature
VI
max
Unit
-20
125
°C
-40
125
°C
Input voltage (See Operating Information Section for input and output voltage relations)
-0.3
75
V
VDD
Primary side driver voltage
-0.3
14
V
VCC
Secondary side driver voltage
-0.3
7
V
VCTRL
Secondary side controller voltage
-0.3
7
V
Cout
Output capacitance
470
Viso
Isolation voltage (input to output qualification test voltage)
1500
Vdc
Vtr
Input voltage transient
Signal I/O voltage
typ
µF
TBD
V
PWMX, PWMY (Satellite inputs, referenced to -IN)
-0.3
6
V
CSN, CSP
-0.3
4
V
All other
-0.3
7
V
Ground voltage differential
-S, GND
-0.3
0.3
V
Analog pin voltage
VO, +S
-0.3
4
V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the Electrical Specification section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Configuration File (Main)
The Main product is designed with a digital control circuit. The control circuit uses a configuration file which determines the functionality and
performance of the product. The Electrical Specification table shows parameter values of functionality and performance with the Standard
configuration, unless otherwise specified. The Standard configuration is designed for standalone Main product operation only. Changes in
Standard configuration is required if adding additional external Satellites connected to the Main. Changes in Standard configuration might also
be required to optimize performance in specific application.
Electrical Specification – Control and Monitoring (Main)
This section includes parameter specifications related to controller incorporated in the Main product. In the table below, PMBus commands for
configurable parameters are written in capital letters.
TP1 = -20 °C to +95 °C, VCTRL = 4.5 to 5.5 V, unless otherwise specified under Conditions.
Typical values given at: TP1 = +25 °C, VCTRL = 5.0 V, unless otherwise specified under Conditions.
Standard configuration. Single phase.
Characteristics
Conditions
Power
Good
Threshold
VR_RDY pin
Turn-on input voltage
From VCTRL > 4.2 V to ready to be
enabled
Turn on delay duration
Delay duration range
PMBus configurable, TON_DELAY
Ramp duration
Ramp duration range, PMBus
configurable, DVID_SR_SLOW_STEP
MFR_SVID_SLOW_SR_SELECTOR
Rising
Falling
VI rising threshold
VIon
Turn-on input voltage
range
PMBus configurable
VIN_ON
TINIT
Initialization Time
TONdel
Output voltage
On Delay Time
TONrise/
TOFFfall
Output voltage
On/Off
Ramp Time
(0-100%-0 of VO)
min
typ
Standard config.
max
12
ms
0
ms
0
127
1.3
0.02
ms
ms
5.1
100
When output voltage disabled
0
0
Unit
ms
% VO
V
60
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
No.
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
Checked
Date
Conditions
UVLOVDD
Under Voltage
Lock-Out
UVLOVCC
Under Voltage
Lock-Out
UVLOVCTRL
Under Voltage
Lock-Out
Remote Sense
Protection
Threshold
28701-BMR481 revF
© Flex
min
VDD rising threshold
Hysteresis
VCC rising threshold
Hysteresis
VCTRL rising threshold
Hysteresis
+S vs VOUT pin
-S vs GND pin
Input Over Voltage
Protection,
IOVP
Input Peak Protection
Output voltage
Under Voltage
Protection,
UVP
Output voltage
Over Voltage
Protection,
OVP
Over Current
Protection,
OCP
Over Temperature
Protection,
OTP
Threshold range
PMBus configurable
VIN_UV_FAULT_LIMIT
Set point accuracy
Fault response
Threshold
VIN_UV_FAULT_RESPONSE
Threshold range
PMBus configurable
VIN_OV_FAULT_LIMIT
Set point accuracy
Response time
Fault response
Threshold
Offset threshold
VIN_OV_FAULT_RESPONSE
Offset threshold range
PMBus configurable
VOUT_UV_FAULT_LIMIT
Fault response
Offset threshold
Offset threshold range
Response time
Fault response
Peak OCP threshold
Peak OCP threshold
range
Peak OCP response time
Average OCP threshold
Average OCP threshold
range
Average OCP warning
threshold
Average OCP warning
threshold range
Response time
Fault response
Threshold
Threshold range
Warning threshold
Response time
Fault response
Input voltage
Output voltage
Monitoring accuracy
Output current
Temperature
May 2022
E
Threshold
Input Under Voltage
Protection,
IUVP
Specification 14
Rev
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Characteristics
10 (21)
typ
Standard config.
4.4
200
3.6
300
4.2
500
700
500
35
0
max
4.3
V
mV
V
mV
V
mV
mV
mV
V
60
V
4.1
125
Ignore (0x00)
65
0
mV
V
70
125
Latch (0x80)
3.045
150
50
PMBus configurable
VOUT_OV_FAULT_LIMIT
Set value
PMBus configurable
IOUT_OC_FAULT_LIMIT
500
READ_VOUT, VO = 1.0 V
READ_IOUT, VO = 1.0 V, VI =
40-60 V, IO > (0.25 x max IO)
READ_TEMPERATURE,
TREAD = 8 to +100 °C
A
A
0
500
A
400
us
Latch (0x80)
130
25
C
130
Latch (0x80)
0.25
C
C
115
400
OT_FAULT_RESPONSE
READ_VIN, VI = 53 V
A
ns
A
75
IOUT_OC_FAULT_RESPONSE
PMBus configurable
OT_FAULT_LIMIT
PMBus configurable
A
600
0
mV
ns
150
80
Set value
PMBus configurable
IOUT_OC_WARN_LIMIT
400
0
mV
mV
90
Latch (0x80)
86
VOUT_OV_FAULT_RESPONSE
Set value
PMBus configurable
MFR_IMON, TEL_IOUT_FSR
400
50
us
V
mV
Latch (0x80)
150
VOUT_UV_FAULT_RESPONSE
V
mV
400
VSRMON pin
Unit
us
V
2.5
mV
3
% of value
3
C
INTERNAL USE ONLY
PRODUCT SPECIFICATION
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No.
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
Checked
Date
VSENSE
VIL
VIH
Input resistance
Internal resistance to VOUT/GND
Logic input low threshold
Logic input high threshold
RLO
Logic output low resistance @ 5 mA
VOL
VOH
IOL
II_LEAK
CI_PIN
Logic output low signal level
Logic output high signal level
Logic output low sink current
Logic input leakage current
Logic input capacitance
RI_PU
Internal pull-up resistance to VCTRL
RI_PD
fSMB
Internal pull-down resistance
SMBus Operating frequency
TBUF
SMBus Bus free time
tset
thold
SMBus SDA setup time from SCL
SMBus SDA hold time from SCL
Conditions
28701-BMR481 revF
May 2022
E
© Flex
min
typ
Standard config.
64
1
max
Unit
1.4
kΩ
kΩ
V
0.45
V
1.5
0.4
1.8
V
V
V
0.65
V
1.7
0.7
25
V
V
Ω
13
Ω
45
250
Ω
mV
V
mA
uA
pF
+S/-S
SCL, SDA
SVDAT_AVSMDAT,
SVCLK_AVSCLK
PUCCS, PUCDTI, RST
EN
SCL, SDA
SVDAT_AVSMDAT,
SVCLK_AVSCLK
PUCCS, PUCDTI, RST
EN
SDA, SALERT
SVDAT_AVSMDAT,
SVALRT_AVSSDAT,
PIN_ALERT, VR_HOT,
VR_RDY
FAULT
PUCDO @ 5 mA
PUCDO @ 1 mA
Open drain outputs
Specification 15
Rev
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Characteristics
11 (21)
125
4.5
20
1
10
SCL, SDA, SALERT,
SVCLK_ASCLK,
SVDAT_AVSMDAT,
SVALRT_AVSSDAT
EN, RST
VSRMON
No internal pull-up
10
10
10
STOP bit to START bit
See section SMBus – Timing
See section SMBus – Timing
See section SMBus – Timing
400
kΩ
kΩ
kHz
1.3
µs
100
300
ns
ns
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
No.
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
12 (21)
Checked
Date
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Specification 16
Rev
28701-BMR481 revF
May 2022
E
© Flex
Electrical Specification – Main / Satellite
BMR 481 002x (1.0V)
TP1 = -20 °C to +95 °C, VI = 40 to 60 V, VDD = VCC = VCTRL = 5.0 V, unless otherwise specified under Conditions.
Typical values given at: TP1 = +25 °C, VI = 53 V, VO = 1.0 V, max IO, unless otherwise specified under Conditions.
Measurements made on Reference board ROA 170 014 P5A. Standard configurations used.
External CIN = 1 x 47 μF OSCON (2 x 47 μF for multiphase) + 2 x 1 μF ceramic for each Main or Satellite.
External COUT = 1 x 470 μF/3 mΩ POSCAP (5 x 470 μF for multiphase) + 20 x 10 μF ceramic.
Characteristics
VI
VDD
VCC
VCTRL
Conditions
VOac
fSW
CI
CO
Input supply
Primary side driver supply
Secondary side driver supply
Controller supply
Default output voltage
Output voltage adjustment range
Output voltage set-point resolution
Output voltage accuracy
(including line, load, temp.)
Line regulation
Load regulation
Output ripple & noise
Switching frequency
Main / Satellite internal input cap.
Main / Satellite internal output cap.
IO
Output current (Main / Satellite)
VO
η
PD
η
PD
5
5
5
1.0
0.5
VO ≤ 1.0 V
VO > 1.0 V
Unit
60
13
5.5
5.5
V
V
V
V
V
V
mV
mV
% VO
mV
mV
mVp-p
kHz
nF
μF
1.35
VO ≤ 1.0 V
VO > 1.0 V
IO = 0 - 100%
VO = 1.0 V, 20 MHz BW
TP1 = +25 °C, Note 1
VI = 0 V
VO = 0 V
max
520
5
10
1
1
1
2
730
600
300
1120
0
70
See Output Current Capability graph
A
Peak value
VO = 1.0 V
91.6
IO = max IO
VO = 1.0 V
88.8
%
IO = max IO
VO = 1.0 V
8.8
W
No load
VO = 1.0 V
1.7
W
Efficiency
Main + 5 Satellites
Note 2
Power dissipation
Main + 5 Satellites
Note 2
Peak value
VO = 1.0 V
92.0
%
IO = max IO
VO = 1.0 V
89.2
%
IO = max IO
VO = 1.0 V
50
W
No load
VO = 1.0 V
1.9
W
Controller power dissipation (Main)
IVDD
VDD input current (Main / Satellite)
VCC input current (Main / Satellite)
IVCTRL
40
4.75
4.5
4.5
typ
Standard config.
Efficiency
Main only
Note 2
Power dissipation
Main only
Note 2
PCTRL
IVCC
min
VCTRL input current (Main)
Phase 1 active only
For each added phase
For each active phase
VO = 1.0 V
For each inactive phase
For each active phase
VO = 1.0 V
For each inactive phase
Phase 1 active only
For each added phase
Turned off with EN pin
RST de-asserted
450
12
20
For VO ≠ 1.0 V, see graphs
6
60
For VO ≠ 1.0 V, see graphs
1
90
2.4
70
10
________________________________
Note 1. Measurement from single unit.
Note 2. Including VCC/VDD driver losses. Excluding controller power dissipation P CTRL. See figure below.
%
mW
mW
22
mA
mA
63
100
mA
mA
mA
mA
mA
mA
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
No.
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
13 (21)
Specification 17
Rev
28701-BMR481 revF
E
May 2022
© Flex
Driver losses included, controller losses
excluded:
PD = VI IVI + VDD IVDD + VCC IVCC − VO IO
ŋ=
VO IO
PD + VO IO
Driver and controller losses included:
PTOT = PD +PCTRL
ŋTOT = ŋ
Calculation of efficiency and power dissipation.
PD + VO IO
PD +PCTRL + VO IO
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
No.
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
14 (21)
Specification 18
Rev
28701-BMR481 revF
May 2022
E
© Flex
Typical Output Characteristics, VO = 1.0 V
BMR 481 002x (1.0V)
Multiphase, TP1=+25 °C, Standard configuration
T
P1=+25 °C
Efficiency
[%]
93.0
92.5
92.0
91.5
91.0
90.5
90.0
89.5
89.0
88.5
88.0
87.5
87.0
86.5
86.0
85.5
85.0
1 phase
2 phases
3 phases
4 phases
5 phases
6 phases
0
25
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
[A]
400
[A]
Efficiency vs. load current and fixed number of phases. VI= 53 V. Driver losses included (VCC, VDD). Controller losses excluded (VCTRL).
Efficiency
[%]
93.0
92.5
92.0
91.5
91.0
90.5
90.0
89.5
89.0
88.5
88.0
87.5
87.0
86.5
86.0
85.5
85.0
Driver and controller losses excluded.
Driver losses included. Controller losses excluded.
Driver and controller losses included.
0
25
50
75
100
125
150
Efficiency vs. load current. 6-phase with phase shedding . VI= 53 V.
175
200
225
250
275
300
325
350
375
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
No.
15 (21)
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
Checked
Date
Specification 19
Rev
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
28701-BMR481 revF
May 2022
E
© Flex
BMR 481 002x (1.0V)
Typical Output Characteristics, VO = 0.5 V
Main only, TP1=+25 °C, Standard configuration
Power Dissipation (PD)
Efficiency (ŋ)
[%]
90
[W]
8
89
7
88
VI
6
VI
5
87
40 V
40 V
4
86
48 V
85
53 V
84
60 V
83
48 V
3
53 V
2
60 V
1
0
82
0
7
14
21
28
35
42
49
56
63
0
70 [A]
7
14
21
28
35
42
49
56
63
70
[A]
Efficiency vs. load current and input voltage. Driver losses included (VCC, VDD).
Controller losses excluded (VCTRL).
Dissipated power vs. load current and input voltage. Driver losses included
(VCC, VDD). Controller losses excluded (VCTRL).
Output Current Derating
Output Ripple and Noise
[A]
70
65
60
55
50
45
40
35
30
25
20
15
4.0 m/s
3.0 m/s
2.0 m/s
1.0 m/s
0.5 m/s
60
70
80
90
100
110
120 [°C]
Available load current vs. ambient air temperature and airflow at
VI= 53 V. See section Thermal Consideration.
Full bandwidth, VI = 53 V, IO = max IO.
COUT = 1 x 470 μF/3 mΩ POSCAP + 20 x 10 μF ceramic.
Scale: 5 mV/div, 0.5 µs/div
See section Output Ripple and Noise.
VDD Input Current
VCC Input Current
[A]
0.020
[A]
0.055
0.050
0.018
0.045
0.016
40 V
48 V
0.014
40 V
0.040
48 V
0.035
53 V
60 V
0.012
53 V
0.030
60 V
0.025
0.010
0.020
0
10
20
30
40
50
VDD input current vs. load and input voltage.
For each active phase.
60
70
[A]
0
10
20
30
40
50
VCC input current vs. load and input voltage.
For each active phase.
60
70
[A]
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
No.
16 (21)
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
Checked
Date
Specification 20
Rev
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
28701-BMR481 revF
May 2022
E
© Flex
BMR 481 002x (1.0V)
Typical Output Characteristics, VO = 0.75 V
Main only, TP1=+25 °C, Standard configuration
Power Dissipation (PD)
Efficiency (ŋ)
[%]
91
[W]
9
90
8
7
89
VI
88
87
86
85
40 V
5
40 V
48 V
4
48 V
3
53 V
2
60 V
53 V
84
VI
6
60 V
83
1
0
82
0
7
14
21
28
35
42
49
56
63
0
70 [A]
Efficiency vs. load current and input voltage. Driver losses included (VCC, VDD).
Controller losses excluded (VCTRL).
7
14
21
28
35
42
49
56
63
70
[A]
Dissipated power vs. load current and input voltage. Driver losses included
(VCC, VDD). Controller losses excluded (VCTRL).
Output Ripple and Noise
Full bandwidth, VI = 53 V, IO = max IO.
COUT = 1 x 470 μF/3 mΩ POSCAP + 20 x 10 μF ceramic.
Scale: 5 mV/div, 0.5 µs/div
See section Output Ripple and Noise.
VDD Input Current
VCC Input Current
[A]
0.020
[A]
0.080
0.018
0.070
0.016
40 V
0.060
40 V
48 V
0.014
53 V
60 V
0.012
0.010
48 V
0.050
53 V
60 V
0.040
0.030
0
10
20
30
40
50
VDD input current vs. load and input voltage.
For each active phase.
60
70
[A]
0
10
20
30
40
50
VCC input current vs. load and input voltage.
For each active phase.
60
70
[A]
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
No.
17 (21)
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
Checked
Date
Specification 21
Rev
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
28701-BMR481 revF
May 2022
E
© Flex
BMR 481 002x (1.0V)
Typical Output Characteristics, VO = 1.0 V
Main only, TP1=+25 °C, Standard configuration
Power Dissipation (PD)
Efficiency (ŋ)
[%]
92
[W]
11
91
10
9
90
VI
89
88
40 V
8
VI
7
40 V
6
87
48 V
5
85
53 V
4
84
60 V
3
86
48 V
53 V
60 V
2
83
1
82
0
7
14
21
28
35
42
49
56
63
0
70 [A]
7
14
21
28
35
42
49
56
63
70
[A]
Efficiency vs. load current and input voltage. Driver losses included (VCC, VDD).
Controller losses excluded (VCTRL).
Dissipated power vs. load current and input voltage. Driver losses included
(VCC, VDD). Controller losses excluded (VCTRL).
Output Current Derating
Output Ripple and Noise
[A]
70
65
60
55
50
45
40
35
30
25
20
15
4.0 m/s
3.0 m/s
2.0 m/s
1.0 m/s
0.5 m/s
40
50
60
70
80
90
100
110 [°C]
Available load current vs. ambient air temperature and airflow at
VI= 53 V. See section Thermal Consideration.
Full bandwidth, VI = 53 V, IO = max IO.
COUT = 1 x 470 μF/3 mΩ POSCAP + 20 x 10 μF ceramic.
Scale: 5 mV/div, 0.5 µs/div
See section Output Ripple and Noise.
VDD Input Current
VCC Input Current
[A]
0.026
[A]
0.095
0.024
0.085
0.022
0.075
40 V
40 V
0.020
48 V
0.065
48 V
0.018
53 V
0.055
53 V
60 V
0.016
60 V
0.045
0.014
0.035
0
10
20
30
40
50
VDD input current vs. load and input voltage.
For each active phase.
60
70
[A]
0
10
20
30
40
50
VCC input current vs. load and input voltage.
For each active phase.
60
70
[A]
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
No.
18 (21)
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
Checked
Date
Specification 22
Rev
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
28701-BMR481 revF
May 2022
E
© Flex
BMR 481 002x (1.0V)
Typical Output Characteristics, VO = 1.35 V
Main only, TP1=+25 °C, Standard configuration
Power Dissipation (PD)
Efficiency (ŋ)
[%]
93
[W]
11
92
10
9
91
VI
90
89
40 V
8
VI
7
40 V
6
88
48 V
5
86
53 V
4
85
60 V
3
87
48 V
53 V
60 V
2
84
1
83
0
7
14
21
28
35
42
49
56
63
0
70 [A]
7
14
21
28
35
42
49
56
63
70
[A]
Efficiency vs. load current and input voltage. Driver losses included (VCC, VDD).
Controller losses excluded (VCTRL).
Dissipated power vs. load current and input voltage. Driver losses included
(VCC, VDD). Controller losses excluded (VCTRL).
Output Current Derating
Output Ripple and Noise
[A]
70
65
60
55
50
45
40
35
30
25
20
15
4.0 m/s
3.0 m/s
2.0 m/s
1.0 m/s
0.5 m/s
30
40
50
60
70
80
90
100
110 [°C]
Available load current vs. ambient air temperature and airflow at
VI= 53 V. See section Thermal Consideration.
Full bandwidth, VI = 53 V, IO = max IO.
COUT = 1 x 470 μF/3 mΩ POSCAP + 20 x 10 μF ceramic.
Scale: 5 mV/div, 0.5 µs/div
See section Output Ripple and Noise.
VDD Input Current
VCC Input Current
[A]
0.029
[A]
0.110
0.027
0.100
0.025
0.090
40 V
40 V
0.023
48 V
0.080
48 V
0.021
53 V
0.070
53 V
60 V
0.019
60 V
0.060
0.017
0.050
0
10
20
30
40
50
VDD input current vs. load and input voltage.
For each active phase.
60
70
[A]
0
10
20
30
40
50
VCC input current vs. load and input voltage.
For each active phase.
60
70
[A]
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
No.
Technical
2/1301-BMR 481 Uen
KARALARS Andreas Larsson
Approved (Document resp)
Checked
Date
19 (21)
Specification 23
Rev
BMR481
series
Direct Conversion(KARTHOLM) 2021-11-10
DALGEDMO
Gary Edmonds
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
28701-BMR481 revF
May 2022
E
© Flex
BMR 481 002x (1.0V)
Typical Characteristics
Main only, Standard configuration, TP1 = +25 °C
Enable by EN pin
Disable by EN pin
EN
EN
VO
VO
VR_RDY
VR_RDY
Output enabled by EN pin. VI = 53 V, VO = 1.0 V, IO = max IO.
VR_RDY pulled up to external voltage.
Scale from top: 5, 0.5, 2 V/div, 0.5 ms/div.
Output disabled by EN pin. VI = 53 V, VO = 1.0 V, IO = max IO.
VR_RDY pulled up to external voltage.
Scale from top: 5, 0.5, 2 V/div, 1 ms/div.
Output Current Capability
Switching Frequency
[A]
71
[kHz]
1200
69
1100
67
VO
65
PID_LP_PRE = 85.
PID_LP_POST = 25nSec/(25nSec + tPOST)*2^7; max 0x7F. E.g. tPOST =
50 ns => PID_LP_POST = 43.
Format
Integer Unsigned
Integer Unsigned
MFR_DUTY_PARAMETER (0xD9)
Description: Used to configure TSTART Correction to control average Duty Cycle for the regulation in case of low VIN value.
Through System register TON_RED_CONFIG[6], it is possible to disable phase shedding and enable all phases when input
voltage is below the threshold (VOLTAGE_DUTY_ENABLE). Note. KDUTY duty cycle threshold is 8 bit wide and split between
this command and MFR_KK_FEEDFRWD_GAIN_CTRL. Only for resonant topology.
Bit
23:14
13:9
8:3
2:0
Function
Vin voltage
threshold
(VOLTAGE_D
UTY_ENABLE
)
KDUTY
Proportional
coeff
KDUTY
Integrative
coeff
KDUTY Duty
cycle threshold
[2:0]
Description
Input voltage value below which the correction engages. [#of 0.125V
steps]; max 127.875V.
Format
Fixed Point
Unsigned
Contains PID coefficient KDUTY_PROPORTIONAL. Max value is 0x1F.
Integer
Unsigned
Contains PID coefficient KDUTY_INTEGRATIVE. Max value is 0x3F.
Integer
Unsigned
kDUTY duty cycle [# of 0.195% Steps]; max = 50%, 0d = OFF. Duty cycle
value above which the correction engages. 5 remaining bits are stored into
MFR_KK_FEEDFRWD_CTRL.
Integer
Unsigned
Unit
V
MFR_UNLOCK (0xDA)
Description: Unlocks write AND read access to critical PMBus commands. Takes password as an argument. Needs
WRITE_PROTECT to be set accordingly. Password can be changed by modifying UNLOCK_PWD SysReg and NVM
accordingly. Unlocks the following PMBus commands: MFR_BODY_BRAKE_CONFIG, MFR_CS_PROP_INTEGR,
MFR_DUTY_PARAMETER, MFR_FILT_PRE_POST, MFR_FSWITCH_PROTECT_COEFF,
MFR_KK_FEEDFRWD_GAIN_CTRL, MFR_PID, MFR_T_START_PH_SHIFT_DELTA_DELAY, MFR_VEXT_NVM,
MFR_SECT_L, MFR_SECT_H, MFR_SECT_RD, MFR_SECT_WR, MFR_MEMORY_WORD, MFR_MEMORY_RD,
MFR_MEMORY_WR.
Bit
39:0
Description
Format
Byte Array
MFR_LOCK (0xDB)
Description: Locks the access to Low Level commands. Needs WRITE_PROTECT to be set accordingly.
MFR_FAULT_CONFIG (0xDC)
Description: Used to set up the FAULT# pin behavior. 0b = The event do NOT trigger the FAULT# pin assertion. 1b = The event
triggers the FAULT# pin assertion.
Bit
10
Function
PUC Error
Description
PUC Error.
Value
1
0
Description
Trigger enabled
Trigger blocked
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 60
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Bit
9
8
7
6
5
4
3
2
1
0
18 (42)
No.
Function
Vin Over-Voltage
Fault
VSRMON peak fault
Description
Vin Over-Voltage Fault.
Vout Over-Voltage
Fault (HW)
Iout Over-Current
Fault (HW)
Catastrophic Fault
Vout Over-Voltage Fault (HW).
Vput Over-Voltage
Fault (HW)
Pout Over-power
Fault
Feedback
disconnection fault
Vin Under-voltage
Fault
Over-Temperature
Fault
Vput over-voltage Fault (HW).
Rev
28701-BMR481 revF
B
May 2022
© Flex
Value
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VSRMON pin peak fault.
Iout Over-Current Fault (HW)
Catastrophic Fault.
Pout Over-power Fault.
Feedback disconnection fault.
Vin under voltage Fault.
Over-temperature fault.
Description
Trigger enabled
Trigger blocked
Trigger enabled
Trigger blocked
Trigger enabled
Trigger blocked
Trigger enabled
Trigger blocked
Trigger enabled
Trigger blocked
Trigger enabled
Trigger blocked
Trigger enabled
Trigger blocked
Trigger enabled
Trigger blocked
Trigger enabled
Trigger blocked
Trigger enabled
Trigger blocked
MFR_IMON (0xDE)
Description: Mfr Imon.
Bit
5:0
Description
Used to define RIMON/RG ratio from 2.678 to 174.120 in 64 steps; RIMON/RG = 2.678571 *
(MFR_IMON + 1), RG=~560 Ohm. Peak OCP limit is impacted as PEAK_OCP = 2.1 /
IMONx2 / DCReq / (RIMON/RG) where IMONx2 is given by System Register IMONX2 (OCP
is triggered when the drop across RIMON reaches 2.1V). Impacts also READ_IOUT
reporting.
Format
Fixed Point
Unsigned
MFR_STORE_MAP (0xDF)
Description: Copies the entire RAM content (PMBus commands and system Register values) into NVM, calculating CRC
accordingly. The payload data reflects the settings of WRITE_PROTECT and MFR_PROTECT_DEFAULT registers that the
stored map will feature (in order to store a map write-protected).
Bit
3:0
7:4
Function
MFR_PROTE
CT_DEFAULT
payload
WRITE_PROT
ECT payload
Description
Format
Fixed Point
Unsigned
Fixed Point
Unsigned
MFR_RESTORE_MAP (0xE0)
Description: Restores the NVM content into RAM, as happens during device initial startup.
MFR_CELL_CONFIG (0xE4)
Description: Used to define the number of phases in design.
Bit
2:0
Description
Number of phases/modules in design.
MFR_OV_LIMIT_OFFSET (0xE5)
Description: MFR_OV_LIMIT_OFFSET.
Value
000
001
010
011
100
101
Function
1 phase
2 phases
3 phases
4 phases
5 phases
6 phases
Description
Main only
1 Main + 1 Satellite.
1 Main + 2 Satellites.
1 Main + 3 Satellites.
1 Main + 4 Satellites.
1 Main + 5 Satellites.
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 61
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Bit
2:0
19 (42)
No.
Rev
28701-BMR481 revF
May 2022
B
© Flex
Description
Used to program the VOUT over voltage threshold as positive offset from 50mV (0x00) to
400mV (0x07) in 50mV steps. OV threshold is set above the commanded Vout setpoint,
regardless of the voltage positioning offset (droop).
Format
Fixed Point
Unsigned
Unit
ΔmV
Format
Fixed Point
Unsigned
Unit
ΔmV
Format
Fixed Point
Unsigned
Unit
V
MFR_UV_LIMIT_OFFSET (0xE6)
Description: MFR_UV_LIMIT_OFFSET.
Bit
2:0
Description
Used to program the VOUT under voltage threshold as negative offset from 50mV (0x00) to
400mV (0x07) in 50mV steps. UV threshold is set below the commanded setpoint
considering the voltage positioning offset (droop).
MFR_VBOOT_SET (0xE7)
Description: MFR_VBOOT_SET.
Bit
9:0
Description
Used to define VBOOT to which the device regulate after receiving valid enable. [VID] data
need to be compliant with format specified in VOUT_MODE. This is the default boot voltage
in SVI Mode (Reg26h) and AVS Mode (when OPERATION is set accordingly).
MFR_SVI_PMBUS_SELECT (0xE8)
Description: Switch ON (0x01) or OFF (0x00) the Vout control on PMBus domain. In AVS mode this command is NACKed.
Bit
0
Description
[0]: 0b0 = CPU-Link / 0b1 = PMBus"
Value
0
1
Function
SVID Bus
PMBus
Description
SVID CPU-Link
PMBus
MFR_ICC_MAX_ADD (0xE9)
Description: Additional bytes to standard SVID commands. Formatted per CPU-link definition. LSB = 2A. Check HC_SUPPORT
for further info.
Bit
7:0
Description
MFR_ICC_MAX_ADD [A].
Format
Integer Unsigned
MFR_PWR_IN_MAX_ADD (0xEA)
Description: Additional bytes to standard SVID commands. Formatted per CPU-link definition. LSB = 4W. Check HC_SUPPORT
for further info.
Bit
7:0
Description
MFR_PWR_IN_MAX_ADD [W].
Format
Integer Unsigned
MFR_PWR_IN_ALERT_ADD (0xEB)
Description: Additional bytes to standard SVID commands. Formatted per CPU-link definition. LSB = 4W. Check HC_SUPPORT
for further info.
Bit
7:0
Description
MFR_PWR_IN_ALERT_ADD [W].
Format
Integer Unsigned
MFR_READ_PIN_PUC (0xEF)
Description: Used to read the Input Power communicated through PuC interface, value averaged over configured
MFR_AVERAGE_TIME_SCALE.
Bit
15:0
Description
LSB=1W.
Format
Linear
Unit
W
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 62
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
20 (42)
No.
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Rev
28701-BMR481 revF
May 2022
B
© Flex
MFR_READ_VIN_PUC (0xF0)
Description: Used to read the Input voltage communicated through PuC interface, value averaged over configured
MFR_AVERAGE_TIME_SCALE.
Bit
15:0
Description
LSB=0.125 V.
Format
Linear
Unit
V
MFR_DPM1_THR (0xF1)
Description: Sets the phase shedding; phase 1 to 2 threshold. Offset by DPM_OFFSET to compensate for current ripple. Realtime current used to increase # of phases, time averaged current used to reduce # of phases. Can be handled as Linear format
when reading, and also when writing if bits(15:11) = exponent = -1 (0b11111).
Bit
9:0
Description
LSB weight is given by System Register IOUT_EXP.
Format
Fixed Point
Unsigned
Unit
A
MFR_DPM2_THR (0xF2)
Description: Sets the phase shedding; phase 1 to 2 threshold. Offset by DPM_OFFSET to compensate for current ripple. Realtime current used to increase # of phases, time averaged current used to reduce # of phases. Can be handled as Linear format
when reading, and also when writing if bits(15:11) = exponent = -1 (0b11111).
Bit
9:0
Description
LSB weight is given by System Register IOUT_EXP.
Format
Fixed Point
Unsigned
Unit
A
MFR_DPM3_THR (0xF3)
Description: Sets the phase shedding; phase 1 to 2 threshold. Offset by DPM_OFFSET to compensate for current ripple. Realtime current used to increase # of phases, time averaged current used to reduce # of phases. Can be handled as Linear format
when reading, and also when writing if bits(15:11) = exponent = -1 (0b11111).
Bit
9:0
Description
LSB weight is given by System Register IOUT_EXP.
Format
Fixed Point
Unsigned
Unit
A
MFR_DPM4_THR (0xF4)
Description: Sets the phase shedding; phase 1 to 2 threshold. Offset by DPM_OFFSET to compensate for current ripple. Realtime current used to increase # of phases, time averaged current used to reduce # of phases. Can be handled as Linear format
when reading, and also when writing if bits(15:11) = exponent = -1 (0b11111).
Bit
9:0
Description
LSB weight is given by System Register IOUT_EXP.
Format
Fixed Point
Unsigned
Unit
A
MFR_DPM5_THR (0xF5)
Description: Sets the phase shedding; phase 1 to 2 threshold. Offset by DPM_OFFSET to compensate for current ripple. Realtime current used to increase # of phases, time averaged current used to reduce # of phases. Can be handled as Linear format
when reading, and also when writing if bits(15:11) = exponent = -1 (0b11111).
Bit
9:0
Description
LSB weight is given by System Register IOUT_EXP.
Format
Fixed Point
Unsigned
Unit
A
MFR_FSWITCH_PROTECT_COEFF (0xF6)
Description: Resonant Loop Only. Used to configure FSW protection during ACLL. Enabled/Disabled through sys reg
DISABLE_DPM_PROT
Bit
3:0
Description
FSW_AVG computed as the average frequency of the previous [16 - FSW_AVGd] cycles.
0x01 = 15 cycles; 0x0F = 1 cycles; 0x00 = 0 cycles.
Format
Integer Unsigned
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 63
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
21 (42)
No.
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Rev
28701-BMR481 revF
B
May 2022
© Flex
MFR_CS_PROP_INTEGR (0xF7)
Description: Sets Proportional (Kp) and Integral (Ki) correction for Active Current Sharing. In resonant topologies: In order to
enable the feature you need to set Ki to 1 or more. The higher value, the faster the regulator recovers current balancing after a
load (or number of turned on phases) change. Leave Kp=0. Algorithm: when a phase current is less than average value of
load/number of phases, then PWMx to START delay is increased. In non-resonant topologies (PSFB): In order to enable the
feature you need to set Kp to 1 or more. The higher value, the faster the regulator recovers current balancing after load (or
number of turned on phases) change. Leave Ki=0. Algorithm: when a phase current is less than average value of load/number
of phases, then PWMx to PWMy time width is increased.
Bit
13:7
6:0
Function
Current
Sharing Loop Ki
Current
Sharing Loop Kp
Description
Integral correction for active current sharing
Format
Integer Unsigned
Proportional correction for active current sharing
Integer Unsigned
MFR_KK_FEEDFRWD_GAIN_CTRL (0xF9)
Description: Setups Input Voltage Feed-Forward Compensation. It also allow to setup other parameters. K Feed Forward: It is
the input voltage FeedForward Gain for resonant topologies. As default value, it is an integer number which value is
=(Tsw_noload*VOUT/VIN*1000) where Tsw_noload is the switching period of one secondary phase at no load in uSeconds.
KDUTY sets the duty cycle value above which the TSTART correction applies (See MFR_DUTY_PARAMETER). Note. kDUTY
is 8 bit wide and split between this command and MFR_KK_FEEDFRWD_GAIN_CTRL. Enable Ph Order: Enables/disables
phase order memory during load transients. V_ERR_CLAMP_SOFTSTART: Used to override ErrorClamp setting (active only
during SoftStart). Enable Memory: Enables Pulse memory during ACLL. If the VCO drives more pulses during the current Pulse,
these are memorized and fired after the current Pulse has elapsed. K_GAIN_CTRL. Defines the bandwidth of the feed forward
loop.
Bit
42:24
Function
Feed Forward
Constant
23:19
KDUTY Duty
cycle threshold
[7:3]
Error clamp
threshold at
soft-start
15:10
7:0
Feed Forward
Gain
Bit
18
Function
Enable Ph
Order On
17
Enable Err
Clamp Pre
Enable
Integrative
During Phase
Memory On
Secure Off
Enable
Enable
Memory
16
9
8
Description
Feed forward constant, integer. As default value, calculate it as
(Tsw_noload*VOUT/VIN*1000) where Tsw_noload is the switching period
of one secondary phase at no load in useconds. For resonant topology
only.
kDUTY duty cycle [# of 0.195% Steps]; max = 50%, 0d = OFF. Duty cycle
value above which the correction engages. 3 remaining bits are stored in
MFR_DUTY_PARAMETER.
During soft-start (Vout ramp-up) this setting overrides the error clamp
setting by CTRL_VERR_CLAMP. LSB = 2mV. Error clamp threshold =
2mV * (63 - set value). Max 126mV (0x01). Set 128mV (0x00) to disable
function.
Sets K_GAIN_CTRL, the FeedForward Gain. Set to 0x01.
Format
Integer
Unsigned
Integer
Unsigned
Integer
Unsigned
Value
0xb1
0xb0
Function
Description
Enabled.
Disabled.
0xb1
Enabled
Enabled.
0xb1
Enabled
Enabled.
Secure Off Enable. Reserved,
need to be 1 (enabled).
Enables pulse memory during
ACLL.
0xb1
Enable
Secure Off enabled.
0xb0
mV
Integer
Unsigned
Description
Phase Order On Enable. 0x01 =
Enable sequential; 0x00 =
Disables Sequential (=Shuffle).
Error Clamp Pre. Reserved, need
to be 1 (enabled).
Integrative During Phase Memory
On Enable. Reserved, need to be
1 (enabled).
0xb1
Unit
Pulse memory during ACLL
enabled.
Pulse memory during ACLL
disabled.
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 64
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
22 (42)
No.
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Rev
28701-BMR481 revF
May 2022
B
© Flex
MFR_VOUT_TRIM (0xFA)
Description: Mfr Vout Trim
Bit
7:0
Description
Sets Mfr VOUT trim value. Applies a fixed offset voltage to the value set by
VOUT_COMMAND (in # of VID steps). [# of VID]. Applied only in PMBus Domain. # of VID
steps to add or remove from setpoint. In AVS mode, if applied, need to be in tracking with
EXTRA_OFFSET.
Format
Integer
Signed
Unit
VID
steps
MFR_MANUAL_CELL_SHED (0xFB)
Description: Sets DPM_NPH_PS00, DPM_NPH_PS01 and DPM_NPH_PS02 which are the minimum # of phases for Intel VR
power states PS00, PS01 and PS02. Unless otherwise commanded by SVID interface, PS00 power state is used. If trying to set
a min # phases higher than # of phases set by MFR_CELL_CONFIG, the write will have no effect and the Unsupported Data bit
in STATUS_CML is set.
Bit
9:6
Function
OFFSET_FRA
CT
Description
Optimizes PSKIP behavior
Bit
12:10
Function
Min # of
phases (PS02SVID)
Description
Minimum # of phases for power
state PS02 (Intel VR/SVID only).
5:3
Min # of
phases (PS01SVID)
Minimum # of phases for power
state PS01 (Intel VR/SVID only).
2:0
Min # of
phases (PS00)
Minimum # of phases for power
state PS00 (default).
Format
Integer Unsigned
Value
001
010
011
100
101
110
001
010
011
100
101
110
001
010
011
100
101
110
Function
Min 1 phase
Min 2 phases
Min 3 phases
Min 4 phases
Min 5 phases
Min 6 phases
Min 1 phase
Min 2 phases
Min 3 phases
Min 4 phases
Min 5 phases
Min 6 phases
Min 1 phase
Min 2 phases
Min 3 phases
Min 4 phases
Min 5 phases
Min 6 phases
Description
MFR_SVID_TEMPZONE (0xFE02)
Description: SVID Temperature Zone Register (reg12h). Not stored in NVM. Formatted as per CPU-link definition. Write
unlocked by MFR_SVID_REGLOCK.
Bit
7:0
Description
Format
Integer Unsigned
MFR_SVID_IOUT (0xFE03)
Description: SVID Output Current Register (reg15h). Not stored in NVM. Formatted as per CPU-link definition. Write unlocked
by MFR_SVID_REGLOCK.
Bit
7:0
Description
Format
Integer Unsigned
MFR_SVID_VIDSETTING (0xFE04)
Description: Last VID code commanded, i.e. actial regulation setpoint. Not stored in NVM. Formatted as per CPU-link definition.
Write unlocked by MFR_SVID_REGLOCK.
Bit
9:0
Description
Format
Integer Unsigned
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 65
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
23 (42)
No.
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Rev
28701-BMR481 revF
B
May 2022
© Flex
MFR_SVID_PWRSTATE (0xFE05)
Description: Last PWRState Commanded. Not stored in NVM. Formatted as per CPU-link definition. Write unlocked by
MFR_SVID_REGLOCK.
Bit
7:0
Description
Format
Integer Unsigned
MFR_SVID_OFFSET (0xFE06)
Description: SVID Commanded Offset (reg33h). See System Register CRC_SPI_EN for additional information. Formatted as
per CPU-link definition. Write unlocked by MFR_SVID_REGLOCK.
Bit
7:0
Description
Format
Integer Unsigned
MFR_START_THREAD (0xFE07)
Description: When sent, IC starts to compute the total power delivered. Average Power delivered in 1.2 mSec interval is
progressively added until the max time programmed T_THREAD = 1.2mSec * MFR_START_THREAD"
Bit
19:0
Description
Number of 1 mSec interval to collect the measure on. Max 1,048,576 => 20.97min. Unit in
ms.
Format
Fixed Point
Unsigned
Unit
ms
MFR_SVID_ICCMAX (0xFE08)
Description: ICCMAX Register (reg21h). This is not linked to OC protection in any way. Write unlocked by
MFR_SVID_REGLOCK
Bit
7:0
Description
Format
Integer Unsigned
MFR_SVID_TEMPMAX (0xFE09)
Description: TMAX Register (reg22h). This is not linked to OT protection in any way. Write unlocked by MFR_SVID_REGLOCK.
Bit
7:0
Description
Format
Integer Unsigned
MFR_SVID_SRFAST (0xFE0A)
Description: Slew Rate Fast (reg24h). Write unlocked by MFR_SVID_REGLOCK. This is for CPU-Link reading only. Actual slew
rate is set through System Register DVID_SR_FAST_STEP.
Bit
7:0
Description
Format
Integer Unsigned
MFR_SVID_SRSLOW (0xFE0B)
Description: Slew Rate Slow (reg25h). Write unlocked by MFR_SVID_REGLOCK. This is for CPU-Link reading only. Actual slew
rate is set through System Register DVID_SR_SLOW_STEP.
Bit
7:0
Description
Format
Integer Unsigned
MFR_SVID_MULTI_VR_CONFIG (0xFE0C)
Description: SVID Multi VR Config (reg34h). Not stored in NVM. Formatted as per CPU-link definition. Write unlocked by
MFR_SVID_REGLOCK.
Bit
1:0
Description
MFR_SVID_VOUTMAX (0xFE0D)
Description: VOUTMAX (reg30h). Write unlocked by MFR_SVID_REGLOCK
Format
Integer Unsigned
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 66
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Bit
7:0
24 (42)
No.
Rev
28701-BMR481 revF
May 2022
B
© Flex
Description
Formatted as per CPU-Link definition
Format
Integer
Unsigned
Unit
V
MFR_SVID_SLOW_SR_SELECTOR (0xFE0E)
Description: Select SVID SR Slow range as fraction of SVID SR Fast range. Write unlocked by MFR_SVID_REGLOCK. It
affects real slew rate as programmed by System Registers DVID_SR_FAST_STEP and DVID_SR_SLOW_STEP. Setting of
VR13.1 HC options.
Bit
7
Function
Enable HC
support
6
Activate HC
Description
Configures VR13.HC support Can
only be written directly to NVM,
read-only in RAM! 0b0: VR13
Protocol support. Exponent for
Iout and Pout read/settings and
TEL_IOUT_FSR is set by
IOUT_EXP. Registers
PWR_IN_MAX_ADD and
PWR_IN_ALERT_ADD are
ignored. 0b1: VR13.HC Protocol
support. Iout exponent = -1
(LSB=0.5A), Pout exponent = 1
(LSB=2W), TEL_IOUT_FSR
exponent = 1 (LSB=2A),
regardless of HC active or not.
Registers PWR_IN_MAX_ADD
and PWR_IN_ALERT_ADD are
supported according to VR13.HC
specs. The following commands
are affected by the exponent
setting: IOUT_OC_FAULT_LIMIT.
IOUT_OC_WARN_LIMIT.
POUT_OP_FAULT_LIMIT.
READ_IOUT. READ_POUT.
MFR_DPM1_THR.
MFR_DPM2_THR.
MFR_DPM3_THR.
MFR_DPM4_THR.
MFR_DPM5_THR.
MFR_READ_PIN_POUT.
TEL_IOUT_FSR.
DPM_HYSTERESIS.
Value
1
1
Function
HC supported
Description
HC supported
HC activated
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 67
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Bit
Function
3:0
Slow vs fast
slew rate
range
FRACTION
25 (42)
No.
Description
Pre-sets the HC_ACTIVE bit
supposed to be commanded
through the SVI interface. Can
only be written directly to NVM,
read-only in RAM! 0b0: HC mode
not active. The device behaves as
a VR13 controller. -> DEFAULT.
ICCMAX = MFR_SVID_ICCMAX
[A]. PIN_MAX =
MFR_SVID_PIN_MAX*2 [W].
PIN_ALERT_THRESHOLD =
MFR_SVID_PIN_ALERT_THR*2
[W]. 0b1: HC mode active.
ICCMAX = MFR_SVID_ICCMAX
+ MFR_ICC_MAX_ADD*2 [A].
PIN_MAX =
MFR_SVID_PIN_MAX*2 +
MFR_PWR_IN_MAX_ADD*4 [W].
PIN_ALERT_THRESHOLD =
MFR_SVID_PIN_ALERT_THR*2
+ MFR_PWR_IN_ALERT_ADD*4
[W].
0x01 = 1/2; 0x02 = 1/4; 0x04 =
1/8; 0x08 = 1/16 Others are
rejected"
Rev
28701-BMR481 revF
May 2022
B
© Flex
Value
0
Function
0x01
0x02
0x04
0x08
1/2
1/4
1/8
1/16
Description
HC not activated
MFR_SVID_PIN_MAX (0xFE0F)
Description: PINMAX (reg2Eh). Used to set the PIN protection threshold. Set threshold to max allowable to disable the
protection. Write unlocked by MFR_SVID_REGLOCK. Formatted per CPU-link definition. LSB = 2W.
Bit
7:0
Description
Format
Integer Unsigned
MFR_SVID_PIN_ALERT_THR (0xFE10)
Description: Used to set the PIN protection ALERT threshold. Set threshold to max allowable to disable the warning signal.
Write unlocked by MFR_SVID_REGLOCK. Formatted per CPU-link definition. LSB = 2W.
Bit
7:0
Description
Format
Integer Unsigned
MFR_SVID_WP0 (0xFE11)
Description: SVID Working point #0 (reg3Ah). Not stored in NVM. Formatted as per CPU-link definition. Write unlocked by
MFR_SVID_REGLOCK.
Bit
7:0
Description
Format
Integer Unsigned
MFR_SVID_WP1 (0xFE12)
Description: SVID Working point #1 (reg3Bh). Not stored in NVM. Formatted as per CPU-link definition. Write unlocked by
MFR_SVID_REGLOCK.
Bit
7:0
Description
Format
Integer Unsigned
MFR_SVID_WP2 (0xFE13)
Description: SVID Working point #2 (reg3Ch). Not stored in NVM. Formatted as per CPU-link definition. Write unlocked by
MFR_SVID_REGLOCK.
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 68
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Bit
7:0
26 (42)
No.
Rev
28701-BMR481 revF
May 2022
B
© Flex
Description
Format
Integer Unsigned
MFR_SVID_WP3 (0xFE14)
Description: SVID Working point #3 (reg3Dh). Not stored in NVM. Formatted as per CPU-link definition. Write unlocked by
MFR_SVID_REGLOCK.
Bit
7:0
Description
Format
Integer Unsigned
MFR_SVID_WP4 (0xFE15)
Description: SVID Working point #4 (reg3Eh). Not stored in NVM. Formatted as per CPU-link definition. Write unlocked by
MFR_SVID_REGLOCK.
Bit
7:0
Description
Format
Integer Unsigned
MFR_RD_TEMPERATURE_PHASE1 (0xFE16)
Description: Reads the temperature for Phase 1. Reporting is active only when Phase 1 is switching.
Bit
15:0
Description
Phase 1 temperature.
Format
Linear
Unit
°C
Format
Linear
Unit
°C
Format
Linear
Unit
°C
Format
Linear
Unit
°C
Format
Linear
Unit
°C
Format
Linear
Unit
°C
MFR_RD_TEMPERATURE_PHASE2 (0xFE17)
Description: Reads the temperature for Phase 2. Reporting is active only when Phase 2 is switching.
Bit
15:0
Description
Phase 2 temperature.
MFR_RD_TEMPERATURE_PHASE3 (0xFE18)
Description: Reads the temperature for Phase 3. Reporting is active only when Phase 3 is switching.
Bit
15:0
Description
Phase 3 temperature.
MFR_RD_TEMPERATURE_PHASE4 (0xFE19)
Description: Reads the temperature for Phase 4. Reporting is active only when Phase 4 is switching.
Bit
15:0
Description
Phase 4 temperature.
MFR_RD_TEMPERATURE_PHASE5 (0xFE1A)
Description: Reads the temperature for Phase 5. Reporting is active only when Phase 5 is switching.
Bit
15:0
Description
Phase 5 temperature.
MFR_RD_TEMPERATURE_PHASE6 (0xFE1B)
Description: Reads the temperature for Phase 6. Reporting is active only when Phase 6 is switching.
Bit
15:0
Description
Phase 6 temperature.
MFR_CTRL_ID (0xFE1C)
Description: Used to read controller internal reference code.
Bit
15:0
Description
Used to read controller internal reference code.
Format
Byte Array
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 69
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
27 (42)
No.
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Rev
28701-BMR481 revF
May 2022
B
© Flex
MFR_SVID_REGLOCK (0xFE1E)
Description: CPU-Link registers are by default accessible only with read operations (locked). This command allows to lock
(0x01) or unlock (0x00) access to these registers. This command is not stored in NVM but will be set to lock state (0x01) efter a
RESTORE from NVM command (e.g. MFR_RESTORE_MAP).
Bit
0
Description
Value
1
0
Description
Protects SVID Registers
Unprotects SVID
Registers
MFR_SECT_L (0xFE20)
Description: 8 bytes low sector image data - Used to access read NVM data after writing MFR_SECT_RD or to write NVM data
before writing MFR_SECT_WR. [63..56] = byte 00 ... [7..0] = byte 07.
Bit
63:0
Description
Format
Integer Unsigned
MFR_SECT_H (0xFE21)
Description: 8 bytes high sector image data - Used to access read NVM data after writing MFR_SECT_RD or to write NVM data
before writing MFR_SECT_WR. [63..56] = byte 08 ... [7..0] = byte 15.
Bit
63:0
Description
Format
Integer Unsigned
MFR_SECT_RD (0xFE24)
Description: Copy from specified NVM sector (0x01 to 0x0E) into a register accessible by PMBus commands MFR_SECT_L and
MFR_SECT_H.
Bit
7:0
Description
Format
Integer Unsigned
MFR_SECT_WR (0xFE25)
Description: Copy from register written by PMBus commands MFR_SECT_L and MFR_SECT_H into specified NVM sector
(0x01 to 0x0E).
Bit
7:0
Description
Format
Integer Unsigned
MFR_MEMORY_WORD (0xFE26)
Description: 8 bytes - Data for read/write of specified RAM memory location (used by MFR_MEMORY_RD or
MFR_MEMORY_WR). [63..56] = Base Address +7 ... [7..0] = Base Address as specified into MFR_MEMORY_RD,
MFR_MEMORY_WR.
Bit
63:0
Description
Format
Integer Unsigned
MFR_MEMORY_RD (0xFE27)
Description: 3 bytes - Used to copy 8 bytes of the specified RAM memory location into PMBusTM accessible register, read by
MFR_MEMORY_WORD. Byte 1 [7:0] : RAM address low byte. Byte 2 [15:8]: RAM address high byte. Byte 3 [23:16]: Source.
0x00 to read from RAM. Other combinations are reserved. Protected by MFR_UNLOCK.
Bit
23:0
Description
Format
Integer Unsigned
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
28 (42)
No.
Technical
Specification 70
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Rev
28701-BMR481 revF
May 2022
B
© Flex
MFR_MEMORY_WR (0xFE28)
Description: "4 bytes - Used to copy the content of PMBusTM accessible registers, written to MFR_MEMORY_WORD, into the
specified RAM memory location. Byte 1 [7:0] : RAM address low byte. Byte 2 [15:8] : RAM address high byte. Byte 3 [23:16]:
Source. 0x00 to read from RAM. Other combinations are reserved. Byte 4 [31:24]: Number of bytes to be written, 1 to 8. Other
combinations are reserved. Protected by MFR_UNLOCK.
Bit
31:0
Description
Format
Integer Unsigned
MFR_READ_BLACKBOX (0xFE29)
Description: NVM BBR Access. Used to copy the content of NVM that contains BBR data into accessible PMBusTM register
MFR_BLACKBOX.
MFR_BLACKBOX (0xFE2A)
Description: NVM BBR Access - Shadow register containing the BBR NVM Sector being read. Status Register array is reported
before and after the BBR trigger.
Bit
125
124
123
122
121
120
115
114
113
112
110
103
102
101
100
99
98
97
96
Function
After trigger VSRMON peak fault
After trigger PATCH_DOWNLOA
D
After trigger MEM_FAULT
After trigger POUT_OP_FAULT
After trigger DATACMD_RCV_FA
ULT
After trigger IOUT_OC_WARN
After trigger CATASTROPHIC_FA
ULT
After trigger VIN_UV_FAULT
After trigger VIN_OV_FAULT
After trigger PUC_CRC_FAULT
After trigger CURR_SHARE_WAR
N
After trigger - OFF
After trigger VOUT_OV_FAULT
After trigger VOUT_UV_FAULT
After trigger IOUT_OC_FAULT
After trigger Feedback
disconnection
After trigger VOUT_MAX_WARNI
NG
After trigger OT_FAULT
Description
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Description
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 71
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Bit
93
92
91
90
89
88
83
82
81
80
78
71
70
69
68
67
66
65
64
Function
After trigger OT_WARNING
Before trigger VSRMON peak fault
Before trigger PATCH_DOWNLOA
D
Before trigger MEM_FAULT
Before trigger POUT_OP_FAULT
Before trigger DATACMD_RCV_FA
ULT
Before trigger IOUT_OC_WARN
Before trigger CATASTROPHIC_FA
ULT
Before trigger VIN_UV_FAULT
Before trigger VIN_OV_FAULT
Before trigger PUC_CRC_FAULT
Before trigger CURR_SHARE_WAR
N
Before trigger - OFF
29 (42)
No.
Description
Rev
28701-BMR481 revF
B
May 2022
© Flex
Value
1
Description
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Before trigger VOUT_OV_FAULT
Before trigger VOUT_UV_FAULT
Before trigger IOUT_OC_FAULT
Before trigger Feedback
disconnection
Before trigger VOUT_MAX_WARNI
NG
Before trigger OT_FAULT
Before trigger OT_WARNING
0
1
0
1
0
1
MFR_CLEAR_BB (0xFE2B)
Description: Clear the content of NVM that contains BBR data.
MFR_CONFIG_BBR (0xFE2C)
Description: "Select which events trigger the writing of the BBR in NVM. Set 1b to enable event to trigger BBR, 0b to disable."
Bit
11
Function
PUC_CRC_FAULT
10
Feedback
disconnection fault
VSRMON peak fault
9
Description
Value
0
1
0
1
0
1
Description
Do not trigger on fault
Trigger event on fault
Do not trigger on fault
Trigger event on fault
Do not trigger on fault
Trigger event on fault
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 72
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Bit
8
Function
VOUT_OV
7
IOUT_OC
6
2
CATASTROFIC
FAULT
VOUT Under Voltage
Fault
Over Output Power
Fault
Current Sharing
Unbalance Warning
VIN OV Fault
VIN Over Voltage Fault
1
VIN UV Fault
VIN Under Voltage Fault
0
Over Temperature
Fault
Over Temperature Fault
5
4
3
30 (42)
No.
Description
Rev
28701-BMR481 revF
May 2022
B
© Flex
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Do not trigger on fault
Trigger event on fault
Do not trigger on fault
Trigger event on fault
Do not trigger on fault
Trigger event on fault
Do not trigger on fault
Trigger event on fault
Do not trigger on fault
Trigger event on fault
Do not trigger on fault
Trigger event on fault
Do not trigger on fault
Trigger event on fault
Do not trigger on fault
Trigger event on fault
Do not trigger on fault
Trigger event on fault
MFR_PROTECT_DEFAULT (0xFE2E)
Description: Protects non volatile memory from writing by inhibiting commands STORE_DEFAULT_ALL and
MFR_STORE_MAP. In case, the PMB_ALRT# signal is asserted and “other ML flag” bit is STATUS_CML register is set. 0x00 =
Unprotected; 0x01 = Protected.
Bit
0
Description
[7:1]: Don't Care [0]: 0b0 = Unprotected; 0b1 = Protected
Value
0
1
Description
Unprotected
Protected
MFR_POUT_THREAD (0xFE2F)
Description: When sent, stops the computation started with MFR_START_THREAD and returns the total energy delivered in the
programmed time (max 1GW).
Bit
31:0
Description
LSB weight is given by System Register IOUT_EXP.
Format
Integer
Unsigned
Unit
Wms
MFR_PMBUSCFG_REVISION (0xFE30)
Description: Can be used for user/custom data.
Bit
15:0
Description
Can be used for user/custom data.
Format
Byte Array
MFR_PMBUSCFG_TIMESTAMP (0xFE31)
Description: Contains product number and revision information. Example: For product number BMR 481 0021/031B R2C the
fields will be: BMR number = 4810021031. Preliminary revision = Not = 0. Product revision number = 2. Product revision letter =
C.
Bit
63:24
22:16
15:8
7:0
Function
BMR number
Product
revision
number
Product
revision letter
Configuration
revision
Description
Number 1-999 9999 999.
Number 1-127
Format
Integer Unsigned
Integer Unsigned
Letter ASCII coded
ASCII
Letter ASCII coded
ASCII
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 73
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Bit
23
Function
Preliminary revision
31 (42)
No.
Rev
28701-BMR481 revF
B
May 2022
© Flex
Description
0=Non-preliminary revision (e.g. R1A),
1=Preliminary revision (e.g. P1A)
Value
0
1
Description
Non-preliminary revision
(e.g. R1A)
Preliminary revision (e.g.
P1A)
MFR_PEAK_FAULT_RESPONSE (0xFE32)
Description: Used to configure how to respond to a peak fault read through VSRMON pin. When enabled, fault is set if
VSRMON pin > 3.045V.
Bit
7:0
Description
Describes the device interruption operation. For all
modes set by bits [7:6], the device pulls SALERT
low and sets the related fault bit in the status
registers. Only 0x00 (Fault Ignored) and 0x80
(Latched) are implemented.
Value
0x00
Function
Ignore Fault
0x80
Latch
Description
Continue operation without
interruption.
Immediate and definite
shutdown of output voltage until
fault is cleared and the output
voltage is re-enabled.
MFR_PMBUSCFG_USERID (0xFE33)
Description: Can be used for user/custom data.
Bit
15:0
Description
Can be used for user/custom data.
Format
Byte Array
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 74
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
32 (42)
No.
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Rev
28701-BMR481 revF
May 2022
B
© Flex
System Registers Details
CURRENT_SHARING_RESET (0xA408)
Bit
Function
Description
5:0
Activation
Activation threshold for current sharing reset. 0x00=126mV, 0x01=124mV,
threshold
0x02=122mV, ... , 0x26=50 mV, ... , 0x3D=4mV, 0x3E=2mV, 0x3F=0 mV.
Bit
7
Function
Enable current
sharing Reset
6
Correction
division
Description
For resonant mode only. Enable
Current sharing Reset. Needed in
case of heavy load transient
release to suddenly reduce the
TSTART signal delay vs PWMx, in
order to avoid secondary phases
overvoltage. Adjusts the current
sharing correction (dividing its
correction /2 or /4) when the
current sharing error exceeds a
programmable threshold in order
to optimize load release.
Dividing correction for current
sharing reset.
HIGH_CURR_PROT_EN (0xA40B)
Bit
Function
Description
7
Add 12.5 ns to Adds 12.5 ns to the base Tshift
base Tshift
correction set by
correction
MFR_T_START_PH_SHIFT_DEL
TA_DELAY[35:31].
6
Add 12.5 ns to Adds 12.5 ns to the base Tshift
base Tshift
set by
MFR_T_START_PH_SHIFT_DEL
TA_DELAY[8:0]. Cannot be 0 (do
not add 12.5 ns) in Resonant
application if NCHECKS = 0x00.
Cannot be 1 (add 12.5 ns) in
NonResonant PSFB if
TPHASE_SHIFT = 0nSec or
25nSec.
5
Enable one
GAIN_REDU_1PH_EN. Reduces
Phase gain
by 1/2 the control loop gain when
reduction
working in single phase.
4
Enable soft
GAIN_REDU_SS_EN. Reduces
start gain
by 1/2 the control loop gain during
reduction
SoftStart.
3
Enable TGB
hysteresis
2
Current
Enables/disables current sharing
sharing
correction to be memorized when
correction
shedding phases. Reserved, set
storage.
to 0x01 (not stored).
1
AVSBus
0b0: EXP = -2; 0b1: EXP = -1
current
monitor
0
Enable High
Reserved, set to 0 (disabled).
Current
Protection
AVS_CONFIG (0xA40D)
Format
Byte Array
Value
0
1
Function
Description
Disable
Enabled
0
1
Divide with 2
Divide with 4
Divide with 2.
Divide with 4.
Value
0
1
Function
Description
Do not add 12.5 ns
Add 12.5 ns
0
1
Do not add 12.5 ns
Add 12.5 ns
0
1
Disable
Enabled
0
1
Disable
Enabled
0
1
0
Disable
Enabled
1
0
1
0
1
Correction
stored
Correction not
stored
EXP = -2
EXP = -1
EXP = -2
EXP = -1
Disable
Enabled
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 75
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Bit
3
Function
SDATA
release
method
2
Do not
produce
response to
wrong address
1
Do not
produce status
response
0
Do not
produce
interrupt over
data line
Description
Controls when SDATA is released
(open) at the end of a frame.
0x00: As per protocol at CLK edge
(rising). 0x01: Data line release
1/2 CLK in advance (CLK falling
edge).
Controls the response to
command with address that
doesn’t match VRM address.
0x00: Response is produced;
0x01: No Response.
Controls the production of status
response frame and response to
broadcast commands. 0x00:
Response is produced; 0x01: No
Response.
Controls interrupt produced from
the interface in case of OC OT on
DAT line of the interface. 0x00:
Interrupt is produced over data
line; 0x01: No interrupt is
produced.
HIZ_HALFB_SYMMETRIC (0xA418)
Bit
Function
Description
5
SFAS
Current reading Chopper
displacement
Amplifiers Control. Configures
which phase shift is applied once
enabled by SFAS. Reserved, set
to 0x01.
4
SFAS enable
Current reading Chopper
Amplifiers Control. Enables phase
shifting between the clock of the
six chopper amplifiers. Reserved,
set to 0x01.
3
HiZ mode for
PWM
Value
0
1
1
0
Symmetric
mode
Bridge
functionality
Rev
28701-BMR481 revF
B
Function
At CLK edge
(per protocol)
1/2 CLK in
advance
Description
Disable
Enabled
0
1
Disable
Enabled
0
1
Disable
Enabled
Value
0
1
Function
12.5 ns
25 ns
0
1
0
0
1
0
1
0
May 2022
© Flex
0
1
1
2
33 (42)
No.
Description
_
_
Disabled
Enabled
PWMX/PWMY
never HiZ
PWMX/PWMY
HiZ @ no
operation
Asymmetric
Symmetric
Full bridge
Half bridge
Soft-off
_
_
_
_
_
_
Use the configured fall time
(slew rate).
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 76
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Bit
Function
Immediate
(HiZ) or softoff
34 (42)
No.
Description
When set, immediate off (HiZ) is
used rather than soft-off when the
output voltage is disabled. When
set, also forces immediate off for
all protection shutdowns.
Because, in some cases, even if
the immediate OFF is configured
by OPERATION, the device is
defaulting the behavior to soft-off.
Vout OVP and OV peak
protections by default always
make a soft-off even if the
OPERATION configures
immediate OFF. This removes
these default; it overrides and
forces a real HiZ when stopping
the operations after a FAULT
event. For Vin UV/OV, Vout UV,
Iout OC, over power and over
temperature protections
immediate off (HiZ) is always used
and this bit has no impact.
CTRL_PFM_ENA_PS (0xB006)
Bit
Description
1:0
Enable the PFM working mode vs power state.
Rev
28701-BMR481 revF
B
© Flex
Value
1
Function
Immediate off
Description
Turn off the output and stop
transferring energy to the output
as fast as possible.
Value
00
Function
PFM enabled
in any PS
PFM enabled
in PS01-03
PFM enabled
in PS02-03
PFM disabled
Description
01
10
11
DPM_HYSTERESIS (0xB007)
Bit
Description
7:0
Used to define the hysteresis for Phase Shedding. DPM_OFFSET may optimize the
hysteresis settings. LSB weight is given by System Register IOUT_EXP.
DVID_SR_FAST_STEP (0xB00C)
Bit
Description
5:0
Programs the [# of 25nSec] to step VOUT by 5mV.
This setting actively drives the reference slew. dV/dt
= 5mV / (SR_FAST_STEP * 25nSec) Actual fast
slew rate (mV/us) = 200 /
DVID_SR_FAST_STEP[5:0]. [7:6]: Don't Care [5:0]:
SR_FAST_STEP. Values accepted from 0x01 to
0x3F. If 0x00, wraps to 0x3F.
May 2022
Value
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
Function
200 mV/us
100 mV/us
66.67 mV/us
50.00 mV/us
40.00 mV/us
33.33 mV/us
28.57 mV/us
25.00 mV/us
22.22 mV/us
20.00 mV/us
18.18 mV/us
16.67 mV/us
15.38 mV/us
14.29 mV/us
13.33 mV/us
12.50 mV/us
11.76 mV/us
11.11 mV/us
10.53 mV/us
10.00 mV/us
Description
Format
Fixed Point
Unsigned
Unit
A
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 77
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Bit
35 (42)
No.
Description
DVID_SR_SLOW_STEP (0xB00D)
Bit
Description
5:0
Programs the [# of 25nSec] to step VOUT by 5mV.
This setting actively drives the reference slew. Data
computed over
MFR_SVID_SLOW_SR_SELECTOR. Actual slow
slew rate (mV/us) = FRACTION x 200 /
DVID_SR_SLOW_STEP[5:0] where FRACTION = 2
x MFR_SVID_SLOW_SR_SELECTOR[3:0]. [7:6]:
Don't Care. [5:0]: SR_SLOW_STEP. Values
accepted from 0x01 to 0x3F. If 0x00, wraps to 0x3F.
Rev
28701-BMR481 revF
B
© Flex
Value
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
Function
9.52 mV/us
9.09 mV/us
8.70 mV/us
8.33 mV/us
8.00 mV/us
7.69 mV/us
7.41 mV/us
7.14 mV/us
6.90 mV/us
6.67 mV/us
6.45 mV/us
6.25 mV/us
6.06 mV/us
5.88 mV/us
5.71 mV/us
5.56 mV/us
5.41 mV/us
5.26 mV/us
5.13 mV/us
5.00 mV/us
4.88 mV/us
4.76 mV/us
4.65 mV/us
4.55 mV/us
4.44 mV/us
4.35 mV/us
4.26 mV/us
4.17 mV/us
4.08 mV/us
4.00 mV/us
3.92 mV/us
3.85 mV/us
3.77 mV/us
3.70 mV/us
3.64 mV/us
3.57 mV/us
3.51 mV/us
3.45 mV/us
3.39 mV/us
3.33 mV/us
3.28 mV/us
3.23 mV/us
3.17 mV/us
Description
Value
0x01
Function
FRACTION x
200 mV/us
FRACTION x
100 mV/us
FRACTION x
66.67 mV/us
FRACTION x
50.00 mV/us
FRACTION x
40.00 mV/us
FRACTION x
33.33 mV/us
FRACTION x
28.57 mV/us
Description
0x02
0x03
0x04
0x05
0x06
0x07
May 2022
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 78
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Bit
Description
36 (42)
No.
Value
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
Rev
28701-BMR481 revF
B
© Flex
Function
FRACTION x
25.00 mV/us
FRACTION x
22.22 mV/us
FRACTION x
20.00 mV/us
FRACTION x
18.18 mV/us
FRACTION x
16.67 mV/us
FRACTION x
15.38 mV/us
FRACTION x
14.29 mV/us
FRACTION x
13.33 mV/us
FRACTION x
12.50 mV/us
FRACTION x
11.76 mV/us
FRACTION x
11.11 mV/us
FRACTION x
10.53 mV/us
FRACTION x
10.00 mV/us
FRACTION x
9.52 mV/us
FRACTION x
9.09 mV/us
FRACTION x
8.70 mV/us
FRACTION x
8.33 mV/us
FRACTION x
8.00 mV/us
FRACTION x
7.69 mV/us
FRACTION x
7.41 mV/us
FRACTION x
7.14 mV/us
FRACTION x
6.90 mV/us
FRACTION x
6.67 mV/us
FRACTION x
6.45 mV/us
FRACTION x
6.25 mV/us
FRACTION x
6.06 mV/us
FRACTION x
5.88 mV/us
FRACTION x
5.71 mV/us
FRACTION x
5.56 mV/us
FRACTION x
5.41 mV/us
Description
May 2022
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 79
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Bit
Description
37 (42)
No.
Value
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
Rev
28701-BMR481 revF
B
May 2022
© Flex
Function
FRACTION x
5.26 mV/us
FRACTION x
5.13 mV/us
FRACTION x
5.00 mV/us
FRACTION x
4.88 mV/us
FRACTION x
4.76 mV/us
FRACTION x
4.65 mV/us
FRACTION x
4.55 mV/us
FRACTION x
4.44 mV/us
FRACTION x
4.35 mV/us
FRACTION x
4.26 mV/us
FRACTION x
4.17 mV/us
FRACTION x
4.08 mV/us
FRACTION x
4.00 mV/us
FRACTION x
3.92 mV/us
FRACTION x
3.85 mV/us
FRACTION x
3.77 mV/us
FRACTION x
3.70 mV/us
FRACTION x
3.64 mV/us
FRACTION x
3.57 mV/us
FRACTION x
3.51 mV/us
FRACTION x
3.45 mV/us
FRACTION x
3.39 mV/us
FRACTION x
3.33 mV/us
FRACTION x
3.28 mV/us
FRACTION x
3.23 mV/us
FRACTION x
3.17 mV/us
Description
DVID_VAR_OFFSET_PARAM (0xB00E)
Bit
Function
Description
47:42 RISE_FAST
Offset can be added to the reference to compensate for the apparent
offset
Droop generated by dV/dt. Offset are expressed in # of VID_Step. Signed
Integer. Offset [+/- # of 5mV Steps].
41:36 RISE_SLOW
Offset can be added to the reference to compensate for the apparent
offset
Droop generated by dV/dt. Offset are expressed in # of VID_Step. Signed
Integer. Offset [+/- # of 5mV Steps].
Format
Integer Signed
Integer Signed
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 80
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Bit
35:30
Function
FALL_FAST
offset
29:24
FALL_SLOW
offset
23:10
Offset
expiration
TauDVID
OC mask after
DVID ends
9:0
Rev
28701-BMR481 revF
B
Description
Offset can be added to the reference to compensate for the apparent
Droop generated by dV/dt. Offset are expressed in # of VID_Step. Signed
Integer. Offset [+/- # of 5mV Steps].
Offset can be added to the reference to compensate for the apparent
Droop generated by dV/dt. Offset are expressed in # of VID_Step. Signed
Integer. Offset [+/- # of 5mV Steps].
Offset application/removal time constant. LP_CONST = (25 * 2^14) / (25 +
TauDVID[nSec]). [# of non-linear steps -> value[ns]= 25 *(1(LP_CONST/2^14)) / (LP_CONST/2^14)].
[9..0] = OCP_TAU = (TOCP-25nSec) / 100nSec. OC Disable TOCP after
DVID ends. [# of 100nSec steps +25ns internal offset].
THERMAL_GAIN (0xB01A)
Bit
Description
7:0
Used to set T_COMP variable for Thermal Compensation of output current sense. T_COMP
makes an adjustment of the correction factor that is ideal for copper, according to: Iinfo_TC =
Iinfo x Kcorr = Iinfo x 1 / (1 + alfa x deltaT_DCR) = Iinfo x 1 / (1 + alfa x deltaT_NTC x
T_COMP / 128) where alfa = 0.0039 and deltaT_NTC is calculated difference from Tmin,
given by TEL_NTC_MAP_Q6. Thus, T_COMP is used to compensate for the temp difference
between NTC-resistor and output inductor DCR. T_COMP = 128 means ideal correction alfa
is used. Note that Kcorr must always be in the range 0.67 to 1.0, which limits the maximum
deltaT_NTC that can be handled.
TEL_IOUT_FSR (0xB01B)
Bit
Description
8:0
Defines the READ_IOUT monitoring ADC Full scale. Shall be set to match the peak OCP
limit as defined by MFR_IMON. LSB weight is given by System Register IOUT_EXP.
TEL_OFFSET_VIN (0xB027)
Bit
Function
Description
10
Sign
1 = Positive 0 = Negative
Number of
0.125V steps
VSRMON ADC: Used to define the Offset correction for VIN monitoring
over VSRMON when Opto Mode is Enabled.
TEL_GAIN_IMON (0xB029)
Bit
Description
7:0
Sets the gain correction to be applied to IMON reading (both PMBus and CPU-Link).
Computed at controller startup as TEL_GAIN_IMON_RAM adjusted per trimming calibration.
Ranges linearly from 0 (0x00) to 2 (0xFF). Note. If modified, when MFR_STORE_MAP is
issued, IC automatically stores into TEL_GAIN_IMON_RAM the RAW value adjusted per
trimming calibration.
SVI_ADDITIONAL_OFFSET (0xB02B)
Bit
Function
Description
1:0
DPM # of
0x01 = NCELL=1 through 0x06 = NCELL=6. Other combinations are not
phases PS2
supported. Configures the minimum number of operating phases in PS02.
Bit
7
Function
Description
Value
0
May 2022
© Flex
TEL_GAIN_VIN (0xB018)
Bit
Description
7:0
VSRMON ADC: Used to define the Gain correction for VIN monitoring over VSRMON when
Opto Mode is Enabled. Ranges linearly from 0 (0x00) to 2 (0xFF). 0x80 = Gain = 1 shall be
used for a 1/40 divider, which is the recommended configuration. VSRMON ADC range is 0
to 3.2V and VSRMON pin has an internal 10k pull-down resistor, thus a 1/40 divider is
achieved by a 390k resistance to VIN.
9:0
38 (42)
No.
Function
Format
Integer Signed
Integer Signed
Integer Unsigned
Integer Unsigned
Format
Integer Unsigned
Format
Fixed Point
Unsigned
Format
Fixed Point
Unsigned
Unit
A
Format
Integer
Unsigned
Integer
Unsigned
Unit
V
Format
Fixed Point
Unsigned
Format
Integer Unsigned
Description
Disable hiccup mode
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 81
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Bit
Function
Enable hiccup
mode
6
IMON divider
@ dynamic
VID
5:4
IMON divider
@ soft start
3
Enable soft
bias current
sense
39 (42)
No.
Description
Enable hiccup fault response
mode. When enabled, after a fault
occurred, the controller reattempts to startup Vout after 1
mSec. When enabled, the hiccup
fault response mode applies for
the fault types that are enabled in
MFR_FAULT_CONFIG. After a
restart due to hiccup, the fault flag
set in STATUS_WORD will be
cleared.
IMON divider in dynamic VID
condition. Delivers reduced IMON
current to the IMON resistor to
prevent from false OC being trip.
IMON divider in soft start
transitions. Delivers reduced
IMON current to the IMON resistor
to prevent from false OC being
trip.
Enable soft bias to allow current
sense below Vout 0.7V. Prevent
damage at startup with short
circuit for full bridge. Optimizes
current reading amplifier biasing
at low output voltages preventing
saturation. Reserved, need to be
0b1 (enabled).
VIN_FEED_FWD_SOURCE (0xB038)
Bit
Description
0
Used to define which input to be used for VIN
FeedForward Compensation. 0x00 = Uses data
from PuC. 0x01 = Uses data from VSRMON at
secondary. Other combinations are not supported.
Rev
28701-BMR481 revF
B
© Flex
Value
1
Function
Description
Enable hiccup mode
0
1
IMON/2
IMON/4
Divide by 2.
Divide by 4.
00
01
10
11
IMON
IMON/2
IMON/4
IMON/8
Divide by 1.
Divide by 2.
Divide by 4.
Divide by 8.
0
1
Disable
Enable
Value
00
01
Function
PuC
VSRMON at
secondary
Description
Value
00
01
Function
PuC
VSRMON at
secondary
Description
IOUT_VR125_PERC_EN (0xB03C)
Bit
Description
0
Used to define whether the IOUT reporting on
reg15h is to be in percentage of ICCMAX (given by
MFR_SVID_ICCMAX) or absolute value in
Amperes.
Value
0
1
Function
Absolute in [A]
% of ICCMAX
Description
VR13_TIME_FRAME (0xB040)
Bit
Description
0
Used to define averaging interval for VR1xx IMON
reporting register. Update interval is always
100uSec while averaging can be programmed.
Value
0
Function
Averaging on
200 us
Averaging on
100 us
Description
VIN_MONITORING_SOURCE (0xB039)
Bit
Description
0
Used to define which input to be used for VIN
monitoring and Protection between PuC and
VSRMON. VSRMON needs to be further
configured. 0x00 = Uses data from PuC. 0x01 =
Uses data from VSRMON at secondary. Other
combinations are not supported.
CTRL_VERR_CLAMP (0xB041)
May 2022
1
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 82
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Bit
5:0
Rev
28701-BMR481 revF
B
Description
When the voltage regulation error increases above the “Unload” threshold, integrator stops to
limit the overshoot at load release. LSB = 2mV. Error clamp threshold = 2mV * (63 - set
value). Max 126mV (0x01). Set 128mV (0x00) to disable function.
TGB_CONFIG (0xB046)
Bit
Function
7:2
TGB/NLR
Load
Threshold
Function
TGB/NLR
Load Mode
Value
0
1
Value
00
01
10
11
Function
Disabled
Enabled when
# of phases >=
2
Enabled
Enabled with
2x threshold
when # of
phases=1
Function
Virtual Droop
Timeframe
Description
Duration of Virtual Droop. Expires
after this time has elapsed.
1:0
Virtual Droop
Mode
Virtual Droop slows the load
transient response in order to
keep the control loop (PID) in
linear region, avoiding control loop
saturation. Typically used in
applications without voltage
positioning (droop) since it adds a
virtual voltage positioning. Virtual
Droop reduces the regulation error
(when overcoming the set
threshold) for the programmed
timeframe. Enabling Virtual Droop
provides a load transient response
worse than without Virtual Droop
but it ensures a better response at
high frequency load transients.
Value
00
01
10
11
00
01
10
11
Function
0.8 us
1.6 us
2.4 us
3.2 us
Disabled
Enabled for
load release
Enabled for
load apply +
release
Enabled for
load apply +
release with
half timeframe
Unit
mV
Format
Fixed Point
Unsigned
Unit
mV
Format
Fixed Point
Unsigned
Unit
mV
Description
VDROOP_CONFIG (0xB047)
Bit
Function
Description
5:2
Virtual Droop
Activation threshold over Control Error (+/-). LSB = 4mV.
Error
Threshold
Bit
1:0
Format
Fixed Point
Unsigned
Description
DPM Protection Enabled
- # of phases reset in
load transient
DPM Protection Disabled
- # of phases NOT reset
in load transient
Description
LSB = 2mV, max 126mV (0b111111)
Description
Used to configure Transient Gain
Boost to improve transient
response. When the voltage
regulation error decreases below
the “Load” threshold, the control
loop gain is doubled to limit the
undershoot during load
application.
May 2022
© Flex
DISABLE_DPM_PROT (0xB044)
Bit
Description
0
Used to disable DPM Protection that, during ACLL, increases the # of phases
by 1 if instantaneous FSW gets greater than averaged FSW_AVG.
FSW_AVG set by MFR_FSWITCH_PROTECT_COEFF in Resonant Loop
while in Non Resonant Loop the comparison is made over the nominal FSW
set. Trigger threshold changes with the number of active phases: # of active
phases = 1 => Fthreshld = 2.00*FSW_AVG. # of active phases = 2 =>
Fthreshld = 1.50*FSW_AVG. # of active phases = 3 => Fthreshld =
1.33*FSW_AVG. # of active phases = 4 => Fthreshld = 1.25*FSW_AVG. # of
active phases = 5 => Fthreshld = 1.20*FSW_AVG.
Bit
1:0
40 (42)
No.
Description
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
41 (42)
No.
Technical
Specification 83
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Rev
28701-BMR481 revF
B
© Flex
TON_RED_CONFIG (0xB04A)
Bit
Function
Description
1:0
ZCDM offset
Used to set an offset on ZCD to optimize PFM (not for Phase 1 which uses
ZCD1_OFFSET). Offset in [uA], how this is translated into [A] on inductor
ripple depends on the real application implemented. 0x03 = 2.4uA ; 0x02 =
4uA; 0x01 = 5.6uA; 0x00 = 7.2uA. Other combinations are not supported.
Bit
7
6
Function
Boost on
Phase number
change
Enable all
phases at low
Vin
5
Force
VR_READY
3
Prevent spec
patterns
2
Enable all
phases Vin
hysteresis
Description
Reserved, disable/set to 0.
Value
0
If enabled, all phases will be
turned on if duty cycle is high and
input voltage is lower than the
threshold
(VOLTAGE_DUTY_ENABLE) set
by
MFR_DUTY_PARAMETER[23:14]
. This will improve transient
response at low input voltage.
Only for resonant topology.
When set/enabled, VRREADY = 0
regardless of regulation. Reserved
bit #4 need to be set to 0b.
NO_PINTA: Prevents issuing
special patterns in case of primary
driver replacement.
Adds 1V hysteresis on the All
phases enable activation Vin
threshold. See
TON_RED_CONFIG[6] and
MFR_DUTY_PARAMETER[23:14]
. Only for resonant topology.
0
1
Disabled
Enabled
0
1
Disabled
Enabled
1
Function
Disabled
Enabled
0
1
Value
00
01
VR_READY_FAST_DISABLE (0xB051)
Bit
Description
0
Used to allow immediate VR_RDY signal deassertion in case of disable from EN pin. If not set,
VR_RDY may be delayed from EN de-assertion up
to 400 us.
MULTIFUNCTION_PIN_MUX (0xB057)
Value
00
01
Format
Fixed Point
Unsigned
Description
Disabled
Enabled
Disabled
Enabled
EN_DROOP_START (0xB04B)
Bit
Description
0
Enables fake droop effect at startup to keep Control-ADC Error negative to
avoid bumps on VOUT at start-up. Other combinations than 0x00 and 0x01
are not supported.
CS_OVERFLOW_DISABLE_IRQ (0xB04E)
Bit
Description
0
Used to disable current sharing overflow fault. 0x00
= Current Sharing FAULT Enable. 0x01 = Current
Sharing FAULT Disable. Other combinations are not
supported.
May 2022
Value
0
1
Description
Disable startup droop
Enable startup droop
Function
Enable
Current
Sharing
FAULT
Disable
Current
Sharing
FAULT
Description
Function
Disable fast
de-assertion
Enable fast
de-assertion
Description
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
Technical
Specification 84
6/1301-BMR 481
Uen
karalars Andreas Larsson
Approved (Document resp)
Checked
Date
BMR481
Direct Conversion
dalgedmoseries
Gary Edmonds
2019-06-20
Input 40-60 V, Output 0.5 V to 1.35 V up to 70 A
Bit
2
Function
Enable IMON
filtering
1:0
Configure
droop effect at
startup
42 (42)
No.
Description
Enable additional analog filtering
on IMON (800nSec time constant)
to prevent from false OC tripping
and to reduce overall ripple noise.
Should always be enabled.
Configure droop effect at startup,
see EN_DROOP_START.
Rev
28701-BMR481 revF
B
May 2022
© Flex
Value
1
Function
Enable
Description
Enable IMON filtering
00
Regulation
error only
(standard)
Regulation
error and
Droop
Regulation
error and 2 x
Droop
Regulation
error and 3 x
Droop
Use regulation error only.
01
10
11
Use regulation error + droop
value by VOUT_DROOP.
Use regulation error + 2 x droop
value by VOUT_DROOP
Use regulation error + 3 x droop
value by VOUT_DROOP
MONITOR_OFFSET (0xB05E)
Bit
Description
4:0
Vout monitoring offset applied to READ_VOUT (not applied to MFR_READ_VOUT). LSB
depends on the table used (10mV or 5mV by VR_TAB_RAIL). Signed. It is an additional
contribute to MFR_VOUT_CAL_OFFSET which is usually tuned to compensate internal ADC
VSS (0.5V).
Format
Fixed Point
Signed
Unit
mV
EXTRA_OFFSET (0xB063)
Bit
Description
7:0
Additional offset for SVID and AVSBus domain (does not apply to PMBus) In AVSBus mode,
if applied, need to be in tracking with MFR_VOUT_TRIM. # of VID LSB to add to setpoint
(unsigned, always positive).
Format
Fixed Point
Unsigned
Unit
mV
DPM_OFFSET (0xB064)
Bit
Description
7:0
DPM threshold offset. Always Negative. Used to offset phase shedding thresholds in order to
compensate for each phase current ripple without playing with DPM_HYSTERESYS. LSB
weight based on IOUT_EXP and HC support enabled or disabled.
Format
Fixed Point
Unsigned
Unit
A
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