Public
Flex internal
TABLE
OF CONTENTS
PRODUCT
SPECIFICATION
Prepared (also
(also subject
subject responsible
responsible ifif other)
other)
Prepared
JidgezouWang
George Zou
Marshall
Approved
Approved
1 (4)
No.
No.
Checked
Checked
BMR467 series PoL Regulators
Input 7.5 - 14 V, Output up to 120 A / 216 W
00152-BMR467 Uen
1/1301-BMR467
Technical
Date
Date
Rev
Rev
2021-03-08
2017-11-24
Specification
Reference
Reference
28701-BMR 467 Rev E
B
C
March 2021
© Flex
Key Features
• Small Package
Laydown: 50.8 x 19.05 x 10.4 mm (2.0 x 0.75 x 0.41 in)
SIP: 50.8 x 8.2 x 19.05 mm (2.0 x 0.32 x 0.75 in)
• Control loop with fast load transient response
• 0.6 V - 1.8 V output voltage range
• High maximum output current, 120 A
• Current sharing up to 4 modules, 480 A
• High efficiency, typ. 93.2% at 12 Vin, 1.8 Vout, half load
• Configuration and monitoring via PMBus
• Phase synchronization & spreading
• Voltage tracking capability
• Margining up/down
• MTBF 10.49 Mh
General Characteristics
•
•
•
•
•
•
•
•
•
•
•
Configuration support via Flex Power Designer
Monotonic soft-start ramp up
Reduced external output decoupling capacitance
Input under-voltage & over-voltage shutdown
Output over current & over voltage protection
Over temperature protection
Remote control & Power Good pins
Differential sense pins
Voltage setting via pin-strap or PMBus
ISO 9001/14001 certified supplier
Highly automated manufacturing ensures quality
Safety Approvals
Design for Environment
Meets requirements in hightemperature lead-free soldering
processes.
Contents
Ordering Information ................................................................................................................................................... 2
General Information .................................................................................................................................................... 2
Safety Specification .................................................................................................................................................... 3
Internal Circuit Diagram .............................................................................................................................................. 4
Pin Descriptions .......................................................................................................................................................... 5
Typical Application Circuit........................................................................................................................................... 7
Electrical Specification
120 A / 0.6-1.8 V
BMR 467 .............................................12
EMC Specification .....................................................................................................................................................18
Operating Information ................................................................................................................................................22
Thermal Consideration ..............................................................................................................................................29
Mechanical Information..............................................................................................................................................31
Soldering Information.................................................................................................................................................34
Delivery Information ...................................................................................................................................................35
Product Qualification Specification ............................................................................................................................37
Appendix – PMBus Commands .................................................................................................................................38
Flex internal
PRODUCT SPECIFICATION
Prepared (also subject responsible if other)
1/1301-BMR467 Technical
Uen
Marshall Wang
Approved
Checked
BMR467 series PoL Regulators
Input 7.5 - 14 V, Output up to 120 A / 216 W
Product program
BMR 467 n1n210/001n8
Output
0.6-1.8 V, 120 A/216 W
Product number and Packaging
BMR 467 n1n2n3n4/n5n6n7n8
Options
/
n1
n2
n3
n4
Mounting
/
/
Packaging
/
Options
Description
n1
0
2
n6
n7
n8
Horizontal through hole mounted
version (Laydown TH)
Horizontal surface mounted
version (Laydown SMD)
Vertical through hole mounted
version (Single in Line, SIP)
n2
0
1
Open frame
Open frame 5.5mm pin length
n3 n4
10
PMBus and pin strap
n5 n6 n7
001
n8
B
CTRL pin positive logic (active
high)
Antistatic tray of 144 products
(SIP)
Antistatic tape & reel of 130
products (Laydown TH and SMD)
C
2017-11-24
Rev
Specification
Reference
28701-BMR 467 Rev E
C
March 2021
© Flex
The products are compatible with the relevant clauses and
requirements of the RoHS directive 2011/65/EU and have
a maximum concentration value of 0.1% by weight in
homogeneous materials for lead, mercury, hexavalent
chromium, PBB and PBDE and of 0.01% by weight in
homogeneous materials for cadmium.
Exemptions in the RoHS directive utilized in Flex Power
Modules products are found in the Statement of
Compliance document.
/
Configuration file
1
n5
/
Digital interface
Date
Compatibility with RoHS requirements
Ordering Information
Mechanical
2 (4)
No.
Example: Product number BMR 467 0010/001C equals a through-hole
mounted, open frame, PMBus and analog pin strap, positive RC logic,
standard configuration variant, package tape&reel.
Flex Power Modules fulfills and will continuously fulfill all its
obligations under regulation (EC) No 1907/2006
concerning the registration, evaluation, authorization and
restriction of chemicals (REACH) as they enter into force
and is through product materials declarations preparing for
the obligations to communicate information on substances
in the products.
Quality Statement
The products are designed and manufactured in an
industrial environment where quality systems and methods
like ISO 9000, Six Sigma, and SPC are intensively in use
to boost the continuous improvements strategy. Infant
mortality or early failures in the products are screened out
and they are subjected to an ATE-based final test.
Conservative design rules, design reviews and product
qualifications, plus the high competence of an engaged
work force, contribute to the high quality of the products.
Warranty
Warranty period and conditions are defined in Flex Power
Modules General Terms and Conditions of Sale.
Limitation of Liability
General Information
Reliability
The failure rate () and mean time between failures
(MTBF= 1/) is calculated at max output power and an
operating ambient temperature (TA) of +40°C. Flex Power
Modules uses Telcordia SR-332 Issue 2 Method 1 to
calculate the mean steady-state failure rate and standard
deviation ().
Telcordia SR-332 Issue 3 also provides techniques to
estimate the upper confidence levels of failure rates based
on the mean and standard deviation.
Mean steady-state
Std. deviation,
failure
rate,
95 nFailures/h
7.6 nFailures/h
MTBF (mean value) for the BMR467 series = 10.49 Mh.
MTBF at 90% confidence level = 9.51 Mh
Flex Power Modules does not make any other warranties,
expressed or implied including any warranty of
merchantability or fitness for a particular purpose
(including, but not limited to, use in life support
applications, where malfunctions of product can cause
injury to a person’s health or life).
© Flex 2021
The information and specifications in this technical
specification is believed to be correct at the time of
publication. However, no liability is accepted for
inaccuracies, printing errors or for any consequences
thereof. Flex reserves the right to change the
contents of this technical specification at any time without
prior notice.
Flex internal
PRODUCT SPECIFICATION
Prepared (also subject responsible if other)
Marshall Wang
Approved
Checked
BMR467 series PoL Regulators
Input 7.5 - 14 V, Output up to 120 A / 216 W
Safety Specification
General information
Flex Power Modules DC/DC converters and DC/DC
regulators are designed in accordance with the safety
standards IEC 60950-1, EN 60950-1 and UL 60950-1
Safety of Information Technology Equipment.
IEC/EN/UL 60950-1 contains requirements to prevent injury
or damage due to the following hazards:
•
•
•
•
•
•
3 (4)
No.
Electrical shock
Energy hazards
Fire
Mechanical and heat hazards
Radiation hazards
Chemical hazards
On-board DC/DC converters and DC/DC regulators are
defined as component power supplies. As components
they cannot fully comply with the provisions of any safety
requirements without “conditions of acceptability”.
Clearance between conductors and between conductive
parts of the component power supply and conductors on
the board in the final product must meet the applicable
safety requirements. Certain conditions of acceptability
apply for component power supplies with limited stand-off
(see Mechanical Information and Safety Certificate for
further information). It is the responsibility of the installer to
ensure that the final product housing these components
complies with the requirements of all applicable safety
standards and regulations for the final product.
Component power supplies for general use should comply
with the requirements in IEC/EN/UL 60950-1 Safety of
Information Technology Equipment. Product related
standards, e.g. IEEE 802.3af Power over Ethernet, and
ETS-300132-2 Power interface at the input to telecom
equipment, operated by direct current (dc) are based on
IEC/EN/UL 60950-1 with regards to safety.
Flex Power Modules DC/DC converters, Power interface
modules and DC/DC regulators are UL 60950-1 recognized
and certified in accordance with EN 60950-1. The
flammability rating for all construction parts of the products
meet requirements for V-0 class material according to
IEC 60695-11-10, Fire hazard testing, test flames – 50 W
horizontal and vertical flame test methods.
Non - isolated DC/DC regulators
The DC/DC regulator output is SELV if the input source
meets the requirements for SELV circuits according to
IEC/EN/UL 60950-1.
1/1301-BMR467 Technical
Uen
Date
2017-11-24
Rev
Specification
Reference
28701-BMR 467 Rev E
C
© Flex
March 2021
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
2/1301-BMR 467
Uen
Technical
Specification
JIDDASUN Dan Sun
Approved (Document resp)
BMR467
series PoL Regulators
Lisa
Li
Checked
Date
Dan Yue
8/7/2020
Input 7.5 - 14 V, Output up to 120 A / 216 W
Internal Circuit Diagram
1 (16)
No.
Rev
28701-BMR 467 Rev E
B
© Flex
March 2021
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
2 (16)
No.
2/1301-BMR 467
Uen
Technical
Specification
JIDDASUN Dan Sun
Approved (Document resp)
BMR467
series PoL Regulators
Lisa
Li
Checked
Date
Dan Yue
8/7/2020
Input 7.5 - 14 V, Output up to 120 A / 216 W
Rev
28701-BMR 467 Rev E
B
March 2021
© Flex
Pin Descriptions – SIP version
Pin layout, top view.
Pin
Designation
Type
1A, 1B, 1C, 1D
VIN
Power
Function
Input Voltage
2A, 2B, 2C, 2D
GND
Power
Power Ground
3A, 3B, 3C, 3D
VOUT
Power
Output Voltage
4A
+S
I
Positive sense. Connect to output voltage close to the load.
4B
-S
I
Negative sense. Connect to power ground close to the load.
5A
VSET
I
Output voltage pin strap. Used with external resistor to set the nominal output
voltage.
5B
VTRK
I
Voltage Tracking input. Allows for tracking of output voltage to an external voltage.
6A
SALERT
6B
SDA
I/O
PMBus Data. Data signal for PMBus communication. Requires a pull-up resistor
even when unused.
7A
SCL
I/O
PMBus Clock. Clock for PMBus communication. Requires a pull-up resistor even
when unused.
7B
NC
N/A
Not Connected. See Note 1.
8A
SA
I
PMBus address pin strap. Used with external resistor to assign a unique PMBus
address to the product. May be left open if PMBus is not used.
8B
SYNC
I/O
External switching frequency synchronization input or output. May be left open if
unused.
9A
PG
9B
CTRL
I
10A
GCB
I/O
10B
PREF
Power
O
PMBus Alert. Asserted low when any of the configured protection mechanisms
Open-Drain indicate a fault or a warning.
O
Power Good output. Asserted high when the product is ready to provide regulated
Open-Drain output voltage to the load.
Remote Control. Can be used to enable/disable the output voltage of the product.
May be left open if unused due to internal pull-up.
Group Communication Bus. Used for current sharing, and inter-device
communication.
Pin-strap reference. Ground reference for pin-strap resistors.
Note 1. The BMR 467 is pin to pin compatible with the BMR 465 except pin 7B. The pin 7B in BMR 467 is not connected while in BMR 465 it is used to indicate fault
in parallel operation. In parallel operation, if desired to be compatible with the BMR 465, Pin 7B of the BMR 467 modules have to be connected together in layout.
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
3 (16)
No.
2/1301-BMR 467
Uen
Technical
Specification
JIDDASUN Dan Sun
Approved (Document resp)
BMR467
series PoL Regulators
Lisa
Li
Checked
Date
Dan Yue
8/7/2020
Input 7.5 - 14 V, Output up to 120 A / 216 W
Rev
28701-BMR 467 Rev E
B
March 2021
© Flex
Pin Descriptions – Lay Down versions
Pin layout, top view (component placement for illustration only).
Pin
Designation
Type
1A, 1B, 1C, 1D
VIN
Power
Function
Input Voltage
2A, 2B, 2C, 2D
GND
Power
Power Ground
3A, 3B, 3C, 3D
VOUT
Power
Output Voltage
4A
+S
I
Positive sense. Connect to output voltage close to the load.
4B
-S
I
Negative sense. Connect to power ground close to the load.
5A
VSET
I
Output voltage pin strap. Used with external resistor to set the nominal output
voltage.
5B
VTRK
I
Voltage Tracking input. Allows for tracking of output voltage to an external voltage.
6A
SALERT
6B
SDA
I/O
PMBus Data. Data signal for PMBus communication. Requires a pull-up resistor
even when unused.
7A
SCL
I/O
PMBus Clock. Clock for PMBus communication. Requires a pull-up resistor even
when unused.
7B
NC
N/A
Not Connected. See Note 2.
8A
SA
I
PMBus address pin strap. Used with external resistor to assign a unique PMBus
address to the product. May be left open if PMBus is not used.
8B
SYNC
I/O
External switching frequency synchronization input or output. May be left open if
unused.
9A
PG
9B
CTRL
I
10A
GCB
I/O
10B
PREF
Power
Pin-strap reference. Ground reference for pin-strap resistors.
11, 12
GND
Power
Power Ground. These pins are available only in lay down versions. See Note 2.
O
PMBus Alert. Asserted low when any of the configured protection mechanisms
Open-Drain indicate a fault or a warning.
O
Power Good output. Asserted high when the product is ready to provide regulated
Open-Drain output voltage to the load.
Remote Control. Can be used to enable/disable the output voltage of the product.
May be left open if unused due to internal pull-up.
Group Communication Bus. Used for current sharing, and inter-device
communication.
Note 2. The BMR 467 is pin to pin compatible with the BMR 465 except pin 7B. The pin 7B in BMR 467 is not connected while in BMR 465 it is used to indicate fault
in parallel operation. In parallel operation, if desired to be compatible with the BMR 465, Pin 7B of the BMR 467 modules have to be connected together in layout.
Pins 11 and 12 are not connected in the BMR 465 however they should be connected to the power GND in the BMR 467 case for thermal reasons.
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
2/1301-BMR 467
Uen
Technical
Specification
JIDDASUN Dan Sun
Approved (Document resp)
BMR467
series PoL Regulators
Lisa
Li
Checked
Date
Dan Yue
8/7/2020
Input 7.5 - 14 V, Output up to 120 A / 216 W
Typical Application Circuit
Standalone operation with PMBus communication.
4 (16)
No.
Rev
28701-BMR 467 Rev E
B
© Flex
March 2021
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
2/1301-BMR 467
Uen
Technical
Specification
JIDDASUN Dan Sun
Approved (Document resp)
BMR467
series PoL Regulators
Lisa
Li
Checked
Date
Dan Yue
8/7/2020
Input 7.5 - 14 V, Output up to 120 A / 216 W
Typical Application Circuit – Parallel Operation
Parallel operation.
5 (16)
No.
Rev
28701-BMR 467 Rev E
B
© Flex
March 2021
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
6 (16)
No.
2/1301-BMR 467
Uen
Technical
Specification
JIDDASUN Dan Sun
Approved (Document resp)
BMR467
series PoL Regulators
Lisa
Li
Checked
Date
Dan Yue
8/7/2020
Input 7.5 - 14 V, Output up to 120 A / 216 W
Rev
March 2021
28701-BMR 467 Rev E
B
© Flex
Absolute Maximum Ratings
Characteristics
min
max
Unit
TP1
Operating temperature
-45
typ
125
°C
TS
Storage temperature (Ambient)
-45
125
°C
VI
Input voltage (See Operating Information Section for input and output voltage relations)
-0.3
16
V
Signal I/O voltage
Ground voltage
differential
CTRL, SA, SALERT, SCL, SDA, VSET, SYNC, PG, GCB
-0.3
6
V
-S, PREF, GND
-0.3
0.3
V
Analog pin voltage
VO, +S, VTRK
-0.3
6.5
V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the Electrical Specification section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. See technical paper TP023 for details on how data retention time of the Non-Volatile
Memory (NVM) of the product is affected by high temperature.
Configuration File
This product is designed with a digital control circuit. The control circuit uses a configuration file which determines the functionality and
performance of the product. The Electrical Specification table shows parameter values of functionality and performance with the Standard
configuration, unless otherwise specified. The Standard configuration is designed to fit most application needs. Changes in Standard
configuration might be required to optimize performance in specific application. Note that current sharing operation requires changed
configuration. See application note AN307 for further information.
Common Electrical Specification
This section includes parameter specifications common to all product versions within the product series. Typically these are parameters defined
by the digital controller of the products. In the table below PMBus commands for configurable parameters are written in capital letters.
TP1 = -40 to +95 °C, VI = 7.5 to 14 V, unless otherwise specified under Conditions.
Typical values given at: TP1 = +25 °C, VI = 12 V, max IO, unless otherwise specified under Conditions.
VO defined by pin-strap. Typical values for PMBus configurable parameters are given for standard (default) configuration.
Characteristics
Conditions
min
Switching Frequency
fSW =
1/TSW
TINIT
TONdel_tot
TONdel
TOFFdel
TONrise /
TOFFfall
Switching Frequency Range, Note 3
Switching Frequency Set-point Accuracy
External Sync Pulse Width
Input Clock Frequency Drift Tolerance
Initialization Time
Output voltage
Total On Delay Time
Output voltage
On Delay Time
Output voltage
Off Delay Time
Output voltage
On/Off
Ramp Time
(0-100%-0 of VO)
typ
max
320
PMBus configurable
FREQUENCY_SWITCH
External sync
From VI > ~2.7 V to ready to be enabled
Enable by input voltage
Enable by CTRL pin
Turn on delay duration
Range PMBus configurable
TON_DELAY
Accuracy (actual delay vs set value)
Turn off delay duration, Note 4
Range PMBus configurable
TOFF_DELAY
Accuracy (actual delay vs set value), Note 5
Turn on ramp duration
Turn off ramp duration
Ramp duration range
PMBus configurable
TON_RISE/TOFF_FALL
Unit
kHz
200
640
kHz
-5
150
-10
5
10
%
ns
%
72
ms
67
TINIT + TONdel
TONdel
5
3
ms
250
-0/+2
0
4
ms
ms
250
-0/+2
5
Disabled in standard configuration. Turn off
immediately upon expiration of Turn off delay.
0
ms
100
ms
ms
ms
ms
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
2/1301-BMR 467
Uen
Technical
Specification
JIDDASUN Dan Sun
Approved (Document resp)
BMR467
series PoL Regulators
Lisa
Li
Checked
Date
Dan Yue
8/7/2020
Input 7.5 - 14 V, Output up to 120 A / 216 W
Rev
Characteristics
Conditions
PG threshold
Rising
Falling
PG thresholds range
PMBus configurable
POWER_GOOD_ON
VOUT_UV_FAULT_LIMIT
Power Good , PG
PG delay
PG delay range
From VO reaching target to
PG assertion
PMBus configurable
POWER_GOOD_DELAY
B
© Flex
±250
min
0
Set point accuracy
IUVP response delay
Fault response
IOVP threshold
IOVP threshold range
Input Over Voltage
Protection,
IOVP
Set point accuracy
IOVP response delay
Fault response
UVP threshold
UVP threshold range
Output Voltage
Over/Under Voltage
Protection,
OVP/UVP
0
PMBus configurable
VIN_OV_FAULT_LIMIT
280
100
Shutdown, automatic restart, 280 ms. Note 6
16
Over Current
Protection,
OCP
Note 7
Over Temperature
Protection,
OTP
Position P1
Note 9
OCP threshold
OCP threshold range
Protection delay
Fault response
OTP threshold
OTP threshold range
OTP hysteresis
Fault response
16
1
PMBus configurable
VIN_OV_WARN_LIMIT
0
VIN_OV_FAULT_RESPONSE
PMBus configurable
VOUT_UV_FAULT_LIMIT
8.9
280
100
Shutdown, automatic restart, 280 ms. Note 6
85
0
100
115
PMBus configurable
VOUT_OV_FAULT_LIMIT
100
Set value per phase
PMBus configurable
IOUT_AVG_OC_FAULT_LIMIT
See Note 8
MFR_IOUT_OC_FAULT_RESPONSE
PMBus configurable
OT_FAULT_LIMIT
PMBus configurable
OT_FAULT_RESPONSE
mV
μs
V
V
V
mV
μs
% VO
% VO
% VO
115
% VO
μs
10
VOUT_UV_FAULT_RESPONSE
VOUT_OV_FAULT_RESPONSE
V
V
-280
UVP/OVP response time
Fault response
7.4
7.1
V
V
-280
VIN_UV_FAULT_RESPONSE
ms
V
14
0.5
PMBus configurable
VIN_UV_WARN_LIMIT
OVP threshold
OVP threshold range
5000
6.6
% VO
ms
6.6
PMBus configurable
VIN_UV_FAULT_LIMIT
Unit
% VO
% VO
100
0
IOVP hysteresis
IOVP hysteresis range
max
2
IUVP hysteresis
IUVP hysteresis range
typ
µs
90
85
IUVP threshold
IUVP threshold range
March 2021
28701-BMR 467 Rev E
Ramp time accuracy for standalone
operation (actual ramp time vs set value)
Input Under Voltage
Protection,
IUVP
7 (16)
No.
Shutdown, automatic restart, 280 ms. Note 6
76
0
A
76
5
Shutdown, automatic restart, 280 ms. Note 6
125
-45
125
15
Shutdown, automatic restart, 280 ms. Note 6
A
TSW
C
C
C
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
2/1301-BMR 467
Uen
Technical
Specification
JIDDASUN Dan Sun
Approved (Document resp)
BMR467
series PoL Regulators
Lisa
Li
Checked
Date
Dan Yue
8/7/2020
Input 7.5 - 14 V, Output up to 120 A / 216 W
Characteristics
Conditions
Input voltage
READ_VIN
Output voltage
READ_VOUT
Monitoring Accuracy
Output current
READ_IOUT, Note 10
Temperature
READ_TEMPERATURE_1
TP1 = 25 C, VO = 1.0 V
TP1 = 0 - 95 C, VO = 1.0 V
Position P1, TP3 = 0 - 95 C
VTRK = 5 V
Tracking Input Voltage Range
VTRK pin
Tracking Rise-Time
VTRK pin
Tracking Accuracy
Regulation 100% tracking
VOL
Logic output low signal level
VOH
Logic output high signal level
IOL
IOH
VIL
VIH
Logic output low sink current
Logic output high source current
Logic input low
Logic input high
II_LEAK
Logic leakage current
CI_PIN
Logic pin input capacitance
RI_PU
Logic pin internal pull-up resistance
TBUF
tset
thold
Tlow
Thigh
Supported SMBus Operating
frequency
SMBus Bus free time
SMBus SDA setup time from SCL
SMBus SDA hold time from SCL
SMBus START/STOP condition
setup/hold time from SCL
SCL low period
SCL high period
March 2021
B
© Flex
min
typ
max
Unit
280
mV
-1.25
±1
1.25
% VO
-4
-7
±2.5
±5.0
4
7
A
A
No tolerance, Read value is the actual value
applied by PWM controller.
Tracking Input Bias Current
Current difference between products in a current
sharing group
Supported number of products in a current
sharing group
Rev
28701-BMR 467 Rev E
-280
Duty cycle
READ_DUTY_CYCLE
fSMB
8 (16)
No.
-10
70
0
Steady state operation
-2
5
°C
200
µA
5
V
1
V/ms
2
% VO
Max 2 x READ_IOUT monitoring accuracy
4
SCL, SDA, SYNC, GCB,
SALERT, PG
Sink / source current = 2 mA
SCL, SDA, CTRL, SYNC,
GCB
SCL, SDA, SYNC, SALERT,
PG
SCL, SDA, CTRL, SYNC,
GCB
SCL, SDA, SALERT
CTRL to +5V
GCB to +5V
0.5
2.25
STOP bit to START bit
V
2
2
0.8
mA
mA
V
V
100
nA
2
-100
12
pF
No internal pull-up
10
47
10
V
kΩ
kΩ
400
kHz
1.3
100
300
µs
ns
ns
600
ns
1.3
0.6
µs
µs
Note 3. There are configuration changes to consider when changing the switching frequency. The switching frequency below 320 kHz is not recommended due to
increased ripple current.
Note 4. A default value of 0 ms forces the device to Immediate Off behavior with TOFF_FALL ramp-down setting being ignored.
Note 5. The specified accuracy applies for off delay times larger than 4 ms. When setting 0 ms the actual delay will be 0 ms.
Note 6. Automatic restart ~280 ms after fault if the fault is no longer present. Continuous restart attempts if the fault reappear after restart.
Note 7. The set OCP limit applies per phase. The total OCP limit will be twice the set value. Note that higher OCP threshold than specified may result in damage of
the module at OC fault conditions.
Note 8. TSW is the switching period.
Note 9. See section Over Temperature Protection (OTP).
Note 10. Monitoring Accuracy of output current is optimized for VI = 12 V and VO = 1.0 V.
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
9 (16)
No.
2/1301-BMR 467
Uen
Technical
Specification
JIDDASUN Dan Sun
Approved (Document resp)
BMR467
series PoL Regulators
Lisa
Li
Checked
Date
Dan Yue
8/7/2020
Input 7.5 - 14 V, Output up to 120 A / 216 W
Rev
March 2021
28701-BMR 467 Rev E
B
© Flex
Product Electrical Specification
BMR 467 0010, BMR 467 1010
BMR 467 2010, BMR 467 2110
TP1 = -40 to +95 °C, VI = 7.5 to 14 V, unless otherwise specified under Conditions.
Typical values given at: TP1 = +25 °C, VI = 12.0 V, max IO, unless otherwise specified under Conditions.
VO defined by pin strap. Standard configuration.
Tested with external CIN = 1000 μF/12 mΩ OS-CON + 24 x 10 μF Ceramic, COUT = 10 x 470 μF/5 mΩ POS-CAP + 10 x 100 μF Ceramic.
In the test set-up sense lines are connected directly to output pins on a converter and all the output voltage measurements are made on output
pins.
Characteristics
VI
VO
Conditions
Input voltage
Input voltage slew rate
Output voltage without pin-strap
Output voltage adjustment range
Output voltage adjustment including
PMBus margining
Output voltage set-point resolution
Output voltage accuracy, Note 11
Internal resistance +S/-S to VOUT/GND
+S bias current
-S bias current
Line regulation
IO = max IO
Load regulation
IO = 0 - 100%
VOac
Output ripple & noise
(up to 20 MHz bandwidth)
IO
Ilim
Output current
Current limit threshold
Isc
Short circuit current
50% of max IO
η
Efficiency
IO = max IO
Pd
Power dissipation at max IO
Pli
Input idling
power
PCTRL
CI
CO
Input standby power
Internal input capacitance
Internal output capacitance
IO = 0
Note 11. For VO < 1.0 V accuracy is +/-10 mV.
min
typ
max
Unit
14
6
V
V/ms
0.6
1.8
V
V
0.54
1.98
V
7.5
Monotonic
1.2
±0.025
Including line, load, temp
-1
-100
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
0
130
1
47
20
20
1
1
1
1
1
1
4.5
5.0
7.0
145
RMS, hiccup mode,
VO = 1.0 V, 1.5 mΩ short
12.5
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
VO = 0.6 V
VO = 1.0 V
VO = 1.8 V
Turned off with CTRL-pin
VI = 0 V
VO = 0 V
86.5
90.5
93.2
83.5
88.6
91.9
14.2
15.5
19.0
2.0
2.5
3.5
0.44
279
700
100
% VO
% VO
Ω
µA
µA
mV
mV
mVp-p
120
150
A
A
A
%
%
18.0
19.5
23.5
W
W
W
μF
μF
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
10 (16)
No.
2/1301-BMR 467
Uen
Technical
Specification
JIDDASUN Dan Sun
Approved (Document resp)
BMR467
series PoL Regulators
Lisa
Li
Checked
Date
Dan Yue
8/7/2020
Input 7.5 - 14 V, Output up to 120 A / 216 W
Rev
B
© Flex
Typical Output Characteristics, VO = 0.6 V
BMR 467 0010, BMR 467 1010
BMR 467 2010, BMR 467 2110
Standard configuration unless otherwise specified, TP1 = +25 °C
Efficiency
March 2021
28701-BMR 467 Rev E
Power Dissipation
[%]
[W]
100
21
18
95
90
85
VI
15
7.5 V
12
9.6 V
9
80
12 V
75
14 V
VI
7.5 V
9.6 V
12 V
6
14 V
3
0
70
0
20
40
60
80
100
0
120 [A]
20
40
60
80
100
120 [A]
Efficiency vs. load current and input voltage.
Dissipated power vs. load current and input voltage.
Output Current Derating for SIP version
Output Current Derating for Lay Down versions
[A]
[A]
120
120
100
4.0 m/s
100
4.0 m/s
80
2.0 m/s
80
2.0 m/s
60
1.0 m/s
60
1.0 m/s
40
0.5 m/s
40
0.5 m/s
20
Nat. Conv.
20
Nat. Conv.
0
0
0
20
40
60
80
100
120 [°C]
0
20
40
60
80
100
120 [°C]
Available load current vs. ambient air temperature and airflow at
VI = 12 V.
Available load current vs. ambient air temperature and airflow at
VI = 12 V.
Output Ripple and Noise
Transient Response
Fundamental output voltage ripple at V I = 12 V, IO = max IO,
COUT = 10 x 470 μF/5 mΩ + 10 x 100 μF.
Scale: 10 mV/div, 2 µs/div, 20 MHz bandwidth.
See section Output Ripple and Noise.
Output voltage response to load current step change (30–90–30 A) at
VI = 12 V, COUT = 10 x 470 μF/5 mΩ + 10 x 100 μF, di/dt = 2 A/µs,
ASCR Gain = 300 and ASCR Residual = 90.
Scale from top: 50 mV/div, 20 A/div, 100 µs/div.
Note: Sense pins are connected to load.
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
11 (16)
No.
2/1301-BMR 467
Uen
Technical
Specification
JIDDASUN Dan Sun
Approved (Document resp)
BMR467
series PoL Regulators
Lisa
Li
Checked
Date
Dan Yue
8/7/2020
Input 7.5 - 14 V, Output up to 120 A / 216 W
Rev
B
© Flex
Typical Output Characteristics, VO = 1.0 V
BMR 467 0010, BMR 467 1010
BMR 467 2010, BMR 467 2110
Standard configuration unless otherwise specified, TP1 = +25 °C
Efficiency
March 2021
28701-BMR 467 Rev E
Power Dissipation
[%]
[W]
100
21
18
95
90
85
VI
15
7.5 V
12
9.6 V
9
80
12 V
75
14 V
VI
7.5 V
9.6 V
12 V
6
14 V
3
0
70
0
20
40
60
80
100
0
120 [A]
20
40
60
80
100
120 [A]
Efficiency vs. load current and input voltage.
Dissipated power vs. load current and input voltage.
Output Current Derating for SIP version
Output Current Derating for Lay Down versions
[A]
[A]
120
120
100
4.0 m/s
100
4.0 m/s
80
2.0 m/s
80
2.0 m/s
60
1.0 m/s
60
1.0 m/s
40
0.5 m/s
40
0.5 m/s
20
Nat. Conv.
20
Nat. Conv.
0
0
0
20
40
60
80
100
120 [°C]
0
20
40
60
80
100
120 [°C]
Available load current vs. ambient air temperature and airflow at
VI = 12 V.
Available load current vs. ambient air temperature and airflow at
VI = 12 V.
Output Ripple and Noise
Transient Response
Fundamental output voltage ripple at V I = 12 V, IO = max IO,
COUT = 10 x 470 μF/5 mΩ + 10 x 100 μF.
Scale: 10 mV/div, 2 µs/div, 20 MHz bandwidth.
See section Output Ripple and Noise.
Output voltage response to load current step change (30–90–30 A) at
VI = 12 V, COUT = 10 x 470 μF/5 mΩ + 10 x 100 μF, di/dt = 2 A/µs,
ASCR Gain = 300 and ASCR Residual = 90.
Scale from top: 50 mV/div, 20 A/div, 100 µs/div.
Note: Sense pins are connected to load.
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
12 (16)
No.
2/1301-BMR 467
Uen
Technical
Specification
JIDDASUN Dan Sun
Approved (Document resp)
BMR467
series PoL Regulators
Lisa
Li
Checked
Date
Dan Yue
8/7/2020
Input 7.5 - 14 V, Output up to 120 A / 216 W
Rev
B
© Flex
Typical Output Characteristics, VO = 1.8 V
BMR 467 0010, BMR 467 1010
BMR 467 2010, BMR 467 2110
Standard configuration unless otherwise specified, TP1 = +25 °C
Efficiency
March 2021
28701-BMR 467 Rev E
Power Dissipation
[%]
[W]
100
21
18
95
90
85
VI
15
7.5 V
12
9.6 V
9
80
12 V
75
14 V
VI
7.5 V
9.6 V
12 V
6
14 V
3
0
70
0
20
40
60
80
100
0
120 [A]
20
40
60
80
100
120 [A]
Efficiency vs. load current and input voltage.
Dissipated power vs. load current and input voltage.
Output Current Derating for SIP version
Output Current Derating for Lay Down versions
[A]
[A]
120
120
100
4.0 m/s
100
4.0 m/s
80
2.0 m/s
80
2.0 m/s
60
1.0 m/s
60
1.0 m/s
40
0.5 m/s
40
0.5 m/s
20
Nat. Conv.
20
Nat. Conv.
0
0
0
20
40
60
80
100
120 [°C]
0
20
40
60
80
100
120 [°C]
Available load current vs. ambient air temperature and airflow at
VI = 12 V.
Available load current vs. ambient air temperature and airflow at
VI = 12 V.
Output Ripple and Noise
Transient Response
Fundamental output voltage ripple at V I = 12 V, IO = max IO,
COUT = 10 x 470 μF/5 mΩ + 10 x 100 μF.
Scale: 10 mV/div, 2 µs/div, 20 MHz bandwidth.
See section Output Ripple and Noise.
Output voltage response to load current step change (30–90–30 A) at
VI = 12 V, COUT = 10 x 470 μF/5 mΩ + 10 x 100 μF, di/dt = 2 A/µs,
ASCR Gain = 300 and ASCR Residual = 90.
Scale from top: 50 mV/div, 20 A/div, 100 µs/div.
Note: Sense pins are connected to load.
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
2/1301-BMR 467
Uen
Technical
Specification
JIDDASUN Dan Sun
Approved (Document resp)
BMR467
series PoL Regulators
Lisa
Li
13 (16)
No.
Checked
Date
Dan Yue
8/7/2020
Input 7.5 - 14 V, Output up to 120 A / 216 W
Rev
28701-BMR 467 Rev E
B
© Flex
Typical On/Off Characteristics
BMR 467 0010, BMR 467 1010
BMR 467 2010, BMR 467 2110
Standard configuration, TP1 = +25 °C, VO = 1.0 V
Enable by input voltage – PG Open-Drain (default)
Disable by input voltage – PG Open-Drain (default)
VI
VI
VO
VO
PG
PG
Output enabled by applying VI. VI = 12 V, IO = max IO.
TON_DELAY = TON_RISE = 5 ms, POWER_GOOD_DELAY = 2 ms.
USER_CONFIG = 0x1480 (default). PG pulled up to external voltage.
Note: PG being high before Vin applied can be avoided by pulling up PG to Vout.
Scale from top: 10, 0.5, 2 V/div, 20 ms/div.
Output disabled by removing VI. VI = 12 V, IO = max IO.
Scale from top: 10, 0.5, 2 V/div, 1 ms/div.
Enable by input voltage – PG Push-Pull
Disable by input voltage – PG Push-Pull
VI
VI
VO
VO
PG
PG
Output enabled by applying VI. VI = 12 V, IO = max IO.
TON_DELAY = TON_RISE = 5 ms, POWER_GOOD_DELAY = 2 ms.
USER_CONFIG = 0x1484 (PG push-pull).
Scale from top: 10, 0.5, 2 V/div, 20 ms/div.
Output disabled by removing VI. VI = 12 V, IO = max IO.
Scale from top: 10, 0.5, 2 V/div, 1 ms/div.
Enable by CTRL pin
Disable by CTRL pin
CTRL
CTRL
VO
VO
PG
PG
Output enabled by CTRL pin. VI = 12 V, IO = max IO.
TON_DELAY = TON_RISE = 5 ms, POWER_GOOD_DELAY = 2 ms.
Scale from top: 5, 0.5, 2 V/div, 10 ms/div.
March 2021
Output disabled by CTRL pin. VI = 12 V, IO = max IO.
Scale from top: 5, 0.5, 2 V/div, 1 ms/div.
INTERNAL USE ONLY
PRODUCT SPECIFICATION
Prepared (Subject resp)
14 (16)
No.
2/1301-BMR 467
Uen
Technical
Specification
JIDDASUN Dan Sun
Approved (Document resp)
BMR467
series PoL Regulators
Lisa
Li
Checked
Date
Dan Yue
8/7/2020
Input 7.5 - 14 V, Output up to 120 A / 216 W
Rev
B
© Flex
Typical Charactersitics
BMR 467 0010, BMR 467 1010
BMR 467 2010, BMR 467 2110
Standard configuration unless otherwise specified, TP1=+25 °C
Efficiency vs. Output Current and
Switching Frequency
March 2021
28701-BMR 467 Rev E
Power Dissipation vs. Output Current and
Switching Frequency
[%]
[W]
100
21
95
200 kHz
VI
90
320 kHz
18
200 kHz
VI
15
320 kHz
12
85
480 kHz
80
640 kHz
75
9
480 kHz
6
640 kHz
3
70
0
0
20
40
60
80
100
120 [A]
0
20
40
60
80
100
120 [A]
Efficiency vs. load current and switching frequency at
VI = 12 V, VO = 1.0 V, CO = 10 x 470 μF/5 mΩ + 10 x 100 μF.
Frequency changed by PMBus command FREQUENCY_SWITCH.
Dissipated power vs. load current and switching frequency at
VI = 12 V, VO = 1.0 V, CO = 10 x 470 μF/5 mΩ + 10 x 100 μF.
Frequency changed by PMBus command FREQUENCY_SWITCH.
Output Ripple vs. Switching Frequency
Load Transient vs. ASCR Gain and
External Output Capacitance
[mVpk-pk]
[mV]
12
100
10
80
10x100
μF +
10x470
μF/5 mΩ
VO
8
0.6 V
60
6
4
2
0
1.0 V
40
1.8 V
20
10x100
μF +
4x470
μF/5 mΩ
0
200
300
400
500
600 [kHz]
Output voltage ripple Vpk-pk vs. switching frequency at
VI = 12 V, IO = max IO, CO = 10 x 470 μF/5 mΩ + 10 x 100 μF.
Frequency changed by PMBus command FREQUENCY_SWITCH.
100
200
300
400
500
Load transient peak voltage deviation vs. ASCR gain and external capacitance.
Step (30–90–30 A).
VI = 12 V, VO = 1.0 V, fsw = 320 kHz, ASCR residual =90, di/dt = 2 A/µs.
ASCR gain changed by PMBus command ASCR_CONFIG.
PUBLIC
PRODUCT SPECIFICATION
Prepared (Subject resp)
1 (14)
No.
3/1301-BMR467Technical Specification
Approved (Document resp)
BMR467George
seriesZou
PoL Regulators
jidgezou
Checked
Input 7.5 - 14 V, Output up to 120 A / 216 W
EMC Specification
Conducted EMI is measured according to the test set-up
below. The typical fundamental switching frequency is 320
kHz.
Conducted EMI Input terminal value (typical for standard
configuration). VI = 12 V, VO = 1.0 V, IO = 120 A.
Date
Rev
8/18/2020
28701-BMR 467 Rev E
D
March 2021
© Flex
Output Ripple and Noise
Output ripple and noise are measured according to figure
below. A 50 mm conductor works as a small inductor forming
together with the two capacitances a damped filter.
50 mm conductor
Vout
+S
Tantalum
Capacitor
10 µF
co
Ceramic
Capacitor
0.1 µF
−S
GND
Load
jidgezou George Zou
50 mm conductor
BNC-contact to
oscilloscope
Output ripple and noise test set-up.
The digital compensation of the product is designed to
automatically provide stability, accurate line and load regulation
and good transient performance for a wide range of operating
conditions (switching frequency, input voltage, output voltage,
output capacitance). Inherent from the implementation and
normal to the product there will be some low frequency ripple
at the output, in addition to the fundamental switching
frequency output ripple. The total output ripple and noise is
maintained at a low level.
EMI without filter
To spectrum
analyzer
RF Current probe
1 kHz – 50 MHz
Battery
supply
Resistive
load
C1
DUT
VI = 12 V, VO = 1.0 V, IO = 120 A, COUT = 10 x 470 μF/5 mΩ + 10 x 100 μF,
5 mV/div, 50 µs/div
50 mm
Example of low frequency ripple at the output.
C1 = 10 µF / 600 VDC
Feed- Thru RF capacitor
800 mm
200 mm
Test set-up conducted emission, power lead.
DUT = Product mounted on a 182 cm2 test board with the external
capacitances CIN = 1000 μF/12 mΩ + 24 x 10 μF and COUT = 10 x 470
μF/5 mΩ + 10 x 100 μF.
PUBLIC
PRODUCT SPECIFICATION
Prepared (Subject resp)
3/1301-BMR467Technical Specification
jidgezou George Zou
Approved (Document resp)
BMR467George
seriesZou
PoL Regulators
jidgezou
2 (14)
No.
Checked
Input 7.5 - 14 V, Output up to 120 A / 216 W
Date
Rev
8/18/2020
March 2021
28701-BMR 467 Rev E
D
© Flex
PMBus Interface
Power Management Overview
This product incorporates a wide range of configurable power
management features that are simple to implement with a
minimum of external components. Additionally, the product
includes protection features that continuously safeguard the
load from damage due to unexpected system faults.
The product’s standard configuration is suitable for a wide
range of operation in terms of input voltage, output voltage and
load. The configuration is stored in an internal Non-Volatile
Memory (NVM). All power management functions can be
reconfigured using the PMBus interface.
Throughout this document, different PMBus commands are
referenced. A detailed description of each command is
provided in the appendix at the end of this specification.
The Flex Power Designer software suite can be used to
configure and monitor this product via the PMBus interface.
For more information please contact your local Flexsales
representative.
RSA [k]
Address
RSA [k]
Address
0 (short)
0x26
42.2
0x28
10
0x19
46.4
0x29
11
0x1A
51.1
0x2A
12.1
0x1B
56.2
0x2B
13.3
0x1C
61.9
0x2C
14.7
0x1D
68.1
0x2D
16.2
0x1E
75
0x2E
17.8
0x1F
82.5
0x2F
19.6
0x20
90.9
0x30
21.5
0x21
100
0x31
23.7
0x22
110
0x32
26.1
0x23
121
0x33
28.7
0x24
133
0x34
31.6
0x25
147
0x35
34.8
0x26
162
0x36
38.3
0x27
178
0x37
Infinite
0x28
SMBus Interface
(open)
2
The product can be used with any standard two-wire I C or
SMBus host device. See Electrical Specification for allowed
clock frequency range. In addition, the product is compatible
Reserved Addresses
with PMBus version 1.2 and includes an SALERT line to help
Addresses listed in the table below are reserved or assigned
mitigate limitations related to continuous fault monitoring. The
according to the SMBus specification and may not be usable.
PMBus signals SCL, SDA and SALERT require passive pull-up
Refer to the SMBus specification for further information.
resistors as stated in the SMBus Specification. Pull-up resistors
values should be selected to guarantee the rise time according
to equation below:
Address
Comment
= RPC p 1 s
0x00
General Call Address / START byte
0x01
CBUS address
where Rp is the pull-up resistor value and Cp is the bus
loading. The maximum allowed bus load is 400 pF. The pull-up
resistor should be tied to an external supply voltage in range
from 2.5 to 5.5 V, which should be present prior to or during
power-up. If the proper power supply is not available, voltage
dividers may be applied. Note that in this case, the resistance
in the equation above corresponds to parallel connection of the
resistors forming the voltage divider.
See application note AN304 for details on interfacing the
product with a microcontroller.
0x02
Address reserved for different bus format
0x03 - 0x07
Reserved for future use
0x08
SMBus Host
0x09 - 0x0B
Assigned for Smart Battery
0x0C
SMBus Alert Response Address
0x28
Reserved for ACCESS.bus host
0x2C - 0x2D
Reserved by previous versions of the SMBus
specification
0x37
PMBus Addressing
The PMBus address is configured with a resistor connected
between the SA pin and the PREF pin, as shown in the Typical
Application Circuit. Recommended resistor values are shown
in the table below. 1% tolerance resistors are required.
0x48 - 0x4B
Reserved for ACCESS.bus default address
Reserved by previous versions of the SMBus
specification
Unrestricted addresses
0x61
SMBus Device Default Address
0x78 - 0x7B
10-bit slave addressing
0x7C - 0x7F
Reserved for future use
0x40 - 0x44
PUBLIC
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3/1301-BMR467Technical Specification
jidgezou George Zou
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seriesZou
PoL Regulators
jidgezou
Checked
Input 7.5 - 14 V, Output up to 120 A / 216 W
Monitoring via PMBus
It is possible to continuously monitor a wide variety of
parameters through the PMBus interface. These include, but
are not limited to, the parameters listed in the table below.
Parameter
Input voltage
PMBus Command
READ_VIN
Output voltage
READ_VOUT
Total output current
Controller temperature (TP1)
READ_IOUT
READ_IOUT0
READ_IOUT1
READ_TEMPERATURE_1
Switching frequency
READ_FREQUENCY
Duty cycle
READ_DUTY_CYCLE
Output current of each phase
Date
Rev
8/18/2020
28701-BMR 467 Rev E
D
March 2021
© Flex
Snapshot Parameter Capture
This product offers a special feature that enables the user to
capture parametric data during normal operation by a single
PMBus command. The following parameters are stored:
•
•
•
•
•
•
•
Input voltage
Output voltage
Output current
Controller temperature
Switching frequency
Duty cycle
Status and fault information
When a fault occurs the Snapshot functionality will
automatically store this parametric data to NVM. The data can
then later be read back using the SNAPSHOT command to
provide valuable information for analysis. It is possible to select
which faults will trigger a store to NVM by the PMBus command
SNAPSHOT_FAULT_MASK.
See application note AN320 for details on using the Snapshot
feature.
Monitoring Faults
Fault conditions can be monitored using the SALERT pin,
which will be asserted low when any number of pre-configured
fault or warning conditions occurs. The SALERT pin will be held PMBus/I2C Timing
low until faults and/or warnings are cleared by the
CLEAR_FAULTS command, or until the output voltage has
been re-enabled.
It is possible to mask which fault conditions should not assert
the SALERT pin by the command MFR_SMBALERT_MASK.
In response to the SALERT signal, the user may read a number
of status commands to find out what fault or warning condition
occurred, see table below.
Fault & Warning Status
PMBus Command
Overview, Power Good
STATUS_WORD
STATUS_BYTE
Output voltage level
STATUS_VOUT
Output current level
STATUS_IOUT
Input voltage level
STATUS_INPUT
Temperature level
STATUS_TEMPERATURE
PMBus communication
STATUS_CML
Miscellaneous
STATUS_MFR_SPECIFIC
Setup and hold times timing diagram.
The setup time, tset, is the time data, SDA, must be stable
before the rising edge of the clock signal, SCL. The hold time
thold, is the time data, SDA, must be stable after the falling edge
of the clock signal, SCL. If these times are violated incorrect
data may be captured or meta-stability may occur and the bus
communication may fail. All standard SMBus protocols must be
followed, including clock stretching. Refer to the SMBus
specification, for SMBus electrical and timing requirements.
This product supports the BUSY flag in the status commands to
indicate product being too busy for SMBus response. A busfree time delay according to this specification must occur
between every SMBus transmission (between every stop &
start condition).
The product supports PEC (Packet Error Checking) according
to the SMBus specification.
When sending subsequent commands to the same module, it is
recommended to insert additional delays according to the table
below.
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Input 7.5 - 14 V, Output up to 120 A / 216 W
After sending PMBus
Command
Required delay before
additional command
STORE_USER_ALL
RESTORE_USER_ALL
RESTORE_DEFAULT_ALL
Any other command
Date
Rev
8/18/2020
28701-BMR 467 Rev E
D
© Flex
Command Protection
The user may write-protect specific PMBus commands in the
User NVM by using the command UNPROTECT.
Initialization Procedure
The product follows an internal initialization procedure after
power is applied to the VIN pins:
100 ms
1. Self-test and memory check.
10 ms
2 ms after reading
10 ms after writing
2. The address pin-strap resistors are measured and the
associated PMBus address is defined.
Non-Volatile Memory (NVM)
The product incorporates two Non-Volatile Memory areas for
storage of the PMBus command values; the Default NVM and
the User NVM.
The Default NVM is pre-loaded with Flexfactory default values.
The Default NVM is write-protected and can be used to restore
the Flexfactory default values through the command
RESTORE_DEFAULT_ALL.
The User NVM is pre-loaded with Flexfactory default values.
The User NVM is writable and open for customization. The
values in NVM are loaded during initialization according to
section Initialization Procedure, whereafter commands can be
changed through the PMBus Interface. The
STORE_USER_ALL command will store the changed
parameters to the User NVM.
Pin-strap resistors
INITIALIZATION
Default NVM
INITIALIZATION
Flexfactory default
Write-protected
RESTORE_DEFAULT_ALL
3. The output voltage pin-strap resistor is measured and the
associated output voltage level will be loaded to operational
RAM of PMBus command VOUT_COMMAND.
4. Flexfactory default values stored in default NVM memory
are loaded to operational RAM. This overwrites any
previously loaded values.
5. Values stored in the User NVM are loaded into operational
RAM memory. This overwrites any previously loaded values
(e.g. VOUT_COMMAND by pin-strap).
6. Check for external clock signal at the SYNC pin and lock
internal clock to the external clock if used.
Once this procedure is completed and the Initialization Time
has passed (see Electrical Specification), the output voltage is
ready to be enabled using the CTRL pin. The product is also
ready to accept commands via the PMBus interface, which in
case of writes will overwrite any values loaded during the
initialization procedure.
VIN
RAM
User NVM
Flexfactory default
Customizable
TINIT
INITIALIZATION
STORE_USER_ALL
VOUT
RESTORE_USER_ALL
WRITE
PMBus interface
March 2021
100 ms
STORE_DEFAULT_ALL
VOUT_MAX
4 (14)
No.
READ
Illustration of memory areas of the product.
Illustration Initialization time.
Ready for output
enable and soft-start
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Input 7.5 - 14 V, Output up to 120 A / 216 W
Date
8/18/2020
Rev
28701-BMR 467 Rev E
D
March 2021
© Flex
Operating Information
Input Voltage
The input voltage range 7.5 - 14 V makes the product easy to
use in intermediate bus applications when powered by a nonregulated bus converter or a regulated bus converter.
Input Under Voltage Protection (IUVP)
The product monitors the input voltage and will turn-on and
turn-off at configured thresholds (see Electrical Specification).
The turn-on input voltage threshold is set higher than the
corresponding turn-off threshold. Hence, there is a hysteresis
between turn-on and turn-off input voltage levels. Once the
input voltage falls below the turn-off threshold, the device can
respond in several ways as follows:
1.
Immediate and definite shutdown of output voltage until
the fault is cleared by PMBus command CLEAR_FAULTS
or the output voltage is re-enabled.
2.
Immediate shutdown of output voltage while the input
voltage is below the turn-on threshold. Operation resumes
automatically and the output is enabled when the input
voltage has risen above the turn-on threshold.
The default response is option 2. The IUVP function can be
reconfigured using the PMBus commands
VIN_UV_FAULT_LIMIT (turn-off threshold),
VIN_UV_WARN_LIMIT (turn-on threshold) and
VIN_UV_FAULT_RESPONSE.
For products configured to operate in current sharing mode,
response option 1 will always be used, regardless of
VIN_UV_FAULT_RESPONSE command settings.
Input Over Voltage Protection (IOVP)
The product monitors the input voltage continuously and will
respond as configured when the input voltage rises above the
configured threshold level (see Electrical Specification). Refer
to section “Input Under Voltage Protection” for functionality,
response configuration options and default setting.
The IOVP function can be reconfigured using the PMBus
commands VIN_OV_FAULT_LIMIT (turn-off threshold),
VIN_OV_WARN_LIMIT (turn-on threshold) and
VIN_OV_FAULT_RESPONSE.
Input and Output Impedance
The impedance of both the input source and the load will
interact with the impedance of the product. It is important that
the input source has low characteristic impedance. If the input
voltage source contains significant inductance, the addition of a
capacitor with low ESR at the input of the product will ensure
stable operation.
External Input Capacitors
The product is a two-phase converter which gives lower input
ripple than a single phase design, see picture below. Thus,
ripple-current-rating requirements for the input capacitors are
lower relatively to a single phase converter.
The input ripple RMS current in a two-phase buck converter
can be estimated to
I inputRMS = I load D(0.5 − D)
(valid for D < 0.5)
Where Iload is the output load current and D is the duty cycle.
The maximum load ripple current becomes Iload/4. The ripple
current is divided into three parts, i.e., currents in the input
source, external input capacitor and internal input capacitor.
How the current is divided depends on the impedance of the
input source, ESR and capacitance values in the capacitors.
For most applications non-tantalum capacitors are preferred
due to the robustness of such capacitors to accommodate high
inrush currents of systems being powered from very low
impedance sources. It is recommended to use a combination of
ceramic capacitors and low-ESR electrolytic/polymer bulk
capacitors. The low ESR of ceramic capacitors effectively limits
the input ripple voltage level, while the bulk capacitance
minimizes deviations in the input voltage at large load
transients.
If several products are connected in a phase spreading setup
the amount of input ripple current, and capacitance per product,
can be reduced. The amount of input ripple current for such
setup can be estimated using the Flex Power Designer
software and capacitor selection can be made based on this
number.
Ceramic input capacitors must be placed close to the input pins
of a converter and with low impedance connections to the VIN
and GND pins in order to be effective. See application note
AN323 for further guidelines on how to choose and apply input
capacitors.
External Output Capacitors
The output capacitor requirement depends on two
considerations; output ripple voltage and load transient
response. To achieve low ripple voltage, the output capacitor
bank must have a low ESR value, which is achieved with
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No.
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Input 7.5 - 14 V, Output up to 120 A / 216 W
ceramic output capacitors. A low ESR value is critical also for a
small output voltage deviation during load transients. Designs
with smaller load transients can use fewer capacitors and
designs with more dynamic load content will require more load
capacitors to minimize output voltage deviation. Improved
transient response can also be achieved by adjusting the
settings of the control loop of the product. Adding output
capacitance decreases loop band-width.
It is recommended to place low ESR ceramic and low ESR
electrolytic/polymer capacitors as close to the load as possible,
using several capacitors in parallel to lower the effective ESR. It
is important to use low resistance and low inductance PCB
layouts in order for capacitance to be effective.
Optimization of output filter together with load step simulations
can be made using the Flex Power Designer software. See
application note AN321 for further guidelines on how to choose
and apply output capacitors.
Date
Rev
March 2021
28701-BMR 467 Rev E
8/18/2020
D
© Flex
[mV]
100
80
10x100
μF +
10x470
μF/5 mΩ
60
10x100
μF +
4x470
μF/5 mΩ
40
20
0
100
200
300
400
500
Load step 30-90-30 A, di/dt = 2 A/µs.
VI = 12 V, VO = 1.0 V, fsw = 320 kHz, Residual factor = 90.
Gain factor changed by PMBus command ASCR_CONFIG.
Voltage deviation vs. control loop gain setting and output capacitance.
Control Loop
The products use a fully digital control loop that achieves
precise control of the entire power conversion process,
resulting in a very flexible device that is also very easy to use.
The control loop utilizes oversampling of the output voltage
compared to the switching frequency, and a dual edge
modulation PWM, to minimize the delay in the control loop. The
actual duty cycle is updated after each sample within each
switching cycle, achieving a smaller total output voltage
variation with less output capacitance than traditional PWM
controllers, thus saving cost and board space.
Control may be set more or less aggressive by adjusting a gain
factor, set by the PMBus command ASCR_CONFIG.
Increasing the gain factor will reduce the voltage deviation at
load transients, at the expense of somewhat increased ripple
on the output. Too high gain can also cause increase in jitter
and instability. Stability analysis can be made using the Flex
Power Designer software. Below graph exemplifies the effect of
the gain factor on the voltage deviation during a load transient.
The typical range of the gain factor is 100 - 600.
The user may also adjust the residual factor, set by the
ASCR_CONFIG command, to improve the recovery time after a
load transient. The typical usable range of the residual factor is
70 - 120. A higher value than 127 may damage the device and
must not be used. Note that the gain factor will also affect the
recovery time.
By default the product is configured with a moderate gain factor
to provide a trade-off between load transient performance and
output ripple for a wide range of operating conditions. For a
specific application the gain factor can be increased to improve
load transient response.
Optimization of control loop settings and output filter, together
with load step simulations, can be made using the Flex Power
Designer software.
Remote Sense
The product has remote sense to compensate the voltage
drops between the output and the point of load. The sense
traces should be laid out as a differential pair and preferably be
shielded by the PCB ground layer to reduce noise
susceptibility.
Generally the module is designed for an external capacitive
decoupling near the module, see Section “External Output
Capacitors” for further information. The Flex Power Designer
software can be used to simulate the condition and help to
place the correct decoupling and configure the module for
optimal performance.
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Input 7.5 - 14 V, Output up to 120 A / 216 W
In case of parasitic or deliberate inductance in the output power
train, it can influence the stability of the regulator. The
placement of the sense point is then critical. For example,
assume the external output filter includes an inductor (forming a
PI filter) according to the picture below. If Co = 2 x 470 µF/5 mΩ
POS-CAP + 2 x 100 µF ceramic and CEXT = 8 x 470 µF/5 mΩ
POS-CAP + 8 x 100 µF ceramic, 30 nH will be the maximum
value of the PI filter inductance (LEXT) to guaranty stability of the
system. In that case, gain factor of the control loop must be
reduced to 100 at cost of higher voltage deviation in case of a
load transient. As mention above, the Flex Power Designer tool
can be used to simulate the condition, stabilize the control loop,
and help to place the output filter.
CO
LEXT
CEXT
Load
Vout
Date
Rev
8/18/2020
28701-BMR 467 Rev E
D
March 2021
© Flex
RSET [kΩ]
VOUT [V]
RSET [kΩ]
VOUT [V]
0 (short)
1.00
26.1
1.10
10
0.60
28.7
1.15
11
0.65
31.6
1.20
12.1
0.70
34.8
1.25
13.3
0.75
38.3
1.30
14.7
0.80
42.2
1.40
16.2
0.85
46.4
1.50
17.8
0.90
51.1
1.60
19.6
0.95
56.2
1.70
21.5
1.00
61.9
1.80
23.7
1.05
Infinite
(open)
1.20
GND
-S
+S
External output filter with inductor (PI filter).
Enabling Output Voltage
The following options are available to enable and disable this
device:
1.
Output voltage is enabled through the CTRL pin.
2.
Output voltage is enabled using the PMBus command
OPERATION.
The CTRL pin can be used with active high (positive) logic or
active low (negative) logic.
RSET also sets the maximum output voltage; see section Output
Voltage Range Limitation. The resistor is sensed only during
the initialization procedure after application of input voltage.
Changing the resistor value during normal operation will not
change the output voltage. See Ordering Information for output
voltage range.
Output Voltage Adjust using PMBus
The output voltage set by pin-strap can be overridden up to a
certain level (see section Output Voltage Range Limitation) by
using the PMBus command VOUT_COMMAND. See Electrical
Specification for adjustment range. Make sure a new
VOUT_COMMAND is not sent 15 ms prior to enabling the
output, until after power good (PG) is asserted.
Voltage Margining Up/Down
Using the PMBus interface it is possible to adjust the output
voltage to one of two predefined levels above or below the
The CTRL pin has an internal 10 kΩ pull-up resistor to 5 V. The nominal voltage setting in order to determine whether the load
device is capable of operating outside its specified supply
external device must have a sufficient sink current ability to be
able pull CTRL pin voltage down below logic low threshold level voltage range. This provides a convenient method for
dynamically testing the operation of the load circuit outside its
(see Electrical Characteristics). When the CTRL pin is left
typical operating range. This functionality can also be used to
open, the voltage on the CTRL pin is pulled up to 5 V.
test of supply voltage supervisors. Margin limits of the nominal
If the device is to be synchronized to an external clock source, output voltage ±5% are default, but the margin limits can be
the clock frequency must be stable prior to enabling the output reconfigured using the PMBus commands
VOUT_MARGIN_LOW and VOUT_MARGIN_HIGH. Margining
voltage.
is activated by the command OPERATION and can be used
regardless of the output voltage being enabled by the CTRL pin
Output Voltage Adjust using Pin-strap Resistor
or by the PMBus.
Using an external pin-strap resistor, RSET, the output voltage
can be set to several predefined levels shown in the table
below. Only the voltage levels specified in the table can be set
by RSET. The resistor should be applied between the VSET pin
and the PREF pin as shown in the Typical Application Circuit.
Maximum 1% tolerance resistors are required.
The CTRL pin polarity can be reconfigured using the PMBus
command ON_OFF_CONFIG.
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Input 7.5 - 14 V, Output up to 120 A / 216 W
Output Voltage Trim
The actual output voltage can be trimmed to optimize
performance of a specific load by setting a non-zero value for
PMBus command VOUT_TRIM. The value of VOUT_TRIM is
summed with the nominal output voltage set by
VOUT_COMMAND, allowing for multiple products to be
commanded to a common nominal value, but with slight
adjustments per load.
Output Voltage Range Limitation
The output voltage range that is possible to set by configuration
or by the PMBus interface is hardware limited by the pin-strap
resistor RSET. The maximum output voltage is set to 115% of
the output value defined by RSET. This protects the application
circuit from an over voltage due to an accidental PMBus
command.
The limitation applies to the actual regulated output voltage
rather than to the configured value. Thus, it is possible to write
and read back a VOUT_COMMAND value higher than the limit,
but the actual output voltage will be limited.
The output voltage limit can be reconfigured to a lower than
115% of Vout value by writing the PMBus command
VOUT_MAX.
Output Over Voltage Protection (OVP)
The product includes over voltage limiting circuitry for
protection of the load. The default OVP limit is 15% above the
nominal output voltage. The product can be configured to
respond in different ways to the output voltage exceeding the
OVP limit:
Date
D
March 2021
© Flex
The time between when the POWER_GOOD_ON threshold is
reached and when the PG pin is actually asserted is set by the
PMBus command POWER_GOOD_DELAY. See Electrical
Specification for default value and range.
By default the PG pin is configured as an open drain output but
it is also possible to set the output in push-pull mode by the
command USER_CONFIG.
The PG output is not defined during ramp up of the input
voltage due to the initialization of the product.
Over Current Protection (OCP)
The product includes robust current limiting circuitry for
protection at continuous overload. After ramp-up is complete
the product can detect an output overload/short condition. The
following OCP response options are available:
1.
Immediate and definite shutdown of output voltage until the 2.
fault is cleared by PMBus command CLEAR_FAULTS or
the output voltage is re-enabled.
2.
Immediate shutdown of output voltage followed by
continuous restart attempts of the output voltage with a
preset interval (“hiccup” mode).
For products configured to operate in current sharing mode,
response option 1 will always be used, regardless of this
command configuration.
28701-BMR 467 Rev E
Power Good
The power good pin (PG) indicates when the product is ready
to provide regulated output voltage to the load. During ramp-up
and during a fault condition, PG is held low. By default, PG is
asserted high after the output has ramped to a voltage above
90% of the nominal voltage, and deasserted if the output
voltage falls below 85% of the nominal voltage. These
thresholds may be changed using the PMBus commands
POWER_GOOD_ON and VOUT_UV_FAULT_LIMIT.
1.
The default response is option 2. The OVP limit and fault
response can be reconfigured using the PMBus commands
VOUT_OV_FAULT_LIMIT, VOUT_OV_FAULT_RESPONSE
and OVUV_CONFIG.
Rev
8/18/2020
Immediate and definite shutdown of output voltage until the
fault is cleared by PMBus command CLEAR_FAULTS or
the output voltage is re-enabled.
Immediate shutdown of output voltage followed by
continuous restart attempts of the output voltage with a
preset interval (“hiccup” mode).
The default response from an over current fault is option 2.
Note that delayed shutdown is not supported. The load
distribution should be designed for the current set by the
current limit threashold. The OCP limit and response can be
reconfigured using the PMBus commands
IOUT_AVG_OC_FAULT_LIMIT and
MFR_IOUT_OC_FAULT_RESPONSE.
For products operated in current sharing mode, response
option 1 will always be used, regardless of configuration.
Under Current Protection (UCP)
The product includes robust current limiting circuitry for
Output Under Voltage Protection (UVP)
protection at continuous reversed current, due to a
The product includes output under voltage limiting circuitry for
synchronous rectifier ability to sink current. Refer to section
protection of the load. The default UVP limit is 15% below the
Over Current Protection for response configuration options and
nominal output voltage. Refer to section Output Over Voltage
default setting. The UCP limit and response can be
Protection for response configuration options and default
reconfigured using the PMBus commands
setting.
The UVP limit and fault response can be reconfigured using the IOUT_AVG_UC_FAULT_LIMIT and
MFR_IOUT_UC_FAULT_RESPONSE.
PMBus commands VOUT_UV_FAULT_LIMIT and
VOUT_UV_FAULT_RESPONSE.
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Input 7.5 - 14 V, Output up to 120 A / 216 W
Switching Frequency
The default switching frequency is chosen as the best tradeoff
between efficiency, thermal performance, output ripple and load
transient performance. The switching frequency can be reconfigured in a certain range using the PMBus command
FREQUENCY_SWITCH. Refer to Electrical Specification for
default switching frequency and range.
Changing the switching frequency will affect efficiency, power
dissipation, load transient response (control loop
characteristics) and output ripple. Control loop settings may
need to be adjusted.
Date
Rev
8/18/2020
March 2021
28701-BMR 467 Rev E
D
© Flex
SYNC
clock
Phase
offset = 60°
PWM pulse
(VO/VI = 0.165)
Illustration of phase offset.
The phase offset is configured using the PMBus command
The default switching frequency will optimize efficiency while an
INTERLEAVE and is defined as:
increase of frequency will improve ripple and load response at
the cost of lower efficiency.
Note that since the product has two phases the effective
switching frequency will be twice the configured.
Synchronization
One or more products may be synchronized with an external
clock to eliminate beat frequencies reflected back to the input
supply rail. Eliminating the slow beat frequencies (usually
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