AZ1515-04S.R7G

AZ1515-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces Features ESD protect for 4 high-speed I/O channels Provide transient protection for each channel to IEC 61000-4-2 (ESD) ±30kV (air / contact) IEC 61000-4-4 (EFT) 80A (5/50ns) IEC 61000-4-5 (Lightning) 30A (8/20µs) for any I/O-to-GND IEC 61000-4-5 (Lightning) 37A (8/20µs) for VDD-to-GND For low operating voltage applications: 5V maximum Low capacitance : 1.8pF typical Fast turn-on and low clamping voltage Array of surge rated diodes with internal equivalent TVS diode Small package saves board space Solid-state silicon-avalanche and active circuit triggering technology Green part equivalent TVS diode in a single package. During transient conditions, the steering diodes direct the transient to either the power supply line or to the ground line. The internal unique design of clamping cell prevents over-voltage on the power line, protecting any downstream components. AZ1515-04S may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 (±15kV air, ±8kV contact discharge). Circuit Diagram 5 1 3 4 6 2 Applications Video graphics cards LAN application USB2.0 power and data lines protection Notebook and PC computers Monitors and flat panel displays Pin Configuration I/O 4 VDD I/O 3 6 5 4 1 2 3 GND I/O 2 Description AZ1515-04S is a high-performance design which includes surge rated diode arrays to protect high-speed data interfaces. The AZ1515-04S has been specifically designed to protect sensitive components, which are connected to data and transmission lines, from over-voltage caused by Electrostatic Discharging (ESD), Electrical Fast Transients (EFT), and Lightning. I/O 1 AZ1515-04S is a unique design which includes surge rated, low capacitance steering diodes and a unique design of clamping cell which is an Revision 2018/01/23 ©2018 Amazing Micro. JEDEC SOT23-6L (Top View) 1 www.amazingIC.com AZ1515-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA= 25oC, unless otherwise specified) PARAMETER Peak Pulse Current (tp =8/20µs, any I/O-to-GND) Peak Pulse Current (tp =8/20µs, VDD-to-GND) Operating Supply Voltage (VDD-to-GND) ESD per IEC 61000-4-2 (Air / Contact) Lead Soldering Temperature Operating Temperature Storage Temperature SYMBOL IPP IPP VDC VESD TSOL TOP TSTO RATING 30 37 5.5 30 260 (10 sec.) -55 to +125 -55 to +150 ELECTRICAL CHARACTERISTICS SYMBOL CONDITIONS PARAMETER Reverse Stand-Off VRWM Voltage Reverse Leakage ILeak Current Channel Leakage ICH-Leak Current Reverse Breakdown VBV Voltage Forward Voltage VF ESD Clamping VCL_ESD_I/O Voltage –I/O (Note 1) ESD Clamping VCL_ESD_VDD Voltage –VDD (Note 1) ESD Dynamic Turn on Rdynamic_I/O Resistance –I/O ESD Dynamic Turn on Rdynamic_VDD Resistance –VDD Surge Clamping VCL_surge_I/O Voltage –I/O Surge Clamping VCL_surge_VDD Voltage –VDD Channel Input Capacitance Channel to Channel Capacitance CIN CI/O-to-I/O UNITS A A V kV o C o C o C MIN TYP MAX UNITS Pin 5 to pin 2, T=25 oC. 5 V VRWM = 5V, T=25 oC, pin 5 to pin 2. 1 µA Vpin5 = 5V, Vpin2 = 0V, T=25 oC. 1 µA 9.5 V 1 V IBV = 1mA, T=25 oC, pin 5 to pin 2. 6 IF = 15mA, T=25 oC, pin 2 to pin 5. IEC 61000-4-2 +8kV (ITLP = 16A), T=25 oC, Contact mode, any I/O pin to GND. IEC 61000-4-2 +8kV (ITLP = 16A), T=25 oC, Contact mode, VDD pin to GND. IEC 61000-4-2, 0~+8kV, T=25 oC, Contact mode, any I/O pin to GND. IEC 61000-4-2, 0~+8kV, T=25 oC, Contact mode, VDD pin to GND. IPP=30A, tp=8/20µs, T=25 oC, any I/O pin to GND. IPP=37A, tp=8/20µs, T=25 oC,VDD pin to GND. Vpin5 =5V, Vpin2 =0V, VIN =2.5V, f =1MHz, T=25 oC, any I/O pin to GND. Vpin5 =floated, Vpin2 =0V, VIN =2.5V, f =1MHz, T=25 oC, any I/O pin to GND. Vpin5 =5V, Vpin2 =0V, VIN =2.5V, f =1MHz, T=25 oC, between I/O pins. Vpin5 =floated, Vpin2 =0V, VIN =2.5V, f =1MHz, T=25 oC, between I/O pins. 0.7 9 V 7 V 0.1 Ω 0.05 Ω 11.5 V 11.2 V 1.8 2.5 pF 2.3 3 pF 0.18 0.3 pF 0.26 0.45 pF Note 1: ESD Clamping Voltage was measured by Transmission Line Pulsing (TLP) System. TLP conditions: Z0= 50Ω, tp= 100ns, tr= 1ns. Revision 2018/01/23 ©2018 Amazing Micro. 2 www.amazingIC.com AZ1515-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces Typical Characteristics Forward Clamping Voltage vs. Peak Pulse Current Reverse Clamping Voltage vs. Peak Pulse Current 8 15 14 7 13 I/O-to-GND 11 Clamping Voltage (V) Clamping Voltage (V) 12 10 9 VDD-to-GND 8 7 6 5 Waveform Parameters: tr = 8µs td = 20µs Source impedance = 42ohm 4 3 2 1 5 10 15 20 25 30 35 40 I/O-to-GND 5 VDD-to-GND 4 3 Waveform Parameters: tr = 8µs td = 20µs Source impedance = 42ohm 2 1 0 0 6 0 45 0 5 10 15 Peak Pulse Current (A) V_pulse Pulse from a transmission line TLP_I + 100ns TLP_V DUT _ I/O-to-GND 0 1 2 3 4 5 6 7 8 9 10 11 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TLP_V 0.40 0.35 Capacitance (pF) Capacitance (pF) 1 2 3.0 VDD=floating 2.0 VDD=5V 3.0 3.5 4.0 4.5 0.00 0.0 5.0 8 9 10 11 Amazing Micro. f = 1MHz, T = 25°C VDD=floating VDD=5V 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Input Voltage (V) Input Voltage (V) Revision 2018/01/23 ©2018 7 Typical Variation of CI/O-to-I/O vs. VIN 0.15 0.05 2.5 6 0.20 0.5 2.0 5 0.25 0.10 1.5 4 0.30 1.0 1.0 3 0.45 3.5 0.5 DUT Transmission Line Pulsing (TLP) Voltage (V) 4.0 0.0 0.0 45 VDD-to-GND 0 f = 1MHz, T = 25°C 1.5 40 _ 0.50 2.5 35 TLP_I + 100ns Typical Variation of CIN vs. VIN 4.5 30 V_pulse Pulse from a transmission line Transmission Line Pulsing (TLP) Voltage (V) 5.0 25 Transmission Line Pulsing (TLP) Measurement Transmission Line Pulsing (TLP) Current (A) Transmission Line Pulsing (TLP) Current (A) Transmission Line Pulsing (TLP) Measurement 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 20 Peak Pulse Current (A) 3 www.amazingIC.com AZ1515-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces Applications Information A. Design Considerations The ESD protection scheme for the system I/O connector is shown in the Fig. 1. In Fig. 1, the diodes D1 and D2 are generally used to protect data line from ESD stress pulse. If the power-rail ESD clamping circuit is not placed between VDD and GND rails, the positive pulse ESD current (IESD1) will pass through the ESD current path1. Thus, the ESD clamping voltage VCL of the data line can be described as follow : VCL = Fwd voltage drop of D1 + supply voltage of VDD rail + L1 × d(IESD1)/dt + L2 × d(IESD1)/dt Where L1 is the parasitic inductance of data line, and L2 is the parasitic inductance of VDD rail. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30A in 1ns. Here d(IESD1)/dt can be approximated by ∆IESD1/∆t, or 30/(1x10-9). So Fig. 1 just 10nH of total parasitic inductance (L1 and L2 combined) will lead to over 300V increment in VCL! Besides, the ESD pulse current which is directed into the VDD rail may potentially damage any components that are attached to that rail. Moreover, it is common for the forward voltage drop of discrete diodes to exceed the damage threshold of the protected IC. This is due to the relatively small junction area of typical discrete components. Of course, the discrete diode is also possible to be destroyed due to its power dissipation capability is exceeded. The AZ1515-04S has an integrated power-rail ESD clamped circuit between VDD and GND rails. It can successfully overcome previous disadvantages. During an ESD event, the positive ESD pulse current (IESD2) will be directed through the integrated power-rail ESD clamped circuit to GND rail (ESD current path2). The clamping voltage VCL on the data line is small and protected IC will not be damaged because power-rail ESD clamped circuit offer a low impedance path to discharge ESD pulse current. Application of positive ESD pulse between data line and GND rail. Revision 2018/01/23 ©2018 Amazing Micro. 4 www.amazingIC.com AZ1515-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces B. Device Connection The AZ1515-04S is designed to protect four data lines and power rails from transient over-voltage (such as ESD stress pulse). The device connection of AZ1515-04S is shown in the Fig. 2. In Fig. 2, the four protected data lines are connected to the ESD protection pins (pin1, pin3, pin4, and pin6) of AZ1515-04S. The ground pin (pin2) of AZ1515-04S is a negative reference pin. This pin should be directly connected to the GND rail of PCB (Printed Circuit Board). To get minimum parasitic inductance, the path length should keep as short as possible. In addition, the power pin (pin 5) of AZ1515-04S is a positive reference pin. This pin should directly connect to the VDD rail of PCB., then the VDD rail also can be protected by the power-rail ESD clamped circuit (not shown) of AZ1515-04S. AZ1515-04S can provide protection for 4 I/O signal lines simultaneously. If the number of I/O signal lines is less than 4, the unused I/O pins can be simply left as NC pins. In some cases, systems are not allowed to be reset or restart after the ESD stress directly applying at the I/O-port connector. Under this situation, in order to enhance the sustainable ESD Level, a 0.1µF chip capacitor can be added between the VDD and GND rails. The place of this chip capacitor should be as close as possible to the AZ1515-04S. In some cases, there isn’t power rail presented on the PCB. Under this situation, the power pin (pin 5) of AZ1515-04S can be left as floated. The protection will not be affected, only the load capacitance of I/O pins will be slightly increased. Fig. 3 shows the detail connection. Fig. 2 Data lines and power rails connection of AZ1515-04S. Fig. 3 Data lines and power rails connection of AZ1515-04S. VDD pin is left as floating when no power rail presented on the PCB. Revision 2018/01/23 ©2018 Amazing Micro. 5 www.amazingIC.com AZ1515-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces Mechanical Details SOT23-6L PACKAGE DIAGRAMS PACKAGE DIMENSIONS SYMBOL TOP VIEW MILLIMETERS MIN. MAX. A -- 1.25 A1 0.00 0.10 A2 0.90 1.20 b 0.30 0.50 c 0.08 0.21 D 2.72 3.12 E 1.40 1.80 E1 2.60 3.00 D b e 0.95BSC e1 1.90BSC L1 e e1 0.30 0.60 L 0.70REF L2 0.25BSC Ɵ 0 8 SIDE VIEW Notes: This dimension complies with JEDEC outline standard MO-178 Variation AB. Dimensioning and tolerancing per ASME Y14.5M-1994. All dimensions are in millimeters. END VIEW L Revision 2018/01/23 ©2018 L1 Amazing Micro. θ 6 www.amazingIC.com AZ1515-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces LAND LAYOUT Dimensions Index Millimeter Inches A 0.60 0.024 B 1.10 0.043 C 0.95 0.037 D 2.50 0.098 E 1.40 0.055 F 3.60 0.141 Notes: This LAND LAYOUT is purposes only. Please for reference consult your manufacturing partners to ensure your company’s PCB design guidelines are met. 4 5 6 MARKING CODE Part Number 124XY Marking Code 124XY (Green Part) Note : Green means Pb-free, RoHS, and Halogen free compliant. 3 2 1 AZ1515-04S.R7G 124 = Device Code X = Date Code Y = Control Code Ordering Information PN# Material Type Reel size MOQ AZ1515-04S.R7G Green T/R 7 inch 3,000/reel Revision 2018/01/23 ©2018 Amazing Micro. 7 MOQ/internal box MOQ/carton 4 reels=12,000/box 6 boxes=72,000/carton www.amazingIC.com AZ1515-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces Revision History Revision Modification Description Revision 2018/01/23 Formal Release. Revision 2018/01/23 ©2018 Amazing Micro. 8 www.amazingIC.com