AW21018
Feb. 2022 V1.1
18 MULTI-FUNCTION LED DRIVER WITH I2C INTERFACE
General Description
⚫
AW21018 is an 18-channel multi-function LED
driver. Each channel has individual 8-bit DC current
setting for color-mixing and maximum 12-bit PWM
resolution for brightness control. The global current
of each channel is recommended to be 40mA
configured via register and external resistor REXT.
⚫
⚫
⚫
⚫
Applications
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AW21018 can be turned off with minimum current
consumption by pulling the EN pin low.
AW21018 is available in QFN 4mmX4mmX
0.85mm-32L package. It operates from 2.7V to 5.5V
over the temperature range of -40°C to +85°C.
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Cell Phone
Keyboard
Programmable phase-shifting and spread spectrum
technology are utilized to reduce EMI and audible
noise caused by MLCC when LEDs turn on or off
simultaneously.
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⚫
⚫
⚫
Group control mode, autonomous breathing pattern
and rapid RGB control mode are provided for
flexible, high efficiency lighting effect programming
and fast display updating.
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⚫
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⚫
18-channel RGB LED Driver
➢ Global 256-levels DC current configuration
➢ Individual 4096-levels PWM for dimming
➢ Individual 256-levels current for colormixing
➢ Dither function
High-precision current sinks
➢ Device-to-device error: ±5%
➢ Channel-to-channel error: ±5%
EMI and audible noise reduction
➢ Phase delay and phase inverting scheme
➢ Slew rate control function
Flexible LED lighting pattern control
LED open/short detection per channel
Auto power save mode when all LEDs off >
32ms
Under voltage lock out and over temperature
protection
1MHz I2C interface, 4 selectable addresses:
20h, 21h, 24h, 25h
Power supply: 2.7V~5.5V
QFN 4mmX4mmX0.85mm-32L package
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Features
PDA/MP3/MP4/CD/Mini display
Smart home appliance
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AW21018
Feb. 2022 V1.1
Typical Application Circuit
VLED
C3
1μF
VDD
VIO
27 V
DD
LED18
26
LED17
25
AD1
AD0
LED16
R1
4.7kΩ
R2
4.7kΩ
30 EN
17
RG
16
RR
en
AW21018
29 SCL
28 SDA
LED3 3
RB
31 ISET
LED2 2
RG
1
RR
33
GND
LED1
on
REXT
4kΩ
RB
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MCU
18
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C2
0.1μF
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C1
1μF
Note: The resistor RR /RG /RB are only thermal reduction. And they are determined by VLED , VF of LED, VHR of LEDx and I LED .
RX=(VLED -VFX-VHR)/ILED .
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Figure 1 AW21018 Application Circuit
Pin Configuration And Top Mark
AW21018QNR Marking
(Top View)
25
32
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AW21018QNR
(Top View)
1
24
33
GND
17
8
16
9
RNAL – AW21018QNR
XXXX – Production Tracing Code
Figure 2 Pin Configuration and Top Marking
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AW21018
Feb. 2022 V1.1
Pin Definition
NAME
DESCRIPTION
1~18
LED1~LED18
Constant current sink, connect to LED’s cathode.
19~24
NC
Not connected
25
AD0
I2C interface device address, connects to GND, VDD for different device addresses of
I2C.
26
AD1
I2C interface device address, connects to GND, VDD for different device addresses of
I2C.
27
VDD
Power supply: 2.7V~5.5V.
28
SDA
Serial data I/O for I2C interface.
29
SCL
Serial clock input for I2C interface.
30
EN
Shutdown the chip when pulled low.
31
ISET
When REXT=4.0kΩ, global current of LED is 40mA.
32
NC
Not connected
33
GND
Ground
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on
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No.
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AW21018
Feb. 2022 V1.1
Functional Block Diagram
POR
VDD
BG
OTP
OSC
Open/Short
Detect
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UVLO
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GND
Phase
Control
AD0
PWM
Modulation
en
EN
BRx
I2C
AD1
Digital
Control
LED
DRIVER
SLx
SCL
SDA
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GCC
LED1
LED2
LED18
Global Current
Setting
on
ISET
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Figure 3 Functional Block Diagram
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AW21018
Feb. 2022 V1.1
Typical Application Circuits
VLED
C3
1μF
VIO
27 V
DD
LED18
26
LED17
25
AD1
AD0
LED16
R1
4.7kΩ
R2
4.7kΩ
30 EN
MCU
RLED
17
RLED
16
RLED
AW21018
29 SCL
28 SDA
LED3 3
RLED
31 ISET
LED2 2
RLED
1
RLED
33
GND
LED1
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REXT
4kΩ
18
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C2
0.1μF
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C1
1μF
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VDD
on
Note: The resistor RLED is only thermal reduction, and it is determined by VLED , VF of LED, VHR of LEDx and ILED .
RLED =(VLED -VF-VHR)/ILED .
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Figure 4 AW21018 Application Circuit
VDD
C1
1μF
C2
0.1μF
18
RB
17
RG
16
RR
29 SCL
28 SDA
LED3 3
RB
31 ISET
LED2 2
RG
1
RR
LED18
26
LED17
AD1
AD0
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R1
4.7kΩ
LED16
R2
4.7kΩ
30 EN
MCU
REXT
4kΩ
C3
1μF
27 V
DD
25
VIO
VLED
33
AW21018
GND
LED1
Note: The resistor RR /RG /RB are only thermal reduction. And they are determined by VLED , VF of LED, VHR of LEDx and I LED .
RX=(VLED -VFX-VHR)/ILED .
Figure 5 AW21018 Application Circuit(RGB)
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AW21018
Feb. 2022 V1.1
Ordering Information
Temperature
Package
Marking
Moisture
Sensitivity Level
Environmental
Information
Delivery Form
AW21018QNR
-40℃～85℃
QFN
4mmX4mmX0.85m
m-32L
RNAL
MSL3
ROHS+HF
6000 units/
Tape and Reel
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Part Number
Parameter
VDD
Input voltage
CIN
Input capacitance
TA
Operating free-air temperature range
Min.
Typ.
Max.
Unit
2.7
3.6
5.5
V
0.1
1
100
μF
-40°
25
85
°C
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Symbol
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Recommended Operating Conditions
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Absolute Maximum Ratings(NOTE1)
PARAMETERS
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Supply voltage range VDD
RANGE
-0.3V to 6V
Input voltage range
SCL, SDA, EN, AD0, AD1
-0.3V to VDD
Output voltage range
LED1~LED18
-0.3V to VDD
42°C/W
Junction-to-case (top) thermal resistance θJC
45°C/W
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Junction-to-ambient thermal resistance θJA
-40°C to 85°C
Operating free-air temperature range
150°C
Storage temperature TSTG
-65°C to 150°C
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Maximum operating junction temperature TJMAX
260°C
Lead temperature (soldering 10 seconds)
ESD (NOTE 2)
HBM
±2000V
CDM
±1500V
Test condition:
Latch-Up
+IT：200mA
JESD78E
-IT：-200mA
NOTE1: Conditions out of those ranges listed in "absolute maximum ratings" may cause permanent damages
to the device. In spite of the limits above, functional operation conditions of the device should within the ranges
listed in "recommended operating conditions". Exposure to absolute-maximum-rated conditions for prolonged
periods may affect device reliability.
NOTE2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Test
method: MIL-STD-883J Method 3015.9
EIA/JESD22-C101F(CDM)
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AW21018
Feb. 2022 V1.1
Electrical Characteristics
TA=36°C, VDD=3.6V (unless otherwise noted), REXT=4kΩ, PWMRES=8bit.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
5.5
V
5
μA
3
10
μA
3
10
μA
2
4
mA
8
10
mA
0.1
1
μA
40
42
mA
5
%
100
150
mV
ILEDX=40mA
120
200
mV
ILEDX=60mA
180
300
mV
16
17.12
MHz
Power supply voltage and current
VCC
Power supply voltage
ISD_VCC
Shutdown current of VCC
VEN=GND
Standby current of VCC
VEN=3.6V,CHIPEN=0
Power-save mode current
consumption
VEN=3.6V, GCR.APSE=1,
All LEDs off >32ms
IACT_VCC
Quiescent current in active
mode
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VEN=VCC,
GCR.CHIPEN=1
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ISTB_VCC
2.7
VEN=VCC,
Iout=20mA per LEDx
Output leakage current
VEN=0V,
VLEDX=5.5V
IMAX
Maximum global current of
LEDX
GCCR.GCC=0xFF,
BRX=COLX=0xFF
IMATCH
Output current match
accuracy
GCCR.GCC=0xFF,
SLX= BRx =0XFF
VDROPOUT
Dropout voltage when the
LED current has dropped
5%
on
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ILEAKAGE
38
-5
TSD
OSC clock frequency
Thermal shutdown
threshold
Thermal shutdown
hysteresis
14.88
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FOSC
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ILEDX=20mA
165
°C
25
°C
AD0,AD1, EN
VIL
VIH
VIL
VIH
Input low level
EN
Input high level
EN
Input low level
AD0,AD1
0.4
1.4
AD0,AD1
VOL
Output low level
SDA,IOL = 10 mA
VIH
Input high level
SCL, SDA
VIL
Input low level
SCL, SDA
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0.7*VCC
EN
7
V
0.3*VCC
Input high level
Internal pull down
RENPD
resistance
2
I C Interface
V
V
V
Ω
1M
0.1
1.2
V
V
0.4
V
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AW21018
Feb. 2022 V1.1
I2C INTERFACE TIMING
FAST MODE
MIN
MAX
-
400
-
1000
kHz
0.26
-
μs
0.5
-
μs
0.26
-
μs
(Repeat-start) START condition hold
time
0.6
-
TLOW
Low level width of SCL
1.3
-
THIGH
High level width of SCL
0.6
-
TSU:STA
(Repeat-start) START condition setup
time
0.6
THD:DAT
Data hold time
0
TSU:DAT
Data setup time
0.1
TR
Rising time of SDA and SCL
TF
Falling time of SDA and SCL
TSU:STO
STOP condition setup time
TBUF
Time between
condition
tLOW
0.26
-
μs
-
0
-
μs
-
0.05
-
μs
-
0.3
-
0.12
μs
-
0.3
-
0.12
μs
0.6
-
0.26
-
μs
1.3
-
0.5
-
μs
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tHIGH
tR
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tBUF
stop
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SDA
en
THD:STA
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MAX
Interface clock frequency
and
VIH
VIL
tF
VIH
SCL
Stop
UNIT
MIN
FSCL
start
FAST MODE PLUS
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PARAMETER
VIL
tHD:STA
Start
tHD:DAT
tSU:DAT
tSU:STA
Start
tSU:STO
Stop
Figure 6 I2C Interface Timing
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AW21018
Feb. 2022 V1.1
Detailed Functional Description
OVERVIEW
AW21018 is an18 channel multi-function LED driver with I2C interface. Each channel has individual 8-bit DC
current setting for color-mixing and maximum 12-bit PWM resolution for brightness control. The global current
of each channel is recommended to be 40mA configured via register and external resistor REXT.
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Phase-control, spread spectrum technology and slew rate control are utilized to reduce EMI and audible noise
caused by MLCC. Output current of each LED can be controlled by one pattern or be configured independently.
The integrated pattern controller provides breathing or group dimming control. The breathing mode includes
auto breathing and manual control mode. All breathing parameters are configurable including rising/falling
slope, on/off time, repeat times and brightness.
OPERATION MODE AND RESET
RESET
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Power On Reset
Upon initial power-up, the AW21018 is reset by internal power-on-reset, and all registers are reset to default
value, and the chip is shut down.
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Once the supply voltage VDD drops below the threshold voltage VPOR(2.0V), the power-on-reset will reset the
chip again. By reading the bit PUST of the register UVCR (address 60h), whether the chip has been reset can
be detected.
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When the VDD ramps up above the threshold voltage VPOR (2.0V) and EN is high, POR is pulled high, meanwhile
the chip enters into initialization mode. The chip needs about 2ms to load the efuse information in initalization
mode. After initialization, it works in lower-power mode. About 200μs delay is required after CHIPEN is pulled
up, otherwise, internal OSCCLK may work incorrectly. Only in low-power and active mode, registers could be
configurated. The recommended operation timing is shown as bellow.
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VDD
EN
POR
2ms
INITIAL
initial
CHIPEN
(bit CHIPEN of GCR register)
Note: The chip needs about 2ms for
initalization after power on
Note: Recommend CHIPEN=1 after Initial
200μs
..
OSC
Configuring
Time
MODE
Note: OSC operates stable,which needs
200μs after CHIPEN=1
Internal registers are configurable
Shutdown
Initialization
Standby
Active
Figure 7 Power On Timing
Software Reset
By writing 00h to register RESET (address 70h) in active mode, the software reset is triggered. Then all
registers will be reset to the default value and the chip enters into initialization mode.
After the software reset command is input by I2C, it needs to wait at least 2ms before any other I2C commands
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AW21018
Feb. 2022 V1.1
are accepted.
Software
Reset
Note: The device need about 2ms for
initalization after power on
2ms
INITIAL
initial
CHIPEN
(bit CHIPEN of GCR register)
Note: Recommend CHIPEN=1 after Initial
200us
..
Configuring
Time
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OSC
MODE
Note: OSC operate stable need 200μs
after CHIPEN=1
Internal registers are configurable
Active
Initialization
Standby
en
Figure 8 Software Reset Timing
Active
OPERATING MODE
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Shutdown mode
The AW21018 enters into shutdown mode automatically when EN is pulled to low. In this situation, I2C interface
is not accessible, all registers will be reset and can not be configured.
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Initialization mode
If EN is high, AW21018 enters into initialization mode. During this period, all registers will be reset and chip
starts loading efuse information automatically.
Standby mode
Active mode
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After initialization, the AW21018 enters into standby mode when the bit CHIPEN of the register GCR (address
20h) is ‘0’, or UVLO is triggered in active mode. In this mode, only POR and I2C circuits work. I2C interface is
accessible, and all registers can be configured now.
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The AW21018 enters into active mode when EN is high and the bit CHIPEN of the register GCR (address 20h)
is ‘1’.
Power save mode
In active mode, when the bit APSE of the register GCR (address 20h) is set to “1”, the auto power-save function
is enabled. When all LEDs are switched off and the value of all registers BR00L~BR17H are 00h and write
00h to register UPDATE(address 45h) for more than 32 ms, AW21018 automatically enters into power saving
mode. In power save mode, most analog blocks are disabled to minimize power consumption, but the registers
retain the data and keep it available via I2C. Once writing a non-zero value into any register among
BR00L~BR17H, the chip exits power-save mode immediately.
Thermal shutdown
The AW21018 enters the thermal shutdown mode when the junction temperature exceeds 165°C(typical)
automatically. In this mode, all the LEDx outputs are shut down. If the junction temperature decreases below
140°C(typical), the AW21018 returns to active mode.
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AW21018
Feb. 2022 V1.1
VDD power on
EN = L
Shutdown
From all modes
EN = H
Software reset
Active mode
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Initialization
CHIPEN=1
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Standby
CHIPEN=0
APSE=1 &&
All LEDs off > 32ms
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OTST=1
Power Save
Active
Thermal Shutdown
APSE=0 or
Write a non-zero value
to register BRx
OTST=0
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Figure 9 AW21018 operating mode transition
FEATURE DESCRIPTION
on
CURRENT SETTING
The average output current of LEDx (x=1~18) can be expressed by the following formula,
𝑮𝑪𝑪 𝑺𝑳𝒙
𝑩𝑹𝒙
×
×
𝟐𝟓𝟓 𝟐𝟓𝟓 𝟐𝑷𝑾𝑴𝑹𝑬𝑺
𝒙 = 𝟏~𝟏𝟖
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𝑰𝑶𝑼𝑻(𝒙) = 𝑰𝑴𝑨𝑿 ×
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Where IMAX=40mA when REXT=4KΩ, GCC is the 8bit global current configured by the register GCCR (address
58h), SLx is 8bit individual constant current parameter configured by the register SLx (address 46h~57h) ,
PWMRES is 8bit/9bit/12bit PWM resolution configured by the register GCR (address 20h), and BRx is
8bit/9bit/12bit individual PWM modulated current parameter configured by the register BRxL/BRxH (address
21h~44h).
PWM MODLULATION
Dither Function
When PWMRES[1:0] of GCR(address 20h) equal to ‘11’, dither function is enabled. Then the final output PWM
has the frequency equal to 9 bits and resolution equal to 12 bits. This is achieved by 9 bits PWM modulation
and 3bits digital dither control. For 3-bit dither, every PWM in the 8 PWM group can be added one LSB or not
according to the 8-bit digital dither timing.
PWM Frequency
The output PWM frequency is decided by bits CLKFRQ [2:0] and PWMRES[1:0] in register GCR (address
20h). Following table shows the relationship of PWM frequency, the CLKFRQ [2:0] and PWMRES[1:0]. To
avoid the MLCC audible noise, it’s recommended to use the PWM frequency lower than 500Hz or higher than
20kHz.
CLKFRQ[2:0]
BR Resolution
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000
001
11
010
011
100
101
110
111
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AW21018
Feb. 2022 V1.1
8bit
62k
32k
4k
2k
1k
500
244
122
9bit
32k
16k
2k
1k
488
244
122
-
12bit
4k
2k
244
122
-
-
-
-
9bit+3bit dither
32k
16k
2k
1k
488
244
122
-
.
PWM Phase Control
Phase2
LED4~LED6
Phase3
LED7~LED9
0
π /3
2π /3
Phase4
3π /3
LED10~LED12
Phase5
on
4π /3
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Phase1
LED1~LED3
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To reduce the peak load current and ceramic-capacitor audible ringing, AW21018 supports 6 PWM phase
shifting (Phase1~Phase6) and phase-inverting scheme. When setting PDE in register PHCR (address 59h) to
‘1’, the phase shifting scheme is enabled, and each adjacent phase differs by 60 degrees，which meaning
only 3 of 18 LEDs could switch on in the same time.
LED13~LED15
Phase6
5π /3
LED16~LED18
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Figure 10 Phase shift scheme
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When setting PINVTEn in register PHCR (address 59h, n=0~5) to ‘1’, the PWM phase of the even-numbered
channels is inverted. As shown below, if setting PINVTEn to ‘1’, the even-numbered channels are rotated 180
degrees counterclockwise when the odd-numbered channels are not, which is good for reducing the inputcurrent ripple. For an example, when setting PINVTE0 to ‘1’, LED2 is rotated 180 degrees counterclockwise
while the LED1 and LED3 are not.
n=0,2,4
PINVTE=“0”
LED[3n +1 ]
LED[3n +2 ]
LED[3n +3 ]
PINVTE=“1”
LED[3n +1 ]
LED[3n +2 ]
LED[3n +3 ]
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AW21018
Feb. 2022 V1.1
n=1,3,5
PINVTE=“0”
LED[3n +1 ]
LED[3n +2 ]
LED[3n +3 ]
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PINVTE=“1”
LED[3n +1 ]
LED[3n +2 ]
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LED[3n +3 ]
Figure 11 Phase invert scheme
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PWM Disable
If the bits DCPWM [2:0] in register SSCR (address 5Fh) is set to “111”, the PWM output is disabled, and the
duty of each PWM is forced to 100%. In this mode, the BRx parameter is not valid, but the SLx parameter is
still effective.
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It should be noted that when performing open-short detection, the bits DCPWM [2:0] need to be set to “111”.
GROUP CONTROL MODE
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AW21018 supports group control mode, in this mode, all selected LEDs are controlled by the group control
registers (GSLR, GSLG, GSLB). The register GCFG select which LEDs are controlled by group control register.
There are total 6 control bits (GEx), each bit set adjacent 3 LEDs are included in or not. User can configure
group control register to setting common brightness and color for all selected LED, so as to simplify lighting
effect programming and speed up display refreshing via I2C interface.
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If bit GSLDIS in register GCFG (address 8bh) is ‘1’, the color parameters of the grouped LED are no longer
configured by register GSLR/G/B but by individual register (SL0~SL15).
The detailed configurations are as follows.
LED
GE
Brightness
Color
GE=0
GE=1
GE=0 or
GSLDIS=1
GE=1 and
GSLDIS=0
BR00
GBR
SL00
GSLR
BR01
GBR
SL01
GSLG
3
BR02
GBR
SL02
GSLB
4
BR03
GBR
SL03
GSLR
BR04
GBR
SL04
GSLG
BR05
GBR
SL05
GSLB
…
…
…
…
BR12
GBR
SL12
GSLR
BR13
GBR
SL13
GSLG
BR14
GBR
SL14
GSLB
1
2
5
GCFG[0]
GCFG[1]
6
…
…
13
14
15
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GCFG[4]
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AW21018
Feb. 2022 V1.1
16
17
GCFG[5]
18
BR15
GBR
SL15
GSLR
BR16
GBR
SL16
GSLG
BR17
GBR
SL17
GSLB
Note: GBR={GBRH,GBRL}.
SPREAD SPECTRUM
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PWM is a troublesome for some application which is concerned about EMI. AW21018 has spread spectrum
function to optimize the EMI performance. If bit SSE in register SSCR (address 5Fh) is set to ‘1’, spread
spectrum function is enabled. By setting the bit SSR in register SSCR, four spread spectrum range
±5%/±15%/±25%/±35% can be selected. The total electromagnetic emitting energy can spread into a wider
range of frequency band that significantly degrades the peak energy of EMI.
RGB CONFIGURE MODE
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In RGB applications, every 3 LEDs in RGB share a same BR parameter. To achieve fast register configuration
for RGB applications, AW21018 provides an RGB configuration mode by setting the bit RGBMD in register
GCR2 (address 61h).
on
If RGBMD=1, register BR00~BR05 configure brightness parameters for corresponding 6 RGB groups. In other
words, in RGB mode, only registers BR00~BR05 need to be configured, and the registers BR06~BR17 are
not valid any more.
If RGBMD=0, register BR00~BR17 configure brightness parameters for corresponding 18 LEDs independently,
more details as follows,
BR parameter source
cC
LED
RGBMD=0
BR00
2
BR01
3
BR02
4
BR03
5
BR04
6
BR05
…
…
13
BR12
14
BR13
15
BR14
16
BR15
17
BR16
18
BR17
aw
ini
1
RGBMD=1
BR00
BR01
…
BR04
BR05
Note: BRxx = {BRxxH,BRxxL}
SINGLE BYTE CONFIGURATION MODE
By default, every LED has a 12bits BR parameter with BRxxL and BRxxH. The effective bit of BRxxH is 4bit.
However, AW21018 provides a single byte configuration mode by setting the bit SBMD in register GCR2
(address 61h). In single byte applications, every LED has a 8bit BR parameter configured by BR00L~BR08H.
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It is worth noting that the effective bit of BRxH(xx is 00~05) is 8 bit in single byte mode compared with default
mode.More details are as follows.
SBMD=1
1
{BR00H,BR00L}
BR00L
2
{BR01H,BR01L}
BR00H
3
{BR02H,BR02L}
BR01L
4
{BR03H,BR03L}
BR01H
5
{BR04H,BR04L}
BR02L
6
{BR05H,BR05L}
BR02H
…
…
…
13
{BR12H,BR12L}
14
{BR13H,BR13L}
15
{BR14H,BR14L}
16
{BR15H,BR15L}
BR07H
17
{BR16H,BR16L}
BR08L
18
{BR17H,BR17L}
BR08H
en
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SBMD=0
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BR parameter source
LED
BR06L
BR06L
on
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BR07L
PATTERN CONTROLLERS
cC
There is a breathing pattern controller in the chip. When bit PATE in register PATCFG (address 80h) is set to
‘1’, breathing pattern controller is enabled. Pattern controller can be configured as autonomous breathing mode
or manual-controlled mode. When corresponding GE is configured as ‘1’, if in pattern controlled mode, each
led group (consisting of three adjacent LEDs) can enter into breathing mode. When GE is ‘0’, the three adjacent
LEDs exit breathing mode directly. For example, when setting GCFG = 0x01 and in pattern controlled mode,
LED1~LED3 will work in breathing mode and other LEDs will work in default mode.
aw
ini
Autonomous Breathing Mode
When bit PATE and PATMD in register PATCFG are set to ‘1’, the pattern controller works in autonomous
breathing mode. In this mode, the pattern controller will generate a breathing lighting effect, which is configured
by the user-defined timing parameter. The waveform of the breathing lighting effect is shown in the following
figure. The parameter T0~T3 define 4 key periods in a complete breathing cycle. T0~T3 composite a breathing
loop, denoting the rise-time, on-time, fall-time and off-time respectively. Register GBRH (address 86h) and
GBRL (address 87h) control the max and min brightness of the breathing respectively.
GBRH
GBRL
T0
T1
T2
T3
Figure 12 LED breath timing in pattern mode
The start point and end point of autonomous breathing loop are configurable. The loop starting point could be
selected among T0~T3, which is set by bits LB [1:0] in register PATT2 (address 84h). The end point of the loop
can only be selected between the end of T3 and the end of T1, which is determined by bits LE [1:0] in register
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PATT2. If bits LE [1:0] is not “00”, the end point of breathing loop is the end of T1, and the loop counter
increment by 1 at the end of T1. If bit LE [1:0] is “00”, the loop end point is the end of T3, and the loop counter
increment by 1 at the end of T3.
The repeat times is decided by bit RPT [11:8] of register PATT2 (address 84h) and RPT [7:0] of register PATT3
(address 85h). When setting RPT [11:0] to ‘0’, the breathing pattern will run unlimited times.
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After the breathing pattern is over, the status bit PATIS in register PATGO (address 81h) will be set to ‘1’, and
PATIS will be cleared to ‘0’ after reading out through I 2C bus. Once breathing loop start again or pattern
controller switches to manual mode by setting PATE bit to ‘0’, the PATIS will also be cleared.
When bit RUN in register PATGO is set to ‘1’, breathing pattern is started. The full process of the autonomous
breathing is as follows:
Set GSLR/G/B, GBRH/L parameter.
2.
Set GCFG to select the LED in breathing pattern mode or not.
3.
Configure PATT0, PATT1, PATT2, and PATT3 for parameters T0~T3, start/stop point, and repeat
times.
4.
Set PATE=1 to enable breathing pattern mode.
5.
Set PATMD=1 to select auto breathing mode.
6.
Set RUN=1 to start the breath pattern.
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Manual Control Mode
en
1.
on
If bit PATMD is set to ‘0’, manual control mode is selected. In manual control mode, user could program the bit
SWITCH of register PATCFG to control the output of pattern controller. When bit SWITCH is ‘1’, the output of
pattern controller is decided by register GBRH. When bit SWITCH is set as “0”, the output is the decided by
register GBRL.
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If bit RAMPE in register PATCFG is set to ‘1’, the smooth ramp up/down will be enabled. At the same time, if
SWITCH changes from “0” to ‘1’, the output will be ramp up to GBRH smoothly. Similarly, if SWITCH changes
from “1” to ‘0’, the output of the pattern controller will ramp down to GBRL smoothly.
However, if the RAMPE is set to ‘0’, the output of the pattern controller will change to GBRH or GBR directly
with no ramp as the SWITCH changes.
aw
ini
GBRH
PATCFG.RAMPE =0
GBRL
GBRH
PATCFG.RAMPE =1
fade-out
fade-in
GBRL
Set PATCFG.SWITCH =1
Set PATCFG.SWITCH =0
Figure 13 Manual Control Mode
PROTECTION FEATURES
Under Voltage Lock Out (UVLO)
When bit UVDIS of the register UVCR (address 60h) is set to ‘0’, the chip monitors the voltage of VDD. If the
supply voltage drops below threshold (2.5V typically), the bit UVST of the register UVCR (address 60h) will be
set to ‘1’. After read-out, the register UVCR will be clear.
If both bit UVDIS and bit UVPD of the register UVCR (address 60h) is set to ‘0’, UVLO protection function is
enabled. Once the event of under voltage occurs, the bit CHIPEN of the register GCR (address 20h) will be
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cleared to ‘0’, and then the chip will enter into standby mode. If the voltage of VDD rises above 2.6V then write
“1” to bit CHIPEN, the chip will enter into active mode again.
By default, control bits UVDIS, UVPD are all “0”. Both UVLO monitor and protection are enabled.
Over Temperature Protection (OTP)
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When bit OTDIS of the register OTCR (address 5Eh) is set to ‘0’, the over-temperature detection is enabled.
Once the temperature of this chip reaches 165°C, the over-temperature condition is detected, and the bit OTST
of the register OTCR (address 5Eh) will be set to ‘1’. The OTST will be cleared to ‘0’ after reading the register
OTCR.
en
If both bit OTDIS and bit OTPD of the register OTCR (address 5Eh) are set to ‘0’, the Over-Temperature
Protection (OTP) function is enabled. Once the temperature is over 165°C, the bit CHIPEN of the register GCR
(address 20h) will be cleared to ‘0’, and then the chip will enter into thermal shutdown mode. When the
temperature returns below 140°C, the chip will enter into active mode again after writing “1” to bit CHIPEN.
By default, control bits OTDIS and OTPD are all “0”, both OT monitor and OT protection are enable.
LED Open/Short Detection
The valid detect result is determined by:
⚫
Short Detection: VLED > VDD- VTHSHORT
⚫
Open Detection: VLED < VTHOPEN
on
fid
AW21018 supports LED open/short detection. When bit OSDE[1:0] of the register OSDCR(address 5Ah) is
set to “10” , short detection is enabled, and the detection results can be read out via the registers
OSST0~2(5Bh~5Dh). Similarly, when set bit OSDE [1:0] of the register OSDCR (address 5Ah) to “11”, open
detection is enabled, and the results also can be read out via the registers OSST0~2.
Where VTHOPEN: Threshold of open detection (When OTH=0, VTHOPEN = 0.1V,else VTHOPEN = 0.2V;).
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VTHSHORT: Threshold of short detection (When STH=0, VTHSHORT = 0.5V,else VTHSHORT = 1V).
VLED:The voltage of chip LED pin.
aw
ini
We recommend the bit DCPWM[2:0] of the register SSCR (address 5Fh) being set to “111” and maintain about
1mA current of each LED when the open/short function is enabled.
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AW21018
Feb. 2022 V1.1
I2C INTERFACE
l
The AW21018 supports the I2C protocol. The maximum frequency supported by the I2C is 1 MHz. The pull-up
resistor for the SDA and SCL can be selected from 1k to 10kΩ. Usually, 4.7kΩ is recommended for 400 kHz
I2C, 1kΩ is recommended for 1 MHz I2C. The voltage from 1.8V to 3.3V is allowed for the I2C interface.
Additionally, the I2C chip supports continuous read and write operations. Particularly, if register address is
00h or 01h, the slave chip will poll register address between 00h and 01h.
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CHIP ADDRESS
GND/GND
GND/VDD
010
VDD/GND
VDD/VDD
A4:A3
A2:A1
00
00
00
01
01
00
01
01
A0
Chip Address
Broadcast Address
20h
fid
A7:A5
0/1
21h
24h
1Ch
25h
on
AD PIN
en
The I2C chip address is 7-bit (A7~A1), followed by the bit R/W (A0). Set A0 to “0” for writing and “1” for reading.
The values of bit A1 and A2 are depended on the pin AD0. A3 and A4 are depended on the pin AD1. There are
2 options: VDD and GND. The A7 to A5 is “010” constantly. The chip also supports using a broadcast slave
address of 1Ch. All slave addresses as followed.
I2C START/STOP
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All transactions begin with a START and are terminated by a STOP sent by master to slave. A high-to-low
transition on the SDA input/output while the SCL input is high defines a START condition. A low-to-high
transition on the SDA input/output while the SCL input is high defines a STOP condition.
In particular, the bus stays busy when a repeated START (Sr) is generated instead of a STOP signal
corresponding to the lastest START (S). Sr and S are usually regarded as equivalent.
aw
ini
SDA
SCL
S/Sr
P
S: START condition
Sr: START Repeated condition
P: STOP condition
Figure 14 I2C START/STOP Condition Timing
DATA VALIDATION
When SCL is high level, SDA level must be constant. SDA can be changed only when SCL is low level.Each
SCL pulse corresponds to one bit data transaction.
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AW21018
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SDA
SCL
Change
of Data
Allowed
Figure 15 Data Validation Diagram
en
ACK (ACKNOWLEDGEMENT)
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Data Line
Stable
Data Valid
ACK means the successful transaction of I 2C bus data. During writing cycle, after master sends 8-bit data,
SDA must be released by master and SDA is pulled down to GND by slave chip when slave sends ACK.
fid
During reading cycle, after slave chip sends 8-bit data, slave releases the SDA and waits for ACK from master.
If master sends ACK with STOP condition, slave chip sends the next data. If master sends NACK, slave chip
stops sending data and waits for I2C stop.
on
Data Output
by Transmitter
Not Acknowledge（NACK）
Data Output
by Receiver
Acknowledge（ACK）
1
cC
SCL From
Master
2
8
9
Clock Pulse for
Acknowledgement
START
condition
Figure 16 I2C ACK Timing
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WRITE CYCLE
One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock
(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the
SDA line aborts the current transaction during the high state of the SCL. New data should be sent to SDA bus
during the low SCL state. This protocol allows a single data line to transfer both command/control information
and data using the synchronous serial clock.
Each data transaction is composed of a start condition, a number of byte transfers and a stop condition to
terminate the transaction. Every byte written to the SDA bus must be 8 bits and is transferred with the most
significant bit first. After each byte, an Ack signal must follow.
1.
In a write process, the following steps should be followed:
2.
Master chip generates START condition. The “START” signal is generated by pulling down the SDA
signal while the SCL signal is high.
3.
̅ = 0.
Master chip sends slave address (7-bit) and the data direction bit R/𝑊
4.
Slave chip sends acknowledge signal if the slave address is correct.
5.
Master sends control register address (8-bit).
6.
Slave sends acknowledge signal.
7.
Master sends data byte to write to the addressed register.
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AW21018
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8.
Slave sends acknowledge signal.
9.
If master send more data bytes, the control register address will be incremented by one after
acknowledge signal (repeat step f and g).
10. Master generates STOP condition to indicate write cycle ends.
SCL
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
A6 A5 A4 A3 A2 A1 A0 R/WAck A7 A6 A5 A4 A3 A2 A1 A0 Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack
Start
Device Address
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SDA
Register Address
Write Data
Figure 17 I2C Write Byte Cycle
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READ CYCLE
Stop
In a read cycle, the following steps should be followed:
Master chip generates START condition
2.
Master chip sends slave address (7-bit) and the data direction bit (R/W = 0).
3.
Slave chip sends acknowledge signal if the slave address is correct.
4.
Master sends control register address (8-bit)
5.
Slave sends acknowledge signal
6.
Master generates STOP condition followed with START condition or REPEAT START condition
7.
Master chip sends slave address (7-bit) and the data direction bit (R/W = 1).
8.
Slave chip sends acknowledge signal if the slave address is correct.
9.
Slave sends data byte from addressed register.
cC
on
fid
1.
10. If the master chip sends acknowledge signal, the slave chip will increase the control register address by
one, then send the next data from the new addressed register. In particular, if register address is 00h or
01h, the slave chip will poll register address between 00h and 01h.
11. If the master chip generates STOP condition, the read cycle ends.
0
1
2
3
4
5
A6
A5
A4
A3
A2
A1
aw
ini
SCL
SDA
start
6
7
8
0
1
2
3
4
5
6
A0 R/W Ack A7
A6
A5
A4
A3
A2
A1
Device Address
……
Using
Repeat start……
1
2
3
4
5
A6
A5
A4
A3
A2
A1
……
P
6
7
8
0
A0 R/W Ack D7
S
1
...
6
D6 …… D1
7
8
D0 Ack
stop
Read Data
Device Address
Separated
Read/write
transaction ……
A0 Ack
Register Address
0
RS
8
7
0
1
2
3
4
5
A6
A5
A4
A3
A2
A1
6
7
8
0
A0 R/W Ack D7
Device Address
1
...
6
7
D6 …… D1
D0
Read Data
8
Ack
stop
Figure 18 I2C Read Byte Cycle
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AW21018
Feb. 2022 V1.1
Register Configuration
ADDR
R/W
NAME
D7
20h
RW
GCR
APSE
21h
RW
BR00L
22h
RW
BR00H
…
…
…
43h
RW
BR17L
44h
RW
BR17H
45h
W
UPDATE
UPDATE
46h
RW
SL00
SL00
…
…
…
57h
RW
SL17
58h
RW
GCCR
59h
RW
PHCR
5Ah
RW
OSDCR
5Bh
R
OSST0
5Ch
R
OSST1
5Dh
R
OSST2
5Eh
RW
OTCR
5Fh
RW
SSCR
60h
RW
UVCR
REXT_ST
61h
RW
GCR2
62h
RW
GCR3
70h
RW
RESET
80h
RW
PATCFG
81h
RW
PATGO
82h
RW
PATT0
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Register List
D6
D5
D4
D3
83h
RW
PATT1
84h
RW
PATT2
85h
RW
PATT3
RPT[7:0]
00h
86h
RW
GBRH
GBRH
00h
87h
RW
GBRL
GBRL
00h
88h
RW
GSLR
GSLR
00h
CLKFRQ
D2
-
D1
PWMRES
D0
DEF
CHIPEN
00h
BR00L
00h
BR00H
…
tia
…
BR17L
00h
BR17H
00h
00h
00h
en
-
-
…
…
SL17
00h
GCC
00h
fid
PDE
00h
l
-
OTH
TROF
STH
OSDE
00h
00h
OP/ST [15:8]
00h
00h
TRTH
00h
CLT
00h
OTST
SSE
SSR
UVST
PUST
OCPTH
UVPD
UVDIS
00h
BSDIS
UDMD
SBMD
RGBMD
00h
-
-
OTPD
OP/ST [17:16]
TRST
DCPWM
OTDIS
APS2E
SRR
SWITCH
-
RAMPE
PATIS
PATMD
PATE
00h
PATST
RUN
00h
T1
00h
T3
00h
RPT[11:8]
00h
T2
LB
00h
02h
T0
LE
SRF[1:0]
RESET/ID
-
aw
ini
00h
OP/ST [7:0]
on
-
PINVTE
89h
RW
GSLG
GSLG
00h
8Ah
RW
GSLB
GSLB
00h
8Bh
RW
GCFG
www.awinic.com
-
GSLDIS
21
GE5
GE4
GE3
GE2
GE1
GE0
00h
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Register Detailed Description
GCR: Global Control Register (Address 20h)
Symbol
R/W
7
APSE
RW
Description
Auto power save enable
0: disable
1: enable
0
RW
3
reserved
-
000: 16MHz
001: 8MHz
010: 1MHz
011: 512kHz
100: 256kHz
101: 125kHz
110: 62.5kHz
111: 31.25kHz
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CLKFRQ
tia
OSC frequency selection
6:4
Default
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Bit
-
0
00
PWMRES
RW
0
CHIPEN
RW
Chip enable
0: disable
1: enable
on
fid
2:1
Brightness resolution selection
00: 8bit
01: 9bit
10: 12bit
11: 12bit with dither enabled
cC
000
0
BRxxL/BRxxH: Brightness Control Register (Addredd 21h~44h)
Symbol
R/W
7:0
BRxxL
RW
3:0
BRxxH
RW
Description
Default
Brightness control LSB8 for LED
00h
Brightness control MSB4 for LED
0000
aw
ini
Bit
UPDATE: Update Register (Address 45h)
Bit
Symbol
R/W
7:0
UPDATE
W
Description
Write 00h to update BR and SL registers
Default
00h
SLxx: Scaling Register (Address 46h~57h)
Bit
Symbol
R/W
7:0
SLxx
RW
Description
Scaling parameter for LED
Default
00h
GCCR: Global Current Control Register (Address 58h)
Bit
Symbol
R/W
7:0
GCC
RW
www.awinic.com
Description
Global current control register
22
Default
00h
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AW21018
Feb. 2022 V1.1
PHCR: Phase Control Register (Address 59h)
R/W
7
PDE
RW
6:4
reserved
-
3:0
PINVTE
RW
Description
Default
PWM phase delay enable
0: disable
1: enable
0
-
000
Phase invert enable for every 3 LEDs
0: phase not invert
1: phase invert 180 degree for even LEDs
en
OSDCR: Open/Short Detect Control Register (Address 5Ah)
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Symbol
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Bit
0000
Bit
Symbol
R/W
Description
Default
7:4
reserved
-
-
0000
3
OTH
RW
2
STH
RW
RW
fid
1: 0.2V
Short threshold
0: 0.5 V
1: 1 V
on
OSDE
0: 0.1V
Open/short detect enable, must set PWMDIS=111 before
detecting
0x: detect disable
10: short detect enable
11: open detect enable
cC
1:0
Open threshold
0
0
00
OSST: Open/Short Status Register (Address 5Bh/5Ch/5Dh)
Symbol
R/W
Description
aw
ini
Bit
Default
7:0
OSST0
R
Open/Short Status of LED1~8
0: no open/short detected
1: open/short detected
7:0
OSST1
R
Open/Short status of LED9~16
0: no open/short detected
1: open/short detected
00h
R
Open/Short status of LED17~18
0: no open/short detected
1: open/short detected
00
1:0
OSST2
00h
OTCR: Over Temperature Control Register (Address 5Eh)
Bit
Symbol
R/W
Description
Default
Thermal roll off percentage of LED output current
7:6
TROF
www.awinic.com
RW
00: 100%
01: 75%
10: 50%
11: 25%
23
00
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AW21018
Feb. 2022 V1.1
TRST
R
4
OTST
R
Over temperature status
0: normal
1: over temperature occurred
0
0
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5
Thermal roll off status
0: normal
1: thermal roll off occurred
2
OTDIS
RW
RW
Over temperature detect disable
0: OT detect enable
1: OT detect disable
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OTPD
en
3
Over temperature protect disable
0: OT protect enable, when OT event occurs, chip will clear
GCR.CHIPEN to 0
1: OT protect disable
0
0
1:0
TRTH
RW
fid
Temperature roll off threshold
00: 140°C
01: 120°C
11: 90°C
on
10: 100°C
00
SSCR: Spread Spectrum Control Register (Address 5Fh)
R/W
7
DCPWM2
RW
6
DCPWM1
RW
5
DCPWM0
4
Description
cC
Symbol
SSE
Default
0: LED 13~18 PWM duty set by 39h~44h
1: LED 13~18 PWM duty set as 100%
0
0: LED 7~12 PWM duty set by 2Dh~38h
1: LED 7~12 PWM duty set as 100%
0
aw
ini
Bit
RW
0: LED 1~6 PWM duty set by 21h~2Ch
1: LED 1~6 PWM duty set as 100%
0
RW
Spread spectrum enable
0: disable
1: enable
0
Spread spectrum range
3:2
SSR
RW
00: ±5%
01: ±15%
10: ±24%
11: ±34%
00
Spread spectrum period
1:0
CLT
www.awinic.com
RW
00: 1980μs
01: 1200μs
10: 820μs
11: 660μs
24
00
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AW21018
Feb. 2022 V1.1
UVCR: UVLO Control Register (Address 60h)
Symbol
R/W
Description
REXT_ST
R
5
UVST
R
UVLO status
0: normal
1: UVLO detected
Power up status
0: normal
1: power up occurred
00
en
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7:6
Rext status
00: normal
01: Rext is short or OCP
10: Rext is open
11: no exist
Default
l
Bit
0
PUST
R
3
OCPTH
RW
OCP threshold
0: 85mA
1: 55mA
RW
OCP disable
0: enable OCP
1: disable OCP
RW
UVLO protect disable
0: UVLO protect enable, when UVLO occurs, chip will clear
GCR.CHIPEN to 0
1: UVLO protect disable
0
UVLO detect disable
0: UVLO detect enable
1: UVLO detect disable
0
0
UVPD
UVDIS
RW
on
0
0
0
cC
1
OCPD
aw
ini
2
fid
4
GCR2: Global Control Register2 (Address 61h)
Bit
Symbol
R/W
Description
Default
7:5
reserved
-
-
000
4
3:2
BSDIS
UDMD
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RW
I2C broadcast slave address disable
0: I2C broadcast slave address enable
1: I2C broadcast slave address disable
0
RW
BR and SL update mode
00: BR is updated at PWM carrier boundary, and SL does not
need to be updated.
01: Both BR and SL are updated at PWM carrier boundary.
10: BR is updated at fast mode, and SL does not need to be
updated.
11: Both BR and SL are updated at fast mode.
00
25
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AW21018
Feb. 2022 V1.1
RGBMD
RW
Single byte mode for BR
0: disable
1: enable
0
RW
RGB mode enable
0: disable
1: enable, every 3 LEDs uses a common BR.
0
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0
SBMD
GCR3: Global Control Register3 (Address 62h)
Bit
Symbol
R/W
Description
7:4
reserved
-
-
3
APS2E
RW
2
SRR
RW
en
Enable PWMIS0 function
0: disable
1: enable
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1
Slew rate control for LED output rising
1: 6ns
fid
0: 1ns
Default
0000
0
0
Slew rate control for LED output falling
1:0
SRF
RW
00: 1 ns
01: 3 ns
on
10: 6 ns
Bit
Symbol
R/W
7:0
RESET
RW
cC
RESET: Reset Register (Address 70h)
00
11:10 ns
Description
Software reset/ID
Write 00h will reset all registers to their default value.
When read, chip ID is read out.
Default
02h
aw
ini
PATCFG: PAT Configuration Register (Address 80h)
Bit
Symbol
R/W
Description
Default
7:4
reserved
-
-
0000
3
SWITCH
RW
Switch on or off at manual mode.
0: switch LED off
1: switch LED on
2
RAMP
RW
Ramp for manual mode
0: direct set
1: ramp enable when transition
0
0
0
1
PATMD
RW
PAT operation mode
0: manual mode
1: auto breath mode
0
PATE
RW
PAT Enable
0: disable
1: enable
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26
0
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AW21018
Feb. 2022 V1.1
PAT Run Control Register (Address 81h)
Bit
Symbol
R/W
Description
Default
7:3
reserved
-
-
00000
2
PATIS
RW
PAT loop over flag
0: pattern is non-over
1: pattern is over
0
PATST
RW
0
RUN
RW
PAT run enable. Transition from 0 to 1 start PAT loop.
en
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1
ABM loop state
0: pattern is in stop state
1: pattern in running
PATT0：PAT Pattern Time 0 (Address 82h)
Bit
Symbol
R/W
Description
T0
RW
0000: 0.00s
0001: 0.13s
0010: 0.26s
0011: 0.38s
0100: 0.51s
0101: 0.77s
0110: 1.04s
0111: 1.60s
1000: 2.10s
1001: 2.60s
1010: 3.10s
1011: 4.20s
1101: 6.20s
1110: 7.30s
1111: 8.30s
0001: 0.13s
0010: 0.26s
0011: 0.38s
1100: 5.20s
0
Default
on
7:4
fid
Pattern rise time
0
0000
Pattern on time
3:0
T1
RW
cC
0000: 0.00s
0100: 0.51s
0101: 0.77s
0110: 1.04s
0111: 1.60s
1000: 2.10s
1001: 2.60s
1010: 3.10s
1011: 4.20s
1100: 5.20s
1101: 6.20s
1110: 7.30s
1111: 8.30s
0000
Bit
aw
ini
PATT1：PAT Pattern Time 1 (Address 83h)
Symbol
R/W
Description
Default
Pattern fall time
7:4
T2
RW
0000: 0.00s
0001: 0.13s
0010: 0.26s
0011: 0.38s
0100: 0.51s
0101: 0.77s
0110: 1.04s
0111: 1.60s
1000: 2.10s
1001: 2.60s
1010: 3.10s
1011: 4.20s
1100: 5.20s
1101: 6.20s
1110: 7.30s
1111: 8.30s
0000: 0.00s
0001: 0.13s
0010: 0.26s
0011: 0.38s
0100: 0.51s
0101: 0.77s
0110: 1.04s
0111: 1.60s
1000: 2.10s
1001: 2.60s
1010: 3.10s
1011: 4.20s
1100: 5.20s
1101: 6.20s
1110: 7.30s
1111: 8.30s
0000
Pattern off time
3:0
T3
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RW
27
0000
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Feb. 2022 V1.1
PATT2 ：Pattern Time 2 (Address 84h)
7:6
Symbol
LE
R/W
Description
RW
Loop stop point
00: stop at the start of T3
Others: stop at the start of T1
LB
RW
3:0
RPT[11:8]
RW
Loop repeat times 4 MSB
Symbol
R/W
7:0
RPT[7:0]
RW -
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Description
Loop repeat times 8 LSB. If RPT[11:0] is all zero, PAT loop will
repeat forever .
on
Bit
fid
PATT3: Pattern Time 3 (Address 85h)
00
l
5:4
Loop start point
00: T0
01: T1
10: T2
11: T3
Default
en
Bit
00
0000
Default
00h
GBRH/GBRL: Group Brightness Register (Address 86h/87h)
R/W
7:0
GBRH
RW
7:0
GBRL
RW
Description
Default
When PATCFG.PATE=1, it is the max fade level of ABM;
When PATCFG.PATE=0, it is the high 4bit of group brightness.
00h
When PATCFG.PATE=1, it is the min fade level of ABM;
When PATCFG.PATE=0, it is the low 8 bit of group brightness.
00h
cC
Symbol
aw
ini
Bit
GSLR/GSLG/GSLB: Group SL Register (Address 88h/89h/8Ah)
Bit
Symbol
R/W
Description
Default
7:0
GSLR
RW
When LEDx (x=1, 4, 7, …) works in group mode, its SL scaling
is decided by GSLR.
00h
7:0
GSLG
RW
When LEDx (x=2, 5, 8, …) works in group mode, its SL scaling
is decided by GSLG.
00h
7:0
GSLB
RW
When LEDx (x=3, 6, 9, …) works in group mode, its SL scaling
is decided by GSLB.
00h
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GCFG: Group Configure Register (Address 8Bh)
Bit
Symbol
R/W
Description
Default
7
reserved
RW
-
0
RW
Group SL disable:
0: Group SL enable, all LEDs in group/pattern mode share the
common SL parameters decided by GSLR/G/B.
1: Group SL disable, all LEDs’ color parameter in group/pattern
mode is configured by their respective register SL
0
GSLDIS
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6
5:0
GEx
RW
fid
en
Group mode enable
If bit PATEN inregister PATCFG is set to “0”,
GE[0]=1: LED1~3 work in group mode
GE[1]=1: LED4~6 work in group mode
GE[2]=1: LED7~9 work in group mode
GE[3]=1: LED10~12 work in group mode
GE[4]=1: LED13~15 work in group mode
GE[5]=1: LED16~18 work in group mode
000000
aw
ini
cC
on
If bit PATEN inregister PATCFG is set to “1”,
GE[0]=1: LED1~3 work in auto breath pattern mode
GE[1]=1: LED4~6 work in auto breath pattern mode
GE[2]=1: LED7~9 work in auto breath pattern mode
GE[3]=1: LED10~12 work in auto breath pattern mode
GE[4]=1: LED13~15 work in auto breath pattern mode
GE[5]=1: LED16~18 work in auto breath pattern mode
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Application Information
REXT
The selection of REXT determined the maximum LED1~LED18 current Imax as described in below formula.
K
Where K = 160V, the recommended minimum value of REXT is 2KΩ.
aw
ini
cC
on
fid
en
When REXT = 4KΩ, Imax = 40mA
l
R EXT
tia
I max =
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PCB Layout Consideration
AW21018 is an 18-channel multi-function LED driver programmed via I2C compatible interface. When all LEDs
are operating, the device power dissipation is large. To obtain the good thermal performance and avoid thermal
shutdown, PCB layout should be considered carefully. Here are some guidelines:
1. The C1、C2 should be placed as close to the chip as possible.
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2. The REXT should be placed as close to the chip as possible.
en
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3. The Thermal PAD must be well connecting to the GND of the PCB, and add as many thermal vias as
possible beneath the thermal PAD on the PCB for the heat conductivity of the device and PCB.
C1
C2
on
AD0
AD1
VDD
SDA
SCL
EN
ISET
NC
NC
LED1
LED2
NC
LED3
NC
GND
NC
cC
LED4
LED5
LED6
LED7
NC
NC
LED18
LED17
Top Layer
LED16
LED15
LED14
LED13
LED12
LED11
LED10
LED9
aw
ini
LED8
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fid
REXT
GND Layer
Via to GND
31
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Tape And Reel Information
TAPE DIMENSIONS
REEL DIMENSIONS
P1
P0
P2
l
K0
tia
W
D1
A0
en
Cavity
B0
fid
A0：Dimension designed to accommodate the component width
B0：Dimension designed to accommodate the component length
K0：Dimension designed to accommodate the component thickness
W：Overall width of the carrier tape
P0：Pitch between successive cavity centers and sprocket hole
P1：Pitch between successive cavity centers
P2：Pitch between sprocket hole
D1：Reel Diameter
D0：Reel Width
D0
on
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pin 1
Q2
Q1
Q1
Q2
Q2
Q1
cC
Q1
Q3
Q4
Q3
Q4
Q3
Q4
Q3
Sprocket Holes
Q2
Q4
User Direction of Feed
Pocket Quadrants
Note：The above picture is for reference only. Please refer to the value in the table below for the actual size
DIMENSIONS AND PIN1 ORIENTATION
D0
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P0
(mm)
P1
(mm)
P2
(mm)
330
12.4
4.3
4.3
1.1
2
8
4
aw
ini
D1
(mm)
W
Pin1 Quadrant
(mm)
12
Q1
All dimensions are nominal
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AW21018
Feb. 2022 V1.1
Package Description
PIN1 CORNER
tia
l
4.00±0.10
fid
TOP VIEW
en
4.00±0.10
0.20 REF
on
0.85±0.05
0.00~0.05
cC
SIDE VIEW
2.80 T YP
9
16
0.40 T YP
8
SYMM
℄
aw
ini
2.90±0.10
17
32x(0.20±0.05)
0.30 REF
www.awinic.com
32x(0.30±0.05)
1
24
32
25
0.30 REF
SYMM
℄
2.90±0.10
BOTTOM VIEW
Unit：mm
33
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AW21018
Feb. 2022 V1.1
Land Pattern Data
3.00 REF
32 X 0.25 REF
1
en
tia
24
l
25
32
fid
2.90 REF
on
8
9
SYMM
℄
3.00 REF
17
16
SYMM
cC
℄
32X 0.20 TYP
32X 0.40 TYP
0.40 TYP
aw
ini
2.90 REF
0.05 MAX
All AROUND
0.05 MIN
All AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK DEFINED
NON SOLDER MASK DEFINED
www.awinic.com
SOLDER MASK
OPENING
Unit：mm
34
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AW21018
Feb. 2022 V1.1
Revision History
Date
Change Record
V1.0
Oct 2020
Officially released
V1.1
Feb 2022
Modified EC table
aw
ini
cC
on
fid
en
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Version
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35
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AW21018
Feb. 2022 V1.1
Disclaimer
All trademarks are the property of their respective owners. Information in this document is believed to be
accurate and reliable. However, Shanghai AWINIC Technology Co., Ltd (AWINIC Technology) does not give
any representations or warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such information.
tia
l
AWINIC Technology reserves the right to make changes to information published in this document, including
without limitation specifications and product descriptions, at any time and without notice. Customers shall
obtain the latest relevant information before placing orders and shall verify that such information is current and
complete. This document supersedes and replaces all information supplied prior to the publication hereof.
en
AWINIC Technology products are not designed, authorized or warranted to be suitable for use in medical,
military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an AWINIC
Technology product can reasonably be expected to result in personal injury, death or severe property or
environmental damage. AWINIC Technology accepts no liability for inclusion and/or use of AWINIC Technology
products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own
risk.
fid
Applications that are described herein for any of these products are for illustrative purposes only. AWINIC
Technology makes no representation or warranty that such applications will be suitable for the specified use
without further testing or modification.
on
All products are sold subject to the general terms and conditions of commercial sale supplied at the time of
order acknowledgement.
Nothing in this document may be interpreted or construed as an offer to sell products that is open for
acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other
industrial or intellectual property rights.
cC
Reproduction of AWINIC information in AWINIC data books or data sheets is permissible only if reproduction
is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices.
AWINIC is not responsible or liable for such altered documentation. Information of third parties may be subject
to additional restrictions.
aw
ini
Resale of AWINIC components or services with statements different from or beyond the parameters stated by
AWINIC for that component or service voids all express and any implied warranties for the associated AWINIC
component or service and is an unfair and deceptive business practice. AWINIC is not responsible or liable for
any such statements.
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