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BY25Q64ESSIG(R)

BY25Q64ESSIG(R)

  • 厂商:

    BOYAMICRO(博雅)

  • 封装:

    SOP8_208MIL

  • 描述:

    FLASH存储器 64MB SPI NOR FLASH 2.7V~3.6V

  • 数据手册
  • 价格&库存
BY25Q64ESSIG(R) 数据手册
Boya Microelectronics Memory Series BY25Q64ES 64M BIT SPI NOR FLASH Features ● Serial Peripheral Interface - Standard SPI: SCLK, /CS, SI, SO, /WP, /HOLD - Dual SPI: SCLK, /CS, IO0, IO1, /WP, /HOLD - Quad SPI: SCLK, /CS, IO0, IO1, IO2, IO3 ● Read - Normal Read (Serial): 100MHz clock rate - Fast Read (Serial): 120MHz clock rate with 30PF load - Dual I/O data transfer up to 240Mbits/S - Quad I/O data transfer up to 480Mbits/S - Allows XIP (execute in place) Operation: Continuous Read with 8/16/32/64-byte Wrap ● Program - Serial-input Page Program up to 256bytes ● Erase - Block Erase (64/32 KB) - Sector Erase (4 KB) - Chip Erase - Erase Suspend and Resume ● Program/Erase Speed - Page Program time: 0.6ms typical - Sector Erase time: 35ms typical - Block Erase time: 0.15/0.25s typical - Chip Erase time: 25s typical ● Flexible Architecture - Sector of 4K-byte - Block of 32/64K-byte ● Low Power Consumption - 12mA maximum active current - 0.7uA maximum power down current ● Software/Hardware Write Protection - 3x1024-Byte Security Registers with OTP Locks - Discoverable Parameters (SFDP) register - Enable/Disable protection with WP Pin - Write protect all/portion of memory via software - Top or Bottom, Sector or Block selection ● Single Supply Voltage - Full voltage range: 2.7~3.6V ● Temperature Range - Commercial (0℃ to +70℃) - Industrial (-40℃ to +85℃) ● Cycling Endurance/Data Retention - Typical 100k Program-Erase cycles on any sector - Typical 20-year data retention Contents BY25Q64ES Contents 1. Description ................................................................................. 4 2. Signal Description ...................................................................... 6 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Input/Output Summary ...................................................................................................6 Chip Select (/CS) ............................................................................................................6 Serial Clock (SCLK).......................................................................................................6 Serial Input (SI)/IO0 .......................................................................................................7 Serial Data Output (SO)/IO1 ..........................................................................................7 Write Protect (/WP)/IO2 .................................................................................................7 HOLD (/HOLD) /RESET /IO3 .......................................................................................7 VCC Power Supply.........................................................................................................7 VSS Ground....................................................................................................................8 3. Block/Sector Addresses ............................................................. 9 4. SPI Operation .......................................................................... 10 4.1 4.2 4.3 Standard SPI Instructions .............................................................................................10 Dual SPI Instructions ....................................................................................................10 Quad SPI Instructions ...................................................................................................10 5. Operation Features ................................................................... 11 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Supply Voltage .............................................................................................................. 11 5.1.1 Operating Supply Voltage ........................................................................ 11 5.1.2 Power-up Conditions ................................................................................ 11 5.1.3 Device Reset ............................................................................................ 11 5.1.4 Power-down.............................................................................................. 11 Active Power and Standby Power Modes..................................................................... 11 Hold Condition .............................................................................................................12 Software Reset & Hardware RESET ............................................................................13 5.4.1 Software Reset ........................................................................................ 13 5.4.2 Hardware Reset (/HOLD pin) .................................................................. 13 Write Protect Features ..................................................................................................14 Status Register ..............................................................................................................15 5.6.1 Status Register Table .............................................................................. 15 5.6.2 The Status and Control Bits .................................................................... 16 Array Memory Protection .............................................................................................18 5.7.1 Block Protect Table .................................................................................. 18 6. Device Identification ................................................................. 20 7. Instructions Description ............................................................ 21 7.1 Configuration and Status Instructions...........................................................................25 7.1.1 Write Enable (06H) .................................................................................. 25 7.1.2 Write Enable for Volatile Status Register (50H) ...................................... 26 7.1.3 Write Disable (04H) ................................................................................. 27 7.1.4 Read Status Register (05H or 35H or 15H) ............................................ 28 7.1.5 Write Status Register (01H or 31H or 11H) ............................................. 29 7.1.6 Enable Reset (66H) and Reset Device (99H) ......................................... 30 7.2 Read Instructions ..........................................................................................................31 7.2.1 Read Data (03H) ..................................................................................... 31 7.2.2 Fast Read (0BH) ..................................................................................... 31 7.2.3 Dual Output Fast Read (3BH) ................................................................. 32 7.2.4 Quad Output Fast Read (6BH)................................................................ 33 7.2.5 Dual I/O Fast Read (BBH) ....................................................................... 34 7.2.6 Quad I/O Fast Read (EBH) ..................................................................... 36 7.2.7 Quad I/O Word Fast Read (E7H) ............................................................ 38 Dec 2022 Rev 1.5 2 / 78 Contents BY25Q64ES 7.2.8 Set Burst with Wrap (77H)....................................................................... 40 7.3 ID and Security Instructions .........................................................................................41 7.3.1 Read Manufacture ID/ Device ID (90H) .................................................. 41 7.3.2 Dual I/O Read Manufacture ID/ Device ID (92H) .................................... 42 7.3.3 Quad I/O Read Manufacture ID/ Device ID (94H) .................................. 43 7.3.4 Read JEDEC ID (9FH) ............................................................................ 44 7.3.5 Read Unique ID Number (4Bh) ............................................................... 45 7.3.6 Deep Power-Down (B9H) ........................................................................ 46 7.3.7 Release from Deep Power-Down/Read Device ID (ABH) ...................... 47 7.3.8 Read Security Registers (48H) ............................................................... 48 7.3.9 Erase Security Registers (44H)............................................................... 49 7.3.10 Program Security Registers (42H) .......................................................... 50 7.3.11 Read Serial Flash Discoverable Parameter (5AH) ................................. 51 7.4 Program and Erase Instructions ....................................................................................56 7.4.1 Page Program (02H) ............................................................................... 56 7.4.2 Quad Page Program (32H) ..................................................................... 57 7.4.3 Sector Erase (20H).................................................................................. 58 7.4.4 32KB Block Erase (52H) ......................................................................... 59 7.4.5 64KB Block Erase (D8H) ......................................................................... 60 7.4.6 Chip Erase (60/C7H) ............................................................................... 61 7.4.7 Erase Suspend (75H) .............................................................................. 62 7.4.8 Erase Resume (7AH) .............................................................................. 64 8. Electrical Characteristics .......................................................... 65 8.1 8.2 8.3 8.4 8.5 8.6 8.7 Absolute Maximum Ratings .........................................................................................65 Operating Ranges..........................................................................................................65 Latch Up Characteristics...............................................................................................66 Power-up Timing ..........................................................................................................66 DC Electrical Characteristics ........................................................................................67 AC Measurement Conditions .......................................................................................68 AC Electrical Characteristics ........................................................................................68 9. Package Information ................................................................ 71 9.1 9.2 9.3 9.4 Package 8-Pin SOP 150-mil..........................................................................................71 Package 8-Pin SOP 208-mil..........................................................................................72 Package 8-Pad WSON (6x5mm) ..................................................................................73 Package USON8 (4*3mm) ...........................................................................................74 10. Order Information ..................................................................... 75 10.1 10.2 Valid part Numbers and Top Side Marking ..................................................................76 Minimum Packing Quantity (MPQ) .............................................................................77 11. Document Change History ....................................................... 78 Dec 2022 Rev 1.5 3 / 78 Description BY25Q64ES 1. Description The BY25Q64ES is 64M-bit Serial Peripheral Interface (SPI) Flash memory, and supports the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (/WP), and I/O3 (/HOLD). The Dual I/O data is transferred with speed of 100Mbits/s and the Quad I/O & Quad output data is transferred with speed of 200Mbits/s. The device uses a single low voltage power supply, ranging from 2.7 Volt to 3.6 Volt. Additionally, the device supports JEDEC standard manufacturer and device ID and three 1024bytes Security Registers. In order to meet environmental requirements, Boya Microelectronics offers 8-pin SOP 208mil, 8-pad WSON 6x5-mm, and other special order packages, please contacts Boya Microelectronics for ordering information. Figure 1. Logic diagram VCC SCLK SO SI /CS BY25QXX /WP /HOLD VSS Figure 2. Pin Configuration SOP 208/150 mil Top View Dec 2022 /CS 1 (IO1)SO 2 8 SOP8 208mil VCC 7 /HOLD(IO3) (IO2)/WP 3 6 SCLK VSS 4 5 SI(IO0) Rev 1.5 4 / 78 Description BY25Q64ES Figure 3. Pin Configuration WSON 5x6-mm and WSON 4*3-mm /CS 8 VCC 2 7 Top View /HOLD(IO3) (IO2)/WP 3 6 SCLK VSS 4 5 SI(IO0) (IO1)SO Dec 2022 1 Rev 1.5 5 / 78 BY25Q64ES Signal Description 2. Signal Description During all operations, VCC must be held stable and within the specified valid range: VCC (min) to VCC (max). All of the input and output signals must be held High or Low (according to voltages of VIH, VOH, VIL or VOL, see DC Electrical Characteristics). These signals are described next. 2.1 Input/Output Summary Table 1. Signal Names Pin Name I/O /CS I SO (IO1) I/O /WP (IO2) I/O VSS SI (IO0) I/O SCLK I /HOLD (IO3) I/O VCC 2.2 Description Chip Select Serial Output for single bit data Instructions. IO1 for Dual or Quad Instructions Write Protect in single bit or Dual data Instructions. IO2 in Quad mode. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad Instructions Ground Serial Input for single bit data Instructions. IO0 for Dual or Quad Instructions Serial Clock Hold (pause) serial transfer in single bit or Dual data Instructions. IO3 in Quad-I/O. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad Instructions Core and I/O Power Supply Chip Select (/CS) The chip select signal indicates when an instruction for the device is in process and the other signals are relevant for the memory device. When the /CS signal is at the logic high state, the device is not selected and all input signals are ignored and all output signals are high impedance. Unless an internal Program, Erase or Write Status Registers embedded operation is in progress, the device will be in the Standby Power mode. Driving the /CS input to logic low state enables the device, placing it in the Active Power mode. After Power Up, a falling edge on /CS is required prior to the start of any instruction. 2.3 Serial Clock (SCLK) This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data input are latched on the rising edge of the SCLK signal. Data output changes after the falling edge of SCLK. Dec 2022 Rev 1.5 6 / 78 BY25Q64ES Signal Description 2.4 Serial Input (SI)/IO0 This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to be programmed. Values are latched on the rising edge of serial SCLK clock signal. SI becomes IO0 an input and output during Dual and Quad Instructions for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial SCLK clock signal) as well as shifting out data (on the falling edge of SCLK). 2.5 Serial Data Output (SO)/IO1 This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the serial SCLK clock signal. SO becomes IO1 an input and output during Dual and Quad Instructions for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial SCLK clock signal) as well as shifting out data (on the falling edge of SCLK). 2.6 Write Protect (/WP)/IO2 When /WP is driven Low (VIL), while the Status Register Protect bits (SRP1 and SRP0) of the Status Registers (SR2[0] and SR1[7]) are set to 0 and 1 respectively, it is not possible to write to the Status Registers. This prevents any alteration of the Status Registers. As a consequence, all the data bytes in the memory area that are protected by the Block Protect, BP4, BP3 bits in the status registers, are also hardware protected against data modification while /WP remains Low. The /WP function is not available when the Quad mode is enabled (QE) in Status Register 2 (SR2[1]=1). The /WP function is replaced by IO2 for input and output during Quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the SCLK signal) as well as shifting out data (on the falling edge of SCLK). /WP has an internal pull-up resistance; when unconnected; /WP is at VIH and may be left unconnected in the host system if not used for Quad mode. 2.7 HOLD (/HOLD) /RESET /IO3 The /HOLD function is only available when QE=0, which can be configured either as a /HOLD pin or as a /RESET pin depending on Status Register setting. If QE=1, the /HOLD function is disabled, the pin acts as dedicated data I/O pin, and the /HOLD or /RESET function is not available. When QE=0 and HOLD/RES= 0, the /HOLD signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write status register, programming, or erasing in progress. The operation of HOLD, need /CS keep low, and starts on falling edge of the /HOLD signal, with SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of /HOLD signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). 2.8 VCC Power Supply VCC is the supply voltage. It is the single voltage used for all device functions including read, program, and erase. Dec 2022 Rev 1.5 7 / 78 BY25Q64ES Signal Description 2.9 VSS Ground VSS is the reference for the VCC supply voltage. Dec 2022 Rev 1.5 8 / 78 Block/Sector Addresses BY25Q64ES 3. Block/Sector Addresses Table 2.Block/Sector Addresses of BY25Q64ES Memory Density Big Block (8M bit) Block (64k byte) Block (32k byte) Half block 0 Block 0 Half block 1 Big Block 0 : : Half block 30 Block 15 Half block 31 : 64Mbit : Half block 224 Block 112 Half block 225 Big Block 7 : : Half block 254 Block 127 Half block 255 Notes: 1. 2. 3. 4. Sector 0 Sector Size(KB) 4 000000h-000FFFh : : : Sector 7 4 007000h-007FFFh Sector 8 4 008000h-008FFFh : 4 : Sector 15 4 00F000h-00FFFFh : : : Sector 240 4 0F0000h-0F0FFFh : : : Sector 247 4 0F7000h-0F7FFFh Sector 248 4 0F8000h-0F8FFFh : : : Sector 255 4 0FF000h-0FFFFFh : : : Sector 1792 4 700000h-700FFFh Sector No. : : Address range : Sector 1799 4 707000h-707FFFh Sector 1800 4 708000h-708FFFh : : : Sector 1807 4 70F000h-70FFFFh : : : Sector 2032 4 7F0000h-7F0FFFh : : : Sector 2039 4 7F7000h-7F7FFFh Sector 2040 4 7F8000h-7F8FFFh : : : Sector 2047 4 7FF000h-7FFFFFh Big Block = Uniform Big Block, and the size is 8M bits. Block = Uniform Block, and the size is 64K bytes. Half block = Half Uniform Block, and the size is 32k bytes. Sector = Uniform Sector, and the size is 4K bytes. Dec 2022 Rev 1.5 9 / 78 SPI Operation BY25Q64ES 4. SPI Operation 4.1 Standard SPI Instructions The BY25Q64ES features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (/CS), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. 4.2 Dual SPI Instructions The BY25Q64ES supports Dual SPI operation when using the “Dual Output Fast Read” (3BH), “Dual I/O Fast Read” (BBH) and “Read Manufacture ID/Device ID Dual I/O” (92H) instructions. These instructions allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI instruction the SI and SO pins become bidirectional I/O pins: IO0 and IO1. 4.3 Quad SPI Instructions The BY25Q64ES supports Quad SPI operation when using the “Quad Output Fast Read”(6BH), “Quad I/O Fast Read” (EBH) ,”Quad I/O word Fast Read”(E7H),”Read Manufacture ID/Device ID Quad I/O”(94H) and “Quad Page Program”(32H) instructions. These instructions allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI instruction the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and /WP and /HOLD pins become IO2 and IO3. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register to be set. Dec 2022 Rev 1.5 10 / 78 Operation Features BY25Q64ES 5. Operation Features 5.1 Supply Voltage 5.1.1 Operating Supply Voltage Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Electrical Characteristics). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10nF to 100nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). 5.1.2 Power-up Conditions When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select (/CS) line is not allowed to float but should follow the VCC voltage, it is therefore recommended to connect the /CS line to VCC via a suitable pull-up resistor. In addition, the Chip Select (/CS) input offers a built-in safety feature, as the /CS input is edge sensitive as well as level sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (/CS). This ensures that Chip Select (/CS) must have been High, prior to going Low to start the first operation. 5.1.3 Device Reset In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a power on reset (POR) circuit is included. At Power-up, the device does not respond to any instruction until VCC has reached the power on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Power-up Timing). When VCC is lower than VWI, the device is reset. 5.1.4 Power-down At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating voltage to below the power on reset threshold voltage(VWI), the device stops responding to any instruction sent to it. During Power-down, the device must be deselected (Chip Select (/CS) should be allowed to follow the voltage applied on VCC) and in Standby Power mode (that is there should be no internal Write cycle in progress). 5.2 Active Power and Standby Power Modes When Chip Select (/CS) is Low, the device is selected, and in the Active Power mode. The device consumes ICC. When Chip Select (/CS) is High, the device is deselected. If a Write cycle is not currently in progress, the device then goes in to the Standby Power mode, and the device consumption drops to ICC1. Dec 2022 Rev 1.5 11 / 78 Operation Features 5.3 BY25Q64ES Hold Condition When QE=0, HOLD/RST=0, the Hold (/HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial Clock (SCLK) are Don’t Care. To enter the Hold condition, the device must be selected, with Chip Select (/CS) Low. Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The Hold condition starts when the Hold (/HOLD) signal is driven Low at the same time as Serial Clock (SCLK) already being Low (as shown in Figure 4).The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C) already being Low. Figure 4 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (SCLK) being Low. Figure 4.Hold condition activation /CS SCLK /HOLD HOLD Dec 2022 Rev 1.5 HOLD 12 / 78 Operation Features 5.4 BY25Q64ES Software Reset & Hardware RESET 5.4.1 Software Reset The BY25Q64ES can be reset to the initial power-on state by a software reset sequence. This sequence must include two consecutive instructions: Enable Reset (66h) & Reset (99h). If the instruction sequence is successfully accepted, the device will take approximately 300uS (tRST) to reset. No instruction will be accepted during the reset period. 5.4.2 Hardware Reset (/HOLD pin) The BY25Q64ES can also be configured to utilize hardware /RESET pin. The HOLD/RST bit in the Status Register-3 is the configuration bit for /HOLD pin function or /RESET pin function. When HOLD/RST=0 (factory default), the pin acts as a /HOLD pin as described above; when HOLD/RST=1, the pin acts as a /RESET pin. Drive the /RESET pin low for a minimum period of ~1us (tRESET(1)) will reset the device to its initial power-on state. Any on-going Program/Erase operation will be interrupted and data corruption may happen. While /RESET is low, the device will not accept any instruction input. If QE bit is set to 1, the /HOLD or /RESET function will be disabled, the pin will become one of the four data I/O pin. Hardware /RESET pin has the highest priority among all the input signals. Drive /RESET low for a minimum period of ~1us (tRESET(1)) will interrupt any on-going external/internal operations, regardless the status of other SPI signals (/CS, CLK, IOs, /WP and /HOLD). Notes: 1. While a faster /RESET pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum pulse is recommended to ensure reliable operation. Dec 2022 Rev 1.5 13 / 78 Operation Features 5.5 1. BY25Q64ES Write Protect Features Software Protection (Memory array): - The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the memory array that can be read but not change. 2. Hardware Protection (Status register): /WP going low to protected the writable bits of Status Register. 3. Deep Power-Down: In Deep Power-Down Mode, all instructions are ignored except the Release from deep Power-Down Mode instruction. 4. Device resets when VCC is below threshold: Upon power-up or at power-down, the BY25Q64ES will maintain a reset condition while VCC is below the threshold value of VWI. While reset, all operations are disabled and no instructions are recognized. 5. Time delay write disable after Power-up: During power-up and after the VCC voltage exceeds VCC (min), all program and erase related instructions are further disabled for a time delay of tVSL. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. 6. Write Enable: The Write Enable instruction is set the Write Enable Latch bit. The WEL bit will return to reset by following situation: -Power –up -Write Disable -Write Status Register (Whether the SR is protected, WEL will return to reset) -Page Program (Whether the program area is protected, WEL will return to reset) -Sector Erase/Block Erase/Chip Erase (Whether the erase area is protected, WEL will return to reset) -Software Reset -Hardware Reset 7. One Time Program (OTP) write protection for array and Security Registers using Status Register. Dec 2022 Rev 1.5 14 / 78 Operation Features 5.6 BY25Q64ES Status Register 5.6.1 Status Register Table See Table 3 for detail description of the Status Register bits. Table 3. Status Register SR3 S23 HOLD/RST 0 Default (1) S22 DRV1 1 S21 DRV0 0 S20 S19 S18 S17 S16 Reserved Reserved Reserved Reserved Reserved × × × × × S11 LB1 0 OTP S10 0 Read Only S9 QE 0 S8 SRP1 0 S3 BP1 0 S2 BP0 0 SR2 Default (1) S15 SUS 0 Read Only S14 CMP 0 S13 LB3 0 OTP S12 LB2 0 OTP S7 SRP0 0 S6 BP4 0 S5 BP3 0 S4 BP2 0 Reserved SR1 Default (1) S1 S0 WEL WIP 0 0 Read Only Read Only Notes: 1. The default value is set by Manufacturer during wafer sort, Marked as Default in following text Dec 2022 Rev 1.5 15 / 78 Operation Features BY25Q64ES 5.6.2 The Status and Control Bits 5.6.2.1 WIP bit The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means the device is not in program/erase/write status register progress. 5.6.2.2 WEL bit The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase, etc. instruction is accepted. 5.6.2.3 BP4, BP3, BP2, BP1, BP0 bits The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register instruction. When WPS=0, and the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table 6-Table 7).becomes protected against Page Program, Sector Erase and Block Erase instructions. The Block Protect (BP4, BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase instruction is executed, if the Block Protect (BP2, BP1, BP0) bits are 0 and CMP=0 or The Block Protect (BP2, BP1, BP0) bits are 1 and CMP=1. 5.6.2.4 SRP1, SRP0 bits The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable protection. Table 4. Status Register protect table SRP1 SRP0 /WP Status Register Software Protected Hardware Protected Hardware Unprotected 0 0 X 0 1 0 0 1 1 1 0 X Power Supply Lock-Down(1) 1 1 X One Time Program(2) Description The Status Register can be written to after a Write Enable instruction, WEL=1.(Factory Default) /WP=0, the Status Register locked and cannot be written. /WP=1, the Status Register is unlocked and can be written to after a Write Enable instruction, WEL=1. Status Register is protected and cannot be written to again until the next Power-Down, Power-Up cycle. Status Register is permanently protected and cannot be written to. Notes: 1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state. 2. The One time Program feature is available upon special order. Please contact Boya Microelectronics for details. Dec 2022 Rev 1.5 16 / 78 Operation Features BY25Q64ES 5.6.2.5 QE bit The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the /WP pin and /HOLD pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the /WP or /HOLD pins directly to the power supply or ground). 5.6.2.6 LB3/LB2/LB1 bits The Security Register Lock (LB3/LB2/LB1) bits are non-volatile One Time Program (OTP) bits in Status Register (S13–S11) that provide the write protect control and status to the Security Registers. The default state of LB is 0, the security registers are unlocked. LB can be set to 1 individually using the Write Register instruction. LB is One Time Programmable, once they are set to 1, the Security Registers will become read-only permanently. 5.6.2.7 CMP bit The Complement Protect (CMP) bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4-BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The default setting is CMP=0. 5.6.2.8 SUS bit The Suspend Status (SUS) bit are read only bits in the status register2 (S15) that are set to 1 after executing an Erase Suspend (75H) instruction. The SUS bit is cleared to 0 by Erase Resume (7AH) instruction as well as a power-down, power-up cycle. 5.6.2.9 HOLD/RST bit The /HOLD or /RESET Pin Function (HOLD/RST) bit is used to determine whether /HOLD or /RESET function should be implemented on the hardware pin. When HOLD/RST=0 (factory default), the pin acts as /HOLD; when HOLD/RST=1, the pin acts as /RESET. However, /HOLD or /RESET functions are only available when QE=0. If QE is set to 1, the /HOLD and /RESET functions are disabled, the pin acts as a dedicated data I/O pin. 5.6.2.10 DRV1/DRV0 bits The Output Driver Strength (DRV1&DRV0) bits are used to determine the output driver strength for the Read instruction. Table 5.The Output Driver Strength DRV1,DRV0 00 01 10 11 Dec 2022 Driver Strength 25% 50% 75%(default) 100% Rev 1.5 17 / 78 Operation Features 5.7 BY25Q64ES Array Memory Protection 5.7.1 Block Protect Table Table 6.BY25Q64ES Block Memory Protection (CMP=0) Status Register Content BP4 BP3 BP2 BP1 BP0 X X 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 X X 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 X 1 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 X 1 1 1 1 0 Dec 2022 Blocks NONE 126 to 127 124 to 127 120 to 127 112 to 127 96 to 127 64 to 127 0 to 1 0 to 3 0 to 7 0 to 15 0 to 31 0 to 63 0 to 127 127 127 127 127 127 0 0 0 0 0 Memory Content Addresses Density NONE NONE 7E0000H-7FFFFFH 128KB 7C0000H-7FFFFFH 256KB 780000H-7FFFFFH 512KB 700000H-7FFFFFH 1MB 600000H-7FFFFFH 2MB 400000H-7FFFFFH 4MB 000000H-01FFFFH 128KB 000000H-03FFFFH 256KB 000000H-07FFFFH 512KB 000000H-0FFFFFH 1MB 000000H-1FFFFFH 2MB 000000H-3FFFFFH 4MB 000000H-7FFFFFH 8MB 7FF000H-7FFFFFH 4KB 7FE000H-7FFFFFH 8KB 7FC000H-7FFFFFH 16KB 7F8000H-7FFFFFH 32KB 7F8000H-7FFFFFH 32KB 000000H-000FFFH 4KB 000000H-001FFFH 8KB 000000H-003FFFH 16KB 000000H-007FFFH 32KB 000000H-007FFFH 32KB Rev 1.5 Portion NONE Upper 1/64 Upper 1/32 Upper 1/16 Upper 1/8 Upper 1/4 Upper 1/2 Lower 1/64 Lower 1/32 Lower 1/16 Lower 1/8 Lower 1/4 Lower 1/2 ALL Top Block Top Block Top Block Top Block Top Block Bottom Block Bottom Block Bottom Block Bottom Block Bottom Block 18 / 78 Operation Features BY25Q64ES Table 7.BY25Q64ES Block Memory Protection (CMP=1) Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion X 0 0 0 0 0 0 0 0 0 0 0 0 X 1 1 1 1 1 1 1 1 1 1 X 0 0 0 0 0 0 1 1 1 1 1 1 X 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 X 0 1 0 1 X 0 ALL 0 to 125 0 to 123 0 to 119 0 to 111 0 to 95 0 to 63 2 to 127 4 to 127 8 to 127 16 to 127 32 to 127 64 to 127 NONE 0 to127 0 to 127 0 to 127 0 to 127 0 to 127 0 to127 0 to 127 0 to 127 0 to 127 0 to 127 000000H-7FFFFFH 000000H-7DFFFFH 000000H-7BFFFFH 000000H-77FFFFH 000000H-6FFFFFH 000000H-5FFFFFH 000000H-3FFFFFH 020000H-7FFFFFH 040000H-7FFFFFH 080000H-7FFFFFH 100000H-7FFFFFH 200000H-7FFFFFH 400000H-7FFFFFH NONE 000000H-7FEFFFH 000000H-7FDFFFH 000000H-7FBFFFH 000000H-7F7FFFH 000000H-7F7FFFH 001000H-7FFFFFH 002000H-7FFFFFH 004000H-7FFFFFH 008000H-7FFFFFH 008000H-7FFFFFH ALL 8064KB 7936KB 7680KB 7MB 6MB 4MB 8064KB 7936KB 7680KB 7MB 6MB 4MB NONE 8188KB 8184KB 8176KB 8160KB 8160KB 8188KB 8184KB 8176KB 8160KB 8160KB ALL Lower 63/64 Lower 31/32 Lower 15/16 Lower 7/8 Lower 3/4 Lower 1/2 Upper 63/64 Upper 31/32 Upper 15/16 Upper 7/8 Upper 3/4 Upper 1/2 NONE L-2047/2048 L-1023/1024 L-511/512 L-255/256 L-255/256 U-2047/2048 U-1023/1024 U-511/512 U-255/256 U-255/256 Dec 2022 Rev 1.5 19 / 78 Device Identification BY25Q64ES 6. Device Identification Three legacy Instructions are supported to access device identification that can indicate the manufacturer, device type, and capacity (density). The returned data bytes provide the information as shown in the below table. Table 8. BY25Q64ES ID Definition table Operation Code 9FH 90H/92H/94H ABH Dec 2022 M7-M0 68 68 Rev 1.5 ID15-ID8 40 ID7-ID0 17 16 16 20 / 78 Instructions Description BY25Q64ES 7. Instructions Description All instructions, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after /CS is driven low. Then, the one byte instruction code must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK. See Table 9, every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. /CS must be driven high after the last bit of the instruction sequence has been shifted in. For the instruction of Read, Fast Read, Read Status Register or Release from Deep Power Down, and Read Device ID, the shifted-in instruction sequence is followed by a data out sequence. /CS can be driven high after any bit of the data-out sequence is being shifted out. For the instruction of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down instruction, etc. /CS must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is /CS must drive high when the number of clock pulses after /CS being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. Dec 2022 Rev 1.5 21 / 78 Instructions Description BY25Q64ES Table 9. Instruction Set Table Instruction Name Byte 1 Byte 2 Configuration and Status Instructions Write Enable 06H Write Enable for Volatile 50H Status Register Write Disable 04H Read Status Register-1 05H (S7-S0) Read Status Register-2 35H (S15-S8) Read Status Register-3 15H (S23-S16) Write Status Register -1 01H (S7-S0) Write Status Register-2 31H (S15-S8) Write Status Register-3 11H (S23-S16) Enable Reset 66H Reset 99H Read Instructions Read Data 03H A23-A16 Fast Read 0BH A23-A16 Dual Output Fast Read 3BH A23-A16 Dual I/O Fast Read BBH A23-A8(2) Quad Output Fast Read 6BH Quad I/O Fast Read EBH Quad I/O Word Fast Read(7) E7H Set Burst with Wrap 77H A23-A16 A23-A0 M7-M0(4) A23-A0 dM7-M0 (4) dummy(9) W7-W0 ID and Security Instructions Manufacturer/ Device ID 90H Manufacturer/ Device ID by Dual I/O dummy Byte 3 Byte 5 Byte 6 N-Bytes continuous continuous continuous A15-A8 A15-A8 A15-A8 A7-A0 M7-M0(2) A15-A8 A7-A0 A7-A0 A7-A0 (D7-D0) dummy dummy Next byte (D7-D0) (D7-D0)(1) continuous continuous continuous (D7-D0)(1) Next byte Next byte continuous A7-A0 dummy (D7-D0)(3) continuous dummy(5) (D7-D0)(3) Next byte Next byte continuous dummy(6) (D7-D0)(3) Next byte Next byte continuous dummy 00H (MID7-MID0) (ID7-ID0) continuous (MID7-MID 0),(DID7-D ID0) 92H A23-A8 A7-A0, dummy 94H A23-A0, dummy (MID7-MID0 Manufacturer/ Device ID by Quad I/O Byte 4 continuous dummy(8) continuous ) (DID7-DID0) JEDEC ID 9FH MID7-MID 0 ID15-ID8 ID7-ID0 Read Unique ID Number 4Bh Dummy Dummy Dummy Dummy Deep Power-Down Release From Deep Power-Down, And Read Device ID Release From Deep Power-Down Read Security Registers(10) B9H dummy dummy dummy (ID7-ID0) A23-A16 A15-A8 A7-A0 dummy Dec 2022 continuous (ID127-ID 0) continuous ABH ABH 48H Rev 1.5 (D7-D0) 22 / 78 continuous Instructions Description Program Security Registers(10) Erase Security Registers(10) Read Serial Flash Discoverable Parameter BY25Q64ES 42H A23-A16 A15-A8 A7-A0 44H A23-A16 A15-A8 A7-A0 5AH A23-A16 A15-A8 A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 Program and Erase Instructions Page Program 02H Quad Page Program 32H Sector Erase 20H 32K Block Erase 52H 64K Block Erase D8H C7/60 Chip Erase H Program/Erase Suspend 75H Program/Erase Resume 7AH (D7-D0) (D7-D0) A7-A0 Dummy D7-D0 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 (D7-D0) (D7-D0)(3) Next byte Next byte continuous continuous continuous continuous Notes: 1. Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3,M1 3. Quad Output Data IO0 = (D4, D0,…..) IO1 = (D5, D1,…..) IO2 = (D6, D2,…..) IO3 = (D7, D3,…..) 4. Quad Input Address IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 5. Fast Read Quad I/O Data IO0 = (x, x, x, x, D4, D0,…) IO1 = (x, x, x, x, D5, D1,…) IO2 = (x, x, x, x, D6, D2,…) IO3 = (x, x, x, x, D7, D3,…) 6. Fast Word Read Quad I/O Data IO0 = (x, x, D4, D0,…) IO1 = (x, x , D5, D1,…) IO2 = (x, x, D6, D2,…) IO3 = (x, x, D7, D3,…) 7. Fast Word Read Quad I/O Data: the lowest address bit must be 0. 8. Address, continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID IO0 = (A20, A16, A12, A8, A4, A0, M4, M0, x, x, x, x, MID4, MID0, DID4, DID0) IO1 = (A21, A17, A13, A9, A5, A1, M5, M1, x, x, x, x, MID5, MID1, DID5, DID1) IO2 = (A22, A18, A14, A10, A6, A2, M6, M2, x, x, x, x, MID6, MID2, DID6, DID2) IO3 = (A23, A19, A15, A11, A7, A3, M7, M3, x, x, x, x, MID7, MID3, DID7, DID3) Dec 2022 Rev 1.5 23 / 78 Instructions Description BY25Q64ES 9. Dummy bits and Wraps Bits IO0 = (x, x, x, x, x, x, w4, x) IO1 = (x, x, x, x, x, x, w5, x) IO2 = (x, x, x, x, x, x, w6, x) IO3 = (x, x, x, x, x, x, x,x) 10. Security Registers Address: Security Register1: A23-A16=00H, A15-A10=000100b, A9-A0= Byte Address; Security Register2: A23-A16=00H, A15-A10=001000b, A9-A0= Byte Address; Security Register3: A23-A16=00H, A15-A10=001100b, A9-A0= Byte Address; Security Register 0 can be used to store the Flash Discoverable Parameters, The feature is upon special order, please contact Boya Microelectronics for details. Table 10. Instructions that need to send the Write Enable/Write Enable for Volatile Status Register instruction Instruction Write Status Register Erase Security Registers Program Security Registers Page Program Quad Page Program Sector Erase 32KB Block Erase 64KB Block Erase Chip Erase Dec 2022 01h/31h/11h 44h 42h 02h 32h 20h 52h D8h 60h/C7h Rev 1.5 Write 06H/50H 06H 06H 06H 06H 06H 06H 06H 06H 24 / 78 Instructions Description 7.1 BY25Q64ES Configuration and Status Instructions 7.1.1 Write Enable (06H) See Figure 5, the Write Enable instruction is for setting the Write Enable Latch bit. The Write Enable Latch bit must be set prior to every Write Status Register, Program and Erase. The Write Enable instruction sequence: /CS goes low sending the Write Enable instruction, /CS goes high. Please note that the Write Enable instruction sent when the Write Enable for Volatile Status Register instruction is valid is not accepted. Therefore, when need to send the Write Enable instruction, but do not know if the Write Enable for Volatile Status Register instruction is valid, please send the Write Disable instruction first. Figure 5. Write Enable Sequence Diagram /CS 0 1 2 3 4 5 6 7 SCLK Instruction SI SO Dec 2022 06H High_Z Rev 1.5 25 / 78 Instructions Description BY25Q64ES 7.1.2 Write Enable for Volatile Status Register (50H) See Figure 6, the non-volatile Status Register bits can also be written to as volatile bits (HOLD/RST, DRV1, DRV0, CMP, QE, SRP1, SRP0, BP4, BP3, BP2, BP1, BP0). This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. Write Enable for Volatile Status Register instruction will not set the Write Enable Latch bit, it is only valid for the Write Status Registers instruction to change the volatile Status Register bit values (After the software reset or re-powered, the volatile Status Register bit values will be restored to the default value or the value input by the Write Enable instruction). Please note that the Write Enable for Volatile Status Register instruction sent when the Write Enable instruction is valid is not accepted. Therefore, when need to send the Write Enable for Volatile Status Register instruction, please first determine whether the Write Enable instruction is not valid. Figure 6. Write Enable for Volatile Status Register /CS 0 1 2 3 4 5 6 7 SCLK Instruction SI SO Dec 2022 50H High_Z Rev 1.5 26 / 78 Instructions Description BY25Q64ES 7.1.3 Write Disable (04H) See Figure 7, the Write Disable instruction is for resetting the Write Enable Latch bit or invalidate the Write Enable for Volatile Status Register instruction. The Write Disable instruction sequence: /CS goes low -> sending the Write Disable instruction -> /CS goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase, Program/Erase Security Registers and Reset instructions. Figure 7. Write Disable Sequence Diagram /CS 0 1 2 3 4 5 6 7 SCLK Instruction SI SO Dec 2022 04H High_Z Rev 1.5 27 / 78 Instructions Description BY25Q64ES 7.1.4 Read Status Register (05H or 35H or 15H) See Figure 8, the Read Status Register (RDSR) instruction is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write in Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously. For instruction code “05H”, the SO will output Status Register bits S7~S0. The instruction code “35H”, the SO will output Status Register bits S15~S8, The instruction code “15H”, the SO will output Status Register bits S23~16. Figure 8. Read Status Register Sequence Diagram /CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Instruction SI 05H or 35H or 15H Register 0/1/2 SO Dec 2022 High_Z 7 6 MSB 5 4 Rev 1.5 3 2 Register 0/1/2 1 0 7 6 MSB 5 4 3 2 1 0 28 / 78 Instructions Description BY25Q64ES 7.1.5 Write Status Register (01H or 31H or 11H) The Write Status Register instruction allows the Status Registers to be written. The Status Register-1 can be written by the Write Status Register 01h instruction; The Status Register-2 be written by the Write Status Register 01h or 31h instruction; Status Register-3 can be written by the Write Status Register 11h instruction. When the Write Status Register instruction 01h is followed by 1 byte data, the data will be written to Status Register-1. When the Write Status Register instruction 01h is followed by 2 bytes of data, the first byte data will be written to Status Register-1, and the second byte data will be written to Status Register-2; And Write Status Register instruction 31h or 11h can only follow 1 byte data, the data will be written to Status Register-2、Status Register-3 respectively. The writable Status Register bits include: SRP0, BP[4:0] in Status Register-1; CMP, LB[3:1], QE, SRP1 in Status Register- 2; DRV1, DRV0 in Status Register- 3. All other Status Register bit locations are read-only and will not be affected by the Write Status Register instruction. LB[3:1] are non-volatile OTP bits, once it is set to 1, it cannot be cleared to 0. The Write Status Register instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable or Write Enable For Volatile SR instruction must previously have been executed After the Write Enable instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register instruction has no effect on S15 (SUS), S1 (WEL) and S0 (WIP) of the Status Register. /CS must be driven high after the 8 or 16 bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as /CS is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register instruction allows the user to change the values of the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 6 and Table 7. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect (/WP) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (/WP) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register instruction is not executed once the Hardware Protected Mode is entered. The sequence of issuing WRSR instruction is: /CS goes low→ sending WRSR instruction code→ Status Register data on SI→/CS goes high. The /CS must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (/CS) goes high. The Write in Progress (WIP) bit still can be checked during the Write Status Register cycle is in progress. The WIP is set 1 during the tW timing, and is set 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Figure 9. Write Status Register Sequence Diagram-01H 2byte /CS SCLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 01H SO 11 12 13 14 15 1 0 16 17 7 MSB 6 5 4 3 2 18 19 20 21 22 23 9 8 Mode 3 Mode 0 Status Register-2 in Status Register-1 in Instruction SI 10 15 14 13 12 11 10 MSB High_Z Dec 2022 Rev 1.5 29 / 78 Instructions Description BY25Q64ES Figure 10. Write Status Register Sequence Diagram-01/31/11H 1byte /CS 0 Mode 3 Mode 0 SCLK 1 2 3 4 5 6 7 8 9 10 01H/31H/11H SO 12 13 14 15 1 0 Mode 3 Mode 0 SR1/SR2/SR3 in Instruction SI 11 7 MSB 6 5 4 2 3 High_Z 7.1.6 Enable Reset (66H) and Reset Device (99H) Because of the small package and the limitation on the number of pins, the BY25Q64ES provides a software reset instruction instead of a dedicated RESET pin. Once the software reset instruction is accepted, any on-going internal operations will be terminated and the device will return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL) status, Erase Suspend status, Continuous Read Mode bit setting (M7-M0) and Wrap Bit setting (W6-W4). To avoid accidental reset, both “Enable Reset (66h)” and “Reset (99h)” instructions must be issued in sequence. Any other instructions other than “Reset (99h)” after the “Enable Reset (66h)” instruction will disable the “Reset Enable” state. A new sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to reset the device. Once the Reset instruction is accepted by the device, the device will take approximately 300us to reset. During this period, no instruction will be accepted. The Enable Reset (66h) and Reset (99h) instruction sequence is shown in Figure 11. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset instruction sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset instruction sequence. Figure 11. Enable Reset (66h) and Reset (99h) Instruction Sequence /CS 0 1 2 3 4 5 6 0 7 1 2 3 4 5 6 7 SCLK Instruction SI Instruction 99h 66H Dec 2022 Rev 1.5 30 / 78 Instructions Description 7.2 BY25Q64ES Read Instructions 7.2.1 Read Data (03H) See Figure 12, the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by driving /CS high. The whole memory can be read with a single Read Data Bytes (READ) instruction. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 12. Read Data Bytes Sequence Diagram /CS 0 1 2 4 3 5 6 7 8 9 28 29 30 10 31 32 33 34 35 36 37 38 39 SCLK 24-Bit Address Instruction SI 21 23 22 03H 3 2 1 0 Data Byte1 MSB High_Z SO 7 6 MSB 5 4 3 High_Z 2 1 0 7.2.2 Fast Read (0BH) See Figure 13, the Read Data Bytes at Higher Speed (Fast Read) instruction is for quickly reading data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fc, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 13. Fast Read Sequence Diagram /CS Mode 3 0 1 2 3 4 5 6 7 9 8 28 29 30 10 31 SCLK Mode 0 Instruction 24-Bit Address 23 22 0BH SI 21 3 2 1 0 High_Z SO /CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Clocks SI SO Dec 2022 High_Z Data Out 7 Rev 1.5 6 5 4 3 2 1 0 31 / 78 Instructions Description BY25Q64ES 7.2.3 Dual Output Fast Read (3BH) See Figure 14, the Dual Output Fast Read instruction is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 14. Dual Output Fast Read Sequence Diagram /CS 0 1 2 3 4 5 6 7 9 8 28 10 29 30 31 SCLK Instruction 24-Bit Address 3BH SI SO 23 22 21 41 42 43 3 2 1 0 High_Z /CS 32 33 34 35 36 37 38 39 40 44 45 46 47 0 6 4 2 0 1 7 SCLK SI Dummy Clocks 6 4 2 Data Byte 2 Data Byte 1 SO Dec 2022 High_Z 7 5 Rev 1.5 3 5 3 1 High_Z High_Z 32 / 78 Instructions Description BY25Q64ES 7.2.4 Quad Output Fast Read (6BH) See Figure 15, the Quad Output Fast Read instruction is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register must be set to enable. Figure 15. Quad Output Fast Read Sequence Diagram /CS Mode 3 SCLK 0 1 3 2 4 5 6 7 8 9 29 30 31 24-Bit Address Instruction SI (IO0) High_Z /WP (IO2) High_Z /HOLD (IO3) High_Z 32 33 34 35 36 37 38 39 40 41 3 2 1 45 46 47 21 23 22 MSB 6BH SO (IO1) /CS 28 10 Mode 0 42 43 44 0 SCLK SI (IO0) Data Out 1 Data Out 2 Data Out 3 Data Out 4 4 0 0 4 0 4 0 4 Dummy Clocks SO (IO1) High_Z /WP (IO2) High_Z /HOLD (IO3) High_Z 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 MSB 3 MSB Dec 2022 Rev 1.5 MSB MSB 33 / 78 Instructions Description BY25Q64ES 7.2.5 Dual I/O Fast Read (BBH) See Figure 16, the Dual I/O Fast Read instruction is similar to the Dual Output Fast Read instruction but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Dual I/O Fast Read with “continuous Read Mode” The Dual I/O Fast Read instruction can further reduce instruction overhead through setting the “continuous Read Mode” bits (M7-4) after the inputs 3-byte address A23-A0).If the “continuous Read Mode” bits(M5-4)=(1,0),then the next Dual I/O fast Read instruction (after CS/ is raised and then lowered) does not require the BBH instruction code. The instruction sequence is shown in the following Figure 16. If the “continuous Read Mode” bits (M5-4) does not equal (1,0), the next instruction requires the first BBH instruction code, thus returning to normal operation. A “continuous Read Mode” Reset instruction can be used to reset (M5-4) before issuing normal instruction. Figure 16. Dual I/O Fast Read Sequence Diagram (Initial instruction or previous (M5-4)≠ (1,0)) /CS 0 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Instruction SI (IO0) BBH SO (IO1) High_Z 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 A23-16 A15-8 A7-0 M7-0 /CS SCLK 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SI (IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 SO (IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 3 5 Byte 4 1 Byte 1 Dec 2022 Byte 2 Byte 3 Rev 1.5 High_Z High_Z 34 / 78 Instructions Description BY25Q64ES Figure 17. Dual I/O Fast Read Sequence Diagram (Previous instruction set (M5-4) =(1,0)) /CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK SI (IO0) 6 SO (IO1) 7 /CS 0 6 4 0 6 4 2 0 6 4 2 0 5 3 1 A23-16 7 5 3 1 A15-8 7 5 3 A7-0 1 7 5 3 M7-0 1 4 2 2 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCLK SI (IO0) 6 4 2 0 6 4 0 6 4 2 0 6 SO (IO1) 7 5 3 Byte1 1 7 5 3 1 Byte2 7 5 3 Byte3 1 7 Dec 2022 2 Rev 1.5 2 0 5 3 Byte4 1 4 35 / 78 Instructions Description BY25Q64ES 7.2.6 Quad I/O Fast Read (EBH) See Figure 18, the Quad I/O Fast Read instruction is similar to the Dual I/O Fast Read instruction but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register must be set to enable for the Quad I/O Fast read instruction, as shown in Figure 18. Quad I/O Fast Read with “Continuous Read Mode” The Quad I/O Fast Read instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), If the “Continuous Read Mode” bits (M5-4 )= (1,0), then the next Fast Read Quad I/O instruction(after /CS is raised and then lowered) does not require the EBH instruction code. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction requires the first EBH instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset (M5-4) before issuing normal instruction. Figure 18. Quad I/O Fast Read Sequence Diagram (Initial instruction or previous (M5-4≠ (1,0))) /CS Mode 3 SCLK 0 1 2 3 4 6 5 7 9 8 10 11 12 13 14 15 Mode 0 Instruction SI (IO0) EBH High_Z SO (IO1) A23-16 A15-8 20 16 12 8 A7-0 4 0 21 17 13 9 5 1 5 1 22 18 14 10 6 2 6 2 23 19 MSB 15 11 7 3 7 3 M7-0 4 0 High_Z /WP (IO2) High_Z /HOLD (IO3) MSB /CS 16 17 18 19 20 21 22 23 24 25 26 27 SCLK Dummy Clocks SI (IO0) SO (IO1) High_Z /WP (IO2) High_Z /HOLD (IO3) Data Out 1 Data Out 2 Data Out 3 Data Out 4 4 0 0 4 0 4 0 4 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 MSB 3 High_Z MSB Dec 2022 MSB Rev 1.5 MSB 36 / 78 Instructions Description BY25Q64ES Figure 19. Quad I/O Fast Read Sequence Diagram (Initial instruction or previous (M5-4=(1,0))) /CS 0 SCLK SI (IO0) SO (IO1) /WP (IO2) /HOLD (IO3) 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 A23-16 A15-8 A7-0 M7-0 Dummy 7 3 Byte1 7 3 Byte2 Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” The Quad I/O Fast Read instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” (77H) instruction prior to EBH. The “Set Burst with Wrap” (77H) instruction can either enable or disable the “Wrap Around” feature for the following EBH instructions. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the instruction. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read instructions. The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. Dec 2022 Rev 1.5 37 / 78 Instructions Description BY25Q64ES 7.2.7 Quad I/O Word Fast Read (E7H) The Quad I/O Word Fast Read instruction is similar to the Quad Fast Read instruction except that the lowest address bit (A0) must equal 0 and 2-dummy clock. The instruction sequence is shown in the followed Figure 20, the first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast Read instruction. The Quad Enable bit (QE) of Status Register must be set to enable. Quad I/O Word Fast Read with “Continuous Read Mode” The Quad I/O Word Fast Read instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte Address bits (A23-0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Quad I/O Fast Read instruction (after /CS is raised and then lowered) does not require the E7H instruction code, the instruction sequence is shown in the followed Figure 21. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction requires the first E7H instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset (M5-4) before issuing normal instruction. Figure 20. Quad I/O Word Fast Read Sequence Diagram (Initial instruction or previous (M5-4)≠(1,0)) /CS 0 1 2 3 4 6 5 9 8 7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK SI (IO0) Instruction E7H SO (IO1) High_Z /WP (IO2) High_Z /HOLD (IO3) High_Z 4 0 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 A23-16 A15-8 7 3 A7-0 7 3 Byte1 7 3 M7-M0 Dummy 7 3 Byte2 7 3 Byte3 Figure 21. Quad I/O Word Fast Read Sequence Diagram (Initial instruction or previous (M5-4)=(1,0)) /CS 0 SCLK SI (IO0) SO (IO1) /WP (IO2) /HOLD (IO3) 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 4 0 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 A23-16 A15-8 A7-0 M7-0 7 3 Dummy Byte1 7 3 Byte2 7 3 Byte3 Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in standard SPI mode Dec 2022 Rev 1.5 38 / 78 Instructions Description BY25Q64ES The Quad I/O Fast Read instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” (77H) instruction prior to E7H. The “Set Burst with Wrap” (77H) instruction can either enable or disable the “Wrap Around” feature for the following E7H instructions. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the instruction. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read instructions. The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. Dec 2022 Rev 1.5 39 / 78 Instructions Description BY25Q64ES 7.2.8 Set Burst with Wrap (77H) See Figure 22, The Set Burst with Wrap instruction is used in conjunction with “EBH” and “E7H” instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page, in standard SPI mode. The Set Burst with Wrap instruction sequence:/CS goes low ->Send Set Burst with Wrap instruction ->Send24 Dummy bits ->Send 8 bits” Wrap bits”->/CS goes high. If W6-4 is set by a Set Burst with Wrap instruction, all the following “EBH” and “E7H” instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap instruction should be issued to set W4=1. The default value of W4 upon power on is 1. W4 = 0 W4 =1 (DEFAULT) W6 , W5 Wrap Around Wrap Length Wrap Around Wrap Length 0 0 Yes 8-byte No N/A 0 1 1 1 0 1 Yes Yes Yes 16-byte 32-byte 64-byte No No No N/A N/A N/A Figure 22. Set Burst with Wrap Sequence Diagram /CS Mode 3 SCLK 0 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 Mode 3 Mode 0 Mode 0 Instruction SI (IO0) SO (IO1) /WP (IO2) /HOLD (IO3) 77H High_Z X X X X X X W4 X X X X X X X W5 X X X X X X X W6 X X X X X X X X X High_Z High_Z High_Z High_Z byte1 Dec 2022 High_Z Rev 1.5 byte2 byte3 High_Z byte4 40 / 78 Instructions Description 7.3 BY25Q64ES ID and Security Instructions 7.3.1 Read Manufacture ID/ Device ID (90H) See Figure 23, The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-Down/Device ID instruction that provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The instruction is initiated by driving the /CS pin low and shifting the instruction code “90H” followed by a 24-bit address (A23-A0) of 000000H. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure 23. Read Manufacture ID/ Device ID Sequence Diagram /CS 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Instruction SI 24-Bit Address 3 2 21 22 23 90H High_Z SO 1 0 /CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI SO Dec 2022 7 6 Manufacturer ID 5 4 3 2 1 0 7 Rev 1.5 6 Device ID 3 2 5 4 1 0 41 / 78 Instructions Description BY25Q64ES 7.3.2 Dual I/O Read Manufacture ID/ Device ID (92H) See Figure 24, the Dual I/O Read Manufacturer/Device ID instruction is an alternative to the Release from Power-Down/Device ID instruction that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by Dual I/O. The instruction is initiated by driving the /CS pin low and shifting the instruction code “92H” followed by a 24-bit address (A23-A0) of 000000H. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure 24. Dual I/O Read Manufacture ID/ Device ID Sequence Diagram /CS 0 2 1 3 4 5 6 7 9 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Instruction SI (IO0) 92H SO (IO1) High_Z 6 A23-16 4 2 0 7 5 1 3 MSB 6 A15-8 4 2 0 7 5 1 3 MSB 6 A7-0 4 2 0 7 5 1 3 MSB 6 Dummy 4 2 0 7 5 3 1 MSB /CS SCLK SI (IO0) SO (IO1) 23 24 25 26 27 28 29 30 39 31 32 44 45 46 47 40 41 42 43 IOs switch from Input to Output 6 4 2 0 6 4 2 6 0 4 2 0 6 4 2 0 High_Z High_Z 7 5 3 1 7 5 3 1 MSB MSB MFR ID Device ID Dec 2022 MFR and Device ID (repeat) Rev 1.5 7 3 1 5 3 1 7 5 MSB MSB Device ID(repeat) MFR ID(repeat) 42 / 78 Instructions Description BY25Q64ES 7.3.3 Quad I/O Read Manufacture ID/ Device ID (94H) See Figure 25, the Quad I/O Read Manufacturer/Device ID instruction is an alternative to the Release from Power-Down/Device ID instruction that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O. The Quad Enable bit (QE) of Status Register must be set to enable. The instruction is initiated by driving the /CS pin low and shifting the instruction code “94H” followed by a 24-bit address (A23-A0) of 000000H and 4 dummy clocks. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure 25. Quad I/O Read Manufacture ID/ Device ID Sequence Diagram /CS 0 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Instruction SI (IO0) 94H SO (IO1) High_Z WP (IO2) High_Z HOLD (IO3) High_Z 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 A23-16 A15-8 A7-0 dummy dummy MFR ID Device ID /CS SCLK 23 24 25 26 27 28 29 30 31 SI (IO0) 4 0 4 0 4 0 4 0 SO (IO1) 5 1 5 1 5 1 5 1 WP (IO2) 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 HOLD (IO3) Dec 2022 MFR ID DID ID MFR ID DID ID (repeat) (repeat) (repeat) (repeat) Rev 1.5 43 / 78 Instructions Description BY25Q64ES 7.3.4 Read JEDEC ID (9FH) The JEDEC ID instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. JEDEC ID instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The JEDEC ID instruction should not be issued while the device is in Deep Power-Down Mode. See Figure 26, the device is first selected by driving /CS to low. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The JEDEC ID instruction is terminated by driving /CS to high at any time during data output. When /CS is driven high, the device is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute instructions. Figure 26. JEDEC ID Sequence Diagram /CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 9FH Instruction SI Manufacturer ID 7 MSB SO /CS 6 16 17 18 19 20 21 22 23 24 25 26 5 4 3 2 1 0 27 28 29 30 31 SCLK SI SO 7 MSB Dec 2022 Memory Type ID15-ID8 1 6 5 4 3 2 0 7 Capacity ID7-ID0 6 5 4 3 2 1 0 MSB Rev 1.5 44 / 78 Instructions Description BY25Q64ES 7.3.5 Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 128-bit number that is unique to each BY25Q64ES device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin low and shifting the instruction code “4Bh” followed by four bytes of dummy clocks. After which, the 128-bit ID is shifted out on the falling edge of SCLK as shown in Figure 27. Figure 27. Read Unique ID Sequence Diagram /CS SCLK 0 Mode 3 Mode 0 1 2 3 4 5 6 7 8 9 10 Instruction SI 11 12 13 14 15 16 Dummy Byte 1 17 18 19 20 21 22 23 Dummy Byte 2 4BH SO High_Z /CS 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 164 165 166 167 SCLK Dummy Byte 3 Mode 3 Mode 0 Dummy Byte 4 SI SO High_Z 127 MSB Dec 2022 Rev 1.5 126 2 1 0 128-bit Unique Serial Number 45 / 78 Instructions Description BY25Q64ES 7.3.6 Deep Power-Down (B9H) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Deep Power-down instruction. The lower power consumption makes the Deep Power-down (DPD) instruction especially useful for battery powered applications (see ICC1 and ICC2). The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in Figure 28. The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Deep Power down instruction will not be executed. After /CS is driven high, the power-down state will entered within the time duration of tDP. While in the power-down state only the Release from Deep Power-down/Device ID instruction, software reset sequence or hardware reset sequence, which restores the device to normal operation, will be recognized. All other Instructions are ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction also makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. Figure 28. Deep Power-Down Sequence Diagram /CS 0 1 2 3 4 5 6 7 tDP SCLK Instruction SI B9H Stand-by mode Dec 2022 Rev 1.5 Power-down mode 46 / 78 Instructions Description BY25Q64ES 7.3.7 Release from Deep Power-Down/Read Device ID (ABH) The Release from Power-Down or Device ID instruction is a multi-purpose instruction. It can be used to release the device from the Power-Down state or obtain the devices electronic identification (ID) number. See Figure 29, to release the device from the Power-Down state, the instruction is issued by driving the /CS pin low, shifting the instruction code “ABH” and driving /CS high Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other instruction are accepted. The /CS pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the Power-Down state, the instruction is initiated by driving the /CS pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 30. The Device ID value for the BY25Q64ES is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high. When used to release the device from the Power-Down state and obtain the Device ID, the instruction is the same as previously described, and shown in Figure 30, except that after /CS is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other instruction will be accepted. If the Release from Power-Down/Device ID instruction is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the instruction is ignored and will not have any effects on the current cycle. Figure 29. Release Power-Down Sequence Diagram /CS 0 1 2 3 4 5 6 tRES1 7 SCLK Instruction SI ABH Power-down mode Stand-by mode Figure 30. Release Power-Down/Read Device ID Sequence Diagram /CS 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 39 SCLK Instruction SI ABH SO High_Z 3 Dummy Bytes 23 22 2 1 MSB tRES2 0 7 MSB 6 Device ID 3 4 5 2 1 0 Deep Power-down mode Dec 2022 Rev 1.5 Stand-by mode 47 / 78 Instructions Description BY25Q64ES 7.3.8 Read Security Registers (48H) See Figure 31, the instruction is followed by a 3-byte address (A23-A0) and the dummy byte. Each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Once the A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H, the instruction is completed by driving /CS high. ADDRESS A23-A16 A15-12 A11-10 A9-0 Security Register #1 00H 0001 00 Byte Address Security Register #2 00H/ 0010 00 Byte Address Security Register #3 00H 0011 00 Byte Address Figure 31. Read Security Registers instruction Sequence Diagram /CS Mode 3 SCLK Mode 0 1 0 2 3 5 4 6 7 8 Instruction SI 48H SO High_Z 28 29 30 31 9 24-Bit Address 3 23 22 MSB 2 1 0 /CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Mode 3 Mode 0 Dummy Byte SI SO Dec 2022 7 6 MSB 5 4 3 2 1 0 Data Byte 1 7 6 MSB Rev 1.5 5 4 3 2 1 0 48 / 78 Instructions Description BY25Q64ES 7.3.9 Erase Security Registers (44H) The BY25Q64ES provides three 1024-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. See Figure 32, the Erase Security Registers instruction is similar to Block/Sector Erase instruction. A Write Enable instruction must previously have been executed to set the Write Enable Latch bit. The Erase Security Registers instruction sequence: /CS goes low sending Erase Security Registers instruction /CS goes high. /CS must be driven high after the eighth bit of the instruction code has been latched in otherwise the Erase Security Registers instruction is not executed. As soon as /CS is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. The Security Registers Lock Bit (LB) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security Registers instruction will be ignored. ADDRESS A23-A16 A15-12 A11-10 A9-0 Security Register #1 00H 0001 00 Byte Address Security Register #2 00H 0010 00 Byte Address Security Register #3 00H 0011 00 Byte Address Figure 32. Erase Security Registers instruction Sequence Diagram CS Mode 3 SCLK 0 1 2 3 4 5 6 Dec 2022 8 9 29 30 31 Mode 3 Mode 0 Mode 0 Instruction SI 7 24-Bit Address 23 22 MSB 44H Rev 1.5 2 1 0 49 / 78 Instructions Description BY25Q64ES 7.3.10 Program Security Registers (42H) See Figure 33, the Program Security Registers instruction is similar to the Page Program instruction. It allows from one byte to 1024 bytes of security register data to be programmed by four times (one time program 256 bytes). A Write Enable instruction must previously have been executed to set the Write Enable Latch bit before sending the Program Security Registers instruction. The Program Security Registers instruction is entered by driving /CS Low, followed by the instruction code (42H), 3-byte address and at least one data byte on SI. As soon as /CS is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. If the Security Registers Lock Bit (LB3/LB2/LB1) is set to 1, the Security Registers will be permanently locked. Program Security Registers instruction will be ignored. ADDRESS A23-A16 A15-12 A11-10 A9-0 Security Register #1 00H 0001 00 Byte Address Security Register #2 00H 0010 00 Byte Address Security Register #3 00H 0011 00 Byte Address Figure 33. Program Security Registers instruction Sequence Diagram /CS Mode 3 SCLK Mode 0 0 4 3 2 1 5 6 7 8 Instruction SI 9 10 28 29 30 31 32 33 34 35 36 37 38 39 24-Bit Address 23 22 21 MSB 42H 3 Data Byte 1 1 2 0 7 MSB 6 5 4 3 2 1 0 /CS 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 2073 2074 2075 2076 2077 2078 2079 SCLK Data Byte 2 SI 7 6 MSB Dec 2022 5 4 3 2 1 0 7 MSB 6 Data Byte 3 5 4 3 2 Rev 1.5 1 0 7 MSB 6 Data Byte 256 3 2 5 4 1 Mode 3 Mode 0 0 50 / 78 Instructions Description BY25Q64ES 7.3.11 Read Serial Flash Discoverable Parameter (5AH) See Figure 34, The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard of JEDEC Standard No.216. The Read SFDP instruction is initiated by driving the /CS pin low and shifting the instruction code “5Ah” followed by a 24-bit address (A23-A0) into the SI pin. Eight “dummy” clocks are also required in SPI mode. Figure 34. Read Serial Flash Discoverable Parameter instruction Sequence Diagram /CS 1 0 2 3 5 4 6 7 8 28 29 30 31 9 SCLK Instruction SI 5AH SO High_Z 23 22 MSB 24-Bit Address 3 2 1 0 /CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK IOs switch from Input to Output Dummy Byte SI SO Dec 2022 7 6 MSB 5 4 3 2 1 0 7 6 MSB Rev 1.5 Data Byte 1 5 4 3 2 1 0 51 / 78 Instructions Description BY25Q64ES Table 9. Signature and Parameter Identification Data Values Description SFDP Signature Comment Add(H) (Byte) DW Add (Bit) Data Data 00H 07:00 53H 53H 01H 15:08 46H 46H 02H 23:16 44H 44H 03H 31:24: 50H 50H Fixed:50444653H SFDP Minor Revision Number Start from 00H 04H 07:00 00H 00H SFDP Major Revision Number Start from 01H 05H 15:08 01H 01H Number of Parameters Headers Start from 00H 06H 23:16 01 H 01 H Unused Contains 0xFFH and can never be changed 07H 31:24 FFH FFH ID number (JEDEC) 00H: It indicates a JEDEC specified header 08H 07:00 00H 00H Parameter Table Minor Revision Number Start from 0x00H 09H 15:08 00H 00H Parameter Table Major Revision Number Start from 0x01H 0AH 23:16 01H 01H Parameter Table Length (in double word) How many DWORDs in the Parameter table 0BH 31:24 09H 09H 0CH 07:00 30H 30H 0DH 15:08 00H 00H 0EH 23:16 00H 00H Parameter Table Pointer (PTP) First address of JEDEC Flash Parameter table Unused Contains 0xFFH and can never be changed 0FH 31:24 FFH FFH ID Number LSB (Manufacturer ID) It is indicates BoyaDevice manufacturer ID 10H 07:00 68H 68H Parameter Table Minor Revision Number Start from 0x00H 11 H 15:08 00H 00H Parameter Table Major Revision Number Start from 0x01H 12H 23:16 01H 01H Parameter Table Length (in double word) How many DWORDs in the Parameter table 13H 31:24 03H 03H 14H 07:00 60H 60H 15H 15:08 00H 00H 16H 23:16 00H 00H 17H 31:24 FFH FFH Parameter Table Pointer (PTP) Unused Dec 2022 First address of Boya Device Flash Parameter table Contains 0xFFH and can never be changed Rev 1.5 52 / 78 Instructions Description BY25Q64ES Table 10. Parameter Table (0): JEDEC Flash Parameter Tables Description Comment Write Granularity 00: Reserved; 01: 4KB erase; 10: Reserved; 11: not support 4KB erase 0: 1Byte, 1: 64Byte or larger Write Enable Instruction Requested for Writing to Volatile Status Registers 0: Nonvolatile status bit 1: Volatile status bit (BP status register bit) Block/Sector Erase Size Write Enable Opcode Select for Writing to Volatile Status Registers Add(H) (Byte) DW Add (Bit) Data 01:00 01b 02 1b 03 0b 30H 0: Use 50H Opcode, 1: Use 06H Opcode, Note: If target flash status register is Nonvolatile, then bits 3 and 4 must be set to 00b. Contains 111b and can never be changed E5H 04 0b 07:05 111b 15:08 20H 16 1b 18:17 00b 19 0b 0=Not support, 1=Support 20 1b (1 -4-4) Fast Read 0=Not support, 1=Support 21 1b (1 -1 -4) Fast Read 0=Not support, 1=Support 22 1b Unused 4KB Erase Opcode (1 -1 -2) Fast Read Address Bytes Number used in addressing flash array Double Transfer Rate (DTR) clocking (1 -2-2) Fast Read 31H 0=Not support, 1=Support 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved 0=Not support, 1=Support 32H Unused Unused Flash Memory Density (1 -4-4) Fast Read Number of Wait states (1 -4-4) Fast Read Number of Mode Bits (1 -4-4) Fast Read Opcode (1 -1 -4) Fast Read Number of Wait states (1 -1 -4) Fast Read Number of Mode Bits (1 -1 -4) Fast Read Opcode (1 -1 -2) Fast Read Number of Wait states (1 -1 -2) Fast Read Number of Mode Bits (1 -1 -2) Fast Read Opcode (1 -2-2) Fast Read Number of Wait states (1 -2-2) Fast Read Number of Mode Bits (1 -2-2) Fast Read Opcode Dec 2022 00000b: Wait states (Dummy Clocks) not support 23 1b 33H 31:24 FFH 37H:34H 31:00 39H 00000b: Wait states (Dummy Clocks) not support 3BH 00000b: Wait states (Dummy Clocks) not support 3DH 07:05 010b 3FH F1H FFH 15:08 EBH 20:16 01000b 23:21 000b 31:24 6BH 04:00 01000b 07:05 000b 15:08 3BH 20:16 00010b 23:21 010b 31:24 BBH 44H EBH 08H 6BH 08H 3EH 000b: Mode Bits not support Rev 1.5 00100b 3CH 000b: Mode Bits not support 0000b: Wait states (Dummy Clocks) not support 04:00 3AH 000b:Mode Bits not support 20H 03FFFFFFH 38H 000b:Mode Bits not support Data 3BH 42H 53 / 78 BBH Instructions Description (2-2-2) Fast Read BY25Q64ES 0=not support 1=support Unused (4-4-4) Fast Read 0=not support 1=support 40H Unused Unused Unused (2-2-2) Fast Read Number of Wait states (2-2-2) Fast Read Number of Mode Bits (2-2-2) Fast Read Opcode Unused (4-4-4) Fast Read Number of Wait states (4-4-4) Fast Read Number of Mode Bits (4-4-4) Fast Read Opcode Sector Type 1 Size 0 0000b: Wait states (Dummy Clocks) not support Sector Type 1 erase Opcode Sector Type 2 Size Sector/block size=2^N bytes 0x00b: this sector type don’t exist Sector Type 2 erase Opcode Sector Type 3 Size Sector/block size=2^N bytes 0x00b: this sector type don’t exist Sector Type 3 erase Opcode Sector Type 4 Size Sector/block size=2^N bytes 0x00b: this sector type don’t exist Sector Type 4 erase Opcode Dec 2022 Rev 1.5 04 0b 07:05 EEH 43H:41H 31:08 45H:44H 15:00 20:16 00000b 23:21 000b 47H 31:24 FFH FFH 49H:48H 15:00 FFFFH FFFFH 20:16 00000b 23:21 000b 4BH 31:24 FFH FFH 4CH 07:00 0CH 0CH 4DH 15:08 20H 20H 4EH 23:16 0FH 0FH 4FH 31:24 52H 52H 50H 07:00 10H 10H 51H 15:08 D8H D8H 52H 23:16 00H 00H 53H 31:24 FFH FFH FFFFF FH FFFFH 46H 00H 4AH 000b: Mode Bits not support Sector/block size=2^N bytes 0x00b: this sector type don’t exist 0b 111b 111b FFFFF FH FFFFH 000b: Mode Bits not support 0 0000b: Wait states (Dummy Clocks) not support 00 03:01 00H 54 / 78 Instructions Description BY25Q64ES Table 11. Parameter Table (1): Boya Device Flash Parameter Tables Description Vcc Supply Maximum Voltage Vcc Supply Minimum Voltage HW Reset# pin HW Hold# pin Deep Power Down Mode SW Reset SW Reset Opcode Program Suspend/Resume Erase Suspend/Resume Unused Wrap-Around Read mode Wrap-Around Read mode Opcode Wrap-Around Read data length Individual block lock Individual block lock bit(Volatile/Nonvolatil e) Individual block lock Opcode Individual block lock Volatile protect bit default protect status Secured OTP Comment Add(H) (Byte) DW Add (Bit) 61H:60H 63H:62H Data Data 15:00 3600H 3600H 31:16 2700H 2700H 00 1b 0=not support 1=support 01 1b 0=not support 1=support 02 1b 0=not support 1=support Should be issue Reset Enable(66H)before Reset cmd. 03 1b 11:04 99H 0=not support 1=support 12 0b 0=not support 1=support 13 1b 14 1b 15 1b 66H 23:16 77H 77H 67H 31:24 64H 64H 00 0b 01 0b 09:02 FFH 10 0b 2000H=2.000V 2700H=2.700V 3600H=3.600V 1650H=1.650V 2250H=2.250V 2350H=2.350V 2700H=2.700V 0=not support 1=support 65H:64H 0=not support 1=support 08H:support 8B wrap-around read 16H:8B&16B 32H:8B&16B&32B 64H:8B&16B&32B&64B 0=not support 1=support 0=Volatile 1=Nonvolatile 0=protect 1=unprotect 6BH:68H 0=not support 1=support 11 1b Read Lock 0=not support 1=support 12 0b Permanent Lock 0=not support 1=support E99FH EBFCH 13 1b Unused 15:14 11b Unused 31:16 FFFFH Dec 2022 Rev 1.5 FFFFH 55 / 78 Instructions Description 7.4 BY25Q64ES Program and Erase Instructions 7.4.1 Page Program (02H) The Page Program instruction is for programming the memory. A Write Enable instruction must previously have been executed to set the Write Enable Latch bit before sending the Page Program instruction. See Figure 35, the Page Program instruction is entered by driving /CS Low, followed by the instruction code, 3-byte address and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). /CS must be driven low for the entire duration of the sequence. The Page Program instruction sequence: /CS goes low-> sending Page Program instruction ->3-byte address on SI ->at least 1 byte data on SI-> /CS goes high. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. /CS must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program instruction is not executed. As soon as /CS is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A Page Program instruction applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table 6-Table 7) are not executed. Figure 35. Page Program Sequence Diagram /CS Mode 3 0 SCLK Mode 0 4 3 2 1 5 6 7 9 8 10 Instruction 31 32 33 34 35 36 37 38 39 24-Bit Address 23 22 21 MSB 02H SI 29 30 28 3 Data Byte 1 1 2 0 7 6 MSB 5 4 3 2 1 0 /CS 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 2073 2074 2075 2076 2077 2078 2079 Mode 3 Mode 0 SCLK Data Byte 2 SI 7 6 MSB Dec 2022 5 4 3 2 1 0 7 6 MSB Data Byte 3 4 3 2 5 Rev 1.5 1 0 7 6 MSB Data Byte 256 3 2 5 4 1 0 56 / 78 Instructions Description BY25Q64ES 7.4.2 Quad Page Program (32H) The Quad Page Program instruction is for programming the memory using for pins: IO0, IO1, IO2 and IO3. To use Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable instruction must previously have been executed to set the Write Enable Latch bit before sending the Page Program instruction. The Quad Page Program instruction is entered by driving /CS Low, followed by the instruction code (32H), three address bytes and at least one data byte on IO pins. The Quad Enable bit (QE) of Status Register must be set to enable. The instruction sequence is shown in Figure 36. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. /CS must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Quad Page Program instruction is not executed. As soon as /CS is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A Quad Page Program instruction applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table 6-Table 7) is not executed Figure 36. Quad Page Program Sequence Diagram /CS Mode 0 0 SCLK Mode 3 1 2 3 4 5 6 7 Instruction SI (IO0) 30 31 32 33 34 35 36 37 38 39 8 24-bits address 32H 23 22 0 1 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 MSB SO (IO1) High_Z WP (IO2) High_Z HOLD (IO3) High_Z 7 3 7 3 7 3 7 3 MSB MSB MSB MSB Byte4 Byte1 Byte2 Byte3 /CS SCLK 40 41 42 43 44 45 46 47 48 535 536 537 538 539 540 541 542 543 SI (IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 SO (IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP (IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 MSB MSB MSB MSB Byte 5 Byte 6 Byte 7 Byte 8 7 3 7 3 7 3 7 3 Mode 0 Mode 3 High_Z High_Z High_Z High_Z HOLD (IO3) Dec 2022 MSB MSB MSB MSB Byte 253 Byte 254 Byte 255 Byte 256 Rev 1.5 57 / 78 Instructions Description BY25Q64ES 7.4.3 Sector Erase (20H) The Sector Erase instruction is for erasing the all data of the chosen sector. A Write Enable instruction must previously have been executed to set the Write Enable Latch bit. The Sector Erase instruction is entered by driving /CS low, followed by the instruction code, and 3-address byte on SI. Any address inside the sector is a valid address for the Sector Erase instruction. /CS must be driven low for the entire duration of the sequence. See Figure 37, The Sector Erase instruction sequence: /CS goes low-> sending Sector Erase instruction-> 3-byte address on SI ->/CS goes high. /CS must be driven high after the eighth bit of the last address byte has been latched in; otherwise the Sector Erase instruction is not executed. As soon as /CS is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A Sector Erase instruction applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table 6-Table 7) is not executed. Figure 37.Sector Erase Sequence Diagram /CS Mode 3 0 SCLK Mode 0 1 2 3 4 5 Instruction SI Dec 2022 6 7 8 9 24-Bit Address 23 22 MSB 20H Rev 1.5 29 30 31 Mode 3 Mode 0 2 1 0 58 / 78 Instructions Description BY25Q64ES 7.4.4 32KB Block Erase (52H) The 32KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable instruction must previously have been executed to set the Write Enable Latch bit. The 32KB Block Erase instruction is entered by driving /CS low, followed by the instruction code, and 3-byte address on SI. Any address inside the block is a valid address for the 32KB Block Erase instruction. /CS must be driven low for the entire duration of the sequence. See Figure 38, the 32KB Block Erase instruction sequence: /CS goes low ->sending 32KB Block Erase instruction ->3-byte address on SI ->/CS goes high. /CS must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase instruction is not executed. As soon as /CS is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A 32KB Block Erase instruction applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table 6-Table 7) is not executed. Figure 38. 32KB Block Erase Sequence Diagram /CS Mode 3 0 SCLK Mode 0 1 2 3 4 5 6 Instruction SI Dec 2022 7 8 9 29 30 31 Mode 3 Mode 0 24-Bit Address 23 22 MSB 52H Rev 1.5 2 1 0 59 / 78 Instructions Description BY25Q64ES 7.4.5 64KB Block Erase (D8H) The 64KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable instruction must previously have been executed to set the Write Enable Latch bit. The 64KB Block Erase instruction is entered by driving /CS low, followed by the instruction code, and 3-byte address on SI. Any address inside the block is a valid address for the 64KB Block Erase instruction. /CS must be driven low for the entire duration of the sequence. See Figure 39, the 64KB Block Erase instruction sequence: /CS goes low sending 64KB Block Erase instruction 3-byte address on SI /CS goes high. /CS must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase instruction is not executed. As soon as /CS is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A 64KB Block Erase instruction applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table 6-Table 7) is not executed. Figure 39. 64KB Block Erase Sequence Diagram /CS Mode 3 0 SCLK Mode 0 1 2 3 4 5 6 Instruction SI Dec 2022 7 8 9 29 30 31 Mode 3 Mode 0 24-Bit Address 23 22 MSB D8H Rev 1.5 2 1 0 60 / 78 Instructions Description BY25Q64ES 7.4.6 Chip Erase (60/C7H) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 40. The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will commence for a time duration of tCE. While the Chip Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the WIP bit. The WIP bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other Instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction is executed only if all Block Protect (BP2, BP1, and BP0) bits are 0.The Chip Erase instruction is ignored if one or more sectors are protected. Figure 40. Chip Erase Sequence Diagram /CS SCLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 Mode 3 Mode 0 Instruction Dec 2022 SI 60H or C7H SO High_Z Rev 1.5 61 / 78 Instructions Description BY25Q64ES 7.4.7 Erase Suspend (75H) The Erase Suspend instruction “75h” allows the system to interrupt a Sector/32K/64K Block Erase operation (The time between the Erase instruction and the Erase Suspend instruction is tES). After the erase operation has entered the suspended state, the memory array can be read or programed except for the sector/32kb block/64kb block being erased. Write status register operation can't be suspended. The Erase Suspend instruction sequence is shown in Figure 41. Table 11. Readable or Programmable Area of Memory While an Erase Operation is Suspended Readable Region or Programmable Of Memory Array All but the Sector being Erased All but the 32KB Block being Erased All but the 64KB Block being Erased Suspended operation Sector Erase(4KB) Block Erase(32KB) Block Erase(64KB) When the Serial NOR Flash receives the Suspend instruction, there is a latency of tESL before the Write Enable Latch (WEL) bit clears to “0” and the SUS sets to “1”, after which the device is ready to accept one of the instructions listed in "Table Acceptable Instructions During Erase Suspend after tESL" (e.g. FAST READ). Refer to " AC Characteristics" for tESL timings. "Table Acceptable instructions During Suspend (tESL not required)" lists the Instructions for which the tESL latencies do not apply. For example, “05h”, “66h” and “99h” can be issued at any time after the Suspend instruction. Status Register bit 15 (SUS) can be read to check the suspend status. The SUS (Erase Suspend Bit) sets to “1” when an erase operation is suspended. The SUS clears to “0” when the erase instruction is resumed. Table 12. Acceptable instructions During Erase Suspend after tESL Instruction code Erase Suspend Write Enable 06h * Write Disable 04h * Read Data 03h * Fast Read 0Bh * Dual Output Fast Read 3Bh * Quad Output Fast Read 6Bh * Dual I/O Fast Read BBh * Quad I/O Fast Read EBh * Quad I/O Word Fast Read E7h * Set Burst with Wrap 77h * Read Mftr./Device ID 90h * Dual IO Read Mftr./Device ID 92h * Quad IO Read Mftr./Device ID 94h * Read JEDEC ID 9Fh * Read Unique ID Number 4Bh * Release Powen-down/Device ID ABh * Instruction Name Dec 2022 Rev 1.5 62 / 78 Instructions Description BY25Q64ES Instruction code Erase Suspend Read Securty Registers 48h * Read SFDP 5Ah * Page Program 02h * Quad Page Program 32h * Program/Erase Resume 7Ah * Instruction Name Table 13. Acceptable Instructions During Suspend(tESL not required) Instruction Name Instruction code Erase Suspend Read Status Register-1 05H * Read Status Register-2 35H * Read Status Register-3 15H * Enable Reset 66H * Reset Device tESL: Erase Suspend Latency. 99H * Figure 41. Erase Suspend Instruction Sequence /CS SCLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 tPSL/tESL Mode 3 Mode 0 Instruction SI 75H SO High_Z Accept instructions Dec 2022 Rev 1.5 63 / 78 Instructions Description BY25Q64ES 7.4.8 Erase Resume (7AH) The Erase Resume instruction “7Ah” must be written to resume the Sector or Block Erase operation after an Erase Suspend. The Resume instruction “7AH” will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the WIP bit equals to 0. After the Resume instruction is issued the SUS bit will be cleared from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200 ns and the Sector or Block will complete the erase operation. If the SUS bit equals to 0 or the WIP bit equals to 1, the Resume instruction “7Ah” will be ignored by the device. The Erase Resume instruction sequence is shown in Figure 42. Figure 42. Erase Resume Instruction Sequence /CS Mode 3 SCLK 0 1 2 3 4 Mode 0 5 6 7 Mode 3 Mode 0 Instruction Dec 2022 SI 7AH SO High_Z Rev 1.5 64 / 78 Electrical Characteristics BY25Q64ES 8. Electrical Characteristics 8.1 Absolute Maximum Ratings Parameter Symbol Supply Voltage VCC Voltage Applied to Any Pin VIO Transient Voltage on any Pin VIOT Storage Temperature TSTG Electrostatic Discharge Voltage VESD Conditions Range Unit. –0.5 to 4 V Relative to Ground –0.5 to 4 V
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