CD4013BE

XBLCD4013 Dual D-Type Flip Flop General Description The CD4013 is a dual D-type flip-flop that features independent set-direct input (SD), clear-direct input (CD), clock input (CP) and outputs (Q, �). Data is accepted when CP is LOW and is transferred to the output on the positive -going edge of the clock. The active HIGH asynchronous CD and SD inputs are independent and override the D or CP inputs. The outputs are buffered for best system performance. The clock input’s Schmitt-trigger action makes the circuit highly tolerant of slower clock rise and fall times. It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. Features  Wide supply voltage range from 3V to 15V  Fully static operation  5V, 10V, and 15V parametric ratings  Standardized symmetrical output characteristics  Tolerant of slow clock rise and fall times  Specified from -40℃ to +85℃  Packaging information: DIP14/SOP14/TSSOP14 ORDERING INFORMATION DEVICE Package Type MARKING Packing Packing QTY CD4013BE CD4013BDTR CD4013BTDTR DIP-14 SOP-14 TSSOP-14 CD4013BE CD4013B CD4013B Tube Tape Tape 1000/Box 2500/Reel 3000/Reel XBLW version 1.0 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 1 页 共 13 页 XBLCD4013 Dual D-Type Flip Flop Block Diagram And Pin Description Block Diagram Figure 1. Functional diagram Figure 2. Logic diagram(one flip-flop) Pin Configurations XBLW version 1.0 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 2 页 共 13 页 XBLCD4013 Dual D-Type Flip Flop Pin Description Pin No. Pin Name Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1Q 1� 1CP 1CD 1D 1SD VSS 2SD 2D 2CD 2CP 2� 2Q VDD true output complement output clock input (LOW to HIGH edge-triggered) asynchronous clear-direct input (active HIGH) data input asynchronous set-direct input(active HIGH) ground (0V) asynchronous set-direct input(active HIGH) data input asynchronous clear-direct input (active HIGH) clock input (LOW to HIGH edge-triggered) complement output true output supply voltage Function Table Input Output nSD nCD nCP nD nQ H L X X H L H X X L H H X X H L L ↑ L L L L ↑ H H Note: H=HIGH voltage level; L=LOW voltage level; X=don’t care; ↑=LOW-to-HIGH clock transition. nQ L H H H L Electrical Parameter Absolute Maximum Ratings (Voltages are referenced to VSS (ground=0V), unless otherwise specified.) Parameter Symbol Conditions Min. Max. Unit supply voltage DC input current input voltage storage temperature total power dissipation device dissipation VDD IIK VI Tstg any one input all inputs - -0.5 -0.5 -65 +18 ±10 VDD +0.5 +150 V mA V ℃ Ptot - - 500 mW - 100 mW ℃ ℃ Soldering temperature XBLW version 1.0 P TL per output transistor DIP 10s SOP 245 250 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 3 页 共 13 页 XBLCD4013 Dual D-Type Flip Flop Note: [1] For DIP14 packages: above 70℃ the value of Ptot derates linearly with 12mW/K. [2] For SOP14 packages: above 70℃ the value of Ptot derates linearly with 8mW/K. [3] For (T)SSOP14 packages: above 60℃ the value of Ptot derates linearly with 5.5mW/K. Recommended Operating Conditions Parameter Symbol Conditions Min. Typ. Max. Unit supply voltage ambient temperature VDD - 3 - 15 V Tamb in free air -40 - +85 ℃ VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V 40 20 15 140 60 40 3.5 8 12 - - - ns ns ns ns ns ns MHz MHz MHz uS us uS ns set-up time tSU clock pulse width twCL 7 fCL 16 24 15 clock rise and fall time trCL, tfCL 10 5 180 Set or reset pulse width twS/R 80 ns 50 ns Note: If more than one unit is cascaded in a parallel clocked operation, trCL must be made less than or equal to the clock input frequency sum of the fixed propagation delay time at 15pF and the transistion time of the output driving stage for the estimated capacitive load. XBLW version 1.0 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 4 页 共 13 页 XBLCD4013 Dual D-Type Flip Flop Electrical Characteristics DC Characteristics 1 (Tamb=25℃, voltages are referenced to VSS (ground=0V), unless otherwise specified.) Parameter supply current LOW-level output current HIGH-level output current LOW-level output voltage HIGH-level output voltage LOW-level input voltage Symbol IDD IOL IOH VOL VOH VIL HIGH-level input voltage VIH input leakage current II XBLW version 1.0 VO Conditions(V) VIN VDD Min. Tamb=25℃ Typ. Max. Unit - 0, 5 5 - 0.02 1 μA - 0, 10 10 - 0.02 2 μA - 0, 15 15 - 0.02 4 μA 0.4 0, 5 5 0.51 1 - mA 0.5 0, 10 10 1.3 2.6 - mA 1.5 0, 15 15 3.4 6.8 - mA 4.6 0, 5 5 -0.51 -1 - mA 2.5 0, 5 5 -1.6 -3.2 - mA 9.5 0, 10 10 -1.3 -2.6 - mA 13.5 0, 15 15 -3.4 -6.8 - mA - 0, 5 5 - 0 0.05 V - 0, 10 10 - 0 0.05 V - 0, 15 15 - 0 0.05 V - 0, 5 5 4.95 5 - V - 0, 10 10 9.95 10 - V - 0, 15 15 14.95 15 - V 0.5, 4.5 - 5 - - 1.5 V 1, 9 - 10 - - 3 V 1.5, 13.5 - 15 - - 4 V 0.5, 4.5 - 5 3.5 - - V 1, 9 - 10 7 - - V 1.5, 13.5 - 15 11 - - V - 0, 15 15 - ±10-5 ±0.1 μA 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 5 页 共 13 页 XBLCD4013 Dual D-Type Flip Flop DC Characteristics 2 (Tamb=-40℃ to +85℃, voltages are referenced to VSS (ground=0V), unless otherwise specified.) Parameter supply current Symbol IDD LOW-level output current IOL HIGH-level output current IOH LOW-level output voltage VOL HIGH-level output voltage VOH LOW-level input voltage VIL HIGH-level input voltage VIH input leakage current II XBLW version 1.0 Conditions(V) VO VIN VDD Tamb=-40℃ Min. Max. Tamb=+85℃ Min. Max. Unit - 0, 5 5 - 1 - 30 μA - 0, 10 10 - 2 - 60 μA - 0, 15 15 - 4 - 120 μA 0.4 0.5 1.5 4.6 2.5 9.5 13.5 0.5, 4.5 1, 9 1.5, 13.5 0.5, 4.5 1, 9 1.5, 13.5 0, 5 0, 10 0, 15 0, 5 0, 5 0, 10 0, 15 0, 5 0, 10 0, 15 0, 5 0, 10 0, 15 - 5 10 15 5 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 0.61 1.5 4 -0.61 -1.8 -1.5 -4 4.95 9.95 14.95 3.5 7 11 0.05 0.05 0.05 1.5 3 4 - 0.42 1.1 2.8 -0.42 -1.3 -1.1 -2.8 4.95 9.95 14.95 3.5 7 11 0.05 0.05 0.05 1.5 3 4 - mA mA mA mA mA mA mA V V V V V V V V V V V V - 0, 15 15 - ±0.1 - ±1 μA 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 6 页 共 13 页 XBLCD4013 Dual D-Type Flip Flop AC Characteristics (Tamb=25℃, VSS=0V, tr, tf=20ns, CL=50pF, RL=20KΩ, unless otherwise specified.) Parameter HIGH to LOW propagation delay Symbol Conditions nCP to nQ,n�; see Figure 4 tPHL nSD to n� or nCD to nQ nCP to nQ,n�; see Figure 4 LOW to HIGH propagation delay tPLH transition time tt see Figure 4 maximum clock frequency fclk(max) see Figure 4 nSD to nQ or nCD to n� nCP input LOW; see Figure 4 pulse width tW set-up time tSU nD to nCP; see Figure 4 hold time th nD to nCP; see Figure 4 clock input rise or fall time trCL,tfCL - input CI capacitance Note: tt is the same as tTLH and tTHL. XBLW version 1.0 nSD input HIGH or nCD input HIGH; see Figure 5 VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V VDD=5V VDD=10V VDD=15V any input Min. Typ. Max. Unit 3.5 8 12 - 150 65 45 200 85 60 150 65 45 150 65 45 100 50 40 7 16 24 70 30 20 90 40 25 20 10 7 2 2 2 - 300 130 90 400 170 120 300 130 90 300 130 90 200 100 80 140 60 40 180 80 50 40 20 15 5 5 5 15 10 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns us us us - 5 7.5 pF 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 7 页 共 13 页 XBLCD4013 Dual D-Type Flip Flop Testing Circuit AC Testing Circuit Figure 3. Test circuit for switching times Definitions for test circuit: DUT=Device Under Test CL=Load capacitance including jig and probe capacitance. RT=Termination resistance should be equal to the output impedance Zo of the pulse generator. AC Testing Waveforms Figure 4. Set-up time, hold time, minimum clock pulse width, propagation delays and transition times XBLW version 1.0 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 8 页 共 13 页 XBLCD4013 Dual D-Type Flip Flop Figure 5. nSD, nCD pulse width Measurement Points Supply voltage VDD 5V to 15V Input VM 0.5×VDD Output VX 0.1×VDD VM 0.5×VDD VY 0.9×VDD Test Data Supply voltage VDD VI tr, tf Load CL 5V to 15V VSS or VDD ≤20ns 50pF XBLW version 1.0 Input 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 9 页 共 13 页 XBLCD4013 Dual D-Type Flip Flop Package Information DIP14 Symbol A A1 A2 B B1 C D E E1 e L E2 XBLW version 1.0 Dimensions In Millimeters Min Max 3.710 4.310 0.510 3.200 3.600 0.380 0.570 1.524(BSC) 0.204 0.360 18.800 19.200 6.200 6.600 7.320 7.920 2.540(BSC) 3.000 3.600 8.400 9.000 Dimensions In Inches Min Max 0.146 0.170 0.020 0.126 0.142 0.015 0.022 0.060(BSC) 0.008 0.014 0.740 0.756 0.244 0.260 0.288 0.312 0.100(BSC) 0.118 0.142 0.331 0.354 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 10 页 共 13 页 XBLCD4013 Dual D-Type Flip Flop SOP14 XBLW version 1.0 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 11 页 共 13 页 XBLCD4013 Dual D-Type Flip Flop TSSOP14 SYMBOL A A1 A2 A3 b b1 c c1 D E1 E e L L1 θ XBLW version 1.0 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ MILLIMETER MIN MAX 1.20 0.05 0.15 0.90 1.05 0.39 0.49 0.20 0.30 0.19 0.25 0.13 0.19 0.12 0.14 4.86 5.06 4.30 4.50 6.20 6.60 0.65BSC 0.45 0.75 1.00BSC 0° 8° 第 12 页 共 13 页 XBLCD4013 Dual D-Type Flip Flop Statements And Notes Part name Lead and lead compounds Lead frame ○ Plastic resin ○ ○ ○ ○ ○ ○ Chip ○ ○ ○ ○ ○ The lead Plastic sheet installed ○ ○ ○ ○ ○ ○ ○ ○ explanation Cadmium and cadmium compounds ○ Hazardous substances or Elements Polybro Hexavalent Polybro minated Dibutyl chromium minated biphenyl phthalate compounds biphenyls ethers ○ ○ ○ ○ Mercury and mercury compounds ○ Butyl benzyl phthalate Di-2ethylhexyl phthalate Diisobutyl phthalate ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○: Indicates that the content of hazardous substances or elements in the detection limit of the following the SJ/T11363-2006 standard. ×: Indicates that the content of hazardous substances or elements exceeding the SJ/T11363-2006 Standard limit requirements Statement：  Shenzhen xinbole electronics co., ltd. reserves the right to change the product specifications, without notice! Before placing an order, the customer needs to confirm whether the information obtained is the latest version, and verify the integrity of the relevant information.  Any semiconductor product is liable to fail or malfunction under certain conditions, and the buyer shall be responsible for complying with safety standards in the system design and whole machine manufacturing using Shenzhen xinbole electronics co., ltd products, and take appropriate security measures to avoid the potential risk of failure may result in personal injury or property losses of the situation occurred!  Product performance is never ending, Shenzhen xinbole electronics co., ltd will be dedicated to provide customers with better performance, better quality of integrated circuit products. XBLW version 1.0 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 13 页 共 13 页