Etek
Microelectronics
The ET7301B is a programmable USB Type-Control IC. It supports the USB Type-C connector application with
Configuration Channel (CC) control logic detection and indication functions. This products support a flexible
hardware solution to configure DFP/UFP/DRP connection. It can connect to a controller through I2C-bus
interface. ET7301B performs USB Type-C detection including attach, detach and orientation. It setup VBUS
threshold detection automatically as well as the various charging current levels. ET7301B provide the software
flexibility for multiple platform support.
The ET7301B integrates the physical layer of the USB BMC PD (Power Delivery) protocol to allow up to 100W
of power and role swap. The BMC PD block enables full support for alternative interfaces of the Type-C
specification.
●
Dual-Role Functionality with Autonomous DRP Toggle
●
Software configurable either as a dedicated host, dedicated device, or dual role. Dedicated devices can
operate both on a Type-C receptacle or a Type-C plug with a fixed CC and VCONN channel
●
Full Type-C Specification 1.1 support. Configuration Channel (CC)
●
–
Role Detection and Configuration: DFP/UFP/DRP
–
Type-C USB Port Detection of Attach and Orientation
–
Type-C Current Mode、Audio Adapter Accessory Mode、Debug Accessory Mode
–
Active Cable Detection
USB Power Delivery(PD) Specification 2.0, Version 1.1 Support
–
Automatic GoodCRC Packet Response
–
Automatic retries of sending a packet if a GoodCRC is not received
–
Automatic soft reset packet sent with retries if needed、Automatic Hard Reset Ordered Set Sent
●
Dead Battery Support (SNKMode Support when No Power Applied)
●
High Speed I2C Interface
●
Supply Voltage:2.8V to 5.5V
●
Low Standby Supply Current: IDD =25uA (Typical)
●
Package:WLCSP9(ET7301B),QFN14(ET7301BY)
Part No.
Package
Size
MSL
ET7301B
WLCSP
1.22mm×1.2mm
Level 1
ET7301BY
QFN14
2.5mm×2.5mm
Level 1
1
Rev 1.2
ET7301B
●
Host, Device, Dual Role Port Applications
●
Smart phones,Tablets and Notebooks
●
USB Peripheral
1
2
3
A
CC2
VBUS
VDD
B
VCONN
INT
SCL
C
CC1
GND
SDA
A
B
C
3
2
1
VDD
VBUS
CC2
SCL
INT
VCONN
SDA
GND
CC1
TOP VIEW
BOOTM VIEW
CSP9(ET7301B)
14
CC2
13
12
VCONN
VCONN
11
CC1
11
CC1
12
13
VCONN
VCONN
14
CC2
1
CC2
10
CC1
10
CC1
1
CC2
2
VBUS
9
GND
9
GND
2
VBUS
3
VDD
8
GND
8
GND
3
VDD
4
VDD
5
__
INT
6
SCL
7
SDA
7
SDA
TOP VIEW
6
SCL
5
__
INT
4
VDD
BOOTM VIEW
QFN14(ET7301BY)
Figure 1. Pin Assignment
2
Rev 1.2
ET7301B
1,14
A1
CC2
2
A2
VBUS
3,4
A3
VDD
13
B1
VCONN
5
B2
6
B3
SCL
I2C communication clock signal
10,11
C1
CC1
Type-C connector configuration channel pin1
8,9
C2
GND
Ground ( All ground must connected together in application)
7
C3
SDA
I2C communication data signal
_______
INT
Type-C connector configuration channel pin2
USB VBUS detect terminal .Expected to be an OVP protect input
Positive supply
Regulated power input for USB3.1 full featured cables or other accessories
Interrupt terminal to u-processor indicating register update
( Low active open-drain output )
VDD
VBUS
BMC Physical Layer
FIFO
PD
Configuration
FIFO
access
Ip
INT
CC1
VCONN
m
Status
&
Control
Rd
CC2
Rd
DAC
&
Analog Fixed Level
IIC Interface
SCL
GND
SDA
Figure 2. Function Block
3
Rev 1.2
ET7301B
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or
be operable above the recommended operating conditions and stressing the parts to these levels is not
recommended.In addition, extended exposure to stresses above the recommended operating conditions may
affect device reliability. The absolute maximum ratings are stress ratings only.
VBUS
VBUS Voltage to GND
-0.3
28
V
VDD
Supply Voltage to GND
-0.3
6
V
VIN
Input Voltage
-0.3
6
V
TJ
Junction Temperature
+150
°C
TSTG
Storage Temperature Range
+150
°C
PD
Power Dissipation
400
mW
ESD/Electrostatic Discharge Capability
-65
Human Body Model, JESD22-A114
4
Charged Device Model,JESD22-C101
1
kV
The Recommended Operating Conditions table defines the conditions for actual device operation.
Recommended operating conditions are specified to ensure optimal performance to the datasheet
specifications. ET7301B does not recommend exceeding them or designing to Absolute Maximum Ratings.
VBUS
VBUS Voltage To GND
GND=0V
4.0
28
V
VDD
Power Supply Voltage To GND
GND=0V
2.8
5.5
V
VCONN
VCONN Supply Voltage To GND
GND=0V
2.7
5.5
V
IVCONN
VCONN Supply Current
560
mA
IOH / IOL
Output Sink/Source Current
200
mA
TA
Operating Temperature, Free Air
+85
°C
VBAT=4.2V
-40
(TA=-40 to +85°C, All typical values are at TA=25°C unless otherwise specified.)
RSW_CCX
ISW_CCX
tSoft_Start
ITOL_CCX
RDEVICE
ZOPEN
RDSON for SW1_CC1 and SW1_CC2
0.4
1.2
Ω
600
800
1000
mA
0.8
1.5
2.2
ms
8
%
VCONN to CC1 & CC2
Over-Current Protection (OCP) limit at which VCONN switch
shuts off over the entire VCONN voltage range. OCPreg=0Fh
Time taken for the VCONN switch to turn on.
Tolerance of CC Current to VDD of 80uA (default), 180uA
(1.5A) and 320 uA (3A)
-8
Device Pull-down Resistance (VDD>3.0 V)
4.59
5.10
5.61
kΩ
Device Pull-down Resistance (VDD=0V. CCx=2.2V)
4.08
5.10
6.20
kΩ
CC Resistance for Disabled State
126
4
kΩ
Rev 1.2
ET7301B
VWAKElow
VWAKEhigh
VBC_LVL
VBC_LVLhys
Wake threshold for CC pin DFP or UFP LOW value. Assumes
bandgap and wake circuit turned on ie PWR[0]=1
Wake threshold for CC pin DFP or UFP HIGH value. Assumes
bandgap and wake circuit turned on ie PWR[0]=1
CC Pin Thresholds. Assumes PWR=4’h7
1.45
V
0.15
0.20
0.25
V
BC=2'b01
0.61
0.66
0.70
V
BC=2'b10
1.56
1.63
1.71
V
Hysteresis on the Ra and Rd Comparators
register. MEAS_VBUS=0
Measure block MDAC step size for each code in MDAC[5:0]
register for VBUS measurement. MEAS_VBUS=1
VVBUSthr
V
BC=2'b00
Measure block MDAC step size for each code in MDAC[5:0]
VMDACstep
0.25
VBUS threshold at which I_VBUSOK interrupt is triggered.
Assumes measure block on ie; PWR[2]=1
20
mV
42
mV
420
mV
4.0
V
When TOGGLE=1, time at which internal versions of
tTOG1
PU_EN1=PU_EN2=0 and PWDN1=PDWN2=1 selected to
30
45
60
ms
20
30
40
ms
present externally as a SNK in the DRP toggle
When TOGGLE=1, time at which internal versions of
tTOG2
PU_EN1=1 or PU_EN2=1 and PWDN1=PDWN2=0 selected to
present externally as a SRC in the DRP toggle
Disable time after a full toggle
tDIS
(tTOG1+tTOG2) cycle so as to save
power
TOG_SAVE_PWR2:1=00
0
ms
TOG_SAVE_PWR2:1=01
40
ms
TOG_SAVE_PWR2:1=10
80
ms
TOG_SAVE_PWR2:1=11
160
ms
TSHUT
Temp. for Vconn Switch Off
145
°C
THYS
Temp. Hysteresis for Vconn Switch Turn On
10
°C
Idisable
Istdby
Disabled
3.0 to
Nothing Attached, No I2C Transactions.
Current
5.5 V
PWR[3:0]=0h
Standby
3.0 to
Current
5.5 V
BMC PD
Ipd_stdby_meas
Standby
Current
3.0 to
5.5 V
0.4
5
uA
25
40
uA
Nothing attached, no I2C traffic,
PWR[3:0]=1h,WAKE_EN=0.TOGGLE=
1 TOG_SAVE_PWR[2:1]=01h
Device Attached, BMC PD Active But
Not Sending or Receiving data.
40
uA
PWR[3:0]=7h
5
Rev 1.2
ET7301B
UI
Unit interval
3.03
3.35
3.7
us
TX Output Resistance
21
50
79
Ω
23
us
Transmitter
ROutput
tEndDriveBMC
tHoldLowBMC
Time to cease driving the line after the end of the last bit of the
Frame
Time to Cease Driving the Line after the final High-to-Low
Transition
1
us
VOH
Logic High Voltage
1.05
1.2
V
VOL
Logic Low Voltage
0
75
mV
-1
1
us
tStartDrive
Time before the start of the first bit of the preamble when the
transmitter shall start driving the line
tRISE_TX
Rise Time
300
ns
tFALL_TX
Fall Time
300
ns
CReceiver
Receiver Capacitance when Driver isn’t Turned On
zBmcRx
Receiver Input Impedance
VSDACstep
VSDAChys
50
pF
1
BMC Receiver SDAC step size for each code in
SDAC[5:0]register
BMC Receiver SDAC hysteresis for each code over the SDAC
range (SDAC_HYS=01)
MΩ
17
mV
85
mV
tRxFilter
Rx Bandwidth Limiting Filter(2)
100
ns
nTransitionCount
Transitions count in time window of 12 µs Min. and 20 µs Max.
3
edges
tACTIVITY
Time from the last BMC
edge(1) to
when ACTIVITY bit goes
LOWin the STATUS register(2)
5
9
us
Notes:
(1) The last BMC edge includes edge when BMC bus is not driven and thus voltage is the result of pull
ups/pull downs to if/when it trips the SDAC receiver threshold to cause another BMC edge.
(2) Guaranteed by characterization. Not production tested
Figure 3. Transmitter Test Load
6
Rev 1.2
ET7301B
tHardReset
If a Soft Reset message fails, a Hard Reset is sent
after tHardReset of CRCReceive Timer expiring
5
ms
5
ms
1.1
ms
75
us
5
ms
195
us
0.4
V
If the ET7301B cannot send a Hard Reset
tHardResetFinish
within tHardResetFinish time because of a busy line, then
aIl_HARDFAIL interrupt is triggered
This is the value for which the CRCReceiveTimer expires.
tReceive
The CRCReceiveTimer is started upon the last bit of
0.9
the EOP of the transmitted packet
Once the CRCReceiveTimer expires, a retry packet has to be
tRetry
sentout within tRetry time. This time is hard to separate externally
fromtReceive since they both happen sequentially with no
visibledifference in the CC output
If a GoodCRC packet is not received within tReceive for
tSoftReset
N_RETRIESthen a Soft Reset packet is
sent within tSoftReset time.
From receiving a packet, we have to send a GoodCRC in
tTransmit
Responsewithin tTransmit time. It is measured from the last bit
of the EOP ofthe received packet to the first bit sent of the
preamble of theGoodCRC packet
(3)
VOL_INTN
INT_N Output Low Voltage (IOL=4mA)
TINT_Mask
Time from global interrupt mask bit cleared to INT_N goes LOW
VILI2C
Low-Level Input Voltage
VIHI2C
High-Level Input Voltage
1.32
V
VHYS
Hysteresis of Schmitt Trigger Inputs
0.09
V
II2C
Input Current of SDA andSCL Pins (Input Voltage 0.26V to 2V)
-10
10
uA
VDD Current when SDA orSCL is HIGH
-10
10
uA
0
0.3
V
ICCTI2C
VOLSDA
us
0.51
(Input Voltage 1.8V)
SDA Open-Drain Low-Level Output Voltage
50
(IOL=3mA)
IOLSDA
SDA Open-Drain Low-Level Output Current(VOLSDA=0.4V)
CI
Capacitance for Each I/O Pin
20
V
mA
5
pF
Note:
(3) The external I2C pull-up voltage must be between 1.71V and VDD.
7
Rev 1.2
ET7301B
fSCL
tHD;STA
I2C SCL Clock Frequency
0
1000
kHz
Hold Time (Repeated) START Condition
0.26
us
tLOW
Low Period of I2C SCL Clock
0.5
us
tHIGH
High Period of I2C SCL Clock
0.26
us
tSU;STA
Set-up Time for Repeated START Condition
0.26
us
tHD;DAT
Data Hold Time
0
us
50
ns
tSU;DAT
tr
tf
tSU;STQ
Data Set-up
Time(1)
Rise Time of
I2C_SDA
Fall Time of
I2C_SDA
and
and
I2C_SCL
I2C_SCL
Signals(2)
Signals(2)
6
120
ns
120
ns
Set-up Time for STOP Condition
0.26
us
tBUF
Bus-Free Time between STOP and START Conditions
0.5
us
tSP
Pulse Width of Spikes that Must Be Suppressed by the Input Filter
Cb
Capacitive Load for each Bus Line
0
50
ns
550
pF
Figure 4. Definition of Timing for Full-Speed Mode Devices on the I2C Bus
The ET7301B integrates the control and detection functionality required to implement a USB Type-C host,
device or dual-role port including: CC Pull-Down(RD)，Pull-Up (Ip)，VCONN Power Switch，USB BMC Power
Delivery Physical Layer and CCx Threshold Comparators. Each CCx pin contains a flexible switch matrix that
allows the host software to control what type of Type-C port is implemented. The switches are shown in
Figure 5.
8
Rev 1.2
ET7301B
VBUS
VDD
BMC Physical Layer
FIFO
PD
Configuratio
n
FIFO
access
INT
CC1
VCONN
Status
&
Control
m
Rd
CC2
Rd
DAC
&
Analog Fixed Level
GND
IIC Interface
SCL
SDA
Figure 5. Configuration Channel Switch
The ET7301B implements multiple comparators and a programmable DAC that can be used by software to
determine the state of the CC and VBUS pins. This status information provides the software all the
information required to determine attach, detach and charging current capabilities based on the specific
Type-C port to which the ET7301B has been configured.
The ET7301B has three fixed threshold comparators that match the USB Type-C specification for the
threecharging current levels that can be detected by a Type-C device. These comparators automatically
cause a BC_LVL interrupt to occur when there is a change of state. In addition to the fixed threshold
comparators, the host software can use the 6-bit DAC to determine the state of the CC lines more accurately.
The ET7301B also has a fixed comparator that monitors if VBUS has reached a valid threshold or not. The
DAC can be used to measure VBUS up to 26.88V which allows the software to confirm that changes to the
VBUS line have occurred as expected based on various communication methods to change the charging
level.
The ET7301B has the capability to do autonomous DRP toggle. In autonomous toggle the ET7301B internally
controls the PDWN1, PDWN2, PU_EN1 and PU_EN2, MEAS_CC1 and MEAS_CC2 and implements a fixed
DRP toggle between presenting as a SRC and presenting as a SNK. Alternately, it can present as a SRC or
SNK only and poll CC1 and CC2 continuously.
9
Rev 1.2
ET7301B
Autonomous Device Toggle register setup through I 2C.
TOGGLE
1
HOST_CUR0
1
HOST_CUR1
0
MEAS_VBUS
0
VCONN_CC1
0
VCONN_CC2
0
Mask Register
0xFE
Maska Register
0xBF
Maskb Register(Except I_TOGDONE and I_BC_LVL Interrupt)
0x01
PWR[3:0]
0x07
When TOGGLE bit (Control2 register) is set theET7301B implements a fixed DRP toggle between presenting
as a SRC and as a SNK. It can also be configured to present as a SRC only or SNK only and poll CC1 and
CC2 continuously. This operation is turned on with TOGGLE=1 and the processor should initially.
WriteHOST_CUR1=0,
HOST_CUR0=1(fordefaultcurrent) ,VCONN_CC1=VCONN_CC2=0,MaskRegister=0xFE,Maskaregister=0xB
F,andMaskb register=0x01, and PWR=0x07. It returns I_TOGDONE and TOGSS1/2. The processor should
also read the interrupt register to clear them prior tosetting the TOGGLE bit.
The ET7301B has the capability to do manual DRP toggle. In manual toggle the ET7301Bis configurable by
the processor software by I2C and setting TOGGLE=0.
The ET7301B implements the Type-C Disabled state which removes all termination from the CC pins. In this
state, the ET7301B monitors the CC pins for any activity which indicates that either a host or a device is
attempting to attach. When the ET7301B detects this activity, it interrupts the host software through the
WAKE interrupt. The host software can then enable the desired termination based on the required port type
and validate the attach per the Type-C specification.
A Type-C device must monitor VBUS to determine if it is attached or detached. The ET7301B provides this
information through the VBUSOK interrupt. After the Type-C device knows that a Type-C host has been
attached, it needs to determine what type of termination is applied to each CC pin. The software determines if
an Ra or Rd termination is present based on the BC_LVL and COMP interrupt and status bits.
Additionally, for Rd terminations, the software can further determine what charging current is allowed by the
Type-C host by reading the BC_LVL status bits. This is summarized in Table 1.
Table 1. Device Interrupt Summary
10
Rev 1.2
ET7301B
2'b00
NA
NA
1
vRA
2'b01
NA
NA
1
vRd-Connect and vRd-USB
2'b10
NA
NA
1
vRd-Connect and vRd-1.5
2'b11
0
1
vRd-Connect and vRd-3.0
Attach
NA
NA
NA
1
Host Attached, VBUS Valid
Detach
NA
NA
NA
0
Host Detached, VBUS Invalid
CC
Detection
6'b11_0100
(2.05 V)
The high level software flow diagram for a Type-C device (UFP) is shown in Figure 6.
Stangdby:
Wating For Attach
Terminal State Changed:
I_TOGDONE Interrupt Occur
Unattched UFP:
Enables Pull-downs & Measure Block To
Detect Attach
Terminal State Updated:
I_VBUSOK Interrupt Occur
Attched UFP:
Determine Attach Orientation
and Port Type
Debug Accessory
Audio Accessory
Terminal State Change
Indecating a detach:
I_VBUSOK Interrupt Occur
Figure 6. UFP Software Flow
When the ET7301B is configured as a Type-C host, the software can use the status of the comparators
andDAC to determine when a Type-C device has been attached or detached and what termination type has
11
Rev 1.2
ET7301B
been attached to each CC pin.
The ET7301B allows the host software to change the charging current capabilities of the port through the
HOST_CUR control bits. If the HOST_CUR bits are changed prior to attach, the ET7301B will automatically
indicate the programmed current capability when a device is attached. If the current capabilities are changed
after a device is attached, the ET7301B will immediately change the CC line to the programmed capability.
The Type-C specification outlines different attach and detach thresholds for a Type-C host that are based on
how much current is supplied to each CC pin. Based on the programmed HOST_CUR setting, the software
adjusts the DAC comparator threshold to match the Type-C specification requirements. The BC_LVL
comparators can also be used as part of the Ra detection flow. This is summarized in Table 2.
Table 2. Host Interrupt Summary
Ra
2'b01
2'b00
NA
NA
2'b10
2'b01
0
6'b00_1000 (0.4 V)
2'b11
2'b10
0
6'b01_0010 (0.8 V)
NA
0
6'b10_0100 (1.6 V)
Attach
NA
1
6'b10_0100 (1.6 V)
Detach
NA
0
6'b11_1101 (2.6 V)
Attach
NA
1
6'b11_1101 (2.6 V)
Detach
NA
2'b01,2'b10
Rd
2'b11
The high level software flow diagram for a Type-C Host (DFP) is shown below in Figure 7.
12
Rev 1.2
ET7301B
Stangdby:
Wating For Attach
Terminal State Changed:
I_TOGDONE Interrupt Occur
Unattched DFP:
Enables Pull-ups & Measure Block To
Detect Attach
Host Software Determine Port Type By I_COMP And
I_BC_LVL Interrupts
Attched DFP:
Host Software Configures ET7301 Based
On Orientation And Enables VBUS and
VCONN
Debug Accessory
Audio Accessory
Terminal State Change Indecating a detach:
I_COMP And I_VBUSOK Interrupt Occur
Figure 7. DFP Software Flow
The Type-C specification allows ports to be both a device or a host depending on what type of port has
attached. This functionality is similar to USB OTG ports with the current USB connectors and is called a
dual-role port. The ET7301B can be used to implement a dual-role port. A Type-C dual role port toggles
between presenting as a Type-C device and a Type-C host. The host software controls the toggle time and
configuration of the ET7301B in each state as shown in Figure 8.
13
Rev 1.2
ET7301B
Stangdby:
Wating For Attach
Terminal State Changed:
I_TOGDONE Interrupt Occur
Host Enables
Low Power State
Unattched UFP:
Enables Pull_downs & Measure Block To
Detect Attach
Host Software
Toggle Expires
Unattched DFP:
Enables Pull-ups & Measure Block To
Detect Attach
Terminal State Updated:
I_VBUSOK Interrupt Occur
Host Software Determine Port Type By I_COMP
And I_BC_LVL Interrupts
Attched UFP:
Determine Attach Orientation
and Port Type
Attched DFP:
Host Software Configures ET7301 Based
On Orientation And Enables VBUS and
VCONN
Terminal State Change Indecating a detach:
I_VBUSOK Interrupt Occur
Terminal State Change Indecating a detach:
I_COMP Interrupt Occur
Figure 8. DRP Software Flow
The Type-C specification outlines the order of precedence for power level determination which covers power
levels from basic USB2.0 levels to the highest levels of USB PD. The host software is expected to follow the
USB Type-C specification for charging current priority based on feedback from the ET7301B detection,
external BC1.2 detection and any USB Power Delivery communication.
The ET7301B does not integrate BC1.2 charger detection which is assumed available in the USB transceiver
or USB charger in the system.
When power is first applied through VDD, the ET7301B is reset and registers are initialized to the default
values shown in the register map. ET7301B can be reset through software by programming the SW_RES bit
in the RESET register.
To properly configure the device in low power operation, place a 0.2uF cap on each CC pin and set the
registers to defaultby programming the SW_RES bit.
The Type-C connector allows USB Power Delivery (PD) to be communicated over the connected CC pin
between two ports. The communication method is the BMC Power Delivery protocol and is used for many
different reasons with the Type-C connector. Possible uses are outlined below.
14
Rev 1.2
ET7301B
●
Negotiating and controlling charging power levels
●
Alternative Interfaces such as MHL, Display Port
●
Vendor specific interfaces for use with custom docks or accessories
●
Role swap for dual-role ports that want to switch who is the host or device
●
Communication with USB3.1 full featured cables
All Messages shall be composed of a Message Header and a variable length (including zero) data
portion. A Message either originates in the Protocol Layer and is passed to the Physical Layer, or it is
received by the Physical Layer and is passed to the Protocol Layer.(Please see the Power Delivery
Specification)
Figure 9.USB Power Delivery Packet Format including Message Payload
The ET7301B integrates a thin BMC PD client which includes the BMC physical layer and packet FIFOs (48
bytes for transmit and 80 bytes for receive) which allows packets to be sent and received by the host software
through I2C accesses. The ET7301B allows host software to implement all features of USB BMC PD through
writes and reads of the FIFO and control of the ET7301B physical interface.
Figure 10. ET7301BBMC Transmitter Block Diagram
Figure 11. ET7301B BMC Receiver Block Diagram
The ET7301B uses tokens to control the transmission of BMC PD packets. These tokens are written to the
transmit FIFO and control how the packet is transmitted on the CC pin. The tokens are designed to be flexible
and support all aspects of the USB PD specification.The ET7301B additionally enables control of the BMC
transmitter through tokens. The transmitter can be enabled or disabled by specific token writes which allow
15
Rev 1.2
ET7301B
faster packet processing by burst writing the FIFO with all the information required to transmit a packet.
The ET7301B receiver stores the received data and the received CRC in the receive FIFO when a valid
packet is received on the CC pin. The BMC receiver automatically enables the internal oscillator , when
activity is sensed on the CC pin , and load the FIFO when a packet is received. The I_ACTIVITY and
I_CRC_CHK interrupts alert the host software that a valid packet was received.
If GoodCRC packet is not received and AUTO_RETRY is set, then a retry of the same message that was in
the TxFIFO written by the processor is executed within tRetry and that is repeated for N_RETRY times.
If the correct GoodCRC packet is still not received for all retries then I_RETRYFAIL interrupt is triggered and if
AUTO_SOFT_RESET is set, then a Soft Reset packet is created (MessageID is set to 0 and the processor
upon servicing I_RETRYFAIL would set the true MessageIDCounter to 0. If this Soft Reset is sent
successfully where a GoodCRC control packet is received with a MessageID=0 then I_TXSENT interrupt
occurs.If no power applied to VDD, then the SRC can recognize the ET7301B as a SNK.
The power delivery packets require a GoodCRC acknowledge packet to be sent for each received packet
where the calculated CRC is the correct value. This calculation is done by the ET7301B and triggers the
I_CRC_CHK interrupt if the CRC is good. If the AUTO_CRC (Switches1 register bit) is set and AUTO_PRE=0,
then the ET7301B will automatically send the GoodCRC control packet in response to alleviate the local
processor from responding quickly to the received packet. If GoodCRC is required for anything beyond SOP,
then enable SOP*.
The ET7301B implements part of the PD protocol layer for sending packets in an autonomous fashion. If not,
this Soft Reset packet is retried N_RETRIES times (MessageID is always 0 for all retries) if a GoodCRC
acknowledge packet is not received with CRCReceiveTimer expiring (tReceive of 1.1 ms max). If all retries fail,
then I_SOFTFAIL interrupt is triggered.
If all retries of the soft reset packet fail and if AUTO_HARD_RESET is set, then a hard reset ordered set is
sent by loading up the TxFIFO with RESET1, RESET1, RESET1, RESET2 and sending a hard reset. Note
only one hard reset is sent since the typical retry mechanism doesn’t apply. The processor’s policy engine
firmware is responsible for retrying the hard reset is it doesn’t receive the required response.
Port software interacts with the port chip in two primary ways:
●
I2C Registers
●
8 bit data tokens sent to or received from the FIFOregister.
●
All reserved bits written in the TxFIFO should be 0 and all reserved bit read from the RxFIFO should
●
be ignored.
Transmit data tokens provide in-sequence transmit control and data for the transmit logic. Note that the token
16
Rev 1.2
ET7301B
codes, and their equivalent USB PD K-Code are not the same. Tokens are read one at a time when they
reach the end of the TX FIFO. I.e., the specified token action is performed before the next token is read from
the TX FIFO.
The tokens are defined as follows:
Alternative method for starting the transmitter with the TX-START bit.This is
not a token written to the TxFIFO but a command much like TX_START but
101xxxx1
(0xA1)
it is more convenient to write it while writing to the TxFIFO in one
TXON
1
contiguous write operation. It is preferred that the TxFIFO is first written
with data and then TXON or TX_START is executed. It is expected that A1h
will be written for TXON not any other bits where x is non-zero such as B1h,
BFh, etc
0x12
SOP1
1
0x13
SOP2
1
0x1B
SOP3
1
0x15
RESET1
1
0x16
RESET2
1
When reaching the end of the FIFO causes a Sync-1 symbol to be
transmitted.
When reaching the end of the FIFO causes a Sync-2 symbol to
betransmitted.
When reaching the end of the FIFO causes a Sync-3 symbol to
betransmitted.
When reaching the end of the FIFO causes a RST-1 symbol to
betransmitted.
When reaching the end of the FIFO causes a RST-2 symbol to
betransmitted.
This data token must be immediately followed by a sequence of N packed
data bytes. This token is defined by the 3 MSB‟s being set to 3’b100. The 5
LSB’s are the number of packed bytes being sent. Note: N cannot be less
0x80
PACKSYM
1+N
than 2 since the minimum control packet has a header that is 2 bytes and N
cannot be greater than 30 since the maximum data packet has 30 bytes (2
byte header +7 data objects each having 4 bytes) Packed data bytes have
two 4 bit data fields. The 4 LSB‟s are sent first, after 4b5b conversion etc in
the chip.
0xFF
JAM_CRC
1
0x14
EOP
1
0xFE
TXOFF
1
Causes the CRC, calculated by the hardware, to be inserted into the
transmit stream when this token reaches the end of the TX FIFO.
Causes an EOP symbol to be sent when this token reaches the end of the
TX FIFO.
Turn off the transmit driver. Typically the next symbol after EOP
Receive Data Tokens
Receive data tokens provide in-sequence receive control and data for the receive logic. The RxFIFO can
absorb as many packets as the number of bytes in the RxFIFO (80 bytes). The tokens are defined as follows :
17
Rev 1.2
ET7301B
111b_bbbb
SOP
1
110b_bbbb
SOP1
1
First byte of a received packet to indicate that the packet is an SOP packet
(“b” is undefined and can be any bit)
First byte of a received packet to indicate that the packet is an SOP’
packet and occurs only if ENSOP1=1 (“b” is undefined and can be any bit)
First byte of a received packet to indicate that the packet is an
101b_bbbb
SOP2
1
SOP”packetand occurs only if ENSOP2=1 (“b” is undefined and can be
any bit)
First byte of a received packet to indicate that the packet is an
100b_bbbb
SOP1DB
1
SOP’_DEBUG packet and occurs only if ENSOP1DB=1 (“b” is undefined
and can be any bit)
First byte of a received packet to indicate that the packet is an
011b_bbbb
SOP2DB
1
SOP”_DEBUG packet and occurs only if ENSOP2DB=1 (“b” is undefined
and can be any bit)
010b_bbbb
001b_bbbb
Do Not
000b_bbbb
1
Use
These can be used in future versions of this device and should not be
relied on to be any special value. (“b” is undefined and can
be any bit)
I2C Interface
The ET7301B includes a full I2C slave controller. The I2C slave fully complies with the I2C specification
Version 6 requirements. This block is designed for fast mode. Examples of an I2C write and read sequence
are shown in Figure 12 and Figure 13 respectively.
Figure 12. I2C Write Example
Note: Single Byte read is initiated by Master with P immediately following first data byte.
Figure 13. I2C Read Example
Note: If Register is not specified Master will begin read from current register. In this case only sequence
showing in Red bracket is needed
Table 3. I2C Slave Address
Name
Size (Bits)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Slave Address
8
0
1
0
0
0
1
0
R/W
18
Rev 1.2
ET7301B
Register Definitions(*)
Address
Register Name
Type
Rst Val
0x01
Device ID
R
8x
0x02
Switches0
R/W
03
PU_EN2
PU_EN1
VCONN_CC2
VCONN_QC1
0x03
Switches1
R/W
20
POWERROLE
SPECRREV1
SPECREV0
DATAROLE
0x04
Measure
R/W
31
MEAS_VBUS
MDAC5
MDAC4
0x05
Slice
R/W
60
SDAC_HYS2
SDAC5
SDAC4
0x06
Control0
R/W/C
24
TX_FLUSH
I NT_MASK
0x07
Control1
R/W/C
00
ENSOP2DB
ENSOP1DB
0x08
Control2
R/W
02
0x09
Control3
R/W
06
0x0A
Mask1
R/W
00
0x0B
Power
R/W
01
0x0C
Reset
W/C
00
0x0D
OCPreg
R/W
0F
0x0E
Maska
R/W
00
0x0F
Maskb
R/W
00
0x3C
Status 0a
R
00
SOFTFAIL
RETRYFAIL
POWER3
POWER2
SOFTRST
HARDRST
0x3D
Status 1a
R
00
TOGSS3
TOGSS2
TOGSS1
RXSOP2DB
RXSOP1DB
RXSOP
0x3E
Interrupta
R/C
00
I_SOFTFAIL
I_RETRYFAIL
I_HARDSENT
I_TXSENT
I_SOFTRST
I_HARDRST
0x3F
Interrupt
R/C
00
0x40
Status0
R
00
VBUSOK
ACTIVITY
COMP
CRC_CHK
ALERT
WAKE
BC_LVL1
BC_LVL0
0x41
Status1
R
28
RXSOP2
RXSOP1
RX_EMPTY
RX_FULL
TX_EMPTY
TX_FULL
OVRTEMP
OCP
0x42
Interrupt
R/C
00
I_VBUSOK
I_ ACTIVITY
I_COMP_CHNG
I_ CRC_CHK
I_ ALERT
I_WAKE
I_COLLISION
I_BC_LVL
0x43
FIFOs
Type C Bits
USB PD Bits
R/W
(11)
00
Bit7
Bit6
Bit5
Bit4
Bit3
Version ID[3:0]
SDAC_HYS1
TOPG_SAVE_
TOPG_SAVE_
PWR2
PWR2
M_VBUSOK
M_OCP_TEMP
Bit2
Bit1
Revision ID[3:0]
MEAS_CC2
MEAS_CC1
PDWN2
PDWN1
AUTO_CRC
TXCC2
TXCC1
MDAC3
MDAC2
MDAC1
MDACO
SDAC3
SDAC2
SDAC1
SDAC0
HOST_CUR1
HOST_CURO
AUTO_PRE
TX_START
RX_FLUSH
ENSOP2
ENSOP1
BIST_MODE2
TOG_RD_ONLY
WAKE_EN
MODE[1:0]
TOGGLE
N_RETRIES[1:0]
AUTO_RETRY
SENDHARD
AUTOHARD
AUTOSOFT
RESET
RESET
RESET
M_CRC_CHK
M_ALERT
M_WAKE
PWR3
PWR2
M_ACTIVITY
M_TOGDONE
Bit0
M_COMP_CHNG
M_SOFTFAIL
M_RETRYFAIL
M_COLLISIO
N
M_BC_LVL
PWR1
PWR0
PD_RESET
SW_RES
OCP_RANGE
OCP_CUR2
OCP_CUR1
OCP_CUR0
M_HARDSENT
M_TXSENT
M_SOFTRST
M_HARDRST
M_GCRCSENT
I_OCP_TEMP
I_TOGDONE
I_GCRCSENT
Write to TX FIFO or read from RX FIFO repeatedly without address auto increment
General Bits
19
Rev 1.2
ET7301B
Note*:
(1) Do not use registers that are blank.
(2) Values read from undefined register bits are not defined and invalid. Do not write to undefined registers.
(3) FIFO register is serially read/written without auto address increment.
Address: 01h-- Device ID
Reset Value: 0x1000_00XX
Type: Read
7:4
Version ID
Device version ID
3:0
Revision ID
Revision History of each version
Address: 02h-- Switches0
Reset Value: 0x0000_0011
Type: Read/write
1: Enable host pull up current to CC2 pin based on
7
PU_EN2
6
PU_EN1
5
VCONN _CC2
1: Enable the VCONN pin to CC2 pin switch
4
VCONN - CC1
1: Enable the VCONN pin to CC1 pin switch
3
MEAS_CC2
2
MEAS_CC1
1
PDWN2
1: Enable Device pull down on CC2 pin
0
PDWN1
1: Enable Device pull down on CC1 pin
Control0registerHOST_CUR[1 :0] setting
1: Enable host pull up current to CC1 pin based on Control0
registerHOST_CUR[1 :0] setting
1: Connect the measure block to CC2 pin to monitor or measure thevoltage
on CC2 pin. Note, PWR=0x07 for proper operation
1: Connect the measure block to CC1 pin to monitor or measure thevoltage
on CC1 pin. Note, PWR=0x07 for proper operation
Address: 03h—Switches1
Reset Value: 0x0010_0000
Type: Read/write
Bit used for constructing the GoodCRC acknowledge packet. Thisbit corresponds
7
POWERROLE
tothe Port Power Role bit in the message header ifan SOP packet is received
1: Source if SOP
0: Sink if SOP
Bit used for constructing the GoodCRC acknowledge packet. Thesebits
correspond to the Specification Revision bits in the messageheader
6:5
SPECREV[1:0]
00: Revision 1.0
01: Revision 2.0
10, 11: Do Not Use
4
DATAROLE
Bit used for constructing the GoodCRC acknowledge packet. Thisbit corresponds
to the Port Data Role bit in the message header.For SOP:
20
Rev 1.2
ET7301B
1: SRC
0: SNK
3
Reserved
Do Not Use
1: Starts the transmitter automatically when a message with a goodCRC is
2
AUTO_CRC
received and automatically sends a GoodCRC acknowledgepacket back to the
relevant SOP*
0: Feature disabled
1
TXCC2
1: Enable BMC transmit driver on CC2 pin
0
TXCC1
1: Enable BMC transmit driver on CC1 pin
Address: 04h--Measure
Reset Value: 0x0011_0001
Type: Read/Write
7
Reserved
Do Not Use
1: Measure VBUS with the MDAC/comparator. This requires MEAS_CCx bits in
6
MEAS_VBUS
Switches0 register to be 0
0: MDAC/comparator measurement is controlled by MEAS_CCx bits
Measure Block DAC data input. The step size is vMDAC step CC which is
dependent on Meas_VBUS register setting. Examples are shown below. Valid
values from 00_0000 to 11_1111 for MEAS_VBUS=1
MDAC[5:0]
5:0
MDAC[5:0]
MEAS_VBUS=0
MEAS_VBUS=1
Unit
00_0000
0.042
0.420
V
00_0001
0.084
0.840
V
11_0000
2.058
20.58
V
11_0011
2.184
21.84
V
11_1110
2.646
26.46
V
11 1111
>2.688
26.88
V
Address: 05h--Slice
Reset Value: 0x0110_0000
Type: Read/Write
Adds hysteresis where there are now two thresholds, the lowerthreshold which is
always the value programmed bySDAC[5:0] and the higher threshold that is:
7:6
SDAC_HYS[1:0]
11: 255 mV hysteresis: higher threshold = (SDAC value + 20hex)
10 :170 mV hysteresis: higher threshold = (SDAC value + 0Ahex)
01 :85 mV hysteresis: higher threshold = (SDAC value + 05hex)
00 : No hysteresis: higher threshold = SDAC value
5:0
SDAC[5:0]
BMC Slicer DAC data input. Allows for a programmable thresholdso as to meet
the BMC receive mask under all noise conditions
21
Rev 1.2
ET7301B
Address: 06h--Control0
Reset Value: 0x0010_0100
Type: (See Column Below)
7
Reserved
N/A
Do Not Use
6
TX_FLUSH
W/C
1: Self clearing bit to flush the content of the transmit FIFO
5
INT_MASK
R/W
4
Reserved
N/A
1: Mask all interrupts
0: Interrupts to host are enabled
Do Not Use
Controls the host pull-up current enabled by PU_EN[2:1]
bits in the Switches0 register:
3:2
HOST_CUR[1 :0]
R/W
00: Current disabled
01: 80 uA - Default USB power
10: 180 uA - Medium Current Mode: 1.5A
11: 330 uA - High Current Mode: 3A
1: Starts the transmitter automatically when a message with a
goodCRC is received. This allows the software to take as much as300
1
AUTO_PRE
R/W
µS to respond after the I_CRC_CHK interrupt is received.Before
starting the transmitter, an internal timer waits forapproximately 170 µS
beforeexecuting the transmit start andpreamble
0: Feature disabled
1: Start transmitter using the data in the transmit FIFO. Preamble is
0
TX_START
W/C
started first. During the preamble period the transmit data can start to
be written to the transmit FIFO. Self clearing
Address: 07h—Control1
Reset Value: 0x0000_0000
Type: (See Column Below)
7
Reserved
N/A
Do Not Use
6
ENSOP2DB
R/W
5
ENSOP1DB
R/W
4
BIST_MODE2
R/W
1: Sent BIST Mode 01s pattern for testing
3
Reserved
N/A
Do Not Use
2
RX_FLLUSH
R/C
1: Self clearing bit to flush the content of the receive FIFO.
1
ENSOP2
R/W
0
ENSOP1
R/W
1: Enable SOP”_DEBUG (SOP double prime debug) packets
0: Ignore SOP”_DEBUG (SOP double prime debug) packets
1: Enable SOP’_DEBUG (SOP prime debug) packets
0: Ignore SOP’_DEBUG (SOP prime debug)
packets
1: Enable SOP”(SOP double prime) packets
0: Ignore SOP”(SOP double prime) packets
1: Enable SOP’(SOP prime) packets
0: Ignore SOP’(SOP prime) packets
22
Rev 1.2
ET7301B
Address: 08h—Control2
Reset Value: Ox0000_0010
Type: (See Column Below)
00: Don’t go into the DISABLE state after one cycle oftoggle
7:6
TOG_SAVE_PWR2
TOG_SAVE_PWR1
R/W
01: Wait between toggle cycles for tDIStime of 40 ms
10: Wait between toggle cycles for tDIS time of 80 ms
11: Wait between toggle cycles for tDIS time of 160 ms
1: When TOGGLE=1 only Rd values will cause the TOGGLEstate
5
TOG_RD_ONLY
R/W
machine to stop toggling and trigger the I_TOGGLEinterrupt
0: When TOGGLE=1, Rd and Ra values will cause theTOGGLE
state machine to stop toggling
4
Reserved
N/A
3
WAKE_EN
R/W
Do Not Use
1: Enable Wake Detection functionality if the power state iscorrect
0: Disable Wake Detection functionality
11: Enable SRC polling functionality if TOGGLE=1
2:1
MODE
R/W
10: Enable SNK polling functionality if TOGGLE=1
01: Enable DRP polling functionality if TOGGLE=1
00: Do Not Use
0
TOGGLE
R/W
1: Enable DRP, SNK or SRC Toggle autonomous functionality
0: Disable DRP, SNK and SRC Toggle functionality
Address: 09h—Control3
Reset Value: Ox0000_0110
Type: (See Column Below)
7
Reserved
N/A
6
SEND_HARD_RESET
W/C
5
Reserved
N/A
4
AUTO_HARDRESET
R/W
3
AUTO_SOFTRESET
R/W
Do Not Use
1: Send a hard reset packet (highest priority)
0: Don’t send a soft reset packet
Do Not Use
1: Enable automatic hard reset packet if soft reset fail
0: Disable automatic hard reset packet if soft reset fail
1: Enable automatic soft reset packet if retries fail
0: Disable automatic soft reset packet if retries fail
11: Three retries of packet (four total packets sent)
2:1
N_RETRIES[1:0]
R/W
10: Two retries of packet (three total packets sent)
01: One retry of packet (two total packets sent)
00: No retries (similar to disabling auto retry)
0
AUTO_RETRY
R/W
1: Enable automatic packet retries if GoodCRC is notreceived
0: Disable automatic packet retries if GoodCRC is notreceived
23
Rev 1.2
ET7301B
Address: 0Ah--Mask0
Reset Value: 0x0000_0000
Type: Read/Write
7
M_VBUSOK
6
M_ACTIVITY
1: Mask I_VBUSOK interrupt bit
0: Do not mask
1: Mask interrupt for a transition in CC bus activity
0: Do not mask
1: Mask I_COMP_CHNG interrupt for change is the value ofCOMP, the
5
M_COMP _CHNG
measure comparator
0: Do not mask
4
M_CRC_CHK
3
M_ALERT
2
M_WAKE
1
M_COLLISION
0
M_BC_LVL
1: Mask interrupt from CRC_CHK bit
0: Do not mask
1: Mask the I_ALERT interrupt bit
0: Do not mask
1: Mask I_WAKE interrupt bit
0: Do not mask
1: Mask the I_COLLISION interrupt bit
0: Do not mask
1: Mask I_BC_LVL interrupt bit
0: Do not mask
Address: 0Bh--Power
Reset Value: 0x0000_0001
Type: Read/write
7:4
Reserved
Do Not Use
Power enables:
PWR[0]: Bandgap and wake circuit
PWR[1]: Receiver powered and current references for Measure block
3:0
PWR[3:0]
PWR[2]: Measure block powered
PWR[3]: Enable internal oscillator,for PD PHY
It is expected that PWR=4'h1 is used for low power WAKE detection.
PWR=4'h7 is used for all other detection
Address: 0Ch--Reset
Reset Value: 0x0000_0000
Type: Write/Clear
7:2
Reserved
N/A
Do Not Use
1
PD_RESET
W/C
1: Reset just the PD logic for both the PD transmitter andreceiver
0
SW_RES
W/C
1: Reset the ET7301B including the I2C registers to their
defaultvalues
24
Rev 1.2
ET7301B
Address: 0Dh--OCPreg
Reset Value: 0x0000_1111
Type: Read/write
7:4
Reserved
3
OCP_RANGE
Do Not Use
1: OCP range between 100 mA-800 mA (max_range=800 mA)
0: OCP range between 10 mA-80 mA (max_range=80 mA)
111: max_range (see bit definition above for OCP_RANGE)
110: 7*max_range/8
101: 6*max_range/8
2:0
OCP_CUR[2:0]
100: 5*max_range/8
011: 4*max_range/8
010: 3*max_range/8
001: 2*max_range/8
000: 1*max_range/8
Address: 0Eh--Maska
Reset Value: 0x0000_0000
Type: Read/Write
7
M_OCP_TEMP
1: Mask the I_OCP_TEMP interrupt
6
M_TOGDONE
1: Mask the I_TOGDONE interrupt
5
M_SOFTFAIL
1: Mask the I_SOFTFAIL interrupt
4
M_RETRYFAIL
1: Mask the I_RETRYFAIL interrupt
3
M_HARDSENT
1: Mask the I_HARDSENT interrupt
2
M_TXSENT
1
M_SOFTRST
1: Mask the I_SOFTRST interrupt
0
M_HARDRST
1: Mask the I_HARDRST interrupt
1: Mask the I_TXSENT interrupt
Address: 0Fh--Maskb
Reset Value: 0x0000_0000
Type: Read/Write
7:1
Reserved
0
M_GCRCSENT
Do Not Use
1: Mask the I_GCRCSENT interrupt
Address: 3Ch—Status0a
Reset Value: 0x0000_0000
Type: Read
7:6
Reserved
5
SOFTFAIL
Do Not Use
1: All soft reset packets with retries have failed to get aGoodCRC acknowledge.
This status is cleared when aSTART_TX, TXON or SEND_HARD_RESET is
25
Rev 1.2
ET7301B
executed
4
RETRYFAIL
1: All packet retries have failed to get a GoodCRCacknowledge.
This status is
cleared when a START_TX,TXON or SEND_HARD_RESET is executed
Internal power state when logic internals needs to control thepower state.
3:2
POWER3
POWER2
POWER3 corresponds to PWR3 bit andPOWER2 corresponds to PWR2 bit.
The power state is thehigher of both PWR[3:0] and {POWER3, POWER2,
PWR[1:0]}
so that if one is 03 and the other is F then the internal powerstate is F
1
SOFTRST
1: One of the packets received was a soft reset packet
0
HARDRST
1: Hard Reset PD ordered set has been received
Address: 3Dh—Status1a
Reset Value: 0x0000_0000
Type: Read
7:6
Reserved
Do Not Use
000: Toggle logic running (processor has previously writtenTOGGLE=1)
001: Toggle functionality has settled to SRCon CC1(STOP_SRC1 state)
TOGSS3
5:3
TOGSS2
TOGSS1
010: Toggle functionality has settled to SRCon CC2(STOP_SRC2 state)
101: Toggle functionality has settled to SNKon CC1(STOP_SNK1 state)
110: Toggle functionality has settled to SNKon CC2(STOP_SNK2 state)
111: Toggle functionality has detected AudioAccessory with VRA on both CC1
and CC2 (settles to STOP_SRC1 state)
Otherwise: Not defined (do not interpret)
2
1
0
RXSOP2DB
1: Indicates the last packet placed in the RxFIFO is typeSOP”_DEBUG
(SOP double prime debug)
1: Indicates the last packet placed in the RxFIFO is typeSOP’_DEBUG
RXSOP1DB
RXSOP
(SOP prime debug)
1: Indicates the last packet placed in the RxFIFO is type SOP
Address: 3Eh—Interrupta
Reset Value: 0x0000_0000
Type: Read/Clear
1: Interrupt from either a OCP event on one of the VCONNswitches or an
7
I_OCP_TEMP
6
I_TOGDONE
5
I_SOFTFAIL
4
I_RETRYFAIL
1: Interrupt from automatic packet retries have failed
3
I_HARDSENT
1: Interrupt from successfully sending a hard reset ordered set
2
I_TXSENT
over-temperature event
1: Interrupt indicating the TOGGLE functionality wasterminated because a
device was detected
1: Interrupt from automatic soft reset packets with retrieshave failed
1: Interrupt to alert that we sent a packet that wasacknowledged with a
GoodCRC response packet
26
Rev 1.2
ET7301B
1
I_SOFTRST
1: Received a soft reset packet
0
I_HARDRST
1: Received a hard reset ordered set
Address: 3Fh—Interruptb
Reset Value: 0x0000_0000
Type: Read/Write
7:1
Reserved
0
I_GCRCSENT
Do Not Use
1: Sent a GoodCRC acknowledge packet in response to an incoming packet
that has the correct CRC value
Address: 40h--Status0
Reset Value: 0x0000_0000
Type: Read
7
VBUSOK
1: VBUS is higher than VVBUSthr threshold
0: VBUS is lower than VVBUSthr threshold
1: Transitions are detected on the active CC* line. This bit goeshigh after a
6
ACTIVITY
minimum of 3 CC transitions, and remains high fortACTIVITY after last transition
on CC
0: inactive
5
COMP
1: Measured CC*input is higher than reference level driven from the MDAC
0: Measured CC*input is lower than reference level driven from the MDAC
1: Indicates the last received packet had the correct CRC. Thisbit remains set until
4
CRC_CHK
the SOP of the next packet
0: Packet received for an enabled SOP* and CRC for the enabled packet received
was incorrect
1: Alert software an error condition has occurred. An alert iscaused by:
3
ALERT
TX_FULL: the transmit FIFO is full
RX_FULL: the receive FIFO is full
2
WAKE
1: Voltage on CCx indicated that either a device, host or dual-role portis attempting
to attach
Current voltage status of the measured CC pin interpreted as host current levels as
follows:
00: < 200 mV (VRA)
01: >200 mV, 660 mV, 1.63 V (VRd-3.0*)
Note the software must measure these at an appropriate time,while there is no
signaling activity on the selected CC line.BC_LVL is only defined when Measure
block is on which iswhen register bits PWR[2]=1 and either MEAS_CC1=1
orMEAS_CC2=1
27
Rev 1.2
ET7301B
Address: 41h--Status1
Reset Value: 0x0010_1000
Type: Read
7
RXSOP2
6
RXSOP1
5
RX_EMPTY
4
RX_FULL
3
TX_EMPTY
2
TX_FULL
1
OVRTEMP
0
OCP
1: Indicates the last packet placed in the RxFIFO is type SOP”(SOP double
prime)
1: Indicates the last packet placed in the RxFIFO is type SOP’(SOP prime)
1: The receive FIFO is empty
1: The receive FIFO is full
1: The transmit FIFO is empty
1: The transmit FIFO is full
1: Temperature of the device is too high
1: Indicates an over-current or short condition has occurred on the VCONN
switch
Address: 42h--Interrupt
Reset Value: 0x0000_0000
Type: Read/Clear
7
I_VBUSOK
6
I_ACTIVITY
5
I_COMP
4
I_CRC_CHK
3
I_ALERT
1: Interrupt occurs when VBUS transitions through 4.5V. This bit typically is
usedto recognize port partner during startup
1: A change in the value of ACTIVITY of the CC bus has occurred
1: A change in the value of COMP has occurred. Indicates selected CC line has
tripped a threshold programmed into the MDAC
1: The value of CRC_CHK newly valid. I.e. The validity of the incoming packet
has been checked
1: Alert software an error condition has occurred. An alert is caused by:
TX_FULL: the transmit FIFO is full
RX_FULL: the receive FIFO is full
2
I_WAKE
1:0
I_CLOLLISION
0
I_BC_LVL
1: Voltage on CC indicated a device attempting to attach .Software must then
Power up the clock and receiver blocks
1: When a transmit was attempted, activity was detected on the active CC line
Transmit is not done. The packet is received normally
1: A change in host requested current level has occurred
Address: 43h--FIFOs
Reset Value: 0x0000_0000
Type: Read or Write
Writing to this register writes a byte into the transmit FIFO. Reading from this
7:0
TX/RX Token
register reads from the receive FIFO. Each byte is a coded token. Or a token
followed by a fixed number of packed data byte
28
Rev 1.2
ET7301B
Typical Application
TYPE-C Receptacle
VBUS
OVP
Charger IC
1.8V/3.3V
ET7301B
Battery Cell
VCONN
CC1
3.3V
CC1
CC2
220PF
5V
0.1uF
VDD
CC2
0.1uF
220PF
VBUS
1K 1K 1K
SCL
SDA
INT
GND
TRX#1
AP
TRX#2
GND
USB 3.1
Switch
USB/DP/MHL
Figure 14
Marking
7301BY
71B
XXXXX
XXXXX
7303BY - Part Number
71B - Part Number
XXXXX - Tracking Number
XXXXX - Tracking Number
29
Rev 1.2
ET7301B
Package Dimension
WLCSP9 Package
COMMON DIMENSIONS
(UNITS OF MEASURE=MILLIMETER)
SYMBOL
MIN
NOM
MAX
A
0.572
0.612
0.652
A1
0.172
0.202
0.232
A2
0.37
0.41
0.45
b
0.23
0.26
0.29
D
1.17
1.2
1.23
E
1.19
1.22
1.25
e
0.400BSC
30
Rev 1.2
ET7301B
QFN14(2.5*2.5)
COMMON DIMENSIONS
(UNITS OF MEASURE=MILLIMETER)
SYMBOL
MIN
NOM
MAX
A
0.7
0.75
0.8
A1
0
0.02
0.05
b
0.20
0.25
0.30
b1
0.18REF
c
0.20REF
D
2.40
2.50
2.60
D2
1.30
1.40
1.50
e
0.50BSC
Ne
1.00BSC
Nd
1.50BSC
E
2.40
2.50
2.60
E2
1.30
1.40
1.50
L
0.25
0.30
0.35
h
0.20
0.25
0.30
K
0.25REF
31
Rev 1.2
ET7301B
Revision History and Checking Table
Function & Spec
Package & Tape
Checking
Checking
Liu Yi Guo
Liu Yi Guo
Liu Jia Ying
Add marking
Liu Yi Guo
Liu Yi Guo
Liu Jia Ying
Update Typeset
Tianqh
Liu Yi Guo
Liu Jia Ying
Version
Date
Revision Item
Modifier
1.0
2018-08-08
Original Version
1.1
2019-02-26
1.2
2022-10-26
32
Rev 1.2
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