GW1N-UV2QN48C7/I6

GW1N series of FPGA Products Data Sheet DS100-1.8E, 07/08/2019 Copyright©2019 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI. Disclaimer GOWINSEMI®, LittleBee®, Arora™, and the GOWINSEMI logos are trademarks of GOWINSEMI and are registered in China, the U.S. Patent and Trademark Office and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders, as described at www.gowinsemi.com.cn. GOWINSEMI assumes no liability and provides no warranty (either expressed or implied) and is not responsible for any damage incurred to your hardware, software, data, or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions of Sale. All information in this document should be treated as preliminary. GOWINSEMI may make changes to this document at any time without prior notice. Anyone relying on this documentation should contact GOWINSEMI for the current documentation and errata. Revision History Date Version Description 06/08/2018 1.19E 07/31/2018 1.2E 09/12/2018 1.3E 12/10/2018 1.4E 01/09/2019 1.5E 02/14/2019 1.6E 06/04/2019 1.7E 07/08/2019 1.8E Initial version published.  PLL Structure diagram updated;  User Flash timing parameters added;  The desxription of systemIO status for blank chips added. The UG256 package added.  GW1N-2B/GW1N-4B added;  The BANK0 and BANK2 of GW1N-6 and GW1N-9 support I3C OpenDrain/PushPull conversion;  Change the step delay of IODELAY from 25ps to 30 ps. Oscillator frequency updated.  Power supply for UV devices updated;  Recommended Operating Conditions for UV devices updated;  Part naming figures updated.  Operating temperature changed to Junction temperature;  GW1N-1S added;  Power supply restrictions of BANK0/1/3 in GW1N-6/9 added;  Description of User Flash in GW1N-2/2B/4/4B/6/9 added；  GW1N-6/9 EQ144 added.  GW1N-6/9 MG196, UG169, and EQ176 added;  GW1N-1S CS30 added. Contents Contents Contents ............................................................................................................... i List of Figures .................................................................................................... iv List of Tables ...................................................................................................... vi 1 About This Guide ............................................................................................. 1 1.1 Purpose .............................................................................................................................. 1 1.2 Supported Products ............................................................................................................ 1 1.3 Related Documents ............................................................................................................ 1 1.4 Abbreviations and Terminology ........................................................................................... 2 1.5 Support and Feedback ....................................................................................................... 3 2 General Description......................................................................................... 4 2.1 Features .............................................................................................................................. 4 2.2 Product Resources ............................................................................................................. 6 2.3 Package Information ........................................................................................................... 7 3 Architecture...................................................................................................... 8 3.1 Architecture Overview ......................................................................................................... 8 3.2 Configurable Function Unit ............................................................................................... 10 3.2.1 CLU ................................................................................................................................ 10 3.2.2 CRU ............................................................................................................................... 12 3.3 IOB .................................................................................................................................... 12 3.3.1 I/O Buffer ....................................................................................................................... 13 3.3.2 True LVDS Design ......................................................................................................... 17 3.3.3 I/O Logic ........................................................................................................................ 18 3.3.4 I/O Logic Modes............................................................................................................. 20 3.4 Block SRAM (B-SRAM) .................................................................................................... 25 3.4.1 Introduction .................................................................................................................... 25 3.4.2 Configuration Mode ....................................................................................................... 26 3.4.3 Mixed Data Bus Width Configuration............................................................................. 27 3.4.4 Byte-enable .................................................................................................................... 27 3.4.5 Parity Bit ........................................................................................................................ 28 3.4.6 Synchronous Operation ................................................................................................. 28 3.4.7 Power up Conditions ..................................................................................................... 28 DS100-1.8E i Contents 3.4.8 Operation Modes ........................................................................................................... 28 3.4.9 B-SRAM Operation Modes ............................................................................................ 32 3.4.10 Clock Operations ......................................................................................................... 34 3.5 User Flash (GW1N-1 and GW1N-1S) .............................................................................. 35 3.5.1 Introduction .................................................................................................................... 35 3.5.2 Port Signal ..................................................................................................................... 35 3.5.3 Data Output Bit Selection .............................................................................................. 37 3.5.4 Operation Mode ............................................................................................................. 37 3.5.5 Read Operation ............................................................................................................. 37 3.5.6 Write Operation .............................................................................................................. 38 3.6 User Flash (GW1N-2/2B/4/4B/6/9) ................................................................................... 38 3.6.1 Introduction .................................................................................................................... 38 3.6.2 Port Signal ..................................................................................................................... 39 3.6.3 Operation Mode ............................................................................................................. 40 3.7 DSP................................................................................................................................... 40 3.7.1 Introduction .................................................................................................................... 40 3.7.2 DSP Operations ............................................................................................................. 44 3.8 Clock ................................................................................................................................. 44 3.8.1 Global Clock .................................................................................................................. 45 3.8.2 PLL ................................................................................................................................ 47 3.8.3 HCLK ............................................................................................................................. 50 3.8.4 DLL ................................................................................................................................ 51 3.9 Long Wire (LW) ................................................................................................................. 52 3.10 Global Set/Reset (GSR) ................................................................................................. 52 3.11 Programming Configuration ............................................................................................ 52 3.11.1 SRAM Configuration .................................................................................................... 52 3.11.2 Flash Configuration ...................................................................................................... 52 3.12 On Chip Oscillator........................................................................................................... 53 4 AC/DC Characteristic..................................................................................... 55 4.1 Operating Conditions ........................................................................................................ 55 4.2 ESD................................................................................................................................... 56 4.3 DC Characteristic .............................................................................................................. 59 4.4 Switching Characteristic ................................................................................................... 62 4.4.1 Internal Switching Characteristics ................................................................................. 62 4.4.2 External Switching Characteristics ................................................................................ 63 4.5 User Flash Characteristics ............................................................................................... 64 1 4.5.1 DC Characteristics ....................................................................................................... 64 4.5.2 Timing Parameters 1,5,6 ................................................................................................... 65 4.5.3 Operation Timing Diagrams (GW1N-1/ GW1N-1S) ....................................................... 67 DS100-1.8E ii Contents 4.5.4 Operation Timing Diagrams (GW1N-2/2B/4/4B/6/9) ..................................................... 68 4.6 Configuration Interface Timing Specification .................................................................... 69 4.6.1 JTAG Port Timing Specifications ................................................................................... 69 4.6.2 AUTO BOOT Port Timing Specifications ....................................................................... 70 4.6.3 SSPI Port Timing Specifications .................................................................................... 71 4.6.4 MSPI Port Timing Specifications ................................................................................... 72 4.6.5 DUAL BOOT .................................................................................................................. 73 4.6.6 CPU ............................................................................................................................... 74 4.6.7 SERIAL .......................................................................................................................... 74 5 Ordering Information ..................................................................................... 75 5.1 Part Name......................................................................................................................... 75 5.2 Package Mark ................................................................................................................... 77 DS100-1.8E iii List of Figures List of Figures Figure 3-1 Architecture Overview of GW1N series of FPGA Products .............................................. 8 Figure 3-2 CFU View.......................................................................................................................... 10 Figure 3-3 Register in CLS ................................................................................................................ 11 Figure 3-4 IOB Structure View ........................................................................................................... 12 Figure 3-5 I/O Bank Distribution View of GW1N-1/2/4/2B/4B ............................................................ 13 Figure 3-6 I/O Bank Distribution View of GW1N-6/9 ...................................................................... 13 Figure 3-7 I/O Bank Distribution View of GW1N-1S .......................................................................... 14 Figure 3-8 True LVDS Design ............................................................................................................ 17 Figure 3-9 I/O Logic Output ............................................................................................................... 18 Figure 3-10 I/O Logic Input ................................................................................................................ 18 Figure 3-11 IODELAY......................................................................................................................... 19 Figure 3-12 Register Structure in I/O Logic ....................................................................................... 19 Figure 3-13 IEM Structure .................................................................................................................. 19 Figure 3-14 I/O Logic in Basic Mode.................................................................................................. 20 Figure 3-15 I/O Logic in SDR Mode ................................................................................................... 21 Figure 3-16 I/O Logic in DDR Input Mode ......................................................................................... 21 Figure 3-17 I/O Logic in DDR Output Mode ....................................................................................... 22 Figure 3-18 I/O Logic in IDES10 Mode .............................................................................................. 22 Figure 3-19 I/O Logic in OSER4 Mode .............................................................................................. 22 Figure 3-20 I/O Logic in IVideo Mode ................................................................................................ 22 Figure 3-21 I/O Logic in OVideo Mode .............................................................................................. 23 Figure 3-22 I/O Logic in IDES8 Mode ................................................................................................ 23 Figure 3-23 I/O Logic in OSER8 Mode .............................................................................................. 23 Figure 3-24 I/O Logic in IDES10 Mode .............................................................................................. 23 Figure 3-25 I/O Logic in OSER10 Mode ............................................................................................ 24 Figure 3-26 I/O Logic in IDES16 Mode .............................................................................................. 24 Figure 3-27 I/O Logic in OSER16 Mode ............................................................................................ 24 Figure 3-28 Single Port Block Memory .............................................................................................. 28 Figure 3-29 Dual Port Block Memory ................................................................................................. 29 Figure 3-30 Semi Dual Port Block Memory 1 .................................................................................... 31 Figure 3-31 ROM Block Memory ....................................................................................................... 32 Figure 3-32 Pipeline Mode in Single Port, Dual Port and Semi Dual Port ......................................... 33 DS100-1.8E iv List of Figures Figure 3-33 Independent Clock Mode ............................................................................................... 34 Figure 3-34 Read/Write Clock Mode .................................................................................................. 35 Figure 3-35 Single Port Clock Mode .................................................................................................. 35 Figure 3-36 GW1N-1/GW1N-1S User Flash Ports ............................................................................ 36 Figure 3-37 GW1N-2/4/2B/4B/6/9 Flash Port Signal ......................................................................... 39 Figure 3-38 DSP Macro ..................................................................................................................... 42 Figure 3-39 GCLK Quadrant Distribution ........................................................................................... 45 Figure 3-40 DQCE Concept ............................................................................................................... 46 Figure 3-41 DCS Concept .................................................................................................................. 46 Figure 3-42 DCS Rising Edge............................................................................................................ 46 Figure 3-43 DCS Falling Edge ........................................................................................................... 47 Figure 3-44 PLL Structure .................................................................................................................. 47 Figure 3-45 GW1N-1 HCLK Distribution ............................................................................................ 50 Figure 3-46 GW1N-2/2B/4 /4B HCLK Distribution ............................................................................. 50 Figure 3-47 GW1N-6/9 HCLK Distribution ......................................................................................... 51 Figure 3-48 GW1N-1S HCLK Distribution ......................................................................................... 51 Figure 3-49 GW1N DLL Function ...................................................................................................... 51 Figure 4-1 Read Mode ....................................................................................................................... 67 Figure 4-2 Write Page Latches Mode ................................................................................................ 68 Figure 4-3 Clear Page Latches Mode ................................................................................................ 68 Figure 4-4 High Level Cycle ............................................................................................................... 68 Figure 4-5 User Flash Read Operation .............................................................................................. 68 Figure 4-6 User Flash Program Operation......................................................................................... 69 Figure 4-7 User Flash Erase Operation ............................................................................................. 69 Figure 4-8 JTAG Timing ..................................................................................................................... 70 Figure 4-9 Power Recycle Timing ...................................................................................................... 71 Figure 4-10 RECONFIG_N Trigger Timing ........................................................................................ 71 Figure 4-11 SSPI Timing Diagram ..................................................................................................... 72 Figure 4-12 MSPI Timing Diagram..................................................................................................... 73 Figure 5-1 Part Naming–ES ............................................................................................................... 75 Figure 5-2 Part Naming–Production .................................................................................................. 76 Figure 5-3 Package Mark ................................................................................................................... 77 DS100-1.8E v List of Tables List of Tables Table 1-1 Abbreviations and Terminologies ....................................................................................... 2 Table 2-1 Product Resources............................................................................................................. 6 Table2-2 Package Information and Max. I/O ..................................................................................... 7 Table3-1 Register Description in CLS ................................................................................................ 11 Table 3-2 Output I/O Standards and Configuration Options .............................................................. 14 Table 3-3 Input Standards and Configuration Options ....................................................................... 16 Table 3-4 B-SRAM Signals ................................................................................................................ 25 Table 3-5 Memory Size Configuration ................................................................................................ 26 Table 3-6 Dual Port Mixed Read/Write Data Width Configuration ..................................................... 27 Table 3-7Semi Dual Port Mixed Read/Write Data Width Configuration ............................................. 27 Table 3-8 Single Port Block Memory Configuration ........................................................................... 29 Table 3-9 Semi Dual Port Memory Configuration .............................................................................. 29 Table 3-10Semi Dual Port Memory Configuration ............................................................................. 31 Table 3-11 Block ROM Configuration ................................................................................................. 32 Table 3-12 Clock Operations in Different B-SRAM Modes ................................................................ 34 Table 3-13 Flash Module Signal Description ..................................................................................... 36 Table 3-14 Data Output Bit Selection ................................................................................................. 37 Table 3-15s Data Input Bit Selection .................................................................................................. 37 Table 3-16 Operation Modes Selection .............................................................................................. 37 Table 3-17 Flash Module Signal Description ..................................................................................... 39 Table 3-18 Truth Table in User Mode ................................................................................................. 40 Table 3-19 DSP Ports Description ..................................................................................................... 42 Table 3-20 Internal Registers Description .......................................................................................... 43 Table 3-21 PLL Ports Definition.......................................................................................................... 48 Table 3-22 GW1N-2/2B/4/4B Oscillator Output Frequency Options .................................................. 53 Table 3-23 GW1N-1/1S/6/9 Oscillator Output Frequency Options .................................................... 53 Table 4-1 Absolute Max. Ratings ....................................................................................................... 55 Table 4-2 Recommended Operating Conditions ................................................................................ 55 Table 4-3 Hot Socket Specifications .................................................................................................. 56 Table 4-4 GW1N ESD - HBM ............................................................................................................. 56 Table 4-5 GW1N ESD - CDM............................................................................................................. 56 Table 4-6 DC Electrical Characteristics over Recommended Operating Conditions ......................... 57 DS100-1.8E vi List of Tables Table 4-7 Static Supply Current ......................................................................................................... 58 Table 4-8 I/O Operating Conditions Recommended .......................................................................... 59 Table 4-9 IOB Single‐Ended DC Electrical Characteristic ............................................................... 60 Table 4-10 IOB Differential Electrical Characteristics ........................................................................ 61 Table 4-11 CFU Block Internal Timing Parameters ............................................................................ 62 Table 4-12 B-SRAM Internal Timing Parameters ............................................................................... 62 Table 4-13 DSP Internal Timing Parameters ..................................................................................... 62 Table 4-14 GearboxInternal Timing Parameters ................................................................................ 62 Table 4-15 External Switching Characteristics ................................................................................... 63 Table 4-16 On chip Oscillator Output Frequency ............................................................................... 63 Table4-17 PLL Parameters ................................................................................................................ 63 Table 4-18 GW1N-1/ GW1N-1S User Flash DC Characteristic ......................................................... 64 Table 4-19 GW1N-2/2B/4/4B/6/9 User Flash DC Characteristic ....................................................... 64 Table 4-20 GW1N-1/GW1N-1S User Flash Timing Parameters ........................................................ 65 Table 4-21 GW1N-2/2B/4/4B/6/9 User Flash Timing Parameters ..................................................... 66 Table 4-22 JTAG Timing Parameters ................................................................................................. 70 Table 4-23 Timing Parameters for Power-on and RECONFIG_N Trigger ......................................... 71 Table 4-24 SSPI Timing parameters .................................................................................................. 72 Table 4-25 MSPI Timing Parameters ................................................................................................. 73 DS100-1.8E vii 1About This Guide 1.1Purpose 1 About This Guide 1.1 Purpose This data sheet describes the features, product resources and structure, AC/DC characteristics, timing specifications of the configuration interface, and the ordering information of the GW1N series of FPGA products. It is designed to help you to understand the GW1N series of FPGA products quickly and select and use devices appropriately. 1.2 Supported Products The information in this guide applies to the following products: GW1N series of FPGA products: GW1N-1, GW1N-1S, GW1N-2, GW1N-2B, GW1N-4, GW1N-4B, GW1N-6, and GW1N-9. 1.3 Related Documents The latest user guides are available on GOWINSEMI Website. You can find the related documents at www.gowinsemi.com: 1. 2. 3. 4. 5. 6. 7. DS100-1.8E GW1N series of FPGA Products Data Sheet Gowin FPGA Products Programming and Configuration User Guide GW1N series of FPGA Products Package and Pinout GW1N-1 Pinout GW1N-1S Pinout GW1N-2&2B&4&4B Pinout GW1N-6&9 Pinout 1(77) 1About This Guide 1.4Abbreviations and Terminology 1.4 Abbreviations and Terminology The abbreviations and terminologies used in this manual are set out in Table 1-1 below. Table 1-1 Abbreviations and Terminologies DS100-1.8E Abbreviations and Terminology Name FPGA Field Programmable Gate Array CFU Configurable Function Unit CLS Configurable Logic Slice CRU Configurable Routing Unit LUT4 4-input Look-up Tables LUT5 5-input Look-up Tables LUT6 6-input Look-up Tables LUT7 7-input Look-up Tables LUT8 8-input Look-up Tables REG Register ALU Arithmetic Logic Unit IOB Input/Output Block S-SRAM Shadow SRAM B-SRAM Block SRAM SP Single Port SDP Semi Dual Port DP Dual Port DSP Digital Signal Processing DQCE Dynamic Quadrant Clock Enable DCS Dynamic Clock Selector PLL Phase-locked Loop DLL Delay-locked Loop CS30 WLCSP30 CM64 WLCSP64 CS72 WLCSP72 QN32 QFN32 QN48 QFN48 LQ100 LQFP100 2(77) 1About This Guide 1.5Support and Feedback Abbreviations and Terminology Name LQ144 LQFP144 EQ144 ELQFP144 LQ176 LQFP176 EQ176 ELQFP176 MG160 MBGA160 MG196 MBGA196 PG204 PBGA204 PG256 PBGA256 PG256M PBGA256M UG332 UBGA332 UG169 UBGA169 TDM Time Division Multiplexing 1.5 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com E-mail: support@gowinsemi.com +Tel: +86 755 8262 0391 DS100-1.8E 3(77) 2General Description 2.1Features 2 General Description The GW1N series of FPGA products are the first generation products in the LittleBee® family. They offer abundant logic resources, multiple I/O standards, embedded BSRAM, DSP, PLL/DLL, and built-in Flash. They are non-volatile FPGA products with low power, instant-start, low-cost, high-security, small size, various packages, and flexible usage. GOWINSEMI provides a new generation of FPGA hardware development environment through market-oriented independent research and development that supports the GW1N series of FPGA products and applies to FPGA synthesizing, layout, place and routing, data bitstream generation and download, etc. 2.1 Features  User Flash (GW1N-1,GW1N-1S) - 100,000 write cycles - Greater than10 years data retention at +85 ℃ -   Selectable 8/16/32 bits data-in and data-out - Page size: 256 bytes - 3 μA standby current - Page write time: 8.2 ms User Flash (GW1N-2/2B/4/4B/6/9) - Up to 608Kbits - 10,000 write cycles Lower power consumption - 55 nm embedded flash technology - LV: supports 1.2 V core voltage - UV: supports same power supply for VCC/ VCCO/ VCCx Note! GW1N-1 and GW1N-1S devices do not support UV Version.The other devices support both LV and UV versions.  DS100-1.8E Clock dynamically turns on and off Multiple I/O Standards 4(77) 2General Description 2.1Features -       DS100-1.8E LVCMOS33/25/18/15/12; LVTTL33, SSTL33/25/18 I, SSTL33/25/18 II, SSTL15; HSTL18 I, HSTL18 II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE MLVDSE, LVPECLE, RSDSE - Input hysteresis option - Supports 4mA,8mA,16mA,24mA,etc. drive options - Slew rate option - Output drive strength option - Individual bus keeper, weak pull-up, weak pull-down, and open drain option - Hot socket - I/Os in the top layer of GW1N-1S and GW1N-6/9 devices support MIPI input - I/Os in the bottom layer of GW1N-6/9 devices support MIPI output - I/Os in the Top layer and Bottom layer of GW1N-6/9 devices support I3C OpenDrain/PushPull conversion High performance DSP - High performance digital signal processing ability - Supports 9 x 9,18 x 18,36 x 36 bits multiplier and 54 bits accumulator; - Multipliers cascading - Registers pipeline and bypass - Adaptive filtering through signal feedback - Supports barrel shifter Abundant slices - Four input LUT (LUT4) - Double-edge flip-flops - Supports shift register and distributed register Block SRAM with multiple modes - Supports dual port, single port, and semi-dual port - Supports bytes write enable Flexible PLLs+DLLs - Frequency adjustment (multiply and division) and phase adjustment - Supports global clock Built-in flash programming - Instant-on - Supports security bit operation - Supports AUTO BOOT and DUAL BOOT Configuration - JTAG configuration 5(77) 2General Description 2.2Product Resources - The GW1N-2B and GW1N-4B devices support JTAG transparent transmission Offers up to six GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT 2.2 Product Resources Table 2-1 Product Resources Device GW1N-1 GW1N-2/ GW1N-2B GW1N-4/ LUT4 1,152 2,304 Flip-Flop (FF) 864 GW1N-6 GW1N-9 GW1N-1S 4,608 6,912 8,640 1,152 1,728 3,456 5,184 6,480 864 0 0 0 13,824 17,280 0 72 K 180 K 180 K 468 K 468 K 72K 4 10 10 26 26 4 User Flash (bits) 96 K 256 K 256 K 608 K 608 K 96K 18 x 18 Multiplier 0 16 16 20 20 0 PLLs+DLLs 1+0 2+2 2+2 2+4 2+4 1+0 Total number of I/O banks 4 4 4 4 4 3 Max. user I/O1 119 207 207 273 273 25 Core Voltage (LV) 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2V Core Voltage (UV) – 1.8V/2.5V/3.3V Shadow SRAM S-SRAM(bits) Block SRAM B-SRAM(bits) B-SRAM quantity B-SRAM GW1N-4B – Note! The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max. I/O noted in this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. DS100-1.8E 6(77) 2General Description 2.3Package Information 2.3 Package Information Table2-2 Package Information and Max. I/O Pitch Size GW1N-1S GW1N-1 GW1N-2/ GW1N-2B GW1N-4/ (mm) (mm) CS30 0.4 2.3 x 2.4 23 24 - QN32 0.5 5x5 - 26 FN32 0.4 4x4 25 QN48 0.4 6x6 - CM64 0.5 4.1 x 4.1 - CS72 0.4 3.6 x 3.3 - - 57（19） QN88 0.4 10 x 10 - - LQ100 0.5 16 x 16 - LQ144 0.5 22 x 22 EQ144 0.5 MG160 Package GW1N-6 GW1N-9 - - - 24（3） 24（3） - - - - - - - 41 40（9） 40（9） 40（12） 40（12） 55（16） 55（16） 57（19） - - 70（11） 70（11） 70（19） 70（19） 79 79（13） 79（13） 79（20） 79（20） - 116 119（22） 119（22） 120（28） 120（28） 22 x 22 - - - - 120（28） 120（28） 0.5 8x8 - - 131（25） 131（25） 131（38） 131（38） UG169 0.8 11 x 11 - - - - 129（38） 129（38） LQ176 0.4 22 x 22 - - - - 147（37） 147（37） EQ176 0.4 22 x 22 - - - - 147（37） 147（37） MG196 0.5 8x8 - - - - 113（35） 113（35） PG256 1.0 17 x 17 - - 207（32） 207（32） 207（36） 207（36） PG256M 1.0 17 x 17 - - 207（32） 207（32） - UG256 0.8 14 x 14 - - - - 207（36） 207（36） UG332 0.8 17 x 17 - - - - 273（43） 273（43） GW1N-4B - Note! DS100-1.8E  The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max. I/O noted in this table refers to when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. See GW1N series of FPGA Products Package and Pinout for further details.  [1] The package types in this data sheet are written with abbreviations. See 5.1Part Name.  “ ” denotes that the various device pins are compatible when the package types are the same.  The GW1N-2/GW1N-2B and GW1N-4/GW1N-4B pins are fully compatible. GW1N-6 and GW1N-9 pins are fully compatible. 7(77) 3Architecture 3.1Architecture Overview 3 Architecture 3.1 Architecture Overview Figure 3-1 Architecture Overview of GW1N series of FPGA Products PLL IOB Top IO CFU CFU CFU CFU CFU PLL IOB Block SRAM Right IO Left IO User Flash CFU CFU Block SRAM CFU OSC CFU DSP CFU DLL IOB User Flash IOB CFU CFU CFU CFU OSC CFU CFU CFU CFU CFU IOB IOB IOB Bottom IO DSP CFU CFU CFU IOB DLL IOB As shown above, the core of GW1N series of FPGA products is CFU. GW1N series of FPGA products also provide B-SRAMs, PLLs, DLLs, User Flash, and on-chip oscillator, and supports Instant-on. See Table 2-1 for more detailed information. Note! GW1N series of FPGA products include the devices of GW1N-1, GW1N-1S, GW1N-2, GW1N-2B, GW1N-4, GW1N-4B, and GW1N-6/9. In these devices, CFU, B-SRAM, GCLK, and on chip crystals are the same, but the other resources, such as DSP, Flash, I/Os, PLL/DLL, high-speed clock, etc, are slightly different. Configurable Function Unit (CFU) is the base cell for the array of GW1N series FPGA Products. Devices with different capacities have different numbers of rows and columns. CFU can be configured as LUT4 mode, ALU mode, and memory mode. Memory mode is supported in GW1N-6 and GW1N -9. For more detailed information, see 3.2 DS100-1.8E 8(77) 3Architecture 3.1Architecture Overview Configurable Function Unit. The I/O resources in the GW1N series of FPGA products are arranged around the periphery of the devices in groups referred to as banks1. Up to four Banks are supported, including Bank0, Bank1, Bank2, and Bank3. The I/O resources support multiple level standards, and support basic mode, SRD mode, and generic DDR mode. For more detailed information, see 3.3 IOB. Note! [1]GW1N-1S includes three Banks, which are Bank0, Bank1, and Bank2 respectively. For further detailed information, please refer to the I/O BANK distribution view in 3.3.1I/O Buffer. The B-SRAM is embedded as a row in the GW1N series of FPGA products. In the FPGA array, each B-SRAM occupies three columns of CFU. Each B-SRAM has 18,432 bits (18 Kbits) and supports multiple configuration modes and operation modes. For more detailed information, see 3.4 Block SRAM (B-SRAM). The User Flash is embedded in the GW1N series of FPGA products, without loss of data, even if powered off. For more detailed information, see 3.5 User Flash (GW1N-1 and GW1N-1S) and 3.6 User Flash (GW1N-2/2B/4/4B/6/9). GW1N-2/GW1N-2B, GW1N-4/GW1N-4B, GW1N-6, and GW1N-9 support DSP. DSP blocks are embedded as row in the FPGA array. Each DSP occupies nine CFU columns. Each DSP block contains two Macros, and each Macro contains two pre-adders, two multipliers with 18 by 18 inputs, and a three input ALU54. For more detailed information, see 3.7 DSP. Note! GW1N-1 and GW1N-1S do not support DSP currently. GW1N-1 and GW1N-1S provide one PLL. GW1N-2/GW1N-2B, GW1N-4/GW1N-4B, GW1N-6, and GW1N-9 provide PLLs and DLLs. PLL blocks provide the ability to synthesize clock frequencies. Frequency adjustment (multiply and division), phase adjustment, and duty cycle can be adjusted using the configuration of parameters. There is an internal programmable on-chip oscillator in each GW1N series of FPGA product. The on-chip oscillator supports the clock frequencies ranging from 2.5 MHz to 125 MHz, providing the clock resource for the MSPI mode. It also provides a clock resource for user designs with the clock precision reaching ±5%. For more detailed information, see 3.8 Clock, 3.12 On Chip Oscillator. FPGA provides abundant CRUs, connecting all the resources in the FPGA. For example, routing resources distributed in CFU and IOB connect resources in CFU and IOB. Routing resources can automatically be generated by Gowin software. In addition, the GW1N series of FPGA Products also provide abundant GCLKs, long wires (LW), global set/reset (GSR), and programming options, etc. For more detailed information, see3.8 Clock, 3.9 Long Wire (LW), 3.10 Global Set/Reset (GSR). DS100-1.8E 9(77) 3Architecture 3.2Configurable Function Unit 3.2 Configurable Function Unit The configurable function unit (CFU) is the base cell for the array of the GW1N series of FPGA Products. Each CFU consists of a configurable logic unit (CLU) and its routing resource configurable routing unit (CRU). In each CLU, there are four configurable logic slices (CLS). Each CLS contains look-up tables (LUT) and registers, as shown in Figure 3-2 below. Figure 3-2 CFU View Carry to Right CLU CFU CLU LUT CLS3 LUT LUT REG LUT REG LUT REG LUT REG LUT REG LUT REG CLS2 CRU CLS1 CLS0 Carry from left CLU 3.2.1 CLU The CLU supports three operation modes: basic logic mode, ALU mode, and memory mode.  Basic Logic Mode Each LUT can be configured as one four input LUT. A higher input number of LUT can be formed by combining LUT4 together. -  Each CLS can form one five input LUT5. - Two CLSs can form one six input LUT6. - Four CLSs can form one seven input LUT7. - Eight CLSs (two CLUs) can form one eight input LUT8. ALU Mode When combined with carry chain logic, the LUT can be configured as DS100-1.8E 10(77) 3Architecture 3.2Configurable Function Unit the ALU mode to implement the following functions. -  Adder and subtractor - Up/down counter - Comparator, including greater-than, less-than, and not-equal-to - MULT Memory mode GW1N-6 and GW1N-9 support memory mode. In this mode, a 16 x 4 S-SRAM or ROM can be constructed by using CLSs. This S-SRAM can be initialized during the device configuration stage. The initialization data can be generated in the bit stream file from Gowin Yunyuan software. Register Each configurable logic slice (CLS0~CLS2) has two registers (REG), as shown in Figure 3-3 below. Figure 3-3 Register in CLS D CE CLK Q SR GSR Table3-1 Register Description in CLS Signal I/O Description D I Data input 1 CE I CLK enable, can be high or low effective 2 CLK I Clock, can be rising edge or falling edge trigging 2 Set/Reset, can be configured as 2: SR I  Synchronized reset  Synchronized set  Asynchronous reset  Asynchronous set  Non Global Set/Reset, can be configured as4: GSR3,4 Q I O  Asynchronous reset  Asynchronous set  Non Register Note!  DS100-1.8E [1] The source of the signal D can be the output of a LUT, or the input of the CRU; as such, the register can be used alone when LUTs are in use. 11(77) 3Architecture 3.3IOB  [2] CE/CLK/SR in CFU is independent.  [3] In the GW1N series of FPGA products,GSR has its own dedicated network.  [4] When both SR and GSR are effective, GSR has higher priority. 3.2.2 CRU The main functions of the CRU are as follows:   Input selection: Select input signals for the CFU. Configurable routing: Connect the input and output of the CFUs, including inside the CFU, CFU to CFU, and CFU to other functional blocks in FPGA. 3.3 IOB The IOB in the GW1N series of FPGA products includes I/O buffer, I/O logic, and its routing unit. As shown in Figure 3-4, each IOB connects to two pins (Marked A and B). They can be used as a differential pair or as two single-end input/output. Figure 3-4 IOB Structure View Differential Pair Differential Pair “True” “Comp” “True” “Comp” PAD A PAD B PAD A PAD B Buffer Pair A & B DI DO TO DI IO Logic A IO Logic B CLK Routing Output Routing Input CLK Routing Output Routing Input CLK Routing Output Routing Input CLK Routing Output Routing Input Routing DO IO Logic B TO DI DO DI TO DO TO IO Logic A Buffer Pair A & B Routing IOB Features:       DS100-1.8E VCCO supplied with each bank LVCMOS, PCI, LVTTL, LVDS, SSTL, and HSTL (true LVDS not supported in GW1N-1 and GW1N-1S) Input hysteresis option Output drive strength option Slew rate option Individual bus keeper, weak pull-up, weak pull-down, and open drain option 12(77) 3Architecture 3.3IOB  Hot socket IO logic supports basic mode, SRD mode, and generic DDR mode I/Os in the top layer of GW1N-1S and GW1N-6/9 devices support MIPI input I/Os in the bottom layer of GW1N-6/9 devices support MIPI output I/Os in the Top layer and Bottom layer of GW1N-6/9 devices support I3C OpenDrain/PushPull conversion     3.3.1 I/O Buffer There are four IO Banks in the GW1N series of FPGA products, as shown in Figure 3-5. Each Bank supports single power supply and has independent I/O power supply VCCO. GW1N-1S includes three IO Banks, as shown in Figure 3-6. Each Bank supports single power supply and has independent I/O power supply VCCO.To support SSTL, HSTL, etc., each bank also provides one independent voltage source (VREF) as referenced voltage. The user can choose from the internal reference voltage of the bank (0.5 x VCCO) or the external reference voltage using any IO from the bank. Figure 3-5 I/O Bank Distribution View of GW1N-1/2/4/2B/4B I/O Bank0 I/O Bank1 I/O Bank3 GW1N I/O Bank2 Figure 3-6 I/O Bank Distribution View of GW1N-6/9 I/O Bank3 I/O Bank0 I/O Bank1 Top I/O Bank1 Right Left I/O Bank3 GW1N-6/9 Bottom I/O Bank2 DS100-1.8E 13(77) 3Architecture 3.3IOB Figure 3-7 I/O Bank Distribution View of GW1N-1S I/O Bank0 I/O Bank1 Top I/O Bank2 Right GW1N-1S The GW1N series of FPGA products support LV and UV. LV devices support 1.2 V VCC to meet users’ low power needs. VCCO can be set as 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V according to requirements1. VCCX supports 2.5 V or 3.3 V power supply. UV devices support 1.8V, 2.5 V, and 3.3 V, and linear voltage regulator is integrated to facilitate single power supply. For the devices of GW1N-1S, GW1N-6, and GW1N-9, I/Os of the top layer support MIPI input. For the devices of GW1N-6 and GW1N-9, I/Os of the bottom layer support MIPI output. I/Os of the top and bottom layer in GW1N-6/9 support MIPI I3C OpenDrain/PushPull conversion. Note!  By default, the systemIO is weak pull-up for blank chips;  For the recommended operating conditions of different devices, please refer to 4.1Operating Conditions;  When the I/O in Top layer of GW1N-6/9 is used as MIPI input, the VCCOx of the used I/O needs to be supplied with 1.2V power supply, where x can be 0, 1, and 3.  When the I/O in Bottom layer of GW1N-6/9 is used as MIPI output, VCCO2 needs to be supplied with 1.2V power supply.  The I/O power supply restrictions of BANK0, BANK1, BANK3 in GW1N-6/9 are as follows: - When VCCO0 is greater than or equal to 1.8V 时，VCCO1 and VCCO3 support 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V. - When VCCO0 is 1.5V 时，VCCO1 and VCCO3 support 1.2V, 1.5V, 1.8V, and 2.5V. For the VCCO requirements of different I/O standards, see Table 3-2. Table 3-2 Output I/O Standards and Configuration Options DS100-1.8E I/O output standard Single/Differ Bank VCCO (V) Driver Strength (mA) LVTTL33 Single end 3.3 4,8,12,16,24 LVCMOS33 Single end 3.3 4,8,12,16,24 14(77) 3Architecture DS100-1.8E 3.3IOB I/O output standard Single/Differ Bank VCCO (V) Driver Strength (mA) LVCMOS25 Single end 2.5 4,8,12,16 LVCMOS18 Single end 1.8 4,8,12 LVCMOS15 Single end 1.5 4,8 LVCMOS12 Single end 1.2 4,8 SSTL25_I Single end 2.5 8 SSTL25_II Single end 2.5 8 SSTL33_I Single end 3.3 8 SSTL33_II Single end 3.3 8 SSTL18_I Single end 1.8 8 SSTL18_II Single end 1.8 8 SSTL15 Single end 1.5 8 HSTL18_I Single end 1.8 8 HSTL18_II Single end 1.8 8 HSTL15_I Single end 1.5 8 PCI33 Single end 3.3 N/A LVPECL33E Differential 3.3 16 MVLDS25E Differential 2.5 16 BLVDS25E Differential 2.5 16 RSDS25E Differential 2.5 8 LVDS25E Differential 2.5 8 LVDS25 Differential 2.5/3.3 3.5/2.5/2/1.25 RSDS Differential 2.5/3.3 2 MINILVDS Differential 2.5/3.3 2 PPLVDS Differential 2.5/3.3 3.5 SSTL15D Differential 1.5 8 SSTL25D_I Differential 2.5 8 SSTL25D_II Differential 2.5 8 SSTL33D_I Differential 3.3 8 SSTL33D_II Differential 3.3 8 SSTL18D_I Differential 1.8 8 SSTL18D_II Differential 1.8 8 HSTL18D_I Differential 1.8 8 15(77) 3Architecture 3.3IOB I/O output standard Single/Differ Bank VCCO (V) Driver Strength (mA) HSTL18D_II Differential 1.8 8 HSTL15D_I Differential 1.5 8 Table 3-3 Input Standards and Configuration Options DS100-1.8E I/O Input Standard Single/Differ Bank VCCO (V) Hysteresis Need VREF LVTTL33 Single end 1.5/1.8/2.5/3.3 Yes No LVCMOS33 Single end 1.5/1.8/2.5/3.3 Yes No LVCMOS25 Single end 1.5/1.8/2.5/3.3 Yes No LVCMOS18 Single end 1.5/1.8/2.5/3.3 Yes No LVCMOS15 Single end 1.2/1.5/1.8/2.5/3.3 Yes No LVCMOS12 Single end 1.2/1.5/1.8/2.5/3.3 Yes No SSTL15 Single end 1.5/1.8/2.5/3.3 No Yes SSTL25_I Single end 2.5/3.3 No Yes SSTL25_II Single end 2.5/3.3 No Yes SSTL33_I Single end 3.3 No Yes SSTL33_II Single end 3.3 No Yes SSTL18_I Single end 1.8/2.5/3.3 No Yes SSTL18_II Single end 1.8/2.5/3.3 No Yes HSTL18_I Single end 1.8/2.5/3.3 No Yes HSTL18_II Single end 1.8/2.5/3.3 No Yes HSTL15_I Single end 1.5/1.8/2.5/3.3 No Yes PCI33 Single end 3.3 Yes No LVDS Differential 2.5/3.3 No No RSDS Differential 2.5/3.3 No No MINILVDS Differential 2.5/3.3 No No PPLVDS Differential 2.5/3.3 No No LVDS25E Differential 2.5/3.3 No No MLVDS25E Differential 2.5/3.3 No No BLVDS25E Differential 2.5/3.3 No No RSDS25E Differential 2.5/3.3 No No LVPECL33 Differential 3.3 No No SSTL15D Differential 1.5/1.8/2.5/3.3 No No 16(77) 3Architecture 3.3IOB I/O Input Standard Single/Differ Bank VCCO (V) Hysteresis Need VREF SSTL25D_I Differential 2.5/3.3 No No SSTL25D_II Differential 2.5/3.3 No No SSTL33D_I Differential 3.3 No No SSTL33D_II Differential 3.3 No No SSTL18D_I Differential 1.8/2.5/3.3 No No SSTL18D_II Differential 1.8/2.5/3.3 No No HSTL18D_I Differential 1.8/2.5/3.3 No No HSTL18D_II Differential 1.8/2.5/3.3 No No HSTL15D_I Differential 1.5/1.8/2.5/3.3 No No 3.3.2 True LVDS Design BANK1/2/3 in the GW1N-2/2B/4/4B/6/9 devices support true LVDS output, but BANK1/2/3 do not support internal 100Ω input differential matched resistance. Bank0 supports internal 100Ω input differential matched resistance. BANK0/1/2/3 support LVDS25E, MLVDS25E, BLVDS25E,etc. For more detailed information about different levels, please refer to Gowin systemIO User Guide. For more detailed information about true LVDS, please refer to GW1N series of FPGA products Pinout. True LVDS input I/O needs external 100Ω terminal resistance for matching. SeeFigure 3-8for the true LVDS design. Figure 3-8 True LVDS Design Sender GW1N-2/4/6/9 txout+ txout- 50Ω 50Ω rxin+ txout+ 50Ω Logic Array 100Ω rxin- txout- Input Buffer 50Ω rxin+ Receiver rxin- Output Buffer For more detailed information about LVDS25E, MLVDS25E, and BLVDS25E on IO terminal matched resistance, please refer to Gowin SystemIO User Guide. DS100-1.8E 17(77) 3Architecture 3.3IOB 3.3.3 I/O Logic Figure 3-9 shows the I/O logic output of the GW1N series of FPGA products. Figure 3-9 I/O Logic Output TCTRL TCFF GND SER ISI TDATA OUTFF IODELAY Figure 3-10 shows the I/O logic input of the GW1N series of FPGA products. Figure 3-10 I/O Logic Input CI DI IODELAY INFF IEM DIN IDES Rate Sel Q A description of the I/O logic modules of the GW1N series FPGA products is presented below. IODELAY See Figure 3-11 for an overview of the IODELAY. Each I/O of the GW1N series of FPGA products has an IODELAY cell. The longest delay it can provide is about 128 steps x 30ps = 3840ps. DS100-1.8E 18(77) 3Architecture 3.3IOB Figure 3-11 IODELAY DI DO DLY UNIT SDTAP SETN DF DLY ADJ VALUE There are two ways to control the delay cell:   Static control: Dynamic control: Usually used to sample delay window together with IEM. The IODELAY cannot be used for both input and output at the same time I/O Register See Figure 3-12 for I/O register in the GW1N series of FPGA products. Each I/O provides one input register, INFF, one output register, OUTFF, and a tristate Register, TCFF. Figure 3-12 Register Structure in I/O Logic D Q CE CLK SR Note!  CE can be either active low (0: enable)or active high (1: enable).  CLK can be either rising edge trigger or falling edge trigger.  SR can be either synchronous/asynchronous SET or RESET or disable.  The register can be programmed as register or latch. IEM IEM is for sampling clock edge and is used in the generic DDR mode. See Figure 3-13 for the IEM structure. Figure 3-13 IEM Structure CLK D RESET DS100-1.8E LEAD IEM MCLK LAG 19(77) 3Architecture 3.3IOB De-serializer DES The GW1N series of FPGA products provide a simple Serializer SER for each output I/O to support advanced I/O protocols. Serializer SER The GW1N series of FPGA products provide a simple Serializer SER for each output I/O to support advanced I/O protocols. 3.3.4 I/O Logic Modes The I/O Logic in the GW1N series of FPGA products supports several operations. In each operation, the I/O (or I/O differential pair) can be configured as output, input, and INOUT or tristate output (output signal with tristate control). GW1N-1S, GW1N-6, and GW1N-9 pins support IO logic. The GW1N-1 pins IOL6 (A,B,C….J) and IOR6 (A,B,C….J) do not support IO logic. The other pins support IO logic. The GW1N-2/GW1N-2B and GW1N-4/GW1N-4B pins IOL10(A,B,C….J) and IOR10(A,B,C….J) do not support IO logic. The other pins support IO logic. Basic Mode In basic mode, the I/O Logic is as shown in Figure 3-14, and the TC, DO, and DI signals can connect to the internal cores directly through CRU. Figure 3-14 I/O Logic in Basic Mode TC DO IO PAD DI SDR Mode In comparison with the basic mode, SDR utilizes the IO register, as shown in Figure 3-15. This can effectively improve IO timing. DS100-1.8E 20(77) 3Architecture 3.3IOB Figure 3-15 I/O Logic in SDR Mode TCTRL D Q CE >CLK SR DOUT D O_CE CE O_CLK IO PAD Q >CLK O_SR SR DIN D I_CE Q CE I_CLK >CLK I_SR SR Note!  CLK enable O_CE and I_CE can be configured as active high or active low;  O_CLK and I_CLK can be either rising edge trigger or falling edge trigger;  Local set/reset signal O_SR and I_SR can be either synchronized reset, synchronized set, asynchronous reset, asynchronous set, or no-function;  I/O in SDR mode can be configured as basic register or latch. Generic DDR Mode Higher speed IO protocols can be supported in generic DDR mode. GW1N-1S, GW1N-6, and GW1N-9 devices support IDES16 mode and OSER16 mode. The other devices do not support. Figure 3-16 shows the generic DDR input, with a speed ratio of the internal logic to PAD 1:2. Figure 3-16 I/O Logic in DDR Input Mode D IDDR 2 Q[1:0] CLK Figure 3-17 shows generic DDR output, with a speed ratio of PAD to FPGA internal logic 2:1. DS100-1.8E 21(77) 3Architecture 3.3IOB Figure 3-17 I/O Logic in DDR Output Mode D[1:0] 2 ODDR Q CLK IDES4 In IDES4 mode, the speed ratio of the PAD to FPGA internal logic is 1:4. Figure 3-18 I/O Logic in IDES10 Mode D FCLK IDES4 PCLK 4 Q[3:0] CALIB RESET OSER4 Mode In OSER4 mode, the speed ratio of the PAD to FPGA internal logic is 4:1. Figure 3-19 I/O Logic in OSER4 Mode TX[1:0] D[3:0] 2 4 FCLK OSER4 2 Q[1:0] PCLK RESET IVideo Mode In IVideo mode, the speed ratio of the PAD to FPGA internal logic is 1:7. Figure 3-20 I/O Logic in IVideo Mode D CE FCLK PCLK IVideo 7 Q[6:0] CALIB RESET Note! IVideo and IDES8/10 will occupy the neighboring I/O logic. If the I/O logic of a single port is occupied, the pin can only be programmed in SDR or BASIC mode. OVideo Mode In OVideo mode, the speed ratio of the PAD to FPGA internal logic is DS100-1.8E 22(77) 3Architecture 3.3IOB 7:1. Figure 3-21 I/O Logic in OVideo Mode D[6:0] 7 FCLK OVideo PCLK Q IDES8 Mode In IDES8 mode, the speed ratio of the PAD to FPGA internal logic is 1:8. Figure 3-22 I/O Logic in IDES8 Mode D FCLK IDES8 PCLK 8 Q[7:0] CALIB RESET OSER8 Mode In OSER8 mode, the speed ratio of the PAD to FPGA internal logic is 8:1. Figure 3-23 I/O Logic in OSER8 Mode TX[3:0] D[7:0] 4 8 FCLK OSER8 2 Q[1:0] PCLK RESET IDES10 Mode In IDES10 mode, the speed ratio of the PAD to FPGA internal logic is 1:10. Figure 3-24 I/O Logic in IDES10 Mode D FCLK PCLK IDES10 10 Q[9:0] CALIB RESET OSER10 Mode In OSER10 mode, the speed ratio of the PAD to FPGA internal logic is 10:1. DS100-1.8E 23(77) 3Architecture 3.3IOB Figure 3-25 I/O Logic in OSER10 Mode D[9:0] 10 FCLK OSER10 PCLK Q RESET IDES16 Mode Only GW1N-1S, GW1N-6, and GW1N-9 devices support this mode. In IDES16 mode, the speed ratio of the PAD to FPGA internal logic is 1:16. Figure 3-26 I/O Logic in IDES16 Mode D FCLK IDES16 PCLK 16 Q[15:0] CALIB RESET OSER16 Mode Only GW1N-1S, GW1N-6, and GW1N-9 devices support this mode. In OSER16 mode, the speed ratio of the PAD to FPGA internal logic is 16:1. Figure 3-27 I/O Logic in OSER16 Mode D[15:0] FCLK PCLK 16 OSER16 Q RESET DS100-1.8E 24(77) 3Architecture 3.4Block SRAM (B-SRAM) 3.4 Block SRAM (B-SRAM) 3.4.1 Introduction The GW1N series of FPGA products provide abundant B-SRAMs. The Block SRAM (B-SRAM) is embedded as a row in the FPGA array and is different from S-SRAM (Shadow SRAM). Each B-SRAM occupies three columns of CFU in the FPGA array. Each B-SRAM has 18,432 bits (18Kbits). There are five operation modes: Single Port, Dual Port, Semi Dual Port, ROM, and FIFO. The signals and functional descriptions of B-SRAM are listed in Table 3-4. An abundance of B-SRAM resources provide a guarantee for the user's high-performance design. B-SRAM features include the following:                Max.18,432 bits per B-SRAM B-SRAM itself can run at 190 MHz at max Single Port Dual Port Semi Dual Port Parity bits ROM Data width from 1 to 36 bits Mixed clock mode Mixed data width mode Enable Byte operation for double byte or above Asynchronous reset, Synchronous reset Normal Read and Write Mode Read-before-write Mode Write-through Mode Table 3-4 B-SRAM Signals DS100-1.8E Port Name I/O Description DIA I Port A data input DIB I Port B data input ADA I Port A address ADB I Port B address CEA I Clock enable, Port A CEB I Clock enable, Port B RESETA I Register reset, Port A RESETB I Register reset, Port B WREA I Read/write enable, Port A 25(77) 3Architecture 3.4Block SRAM (B-SRAM) Port Name I/O Description WREB I Read/write enable, Port B BLKSEL I Block select CLKA I Read/write cycle clock for Port A input registers CLKB I Read/write cycle clock for Port B input registers OCEA I Clock enable for Port A output registers OCEB I Clock enable for Port B output registers DOA O Port A data output DOB O Port B data output 3.4.2 Configuration Mode The B-SRAM mode in the GW1N series of FPGA products supports different data bus widths. See Table 3-5. Table 3-5 Memory Size Configuration Single Mode DS100-1.8E Port Dual Port Mode Semi-Dual Mode Port 16 K x 1 16 K x 1 16 K x 1 16K x 1 8K x 2 8K x 2 8K x 2 8K x 2 4K x 4 4K x 4 4K x 4 4K x 4 2K x 8 2K x 8 2K x 8 2K x 8 1K x 16 1K x 16 1K x 16 1K x 16 512 x 32 - 512 x 32 512 x 32 2K x 9 2K x 9 2K x 9 2K x 9 1K x 18 1K x 18 1K x 18 1K x 18 512 x 36 - 512 x 36 512 x 36 Read Only 26(77) 3Architecture 3.4Block SRAM (B-SRAM) 3.4.3 Mixed Data Bus Width Configuration The B-SRAM in the GW1N series of FPGA products supports mixed data bus width operation. In the dual port and semi-dual port modes, the data bus width for read and write can be different. For the configuration options that are available, please see Table 3-6 and Table 3-7 below. Table 3-6 Dual Port Mixed Read/Write Data Width Configuration Read Port Write Port 16K x 1 8K x 2 4K x 4 2K x 8 1K x 16 16K x 1 * * * * * 8K x 2 * * * * * 4K x 4 * * * * * 2K x 8 * * * * * 1K x 16 * * * * * 2K x 9 1K x 18 2K x 9 * * 1K x 18 * * Note! ”*”denotes the modes supported. Table 3-7Semi Dual Port Mixed Read/Write Data Width Configuration Read Port Write Port 16K x 1 8K x 2 4K x 4 2K x 8 1K x 16 512 x 32 16K x 1 * * * * * * 8K x 2 * * * * * * 4K x 4 * * * * * * 2K x 8 * * * * * * 1K x 16 * * * * * * 512 x 32 * * * * * * 2K x 9 1K x 18 512 x 36 2K x 9 * * * 1K x 18 * * * Note! ”*”denotes the modes supported. 3.4.4 Byte-enable The B-SRAM in the GW1N series of FPGA products supports byte-enable. For data longer than a byte, the additional bits can be blocked, and only the selected portion can be written into. The blocked bits will be retained for future operation. Read/write enable ports (WREA, WREB), and byte-enable parameter options can be used to control the B-SRAM write DS100-1.8E 27(77) 3Architecture 3.4Block SRAM (B-SRAM) operation. 3.4.5 Parity Bit There are parity bits in B-SRAM. The 9th bit in each byte can be used as a parity bit or for data storage. However, the parity operation is not yet supported. 3.4.6 Synchronous Operation    All the input registers of B-SRAM support synchronous write; The output registers can be used as pipeline register to improve design performance; The output registers are bypass-able. 3.4.7 Power up Conditions B-SRAM initialization is supported when powering up. During the power-up process, B-SRAM is in standby mode, and all the data outputs are “0”. This also applies in ROM mode. 3.4.8 Operation Modes The input registers of B-SRAM can be used for synchronous write. The output registers can be used as pipeline register to improve design performance. In the dual port mode, the two ports of B-SRAM can be operated totally independently. Port A and Port B have their own clock and are write-enabled; as such, both ports can be written to and read independently from each other. Single Port Mode In the single port mode, as shown below, B-SRAM can write to or read from one port at one clock edge. During the write operation, the data can show up at the output of B-SRAM. Normal write mode (Normal-write Mode) and write-through mode can be supported. When the output register is bypassed, the new data will show at the same write clock rising edge. For the single port 2 K x 9bit block memory, see Figure 3-28 below. Figure 3-28 Single Port Block Memory DI[8:0] 9 AD[10:0] 11 WRE CE B-SRAM CLK 9 DO[8:0] RESET OCE BLKSEL[2:0] DS100-1.8E 3 BYTE_ENABLE 28(77) 3Architecture 3.4Block SRAM (B-SRAM) The table below shows all the configuration options that are available in the single port mode: Table 3-8 Single Port Block Memory Configuration Primitive Configuration RAM (Bit) Port Mode Memory Depth Data Depth B-SRAM_16K_S1 16 K 16 K x 1 16,384 1 B-SRAM_8K_S2 16K 8K x 2 8,192 2 B-SRAM_4K_S4 16K 4K x 4 4,096 4 B-SRAM_2K_S8 16K 2K x 8 2,048 8 B-SRAM_1K_S16 16K 1K x 16 1,024 16 B-SRAM_512_S32 16K 512 x 32 512 32 B-SRAM_2K_S9 18K 2K x 9 2,048 9 B-SRAM_1K_S18 18K 1K x 18 1,024 18 B-SRAM_512_S36 18K 512 x 36 512 36 SP SPX9 Dual Port Mode B-SRAM support Dual Port mode, as shown in Figure 3-29. The applicable operations are as follows:    Two independent read Two independent write An independent read and an independent write at different clock frequencies Figure 3-29 Dual Port Block Memory DIA[15:0] 16 ADA[9:0] 10 16 DIB[15:0] 10 ADB[9:0] WREB WREA CEB CEA B-SRAM CLKA CLKB RESETB RESETA OCEB OCEA DOA[15:0] 16 BYTE_ENABLE 16 DOB[15:0] 3 BLKSEL[2:0] All the configuration options for the dual port mode are as shown in Table 3-9 . Table 3-9 Semi Dual Port Memory Configuration Primitive Configuration RAM (Bit) Port Mode Memory Depth Data Depth B-SRAM_16K_D1 16K 16K x 1 16384 1 B-SRAM_8K_D2 16K 8K x 2 8192 2 DP DS100-1.8E 29(77) 3Architecture 3.4Block SRAM (B-SRAM) Primitive Configuration RAM (Bit) Port Mode Memory Depth Data Depth B-SRAM_4K_D4 16K 4K x 4 4096 4 B-SRAM_2K_D8 16K 2K x 8 2048 8 B-SRAM_1K_D16 16K 1K x 16 1024 16 B-SRAM_2K_D9 18K 2K x 9 2048 9 B-SRAM_1K_D18 18K 1K x 18 1024 18 DPX9 DS100-1.8E 30(77) 3Architecture 3.4Block SRAM (B-SRAM) Semi-Dual Port Mode The figure below shows the semi Dual Port 1K x 16bit mode. It supports read and write at the same time on different ports. It is not possible to write and read to the same port at the same time. The system only supports write on Port A , read on Port B. Figure 3-30 Semi Dual Port Block Memory 1 DIA[15:0] 16 ADA[9:0] 10 10 WREA CEB CEA B-SRAM CLKB CLKA RESETB RESETA BLKSEL[2:0] ADB[9:0] OCEB 3 BYTE_ENABLE 16 DOB[15:0] All the configuration options for the dual port mode are as shown in Table 3-10. Table 3-10Semi Dual Port Memory Configuration Primitive Configuration RAM (Bit) Port Mode Memory Depth Data Depth B-SRAM_16K_SD1 16K 16K x 1 16,384 1 B-SRAM_8K_SD2 16K 8K x 2 8,192 2 B-SRAM_4K_SD4 16K 4K x 4 4,096 4 B-SRAM_2K_SD8 16K 2K x 8 2,048 8 B-SRAM_1K_SD16 16K 1K x 16 1,024 16 B-SRAM_512_SD32 16K 512 x 32 512 32 B-SRAM_2K_SD9 18K 2K x 9 2,048 9 B-SRAM_1K_SD18 18K 1K x 18 1,024 18 B-SRAM_512_SD36 18K 512 x 36 512 36 SDP SDPX9 DS100-1.8E 31(77) 3Architecture 3.4Block SRAM (B-SRAM) Read Only B-SRAM can be configured as ROM, as shown in Figure 3-31. The ROM can be initialized during the device configuration stage, and the ROM data needs to be provided in the initialization file. Initialization completes during the device power-on process. Figure 3-31 ROM Block Memory AD[9:0] 16 CE CLK B-SRAM RESET BLKSEL[2:0] 3 DO[17:0] 18 Each B-SRAM can be configured as one 16 Kbits ROM. Table 3-11 lists all the configuration options for the ROM mode. Table 3-11 Block ROM Configuration Primitive Configuration RAM (Bit) Port Mode Memory Depth Data Depth B-SRAM_16K_O1 16K 16K x 1 16,384 1 B-SRAM_8K_O2 16K 8K x 2 8,192 2 B-SRAM_4K_O4 16K 4K x 4 4,096 4 B-SRAM_2K_O8 16K 2K x 8 2,048 8 B-SRAM_1K_O16 16K 1K x 16 1,024 16 B-SRAM_512_O32 16K 512 x 32 512 32 B-SRAM_2K_O9 18K 2K x 9 2,048 9 B-SRAM_1K_O18 18K 1K x 18 1,024 18 B-SRAM_512_O36 18K 512 x 36 512 36 ROM ROMX9 Note! In the ROM mode, the RESET signal can only reset the input and output registers. It cannot clear the ROM content. 3.4.9 B-SRAM Operation Modes B-SRAM supports five different operations, including two read operations (Bypass Mode and Pipeline Read Mode) and three write operations (Normal Write Mode, Write-through Mode, and Read-before-write Mode). DS100-1.8E 32(77) 3Architecture 3.4Block SRAM (B-SRAM) Read Mode Read data from the B-SRAM via output registers or without using the registers. Pipeline Mode While writing in the B-SRAM, the output register and pipeline register are also being written. The data bus can be up to 36 bits in this mode. Bypass Mode The output register is not used. The data is kept in the output of memory array. Figure 3-32 Pipeline Mode in Single Port, Dual Port and Semi Dual Port AD DI Input Register Memory Array Output Register ADA WREB OCE DO CLK WRE OCE WREA ADB DIA Input Register Memory Array Output Register DOB CLKA CLKB CLKA ADA DIA ADB Input Register WREA CLKB Input Register WREB Memory Array Output Register Output Register OCEA OCEB DOA DS100-1.8E DIB DOB 33(77) 3Architecture 3.4Block SRAM (B-SRAM) Write Mode NORMAL WRITE MODE In this mode, when the user writes data to one port, and the output data of this port does not change. The data written in will not appear at the read port. WRITE-THROUGH MODE In this mode, when the user writes data to one port, and the data written in will also appear at the output of this port. READ-BEFORE-WRITE MODE In this mode, when the user writes data to one port, and the data written in will be stored in the memory according to the address. The original data in this address will appear at the output of this port. 3.4.10 Clock Operations Table 3-12 lists the clock operations in different B-SRAM modes: Table 3-12 Clock Operations in Different B-SRAM Modes Clock Operations Dual Port Mode Semi-Dual Port Mode Single Port Mode Independent Clock Mode Yes No No Read/Write Clock Mode Yes Yes No Single Port Clock Mode No No Yes Independent Clock Mode Figure 3-33 shows the independent clocks in the dual port mode with each port with one clock. CLKA controls all the registers at Port A; CLKB controls all the registers at Port B. Figure 3-33 Independent Clock Mode CLKA ADA DIA ADB Input Register WREA CLKB Input Register WREB Memory Array Output Register Output Register OCEA OCEB DOA DS100-1.8E DIB DOB 34(77) 3Architecture 3.5User Flash (GW1N-1 and GW1N-1S) Read/Write Clock Operation Figure 3-34 shows the read/write clock operations in the semi-dual port mode with one clock at each port. The write clock (CLKA) controls Port A data inputs, write address and read/write enable signals. The read clock (CLKB) controls Port B data output, read address, and read enable signals. Figure 3-34 Read/Write Clock Mode WREA ADA ADB WREB OCE DIA Input Register Memory Array Output Register DOB CLKA CLKB Single Port Clock Mode Figure 3-35shows the clock operation in single port mode. Figure 3-35 Single Port Clock Mode AD DI Input Register Memory Array Output Register DO CLK WRE OCE 3.5 User Flash (GW1N-1 and GW1N-1S) 3.5.1 Introduction GW1N-1 and GW1N-1S devices support User Flash with 12 Kbytes (48 page x 256 Bytes). The features are as following:  100,000 write cycles  Greater than10 years Data Retention at +85 ℃  Selectable 8/16/32 bits data-in and data-out Page size: 256 Bytes 3 μA standby current Page Write Time: 8.2 ms    3.5.2 Port Signal See Figure 3-36 for GW1N-1 and GW1N-1S user flash: DS100-1.8E 35(77) 3Architecture 3.5User Flash (GW1N-1 and GW1N-1S) Figure 3-36 GW1N-1/GW1N-1S User Flash Ports Ra[5:0] 6 6 Pa[5:0] Ca[5:0] 6 2 Wmod[1:0] Mode[3:0] 4 2 Wbytesel[1:0] Rmod[1:0] 2 Rbytesel[1:0] 2 Seq[1:0] 2 Oe Din[31:0] 32 Sleep Pw GW1N-1 NVM Aclk Pe 32 Dout[31:0] Reset Table 3-13 Flash Module Signal Description Pin name1 I/O Ra[5:0] I Ca[5:0] I Pa[5:0]2 I I Mode[3:0] I Seq[1:0] I Aclk I Rmod[1:0] I Wmod[1:0] I Select operation mode. Control operation sequence. Synchronize clock for read-write operations. Read data bit width selection. Write data bit width selection. Rbytesel[1:0] I Read data byte selection. Wbytesel[1:0] I Write data bit width selection. Pw I Write Page latch clock. Reset I Pe I I Reset signal, active-high. Charge pump enabled. Data output enable. Sleep mode, active-high. Din[31:0] I Data input bus. Dout[31:0] O Data output bus. 3 Oe I Sleep 4 Description X address bus, used to select one row within memory block. Y address bus, used to select one column within memory block. Note! DS100-1.8E  [1] Port names of Control, address,and data signals.  [2] Pa signal has the same function as Ca signal, except that Pa signal is used for programming operation of page latch data, and Ca signal is used for other operations related to column selection in Flash.  [3] The high-level effective time of reset signal is not less than 20ns. Wait for 6μs after that the reset signal changes to low-level, and then move on. 36(77) 3Architecture 3.5User Flash (GW1N-1 and GW1N-1S)  [4] Save power through flash memory resources entering into sleep mode. Wait for 6μs after that the sleep signal changes to low-level, and then move on. 3.5.3 Data Output Bit Selection Change data I/O bit width by Rmod/Wmod and Rbytesel/ Wbytesel. The correspondence between data bit width and control signal is shown in Table 3-14 and Table 3-15. Table 3-14 Data Output Bit Selection Rmod[1:0] Rbytesel Dout [1] [0] [31:24] [23:16] [15:8] [7:0] 0.0 √ √ × × × √ 0.1 √ × × × √ √ × × √ √ √ √ 1X Table 3-15s Data Input Bit Selection Wbytesel Din [1] [0] [31:24] [23:16] [15:8] [7:0] 0.0 √ √ × × × √ 0.1 √ × × × √ √ 1X × × √ √ √ √ Wmod[1:0] Note! “√” means valid input; “×”means invalid input. 3.5.4 Operation Mode User can set Mode [3: 0] to select different operation modes, as shown in Table 3-16. Table 3-16 Operation Modes Selection Mode[3:0] Description 0000 Normal read operation and page latch write operation 0001 0100 1000 1100 Set pre-program and clear after any program cycle automatically Clear page latches Erase Page (or row) Program Page (or row) 3.5.5 Read Operation When the Mode input is set as "0000", the user flash enters into read operation mode at the rising edge of Aclk. Seq [1: 0] should be "00" for read operation mode. When the data access time ( 2> 3> 0, which are long operations requiring milliseconds. It is forbidden to program the same page twice after an erasure operation. Before erasing and programming, program all the selected memory locations to pseudo "1". To execute pre-program operation, set PEP (pre-program) first (Mode "0001"), and then program (Mode "1100") the selected locations with high-voltage duration in time of hundreds of microseconds. 3.6 User Flash (GW1N-2/2B/4/4B/6/9) 3.6.1 Introduction GW1N-2/2B/4/4B/6/9 offers User Flash. The capacity of the user Flash in GW1N-2/2B/4/4B is 256Kbits. The capacity of the user flash in GW1N-6/9 is 608Kbits. The user Flash memory is composed of row memory and column memory. One row memory is composed of 64 column memories. The capacity of one column memory is 32 bits, and the capacity DS100-1.8E 38(77) 3Architecture 3.6User Flash (GW1N-2/2B/4/4B/6/9) of one row memory is 64*32=2048 bits. Page erase is supported, and one page capacity is 2048 bytes, i.e., one page includes 8 rows. The features are shown below:  10,000 write cycles  Greater than10 years Data Retention at +85 ℃  Data Width: 32 GW1N-2/2B/4/4B capacity: 128 rows x 64 columns x 32 = 256kbits GW1N-6/9 capacity: 304 rows x 64 columns x 32 = 608kbits Page Erase Capability: 2,048 bytes per page Fast Page Erasure/Word Programming Operation Clock frequency: 40 MHz Word Programming Time:≤16 μs Page Erasure Time:≤120 ms Electric current - Read current/duration:2.19 mA/25 ns (VCC) & 0.5 mA/25 ns (VCCX) (MAX) - Program / Erase operation: 12/12 mA(MAX)         3.6.2 Port Signal SeeFigure 3-37 for GW1N-2/4/2B/4B/6/9 user flash: Figure 3-37 GW1N-2/4/2B/4B/6/9 Flash Port Signal XADR[6:0] 7 YADR[5:0] 6 DIN[31:0] 32 DOUT[31:0] 32 XE YE GW1N-4 NVM 8K×32 NVSTR SE PROG ERASE Table 3-17 Flash Module Signal Description Pin name1 XADR[5:0]2 I/O Description I X address bus, used to access row address. XADR[n:3] is used to select one page; XADR[2:0] is used to select one row on one page. One page is composed of eight rows, and one row is composed of 64 columns. GW1N-2/2B/4/4B: 128 rows in all, n=6 GW1N-6/9: 304 rows in all, n=8 DS100-1.8E YADR[5:0]2 I Y address bus, used to select one column within a row of memory block. One row consists of 64 columns. DIN[31:0] I Data input bus. DOUT[31:0] O Data output bus. 39(77) 3Architecture 3.7DSP Pin name1 I/O Description XE2 I X address enable signal, if XE is 0, all of row addresses are not enabled. YE2 I Y address enable signal, if YE is 0, all of column addresses are not enabled. SE2 I Detect amplifier enable signal, active high. ERASE I Erase port, active-high. PROG I Programming port, active-high. NVSTR I Flash data storage port, active-high. Note!  [1] Port names of Control, address,and data signals.  [2] The read operation is valid only if XE = YE = V CC and SE meets the pulse timing requirements (Tpws, Tnws). The address of read data is determined by XADR [5: 0] and YADR [5: 0]. 3.6.3 Operation Mode Table 3-18 Truth Table in User Mode Mode XE YE SE PROG ERASE NVSTR Read Mode H H H L L L Programming Mode H H L H L H Page Erasure Mode H L L L H H Note! “H” and “L” means high level and low level of VCC. 3.7 DSP 3.7.1 Introduction GW1N-2/4/2B/4B/6/9 devices offer abundant DSP modules. Gowin DSP solutions can meet user demands for high performance digital signal processing design, such as FIR, FFT, etc. DSP blocks have the advantages of stable timing performance, high-usage, and low-power. DSP offers the following functions:       DS100-1.8E Multiplier with three widths: 9-bit, 18-bit, 36-bit 54-bit ALU Multipliers cascading to support wider data Barrel shifter Adaptive filtering through signal feedback Computing with options to round to a positive number or a prime number 40(77) 3Architecture 3.7DSP  Supports pipeline mode and bypass mode. Macro DSP blocks are embedded as rows in the FPGA array. Each DSP occupies nine CFU columns. Each DSP block contains two Macro, and each Macro contains two pre-adders, two 18 x 18 bit multipliers, and one three-input ALU. Figure 3-38 shows the structure of one Macro. DS100-1.8E 41(77) 3Architecture 3.7DSP Figure 3-38 DSP Macro B0[17:0] A0[17:0] 18 A1[17:0] PADDSUB[1:0] 18 2 “0” SDIA INC[17:0] INC[44:27] INA0 MUXA0 REGA0 54 18 MUXB1 REGC REGB1 REGA1 54 18 INB1 18 INA1 INA0 “0” C[53:0] 18 INA1 “0” MUXA1 REG_PADDSUB INA0 18 “0” 18 18 B1[17:0] SBI[17:0] 18 INC MUXB0 REGB0 18 INB0 SBO[17:0] 18 PADDSUB[1] PADDSUN[0] +/- 18 PADD0 SIB[17:0] SIA[17:0] B0 18 A0 18 +/- ALUSEL ALUMODE 18 PADD1 18 18 A1 BSEL[1:0] ASIGN[1:0] BSIGN[1:0] 18 MROB1 REGMA1 18 MROA0 ASEL[1:0] REGMB1 MUXMA1 18 MROB0 REGMA0 MUXMB1 18 REGMB0 MUXMA0 INC[44:27] B1 18 18 INC[17:0] MUXMB0 18 Pre-adder 18 18 MROA1 4 REG_CNTLI 2 × 2 × 36 M0 2 4 REGSD 4 CLK[3:0] CE[3:0] RESET[3:0] 36 M1 18 2 REGP0 REG_CNTLP REGP1 LOADA “0” alusel[6:4] A_MUX 54 LOADA C_MUX CASI>>18 INC MULT LOADB MDI1,000V HBM>1,000V HBM>1,000V HBM>1,000V - LQ144 HBM>1,000V HBM>1,000V HBM>1,000V HBM>1,000V HBM>1,000V - EQ144 HBM>1,000V HBM>1,000V HBM>1,000V HBM>1,000V HBM>1,000V - LQ176 - - - HBM>1,000V HBM>1,000V - EQ176 - - - HBM>1,000V HBM>1,000V - MG160 - HBM>1,000V HBM>1,000V HBM>1,000V HBM>1,000V - MG196 - - - HBM>1,000V HBM>1,000V - PG256 - HBM>1,000V HBM>1,000V HBM>1,000V HBM>1,000V - PG256 M - HBM>1,000V HBM>1,000V - - - UG169 - - - HBM>1,000V HBM>1,000V - UG256 - - - HBM>1,000V HBM>1,000V - UG332 - - - HBM>1,000V HBM>1,000V - QN32 HBM>1,000V HBM>1,000V HBM>1,000V - - - QN48 HBM>1,000V HBM>1,000V HBM>1,000V HBM>1,000V HBM>1,000V - CS30 HBM>1,000V - - - - - CS72 - HBM>1,000V HBM>1,000V - - - QN88 - HBM>1,000V HBM>1,000V HBM>1,000V HBM>1,000V - FN32 - - - - - HBM>1,000V Table 4-5 GW1N ESD - CDM Device GW1N-1 GW1N-2/ GW1N-2B GW1N-4/ GW1N-4B GW1N-6 GW1N-9 GW1N-1S LQ100 CDM>500V CDM>500V CDM>500V CDM>500V CDM>500V - LQ144 CDM>500V CDM>500V CDM>500V CDM>500V CDM>500V - EQ144 CDM>500V CDM>500V CDM>500V CDM>500V CDM>500V - LQ176 - - - CDM>500V CDM>500V - DS100-1.8E 56(77) 4AC/DC Characteristic 4.2ESD Device GW1N-1 GW1N-2/ GW1N-2B GW1N-4/ GW1N-4B GW1N-6 GW1N-9 GW1N-1S EQ176 - - - CDM>500V CDM>500V - MG160 - CDM>500V CDM>500V CDM>500V CDM>500V - MG196 - - - CDM>500V CDM>500V - PG256 - CDM>500V CDM>500V CDM>500V CDM>500V - PG256M - CDM>500V CDM>500V - - - CDM>500V CDM>500V UG169 UG256 - - - CDM>500V CDM>500V - UG332 - - - CDM>500V CDM>500V - QN32 CDM>500V - - - - - QN48 CDM>500V CDM>500V CDM>500V CDM>500V CDM>500V - CS30 CDM>500V - - - - - CS72 - CDM>500V CDM>500V - - - QN88 - CDM>500V CDM>500V CDM>500V CDM>500V - FN32 - - - - - CDM>500V Table 4-6 DC Electrical Characteristics over Recommended Operating Conditions Name Description Condition Min. Typ. Max. Input or I/O leakage VCCO