SG3525ADTR

XBLW SG3525 Pulse Width Modulator Control Circuit General Description The SG3525 pulse width modulator control circuit offers improved performance and lower external parts count when Implemented for controlling all types of switching power supplies. The on−chip +5.1 V reference is trimmed to ±1% and the error amplifier has an input common−mode voltage range that includes the reference voltage, thus eliminating the need for external divider resistors.A sync input to the oscillator enables multiple units to be slaved or a single unit to be synchronized to an external system clock. A wide range of deadtime can be programmed by a single resistor connected between the CT and Discharge pins. This device also features built−in soft−start circuitry, requiring only an external timing capacitor. A shutdown pin controls both the soft−start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft−start recycle with longer shutdown commands. The under voltage lockout inhibits the outputs and the changing of the soft−start capacitor when V CC is below nominal. The output stages are totem−pole design capable of sinking and sourcing in excess of 200 mA. The output stage of the SG3525 features NOR logic resulting in a low output for an off−state. Features ● ● ● ● ● ● ● ● ● 8.0 V to 35 V Operation 5.1 V ± 1.0% Trimmed Reference 100 Hz to 400 kHz Oscillator Range Separate Oscillator Sync Pin Adjustable Deadtime Control Input Undervoltage Lockout Latching PWM to Prevent Multiple Pulses Pulse−by−Pulse Shutdown Dual Source/Sink Outputs: ±400 mA Peak Ordering Information DEVICE Package Type MARKING Packing SG3525AN DIP16 SG3525AN Tube 1000/box SG3525ADTR SOP16 SG3525A Reel 2500/reel XBLWversion1.0 Packing QTY 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第1页共8页 XBLW SG3525 Pulse Width Modulator Control Circuit PIN CONNECTIONS SG3525 (Top View) SOP-16/DIP-16 Figure 1. Representative Block Diagram XBLWversion1.0 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第2页共8页 XBLW SG3525 Pulse Width Modulator Control Circuit MAXIMUM RATINGS Symbol Value Unit Supply Voltage V CC +40 Vdc Collector Supply Voltage VC +40 Vdc Logic Inputs −0.3 to +5.5 V Analog Inputs −0.3 to V CC V Rating Output Current, Source or Sink IO ±500 mA Reference Output Current Iref 50 mA 5.0 mA Oscillator Charging Current Power Dissipation TA = +25oC (Note 1) TC = +25oC (Note 2) PD mW 1000 2000 Thermal Resistance, Junction−to−Air RθJA 100 oC/W Thermal Resistance, Junction−to−Case RθJC 60 oC/W TJ +150 oC Tstg −55 to +125 oC Operating Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 seconds) +300 oC T Solder Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Derate at 10 mW/oC for ambient temperatures above +50oC. 2. Derate at 16 mW/oC for case temperatures above +25oC. RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Max Unit Supply Voltage VCC 8.0 35 Vdc Collector Supply Voltage VC 4.5 35 Vdc Output Sink/Source Current (Steady State) (Peak) IO 0 0 ±100 ±400 Reference Load Current mA Iref 0 20 mA Oscillator Frequency Range fosc 0.1 400 kHz Oscillator Timing Resistor RT 2.0 150 kΩ Oscillator Timing Capacitor CT 0.001 0.2 uF Deadtime Resistor Range RD 0 500 Ω Operating Ambient Temperature Range TA 0 +70 oC MAXIMUM RATINGS Since both the compensation and soft−start terminals (Pins 9 and 8) have current source pull−ups, either can readily accept a pull−down signal which only has to sink a maximum of 100 uA to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins. An alternate approach is the use of the shutdown circuitry of Pin 10 which has been improved to enhance the available shutdown options. Activating this circuit by applying a positive signal on Pin 10 performs two functions: the PWM latch is immediately set providing the fastest turn−off signal to the outputs; and a 150 uA current sink begins to discharge the external soft−start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft−start capacitor, thus, allowing, for example, a convenient implementation of pulse−by−pulse current limiting. Holding Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn−on upon release. Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation. XBLWversion1.0 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第3页共8页 XBLW SG3525 Pulse Width Modulator Control Circuit ELECTRICAL CHARACTERISTICS (VCC = +20 Vdc, TA = T low to Thigh[Note 3], unless otherwise noted.) Characteristics Symbol Min Typ Max Unit Reference Output Voltage (TJ = +25oC) Vref 5.00 5.10 5.20 Vdc Line Regulation (+8.0 V ≤ VCC≤ +35 V) Regline − 10 20 mV Load Regulation (0 mA ≤ IL≤ 20 mA) Regload − 20 50 mV Temperature Stability ΔV ref/ΔT − 20 − mV Total Output Variation Includes Line and Load Regulation over Temperature ΔV ref 4.95 − 5.25 Vdc Short Circuit Current (Vref = 0 V,TJ = +25oC) ISC − 80 100 mA Output Noise Voltage (10 Hz ≤ f ≤ 10 kHz, TJ = +25oC) Vn − 40 200 uVrms Long Term Stability (TJ = +125oC) (Note 4) S − 20 50 mV/khr − ±2.0 ±6.0 % REFERENCE SECTION OSCILLATOR SECTION (Note 5, unless otherwise noted.) Initial Accuracy (TJ = +25oC) Frequency Stability with Voltage (+8.0 V ≤ V CC≤ +35 V) Δfosc DVCC − ±1.0 ±2.0 % Frequency Stability with Temperature Δfosc DT − ±0.3 − % Minimum Frequency (RT = 150 kΩ, CT = 0.2 uF) fmin − 50 − Hz Maximum Frequency (RT = 2.0 kΩ, CT = 1.0 nF) fmax 400 − − kHz 1.7 2.0 2.2 mA V Current Mirror (IRT = 2.0 mA) Clock Amplitude 3.0 3.5 − Clock Width (TJ = +25oC) 0.3 0.5 1.0 us Sync Threshold 1.2 2.0 2.8 V Sync Input Current (Sync Voltage = +3.5 V) − 1.0 2.5 mA VIO − 2.0 10 mV 1.0 10 uA ERROR AMPLIFIER SECTION (V CM = +5.1 V) Input Offset Voltage IIB − Input Offset Current IIO − − 1.0 uA DC Open Loop Gain (RL之 10 MΩ) AVOL 60 75 − dB Low Level Output Voltage VOL − 0.2 0.5 V High Level Output Voltage V OH 3.8 5.6 − V dB Input Bias Current Common Mode Rejection Ratio (+1.5 V ≤ V CM≤ +5.2 V) CMRR 60 75 − Power Supply Rejection Ratio (+8.0 V ≤ V CC≤ +35 V) PSRR 50 60 − dB DCmin − − 0 % % PWM COMPARATOR SECTION Minimum Duty Cycle Maximum Duty Cycle DCmax 45 49 − Input Threshold, Zero Duty Cycle (Note 5) Vth 0.6 0.9 − V Input Threshold, Maximum Duty Cycle (Note 5) Vth − 3.3 3.6 V Input Bias Current IIB − 0.05 1.0 uA 3. Tlow = 0o Thigh = +70oC 4. Since long term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability from lot to lot. 5. Tested at fosc = 40 kHz (RT = 3.6 kΩ, CT = 0.01 uF, RD = 0 Ω). XBLWversion1.0 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第4页共8页 XBLW SG3525 Pulse Width Modulator Control Circuit ELECTRICAL CHARACTERISTICS (continued) Characteristics Symbol Min Typ Max Unit Soft−Start Current (Vshutdown = 0 V) 25 50 80 uA Soft−Start Voltage (Vshutdown = 2.0 V) − 0.4 0.6 V Shutdown Input Current (Vshutdown = 2.5 V) − 0.4 1.0 mA − − 0.2 1.0 0.4 2.0 18 17 19 18 − − SOFT−START SECTION OUTPUT DRIVERS (Each Output, VCC = +20 V) Output Low Level (Isink = 20 mA) (Isink = 100 mA) VOL Output High Level (Isource = 20 mA) (Isource = 100 mA) VOH Under Voltage Lockout (V8 and V9 = High) V V V UL 6.0 7.0 8.0 V Collector Leakage, VC = +35 V (Note 6) IC(leak) − − 200 uA Rise Time (CL = 1.0 nF, TJ = 25oC) tr − 100 600 ns Fall Time (CL = 1.0 nF, TJ = 25oC) tf − 50 300 ns Shutdown Delay (VDS = +3.0 V, CS = 0, TJ = +25oC) tds − 0.2 0.5 us Supply Current (VCC = +35 V) ICC − 14 20 mA 6. Applies to SG3525 only, due to polarity of output pulses. Figure 2. Lab Test Fixture XBLWversion1.0 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第5页共8页 XBLW SG3525 Pulse Width Modulator Control Circuit Figure 3. Oscillator Charge Time versus RT Figure 5. Error Amplifier Open Loop Frequency Response Figure 7. Oscillator Schematic XBLWversion1.0 Figure 4. Oscillator Discharge Time versus RD Figure 6. Output Saturaton Characteristics Figure 8. Error Amplifier Schematic 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第6页共8页 XBLW SG3525 Pulse Width Modulator Control Circuit XBLWversion1.0 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第7页共8页 XBLW SG3525 Pulse Width Modulator Control Circuit Statement：  Shenzhen xinbole electronics co., ltd. reserves the right to change the product specifications, without notice! Before placing an order, the customer needs to confirm whether the information obtained is the latest version, and verify the integrity of the relevant information.  Any semiconductor product is liable to fail or malfunction under certain conditions, and the buyer shall be responsible for complying with safety standards in the system design and whole machine manufacturing using Shenzhen xinbole electronics co., ltd products, and take appropriate security measures to avoid the potential risk of failure may result in personal injury or property losses of the situation occurred!  Product performance is never ending, Shenzhen xinbole electronics co., ltd will be dedicated to provide customers with better performance, better quality of integrated circuit products. XBLWversion1.0 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第8页共8页