CD4046B
Micro power Phase-Locked Loop
Features
Wide supply voltage range：3.0V to 18V
Low dynamic：70µW (typ.) at
DIP-16
power consumption：fo = 10 kHz, VDD = 5V
VCO frequency：1.3 MHz (typ.) at VDD = 10V
Low frequency drift：0.06%/°C at VDD = 10V with temperature
High VCO linearity：1% (typ.)
SOP-16
TSSOP-16
Ordering Information
DEVICE
CD4046BE/
CD4046BN
CD4046BM/TR
CD4046BMT/TR
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Package Type
MARKING
Packing
Packing Qty
DIP-16
CD4046B
TUBE
1000pcs/box
SOP-16
CD4046B
REEL
2500pcs/reel
TSSOP-16
CD4046B
REEL
2500pcs/reel
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2014 JUN
CD4046B
General Description
The CD4046B micropower phase-locked loop (PLL) consists of a low power, linear, voltage-controlled
oscillator (VCO), a source follower, a zener diode, and two phase comparators. The two phase comparators
have a common signal input and a common comparator input. The signal input can be directly coupled for a
large voltage signal, or capacitively coupled to the self-biasing amplifier at the signal input for a small voltage
signal.Phase comparator I, an exclusive OR gate, provides a digital error signal (phase comp. I Out) and
maintains 90° phase shifts at the VCO center frequency. Between signal input and comparator input (both at
50% duty cycle), it may lock onto the signal input frequencies that are close to harmonics of the VCO center
frequency.Phase comparator II is an edge-controlled digital memory network. It provides a digital error signal
(phase comp. II Out) and lock-in signal (phase pulses) to indicate a locked condition and maintains a 0° phase
shift between signal input and comparator input.
The linear voltage-controlled oscillator (VCO) produces an output signal (VCO Out) whose frequency is
determined by the voltage at the VCOIN input, and the capacitor and resistors connected to pin C1A, C1B, R1
and R2.The source follower output of the VCOIN (demodulator Out) is used with an external resistor of 10 kΩ or
more. The INHIBIT input, when high, disables the VCO and source follower to minimize standby power
consumption. The zener diode is provided for power supply regulation, if necessary.
Applications
FM demodulator and modulator
Frequency synthesis and multiplication
Frequency discrimination
Data synchronization and conditioning
Voltage-to-frequency conversion
Tone decoding
FSK modulation
Motor speed control
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CD4046B
Block & Connection Diagrams
FIGURE 1
Dual-In-Line Package
Top View
Order Number CD4046B
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2014 JUN
CD4046B
Absolute Maximum Ratings (Notes 1 & 2)
Condition
Min
Max
UNITS
DC Supply Voltage (VDD)
-0.5
+18
V
Input Voltage (VIN)
-0.5
+0.5
V
Storage Temperature Range (TS)
-65
150
°C
Power Dissipation (PD)
-
-
-
Dual-In-Line
-
700
mW
Small Outline
-
500
mW
-
245
°C
Lead Temperature (TL)(Soldering, 10 seconds)
Recommended Operating Conditions (Note 2)
Condition
DC Supply Voltage (VDD)
Min
Max
UNITS
+3
+15
V
Input Voltage (VIN)
0 to VDD
Operating Temperature Range (TA)
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-40
4 / 15
V
+85
°C
2014 JUN
CD4046B
DC Electrical Characteristics (Note 2)
Symbol
Parameter
-40°C
Conditions
Min
+25°C
Max
Min
+85°C
Min
Max
Units
Typ
Max
0.005
20
150
µA
Pin 5 = VDD, Pin 14 = VDD,
Pin 3, 9 = VSS
IDD
Quiescent Device Current
VDD = 5V
20
VDD = 10V
40
0.01
40
300
µA
VDD = 15V
80
0.015
80
600
µA
Pin 5 = VDD, Pin 14 = Open,
Pin 3, 9 = VSS
VOL
Low Level Output Voltage
VDD = 5V
70
5
55
205
µA
VDD = 10V
530
20
410
710
µA
VDD = 15V
1500
50
1200
1800
µA
VDD = 5V
0.05
0
0.05
0.05
V
VDD = 10V
0.05
0
0.05
0.05
V
VDD = 15V
0.05
0
0.05
0.05
V
VDD = 5V
VOH
VIL
VIH
IOL
IOH
High Level Output Voltage
Low Level Input Voltage
Comparator and Signal In
High Level Input Voltage
Comparator and Signal In
Low Level Output Current
(Note 4)
High Level Output Current
(Note 4)
4.95
4.95
5
4.95
V
VDD = 10V
9.95
9.95
10
9.95
V
VDD = 15V
14.95
14.95
15
14.95
V
VDD = 5V, VO = 0.5V or 4.5V
1.5
2.25
1.5
1.5
V
VDD = 10V, VO = 1V or 9V
3.0
4.5
3.0
3.0
V
6.25
4.0
4.0
V
VDD = 15V, VO = 1.5V or 13.5V
VDD = 5V, VO = 0.5V or 4.5V
4.0
3.5
3.5
2.75
3.5
V
VDD = 10V, VO = 1V or 9V
7.0
7.0
5.5
7.0
V
VDD = 15V, VO = 1.5V or 13.5V
11.0
11.0
8.25
11.0
V
VDD = 5V, VO = 0.4V
0.52
0.44
0.88
0.36
mA
VDD = 10V, VO = 0.5V
1.3
1.1
2.25
0.9
mA
VDD = 15V, VO = 1.5V
3.6
3.0
8.8
2.4
mA
VDD = 5V, VO = 4.6V
-0.52
-0.44
-0.88
-0.36
mA
VDD = 10V, VO = 9.5V
-1.3
-1.1
-2.25
-0.9
mA
VDD = 15V, VO = 13.5V
-3.6
-3.0
-8.8
-2.4
mA
All Inputs Except Signal Input
IIN
CIN
Input Current
Input Capacitance
VDD = 15V, VIN = 0V
-0.3
-10-5
-0.3
-1.0
µA
VDD = 15V, VIN = 15V
0.3
10-5
0.3
1.0
µA
Any Input (Note 3)
7.5
pF
fo = 10 kHz, R1 = 1 MΩ
R2 = ∞, VCOIN = VDD/2
PT
Total Power Dissipation
VDD = 5V
0.07
mW
VDD = 10V
0.6
mW
VDD = 15V
2.4
mW
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to
imply that the devices should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical
Characteristics’’ provides conditions for actual device operation.
Note 2: VSS e 0V unless otherwise specified.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: IOH and IOL are tested one output at a time.
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2014 JUN
CD4046B
AC Electrical Characteristics*
Symbol
TA = 25°C, CL = 50 pF
Parameter
Conditions
Min
Typ
Max
Units
VCO SECTION
fo = 10 kHz, R1 = 1 MΩ
R2 = ∞, VCOIN = VDD/2
IDD
Operating Current
VDD = 5V
20
µA
VDD = 10V
90
µA
VDD = 15V
200
µA
C1 = 50 pF, R1 = 10 kΩ,
R2 = ∞, VCOIN = VDD
Maximum Operating Frequency
VDD = 5V
0.4
0.8
MHz
VDD = 10V
0.6
1.2
MHz
VDD = 15V
1.0
1.6
MHz
1
%
1
%
1
%
VDD = 5V
0.12 –0.24
%/ °C
VDD = 10V
0.04 –0.08
%/ °C
VDD = 15V
0.015 –0.03
%/ °C
VDD = 5V
0.06 –0.12
%/ °C
VDD = 10V
0.05 –0.1
%/ °C
VDD = 15V
0.03 –0.06
%/ °C
VDD = 5V
10
MΩ
VDD = 10V
6
10
MΩ
VDD = 15V
106
MΩ
VDD = 5V
50
%
VDD = 10V
50
%
VDD = 15V
50
VDD = 5V
90
200
ns
VDD = 10V
50
100
ns
VDD = 15V
45
80
ns
VCOIN = 2.5V ± 0.3V,
R1 ≥ 10 kΩ, VDD = 5V
Linearity
VCOIN = 5V ± 2.5V,
R1 ≥ 400 kΩ, VDD = 10V
VCOIN = 7.5V ± 5V,
fMAX
R1 ≥ 1 MX, VDD = 15V
%/°C∞1/f. VDD
Temperature-Frequency Stability No
Frequency Offset, fMIN = 0
Frequency Offset, fMIN ≠ 0
VCOIN
VCO
tTHL
tTHL
Input Resistance
Output Duty Cycle
VCO Output Transition Time
R2 = ∞
6
%
*AC Parameters are guaranteed by DC correlated testing.
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2014 JUN
CD4046B
AC Electrical Characteristics*
Symbol
TA e 25°C, CL = 50 pF (Continued)
Parameter
Conditions
Min
Typ
Max
Units
PHASE COMPARATORS SECTION
Input Resistance
Signal Input
Comparator Input
RIN
VDD = 5V
1
3
MΩ
VDD = 10V
0.2
0.7
MΩ
VDD = 15V
0.1
0.3
MΩ
VDD = 5V
106
MΩ
VDD = 10V
106
MΩ
VDD = 15V
106
MΩ
CSERIES = 1000 pF
AC-Coupled Signal Input Voltage
Sensitivity
f = 50 kHz
VDD = 5V
200
400
mV
VDD = 10V
VDD = 15V
400
800
mV
700
1400
mV
RS ≥ 10 kΩ, VDD = 5V
1.50
2.2
V
RS ≥ 10 kΩ, VDD = 10V
1.50
2.2
V
RS ≥ 50 kΩ, VDD = 15V
1.50
2.2
V
DEMODULATOR OUTPUT
Offset Voltage
VCOIN-
RS ≥ 50 kΩ
VDEM
Linearity
VCOIN = 2.5V±0.3V, VDD = 5V
0.1
%
VCOIN = 5V±2.5V, VDD = 10V
0.6
%
VCOIN = 7.5V±5V, VDD = 15V
0.8
%
ZENER DIODE
VZ
Zener Diode Voltage
IZ = 50 µA
RZ
Zener Dynamic Resistance
IZ = 1 mA
6.3
7.0
100
7.7
V
Ω
*AC Parameters are guaranteed by DC correlated testing.
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7 / 15
2014 JUN
CD4046B
Phase Comparator State Diagrams
FIGURE 2
Typical Waveforms
PHASE COMPARATORI
PHASE COMPARATORI
FIGURE 3. Typical Waveform Employing Phase
FIGURE 4. Typical Waveform Employing Phase
Comparator I in Locked Condition
Comparator II in Locked Condition
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2014 JUN
CD4046B
Typical Performance Characteristics
FIGURE 5a
FIGURE 5b
FIGURE 5C
FIGURE 6a
Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, PD (Total) - PD (fo) + PD (fMIN)
+ PD (RS); Phas - Comparator II, PD (Total) - PD (fMIN).
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2014 JUN
CD4046B
Typical Performance Characteristics (Continued)
FIGURE 6b
FIGURE 6c
FIGURE 7. Typical VCO Linearity vs R1 and C1
Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, PD (Total) - PD (fo) + PD (fMIN)
+ PD (RS); Phase Comparator II, PD (Total) - PD (fMIN).
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2014 JUN
CD4046B
Design Information
This information is a guide for approximating the value of external components for the CD4046B in a phase-lockedloop
system. The selected external components must be within the following ranges: R1, R2 ≥ 10 kΩ, RS ≥ 10 kΩ, C1 ≥ 50 pF. In
addition to the given design information, refer to Figure 5 for R1, R2 and C1 component selections.
Using Phase Comparator I
Characteristics
VCO Without Offset
Using Phase Comparator II
VCO With Offset
R2= ∞
VCO Without Offset
VCO With Offset
R2= ∞
VCO Frequency
VCO in PLL system will adjust
to center frequency, fo
For No Signal Input
Frequency Lock
Range, 2 fL
VCO in PLL system will adjust to
lowest operating frequency, fmin
2 fL = full VCO frequency range 2 fL = fmax - fmin
Frequency Capture
2fc ≈
Range, 2 fC
1
2πfL
π
π1
fC = fL
Loop Filter
Component
For 2 fC, see Ref.
Selection
Phase Angle Between
Single and Comparator
90° at center frequency (fo), approximating
0° and 180° at ends of lock range (2 fL)
Always 0° in lock
Locks on Harmonics of
Center Frequency
Yes
No
Signal Input Noise
Rejection
High
Low
VCO Component
Given: fo.
Given: fo and fL.
Given: fmax.
Given：fmin and fmax
Selection
Use fo with Figure 5a to
Calculate fmin
Calculate fo from the
Use fmin with
determine R1 and C1.
from the equation
equation
Figure 5b to
fmin = fo - fL.
fmax
Fo =
Use fmin with Figure 5b
to determine R2 and C1.
Calculate
fmax
fmin
from the equation
fmax
fmin
Use
fmax
fmin
=
2
Use fo with Figure 5a to
determine R1 and C1.
Determine
fmax
fmin
fmax
Use
with Figure 5c
fmin
to determine ration
R2/R1 to obtain R1.
fo + fL.
fo − fL
with Figure 5c
to determine ratio R2/ R1 to
obtain R1.
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CD4046B
Physical Dimensions
DIP-16
B
L1
L
E
D1
d
D
A
c
a
b
Dimensions In Millimeters(DIP-16)
A
B
D
D1
E
L
L1
a
b
c
Min：
6.10
18.94
8.10
7.42
3.10
0.50
3.00
1.50
0.85
0.40
Max：
6.68
19.56
10.9
7.82
3.55
0.70
3.60
1.55
0.90
0.50
Symbol：
d
2.54 BSC
SOP-16
Q
A
C1
C
B
D
A1
a
0.25
b
Dimensions In Millimeters(SOP-16)
A
A1
B
C
C1
D
Min：
1.35
0.05
9.80
5.80
3.80
0.40
0°
0.35
Max：
1.55
0.20
10.0
6.20
4.00
0.80
8°
0.45
Symbol：
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Q
a
b
1.27 BSC
2014 JUN
CD4046B
Physical Dimensions
TSSOP-16
Dimensions In Millimeters(TSSOP-16)
A
A1
B
C
C1
D
Min：
0.85
0.05
4.90
6.20
4.30
0.40
0°
0.20
Max：
0.95
0.20
5.10
6.60
4.50
0.80
8°
0.25
Symbol：
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Q
a
b
0.65 BSC
2014 JUN
CD4046B
Revision History
DATE
REVISION
2014-6-9
New
2023-11-14
Modify the package dimension diagram TSSOP-16、Update encapsulation type、
Update Lead Temperature、Updated DIP-16 dimension、Add annotation for 1、4、12、13
Maximum Ratings、Update DIP Package New Model
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PAGE
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CD4046B
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