PCF8575MS/TR

PCF8575 Remote16-BIT I2C AND SMBus I/O Expander with Interrupt Output Features        I2C to Parallel-Port Expander Open-Drain Interrupt Output Low Standby-Current Consumption of 10μA Max Compatible With Most Micro controllers SSOP-24 400-kHz Fast I2C Bus Address by Three Hardware Address Pins for Use of up to Eight Devices Latched Outputs With High-Current Drive Capability for Directly Driving LEDs    Current Source to VCC for Actively Driving a High at the Output Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model - 200-V Machine Model - 1000-V Charged-Device Model Ordering Information DEVICE PCF8575MS/TR http://www.hgsemi.com.cn Package Type MARKING Packing Packing Qty SSOP-24 PCF8575 REEL 2500pcs/reel 1 / 21 2013 MAR PCF8575 Description This 16-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.5-V to 5.5-V VCC operation. The PCF8575 device provides general-purpose remote I/O expansion for most microcontroller families by way of the I2C interface [serial clock (SCL), serial data (SDA)]. The device features a 16-bit quasi-bidirectional input/output (I/O) port (P07–P00, P17–P10), including latched outputs with high-current drive capability for directly driving LEDs. Each quasi-bidirectional I/O can be used as an input or output without the use of a data-direction control signal. At power on, the I/Os are high. In this mode, only a current source to VCC is active. Applications        Telecom Shelters: Filter Units Servers Routers (Telecom Switching Equipment) Personal Computers Personal Electronics Industrial Automation Products with GPIO-Limited Processors Simplified Schematic http://www.hgsemi.com.cn 2 / 21 2013 MAR PCF8575 Pin Configuration and Functions SSOP-24（Top View） Pin Functions NAME PIN TYPE DESCRIPTION A0 21 I Address input 0. Connect directly to VCC or ground. Pull-up resistors are not needed. A1 2 I Address input 1. Connect directly to VCC or ground. Pull-up resistors are not needed. A2 3 I Address input 2. Connect directly to VCC or ground. Pull-up resistors are not needed. INT 1 O Interrupt output. Connect to VCC through a pull-up resistor. P00 4 I/O P-port input/output. Push-pull design structure. P01 5 I/O P-port input/output. Push-pull design structure. P02 6 I/O P-port input/output. Push-pull design structure. P03 7 I/O P-port input/output. Push-pull design structure. P04 8 I/O P-port input/output. Push-pull design structure. P05 9 I/O P-port input/output. Push-pull design structure. P06 10 I/O P-port input/output. Push-pull design structure. P07 11 I/O P-port input/output. Push-pull design structure. GND 12 — Ground P10 13 I/O P-port input/output. Push-pull design structure. P11 14 I/O P-port input/output. Push-pull design structure. P12 15 I/O P-port input/output. Push-pull design structure. P13 16 I/O P-port input/output. Push-pull design structure. P14 17 I/O P-port input/output. Push-pull design structure. P15 18 I/O P-port input/output. Push-pull design structure. P16 19 I/O P-port input/output. Push-pull design structure. P-port input/output. Push-pull design structure. P17 20 I/O SCL 22 I Serial clock line. Connect to VCC through a pull-up resistor SDA 23 I/O Serial data line. Connect to VCC through a pull-up resistor. VCC 24 — Supply voltage http://www.hgsemi.com.cn 3 / 21 2013 MAR PCF8575 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 VCC + 0.5 V VO Output voltage range –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –20 mA IOK Input/output clamp current VO < 0 or VO > VCC –20 mA IOL Continuous output low current VO = 0 to VCC 50 mA IOH Continuous output high current VO = 0 to VCC –4 mA Continuous current through VCC or GND ±100 mA Storage temperature range 150 °C VCC (2) Tstg 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins V(ESD) Electrostatic discharge UNIT 2000 Charged device model (CDM), per JEDEC specification V 1000 JESD22- C101, all pins Recommended Operating Conditions MIN MAX UNIT 2.5 5.5 V VCC Supply voltage VIH High-level input voltage 0.7 × VCC VCC + 0.5 V VIL Low-level input voltage –0.5 0.3 × VCC V IOH P-port high-level output current –1 mA IOHT P-port transient pullup current –10 mA IOL P-port low-level output current 25 mA TA Operating free-air temperature 85 °C –40 Thermal Information THERMAL METRIC(1) RθJA Junction-to-ambient thermal resistance PCF8575MS UNIT 63 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. http://www.hgsemi.com.cn 4 / 21 2013 MAR PCF8575 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK Input diode clamp voltage II = –18mA VPOR Power-on reset voltage(2) VI = VCC or GND, IO = 0 P port VO = GND P-port transient pullup curren High during ACK, VOH = GND SDA VOL = 0.4 V IOH IOHT IOL P port INT SCL, SDA II A0, A1, A2 IIHL P port Operating mode ΔICC CI Cio Supply current increase SCL SDA P port MIN 2.5 V to 5.5 V -1.2 VPOR TYP(1) MAX V 1.2 2.5 V to 5.5 V -30 2.5 V -0.5 UNIT 1.8 V -300 μA -1 mA 3 VOL = 0.4 V 2.5 V to 5.5 V VOL = 1 V VOL = 0.4 V 5 15 10 25 mA 1.3 VI = VCC or GND 2.5 V to 5.5 V VI ≥ VCC or VI ≤ GND 2.5 V to 5.5 V VI = VCC or GND, IO = 0, fscl = 400 kHz ICC Standby mode VCC VI = VCC or GND, IO = 0, fscl = 0 kHz One input at VCC – 0.6 V, Other inputs at VCC or GND VI = VCC or GND ±1 ±400 5.5 V 100 200 3.6 V 30 75 2.7 V 20 50 5.5 V 2.5 10 3.6 V 2.5 10 2.7 V 2.5 10 2.5 V to 5.5 V 2.5 V to 5.5 V VIO = VCC or GND ±5 2.5 V to 5.5 V μA μA 3 7 pF 3 7 4 10 All typical values are at nominal supply voltage (2.5V, 3.3V, or 5V VCC) and TA = 25°C. (2) The power-on reset circuit resets the I2C bus logic with VCC < VPOR and sets all I/Os to logic high (with current source to VCC). 5 / 21 μA 200 (1) http://www.hgsemi.com.cn μA pF 2013 MAR PCF8575 I2C Interface Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 12) MIN fscl I2C clock frequency MAX UNIT 400 kHz tsch I2C clock high time 0.6 μs tscl I2C clock low time 1.3 μs tsp I2C spike time 50 ns tsds I2C serial data setup time 100 ns tsdh I2C serial data hold time 0 ns ticr I2C input rise time 20+0.1Cb (1) 300 ns ticf I2C input fall time 20+0.1Cb (1) 300 ns tocf I C output fall time 300 ns tbuf I C bus free time between Stop and Start 1.3 μs tsts I C start or repeated Start condition setup 0.6 μs tsth I C start or repeated Start condition hold 0.6 μs 0.6 μs 10-pF to 400-pF bus 2 2 2 2 tsps I C Stop condition setup 2 tvd Valid-data time Cb I C bus capacitive load SCL low to SDA output valid 2 1.2 μs 400 pF Switching Characteristics over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 13 and Figure 14) PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX UNIT tiv Interrupt valid time P port INT 4 μs tir Interrupt reset delay time SCL INT 4 μs tpv Output data valid SCL P port 4 μs tsu Input data setup time P port SCL 0 μs th Input data hold time P port SCL 4 μs http://www.hgsemi.com.cn 6 / 21 2013 MAR PCF8575 Typical Characteristics TA = 25°C (unless otherwise noted) Figure 1. Supply Current vs Temperature Figure 2. Standby Supply Current vs Temperature Figure 3. Supply Current vs Supply Voltage Figure 4. I/O Sink Current vs Output Low Voltage Figure 5. I/O Sink Current vs Output Low Voltage Figure 6. I/O Sink Current vs Output Low Voltage http://www.hgsemi.com.cn 7 / 21 2013 MAR PCF8575 Typical Characteristics(continued) TA = 25°C (unless otherwise noted) Figure 7. I/O Output Low Voltage vs Temperature Figure 8. I/O Source Current vs Output High Voltage Figure 9. I/O Source Current vs Output High Voltage Figure 10. I/O Source Current vs Output High Voltage Figure 11. I/O High Voltage vs Temperature http://www.hgsemi.com.cn 8 / 21 2013 MAR PCF8575 Parameter Measurement Information VOLTAGE WAVEFORMS BYTE DESCRIPTION 1 I2C address 2, 3 P-port data Figure 12. I2C Interface Load Circuit and Voltage Waveforms http://www.hgsemi.com.cn 9 / 21 2013 MAR PCF8575 Parameter Measurement Information(continued) Figure 13. Interrupt Load Circuit and Voltage Waveforms http://www.hgsemi.com.cn 10 / 21 2013 MAR PCF8575 Parameter Measurement Information(continued) Figure 14. P-Port Load Circuits and Voltage Waveforms http://www.hgsemi.com.cn 11 / 21 2013 MAR PCF8575 Detailed Description Overview The PCF8575 provides general-purpose remote I/O expansion for most micro controller families via the I 2C interface serial clock (SCL) and serial data (SDA). The device features a 16-bit quasi-bidirectional input/output (I/O) port (P07–P00, P17–P10), including latched outputs with high-current drive capability for directly driving LEDs. Each quasi-bidirectional I/O can be used as an input or output without the use of a data-direction control signal. At power on, the I/Os are high. In this mode, only a current source (IOH) to VCC is active. An additional strong pullup to VCC (IOHT) allows fast-rising edges into heavily loaded outputs. This device turns on when an output is written high and is switched off by the negative edge of SCL. The I/Os should be high before being used as inputs. After power on, as all the I/Os are set high, all of them can be used as inputs. Any change in setting of the I/Os as either input or outputs can be done with the write mode. If a high is applied externally to an I/O that has been written earlier to low, a large current (IOL) will flow to GND. The PCF8575 provides an open-drain interrupt (INT) output, which can be connected to the interrupt input of a micro controller. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the signal INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the port is changed to the original setting, or data is read from or written to the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal or in the write mode at the ACK bit after the falling edge of the SCL signal. Interrupts that occur during the ACK clock pulse can be lost (or be very short), due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit. This device does not have internal configuration or status registers. Instead, read or write to the device I/Os directly after sending the device address (see Figure 18 and Figure 19). By sending an interrupt signal on this line, the remote I/O can inform the micro controller if there is incoming data on its ports, without having to communicate via the I 2C bus. Thus, the PCF8575 can remain a simple slave device. Every data transmission to or from the PCF8575 must consist of an even number of bytes. The first data byte in every pair refers to port 0 (P07–P00), and the second data byte in every pair refers to port 1 (P17–P10). To write to the ports (output mode), the master first addresses the slave device, setting the last bit of the byte containing the slave address to logic 0. The PCF8575 acknowledges, and the master sends the first data byte for P07–P00. After the first data byte is acknowledged by the PCF8575, the second data byte (P17–P10) is sent by the master. Once again, the PCF8575 acknowledges the receipt of the data, after which this 16-bit data is presented on the port lines. The number of data bytes that can be sent successively is not limited. After every two bytes, the previous data is overwritten. When the PCF8575 receives the pairs of data bytes, the first byte is referred to as P07–P00 and the second byte as P17–P10. The third byte is referred to as P07–P00, the fourth byte as P17–P10, and so on. Before reading from the PCF8575, all ports desired as input should be set to logic 1. To read from the ports (input mode), the master first addresses the slave device, setting the last bit of the byte containing the slave address to logic 1. The data bytes that follow on the SDA are the values on the ports. If the data on the input port changes faster than the master can read, this data may be lost. http://www.hgsemi.com.cn 12 / 21 2013 MAR PCF8575 When power is applied to VCC, an internal power-on reset holds the PCF8575 in a reset state until VCC has reached VPOR. At that time, the reset condition is released, and the device I 2C-bus state machine initializes the bus to its default state. The hardware pins (A0, A1, and A2) are used to program and vary the fixed I 2C address and allow up to eight devices to share the same I 2C bus or SMBus. The fixed I 2C address of the PCF8575 is the same as the PCF8575C, PCF8574, PCA9535, and PCA9555, allowing up to eight of these devices, in any combination, to share the same I 2C bus or SMBus. http://www.hgsemi.com.cn 13 / 21 2013 MAR PCF8575 Functional Block Diagram Logic Diagram (Positive Logic) Simplified Schematic Diagram of Each P-Port Input/Output http://www.hgsemi.com.cn 14 / 21 2013 MAR PCF8575 Feature Description I2C Interface The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on the SDA input/output while the SCL input is high (see Figure 15). After the Start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/W). This device does not respond to the general call address. After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output during the high of the ACK-related clock pulse. The address inputs (A2–A0) of the slave device must not be changed between the Start and Stop conditions. The data byte follows the address ACK. If the R/W bit is high, the data from this device are the values read from the P port. If the R/W bit is low, the data are from the master, to be output to the P port. The data byte is followed by an ACK sent from this device. If other data bytes are sent from the master, following the ACK, they are ignored by this device. Data are output only if complete bytes are received and acknowledged. The output data is valid at time (tpv) after the low-to-high transition of SCL, during the clock cycle for the ACK. On the I 2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop) (see Figure 16). A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 15). The number of data bytes transferred between the Start and Stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. A slave receiver that is addressed must generate an ACK after the reception of each byte. Also, a master must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 17). Setup and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after the last byte that has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition. Figure 15. Definition of Start and Stop Conditions http://www.hgsemi.com.cn 15 / 21 2013 MAR PCF8575 Feature Description (continued) Figure 16. Bit Transfer Figure 17. Acknowledgment on I2C Bus Interface Definition BYTE BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) I2C slave address L H L L A2 A1 A0 R/W P0x I/O data bus P07 P06 P05 P04 P03 P02 P01 P00 P1x I/O data bus P17 P16 P15 P14 P13 P12 P11 P10 http://www.hgsemi.com.cn 16 / 21 2013 MAR PCF8575 Address Reference INPUTS I2C BUS SLAVE 8-BIT READ ADDRESS I2C BUS SLAVE 8- BIT WRITE ADDRESS A2 A1 A0 L L L 65 (decimal), 41 (hexadecimal) 64 (decimal), 40 (hexadecimal) L L H 67 (decimal), 43 (hexadecimal) 66 (decimal), 42 (hexadecimal) L H L 69 (decimal), 45 (hexadecimal) 68 (decimal), 44 (hexadecimal) L H H 71 (decimal), 47 (hexadecimal) 70 (decimal), 46 (hexadecimal) H L L 73 (decimal), 49 (hexadecimal) 72 (decimal), 48 (hexadecimal) H L H 75 (decimal), 4B (hexadecimal) 74 (decimal), 4A (hexadecimal) H H L 77 (decimal), 4D (hexadecimal) 76 (decimal), 4C (hexadecimal) H H H 79 (decimal), 4F (hexadecimal) 78 (decimal), 4E (hexadecimal) Device Functional Modes Figure 18 and Figure 19 show the address and timing diagrams for the write and read modes, respectively. Figure 18. Write Mode (Output) http://www.hgsemi.com.cn 17 / 21 2013 MAR PCF8575 Device Functional Modes (continued) Figure 19. Read Mode (Input) http://www.hgsemi.com.cn 18 / 21 2013 MAR PCF8575 Typical Application The SCL and SDA pins must be tied directly to VCC because if SCL and SDA are tied to an auxiliary power supply that could be powered on while VCC is powered off, then the supply current, ICC, will increase as a result. A. Device address is configured as 0100000 for this example. B. P0, P2, and P3 are configured as outputs. C. P1, P4, and P5 are configured as inputs. D. P6 and P7 are not used and must be configured as outputs. Figure 20. Application Schematic http://www.hgsemi.com.cn 19 / 21 2013 MAR PCF8575 Physical Dimensions SSOP24 A Q C1 C B D A1 a 0.25 b Dimensions In Millimeters(SSOP24) A A1 B C C1 D Q a b Min： 1.30 0.10 8.55 5.80 3.80 0.50 0° 0.23 0.63 Max： 1.50 0.25 8.75 6.20 4.00 0.80 8° 0.31 TYP Symbol： http://www.hgsemi.com.cn 20 / 21 2013 MAR PCF8575 IMPORTANT STATEMENT: Huaguan Semiconductor reserves the right to change its products and services without notice. Before ordering, the customer shall obtain the latest relevant information and verify whether the information is up to date and complete. Huaguan Semiconductor does not assume any responsibility or obligation for the altered documents. Customers are responsible for complying with safety standards and taking safety measures when using Huaguan Semiconductor products for system design and machine manufacturing. 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You should fully compensate Huaguan Semiconductor and its agents for any claims, damages, costs, losses and debts caused by the use of these resources. Huaguan Semiconductor accepts no liability for any loss or damage caused by infringement. http://www.hgsemi.com.cn 21 / 21 2013 MAR