XBLW SN74HC/HCT165
8-bit Parallel-in, Serial out Shift Register
General Description
The SN74HC/HCT165 is 8-bit serial or parallel-in/serial-out shift registers. The device features a serial data input
—
(DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel
—
load input ( PL) is LOW the data from D0 to D7 is loaded into the shift register
—
asynchronously. When PL is HIGH data enters the register serially at DS. When the clock enable input (
—
—
CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on CE will disable the CP
input. Inputs are overvoltage tolerant to 15V. This enables the device to be used in HIGH-to-LOW level shifting
applications.
Features
Input levels:
For SN74HC165: CMOS level
For SN74HCT165: TTL level
Asynchronous 8-bit parallel load
Synchronous serial input
Specified from -40℃ to +85℃
Packaging information: DIP16/SOP16/TSSOP16
Ordering Information
DEVICE
SN74HC165N
SN74HC165DTR
SN74HCT165DTR
SN74HCT165TDTR
XBLWversion1.0
Package Type
DIP-16
SOP-16
SOP-16
TSSOP-16
MARKING
Packing
Packing QTY
74HC165N
74HC165
74HCT165
74HCT165
Tube
Tape
Tape
Tape
1000/Box
2500/Reel
2500/Reel
3000/Reel
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第 1 页 共 18 页
XBLW SN74HC/HCT165
8-bit Parallel-in, Serial out Shift Register
2 、Block Diagram And Pin Description
2.1
Block Diagram
Figure 1. Logic symbol
Figure 2. Functional diagram
Figure 3. Functional diagram
XBLWversion1.0
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第 2 页 共 18 页
XBLW SN74HC/HCT165
8-bit Parallel-in, Serial out Shift Register
Figure 4. Timing diagram
2.2
Pin Configurations
XBLWversion1.0
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第 3 页 共 18 页
XBLW SN74HC/HCT165
8-bit Parallel-in, Serial out Shift Register
2.3 Pin Description
Pin No.
Pin Name
Description
1
PL
—
asynchronous parallel load input (active LOW)
2
3
4
5
6
CP
D4
D5
D6
D7
clock input ( LOW- to- HIGH, edge- triggered)
7
—
Q7
complementary output from the last stage
8
9
10
11
12
13
14
GND
Q7
DS
D0
D1
D2
D3
ground ( 0 V)
15
—
CE
clock enable input (active LOW)
16
VCC
supply voltage
parallel data input ( also referred to as Dn)
parallel data input ( also referred to as Dn)
parallel data input ( also referred to as Dn)
parallel data input ( also referred to as Dn)
serial output from the last stage
serial data input
parallel data input ( also referred to as Dn)
parallel data input ( also referred to as Dn)
parallel data input ( also referred to as Dn)
parallel data input ( also referred to as Dn)
2.4 Function Table
Operating
mode
parallel load
serial shift
Input
PL
CE
CP
DS
D0 to D7
Q0
Q1 to Q6
Q7
Q7
L
L
X
X
X
X
X
X
L
H
L
H
L to L
H to H
L
H
H
L
H
L
t
l
X
L
q0 to q5
q6
—
H
q0 to q5
q6
—
L
q0 to q5
q6
—
H
q0 to q5
q6
—
q0
q1 to q6
q7
—
q0
q1 to q6
q7
—
H
H
H
hold "do
nothing"
Output
Qn register
—
—
H
H
t
L
t
L
t
L
H
X
X
H
h
l
h
X
X
X
X
X
X
X
—
q6
q6
q6
q6
q7
q7
Note: H= HIGH voltage level;
h=HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L=LOW voltage level; t=LOW-to-HIGH clock transition;
l=LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q=state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X=don’t care;
t=LOW-to-HIGH clock transition.
XBLWversion1.0
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第 4 页 共 18 页
XBLW SN74HC/HCT165
8-bit Parallel-in, Serial out Shift Register
3 、Electrical Parameter
3.1
Absolute Maximum Ratings
Symbol
Parameter
supply voltage
VCC
input clamping
current
output clamping
current
output current
supply current
ground current
total power
dissipation
storage
temperature
soldering
temperature
-
Min.
-0.5
Max.
+7
Unit
V
IIK
VI < -0.5V or VI > VCC+0.5V
-
±20
mA
IOK
VO < -0.5V or VO > VCC+0.5V
-
±20
mA
IO
ICC
IGND
-0.5V < VO < VCC+0.5V
-
-50
±25
50
-
mA
mA
mA
Ptot
-
-
500
mW
Tstg
-
-65
+150
℃
TL
Conditions
DIP
SOP
10s
℃
℃
245
250
(Voltages are referenced to GND (ground=0V), unless otherwise specified.)
Note:
[1] For DIP16 packages: above 70℃ the value ofPtot derates linearly with 12mW/K.
[2] For SOP16 packages: above 70℃ the value ofPtot derates linearly with 8mW/K.
[3] For (T)SSOP16 packages: above 60℃ the value ofPtot derates linearly with 5.5mW/K.
3.2
Recommended Operating Conditions
Symbol
Parameter
supply voltage
input voltage
output voltage
VCC
VI
VO
input transition
rise and fall rate
Δt/ΔV
ambient
temperature
Tamb
supply voltage
input voltage
output voltage
VCC
VI
VO
input transition
rise and fall rate
Δt/ΔV
ambient
temperature
Tamb
XBLWversion1.0
Conditions
SN74HC165
Min.
Typ.
Max.
Unit
VCC=2.0V
VCC=4.5V
VCC=6.0V
2.0
0
0
5.0
-
6.0
VCC
VCC
625
139
83
V
V
V
ns/V
ns/V
ns/V
-
-40
-
+85
℃
VCC=2.0V
VCC=4.5V
VCC=6.0V
4.5
0
0
5.0
5.5
VCC
VCC
-
-40
-
1.67
SN74HCT165
-
-
-
V
V
V
ns/V
ns/V
ns/V
-
+85
℃
1.67
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139
第 5 页 共 18 页
XBLW SN74HC/HCT165
8-bit Parallel-in, Serial out Shift Register
3.3
Electrical Characteristics
3.3.1 DC Characteristics 1
( Tamb=2 5 C, voltages are referenced to GND ( ground=0 V), unless otherwise specified.)
Symbol
Parameter
Conditions
Min.
Typ.
SN74HC165
VCC=2.0V
1.5
1.2
HIGH-level
V
=4.5V
3.15
2.4
CC
V
IH
input voltage
VCC=6.0V
4.2
3.2
VCC=2.0V
0.8
LOW-level
V
=4.5V
CC
2.1
V
IL
input voltage
VCC=6.0V
2.8
IO=-20uA; VCC=2.0V
1.9
2.0
IO=-20uA; VCC=4.5V
4.4
4.5
HIGH-level
VI = VIH or VIL
IO=-20uA; VCC=6.0V
5.9
6.0
VOH
output voltage
IO=-4.0mA; VCC=4.5V
3.98
4.32
IO=-5.2mA; VCC=6.0V
5.48
5.81
IO=20uA; VCC=2.0V
0
IO=20uA; VCC=4.5V
0
LOW-level
I
=20uA;
V
=6.0V
V
=
V
or
V
O
CC
I
IH
IL
0
V
OL
output voltage
IO=4.0mA; VCC=4.5V
0.15
IO=5.2mA; VCC=6.0V
0.16
input leakage
current
II
supply current
ICC
input
capacitance
CI
Max.
Unit
0.5
1.35
1.8
0.1
0.1
0.1
0.26
0.26
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VI= VCC or GND;
VCC= 6.0 V
-
-
±0. 1
uA
VCC= 6 . 0 V
-
-
8
uA
-
-
3.5
-
pF
VI= VCC or GND; IO= 0 A;
SN74HCT165
HIGH- level
input voltage
LOW- level
input voltage
VIH
VCC=4.5V to 5.5V
2.0
1.6
-
V
VIL
VCC=4.5V to 5.5V
-
1.2
0.8
V
4.4
3.98
-
4.5
4.32
0
0.16
0.1
0.26
V
V
V
V
-
-
±0. 1
uA
-
-
8.0
uA
-
35
126
uA
CP, CE, and PL inputs
-
65
234
uA
-
-
3.5
-
pF
HIGH-level
output voltage
VOH
VI = VIH or VIL ;
VCC= 4 . 5 V
LOW-level
output voltage
VOL
VI = VIH or VIL
input leakage
current
II
supply current
ICC
VI= VCC or GND;
VCC= 6.0 V
VI= VCC or GND; IO= 0 A;
VCC= 6.0 V
per input pin;
VI= VCC-2 . 1 V;
additional
supply current
ΔICC
input
capacitance
CI
XBLWversion1.0
IO=-20uA
IO=-4.0mA
IO=20uA; VCC=4.5V
IO=5.2mA; VCC=6.0V
other inputs at VCC
or GND;
VCC=4.5 V to 5.5V
Dn and DS inputs
—
—
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第 6 页 共 18 页
XBLW SN74HC/HCT165
8-bit Parallel-in, Serial out Shift Register
3.3.2 DC Characteristics 2
(Tamb=-40C to +85C, voltages are referenced to GND (ground=0V), unless otherwise specified.)
Symbol
Parameter
Conditions
Min.
Typ. Max. Unit
SN74HC165
VCC=2.0V
1.5
V
HIGH-level
VCC=4.5V
3.15
V
VIH
input voltage
VCC=6.0V
4.2
V
VCC=2.0V
0.5
V
LOW-level
VCC=4.5V
1.35
V
VIL
input voltage
VCC=6.0V
1.8
V
IO=-20uA; VCC=2.0V
1.9
V
IO=-20uA; VCC=4.5V
4.4
V
HIGH-level
VI = VIH or VIL
IO=-20uA; VCC=6.0V
5.9
V
VOH
output voltage
IO=-4.0mA; VCC=4.5V
3.84
V
IO=-5.2mA; VCC=6.0V
5.34
V
IO=20uA; VCC=2.0V
0.1
V
IO=20uA; VCC=4.5V
0.1
V
LOW-level
IO=20uA; VCC=6.0V
VI = VIH or VIL
0.1
V
VOL
output voltage
IO=4.0mA; VCC=4.5V
0.33
V
IO=5.2mA; VCC=6.0V
0.33
V
input leakage
current
II
supply current
ICC
HIGH- level
input voltage
LOW- level
input voltage
VI= VCC or GND;
VCC= 6.0 V
VI= VCC or GND; IO= 0 A;
VCC= 6.0 V
SN74HCT165
±1
uA
-
-
80
uA
VCC=4.5V to 5.5V
2.0
-
-
V
VIL
VCC=4.5V to 5.5V
-
-
0.8
V
4.4
3.84
-
-
0.1
0.33
V
V
V
V
-
-
±1
uA
-
-
80
uA
-
-
157.5
uA
-
-
292.5
uA
VOH
VI = VIH or VIL ;
VCC= 4 . 5 V
LOW-level
output voltage
VOL
VI = VIH or VIL
input leakage
current
II
supply current
ICC
XBLWversion1.0
-
VIH
HIGH-level
output voltage
additional
supply current
-
ΔICC
IO=-20uA
IO=-4.0mA
IO=20uA; VCC=4.5V
IO=5.2mA; VCC=6.0V
VI= VCC or GND;
VCC= 6.0 V
VI= VCC or GND; IO= 0 A;
VCC= 6 . 0 V
per input pin;
Dn and DS inputs
VI= VCC-2 . 1 V;
other inputs at VCC
or GND;
VCC=4.5V to 5.5V
—
—
CP, CE, and PL inputs
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第 7 页 共 18 页
XBLW SN74HC/HCT165
8-bit Parallel-in, Serial out Shift Register
3.3.3 DC Characteristics 3
(Tamb=25℃, GND=0V, CL=50pf, unless otherwise specified.)
Symbol
Parameter
Conditions
SN74HC165
VCC=2.0V
—
—
VCC=4.5V
CP, CE to Q7, Q7;
VCC=5.0V;CL=15pF
see Figure 6
propagation
delay
—
—
PL to Q7, Q7;
see Figure 7
tpd
—
D7 to Q7, Q7;
see Figure 8
transition time
pulse width
—
Q7 , Q7 output;
see Figure 6
tt
tW
CP input HIGH or
LOW;
see Figure 6
—
PL input LOW;
see Figure 7
recovery time
—
—
PL to CP, CE;
see Figure 7
trec
—
DS to CP, CE;
see Figure 9
—
set-up time
tsu
CE to CP and CP to
—
CE;
see Figure 9
—
Dn to PL;
see Figure 1 0
—
hold time
th
DS to CP, CE and
—
Dn to PL;
see Figure 9
—
CE to CP and CP to
—
CE;
see Figure 9
maximum
frequency
XBLWversion1.0
f max
CP input;
see Figure 6
Min.
Typ.
Max.
Unit
80
16
14
80
16
14
100
20
17
80
16
14
80
16
14
80
16
14
5
5
5
5
5
5
6
30
52
19
16
15
50
18
15
14
36
13
11
10
19
7
6
17
6
5
14
5
4
22
8
6
11
4
3
17
6
5
22
8
6
2
2
2
- 17
-6
-5
17
51
165
33
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=5.0V;CL=15pF
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=5.0V;CL=15pF
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
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28
165
33
28
120
24
20
75
15
13
-
第 8 页 共 18 页
XBLW SN74HC/HCT165
8-bit Parallel-in, Serial out Shift Register
VCC=5.0V;CL=15pF
VCC=6.0V
power
dissipation
capacitance
35
56
61
-
MHz
MHz
per package;
VI= GND to VCC
-
35
-
pF
SN74HCT165
VCC=4.5V
CP, CE to Q7, Q7;
VCC=5.0V;CL=15pF
see Figure 6
-
34
ns
ns
-
17
14
20
17
14
11
VCC=4.5V
-
VCC=4.5V
CPD
—
propagation
delay
—
7
15
ns
16
6
-
ns
VCC=4.5V
20
9
-
ns
VCC=4.5V
20
8
-
ns
VCC=4.5V
20
2
-
ns
VCC=4.5V
20
7
-
ns
VCC=4.5V
20
10
-
ns
VCC=4.5V
7
-1
-
ns
CE;
see Figure 9
VCC=4.5V
0
-7
-
ns
CP input;
see Figure 6
VCC=4.5V
VCC=5.0V;CL=15pF
26
-
44
48
-
MHz
MHz
-
35
-
pF
—
D7 to Q7, Q7;
see Figure 8
transition time
pulse width
recovery time
—
Q7 , Q7 output;
tt
see Figure 6
CP input;
see Figure 6
tW
—
PL input;
see Figure 7
—
—
PL to CP, CE;
see Figure 7
trec
40
-
—
PL to Q7, Q7;
see Figure 7
tpd
VCC=4.5V
VCC=5.0V;CL=15pF
VCC=4.5V
VCC=5.0V;CL=15pF
ns
ns
ns
ns
—
—
DS to CP, CE;
see Figure 9
28
—
set-up time
tsu
CE to CP and CP to
—
CE;
see Figure 9
—
Dn to PL;
see Figure 1 0
—
hold time
th
DS to CP, CE and
—
Dn to PL;
see Figure 9
—
CE to CP and CP to
—
maximum
frequency
f max
power
dissipation
capacitance
CPD
per package;
VI= GND to VCC- 1.5V
Note:
[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTHL and tTLH .
[3] CPD is used to determine the dynamic power dissipation (PD in uW).
PD=(CPD ×VCC2 ×fi ×N)+∑(CL ×VCC2 ×fo) where:
fi=input frequency in MHz;
fo=output frequency in MHz;
CL=output load capacitance in pF;
VCC=supply voltage in V;
N=number of inputs switching;
∑(CL ×VCC2 ×fo)=sum of outputs.
XBLWversion1.0
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第 9 页 共 18 页
XBLW SN74HC/HCT165
8-bit Parallel-in, Serial out Shift Register
3.3.4 AC Characteristics 2
(Tamb=-40℃ to +85℃, GND=0V, CL=50pf, unless otherwise specified.)
Parameter
Symbol
propagation
delay
tpd
transition time
tt
pulse width
tW
recovery time
trec
set-up time
tsu
hold time
th
XBLWversion1.0
Conditions
SN74HC165
VCC=2.0V
—
—
CP, CE to Q7, Q7;
VCC=4.5V
see Figure 6
VCC=6.0V
VCC=2.0V
—
—
PL to Q7, Q7;
VCC=4.5V
see Figure 7
VCC=6.0V
VCC=2.0V
—
D7 to Q7, Q7;
VCC=4.5V
see Figure 8
VCC=6.0V
VCC=2.0V
—
Q7 , Q7 output;
VCC=4.5V
see Figure 6
VCC=6.0V
VCC=2.0V
CP input HIGH or
VCC=4.5V
LOW;
see Figure 6
VCC=6.0V
VCC=2.0V
—
PL input LOW;
VCC=4.5V
see Figure 7
VCC=6.0V
VCC=2.0V
—
—
PL to CP, CE;
VCC=4.5V
see Figure 7
VCC=6.0V
VCC=2.0V
—
DS to CP, CE;
VCC=4.5V
see Figure 9
VCC=6.0V
—
VCC=2.0V
CE to CP and CP to
—
VCC=4.5V
CE;
VCC=6.0V
see Figure 9
VCC=2.0V
—
Dn to PL;
VCC=4.5V
see Figure 1 0
VCC=6.0V
—
VCC=2.0V
DS to CP, CE and
—
VCC=4.5V
Dn to PL;
VCC=6.0V
see Figure 9
—
VCC=2.0V
CE to CP and CP to
—
VCC=4.5V
CE;
VCC=6.0V
see Figure 9
Min.
Typ.
Max.
Unit
100
20
17
100
20
17
125
25
21
100
20
17
100
20
17
100
20
17
5
5
5
5
5
5
-
205
41
35
205
41
35
150
30
26
95
19
16
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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第 10 页 共 18 页
XBLW SN74HC/HCT165
8-bit Parallel-in, Serial out Shift Register
maximum
frequency
VCC=2.0V
VCC=4.5V
VCC=6.0V
SN74HCT165
f max
—
—
CP, CE to Q7, Q7;
see Figure 6
propagation
delay
—
—
PL to Q7, Q7;
see Figure 7
tpd
—
D7 to Q7, Q7;
see Figure 8
transition time
pulse width
recovery time
5
24
28
-
-
MHz
MHz
MHz
VCC=4.5V
-
-
43
ns
VCC=4.5V
-
-
50
ns
VCC=4.5V
-
-
35
ns
VCC=4.5V
-
-
19
ns
VCC=4.5V
20
-
-
ns
VCC=4.5V
25
-
-
ns
VCC=4.5V
25
-
-
ns
VCC=4.5V
25
-
-
ns
VCC=4.5V
25
-
-
ns
VCC=4.5V
25
-
-
ns
VCC=4.5V
9
-
-
ns
VCC=4.5V
0
-
-
ns
VCC=4.5V
21
-
-
MHz
CP input;
see Figure 6
—
Q7 , Q7 output;
tt
see Figure 6
CP input;
see Figure 6
tW
—
PL input;
see Figure 7
—
—
PL to CP, CE;
see Figure 7
trec
—
DS to CP, CE;
see Figure 9
—
set-up time
tsu
CE to CP and CP to
—
CE;
see Figure 9
—
Dn to PL;
see Figure 1 0
—
DS to CP, CE and
—
hold time
th
Dn to PL;
see Figure 9
—
CE to CP and CP to
—
maximum
frequency
Note:
f max
CE;
see Figure 9
CP input;
see Figure 6
[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTHL and tTLH .
[3] CPD is used to determine the dynamic power dissipation (PD in uW).
PD=(CPD ×VCC2 ×fi ×N)+∑(CL ×VCC2 ×fo) where:
fi=input frequency in MHz;
fo=output frequency in MHz;
CL=output load capacitance in pF;
VCC=supply voltage in V;
N=number of inputs switching;
∑(CL ×VCC2 ×fo)=sum of outputs.
XBLWversion1.0
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第 11 页 共 18 页
XBLW SN74HC/HCT165
8-bit Parallel-in, Serial out Shift Register
4 、Testing Circuit
4.1 AC Testing Circuit
Figure 5. Test circuit for measuring switching times
Definitions for test circuit:
CL=load capacitance including jig and probe capacitance.
RT=termination resistance should be equal to the output impedance Zo of the pulse generator. RL=Load
resistance.
S1=Test selection switch.
4.2 AC Testing Waveforms
—
—
Figure 6. The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the
maximum clock frequency and the output transition times
XBLWversion1.0
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XBLW SN74HC/HCT165
8-bit Parallel-in, Serial out Shift Register
—
—
Figure 7. The parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the
—
parallel load to clock (CP) and clock enable (CE) recovery time
—
—
Figure 8. The data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW
—
Figure 9. The set-up and hold times from the serial data input (DS) to the clock (CP) and clock enable (CE) inputs,
—
from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the clock
—
enable input (CE)
XBLWversion1.0
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XBLW SN74HC/HCT165
8-bit Parallel-in, Serial out Shift Register
—
Figure 10. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL)
4.3
Measurement Points
Input
Type
VI
VCC
3V
SN74 HC16 5
SN7 4 HCT1 6 5
4.4
Test Data
Type
SN74 HC16 5
SN7 4 HCT1 6 5
XBLWversion1.0
VM
0.5×VCC
1.3V
Input
VI
VCC
3.0V
Output
VM
0.5×VCC
1.3V
S1 position
Load
tr , tf
6.0ns
6.0ns
CL
15pF, 50pF
15pF, 50pF
RL
1kΩ
1kΩ
tPHL, tPLH
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open
open
第 14 页 共 18 页
XBLW SN74HC/HCT165
8-bit Parallel-in, Serial out Shift Register
5 、Package Information
5.1 DIP16
XBLWversion1.0
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第 15 页 共 18 页
XBLW SN74HC/HCT165
8-bit Parallel-in, Serial out Shift Register
5.2、SOP16
XBLWversion1.0
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第 16 页 共 18 页
XBLW SN74HC/HCT165
8-bit Parallel-in, Serial out Shift Register
5.3,TSSOP16
XBLWversion1.0
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第 17 页 共 18 页
XBLW SN74HC/HCT165
8-bit Parallel-in, Serial out Shift Register
Statement：
Shenzhen xinbole electronics co., ltd. reserves the right to change the product specifications, without notice!
Before placing an order, the customer needs to confirm whether the information obtained is the latest version,
and verify the integrity of the relevant information.
Any semiconductor product is liable to fail or malfunction under certain conditions, and the buyer shall be
responsible for complying with safety standards in the system design and whole machine manufacturing using
Shenzhen xinbole electronics co., ltd products, and take appropriate security measures to avoid the potential risk
of failure may result in personal injury or property losses of the situation occurred!
Product performance is never ending, Shenzhen xinbole electronics co., ltd will be dedicated to provide
customers with better performance, better quality of integrated circuit products.
XBLWversion1.0
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