XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
General Description
The SN74HC/HCT192 is a synchronous BCD up/down counter. Separate up/down clocks, CPU and CPD
respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either
clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed
while CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at any time to
guarantee predictable behavior. The device can be cleared at any time by the asynchronous master reset input (MR); it
may also be loaded in parallel by activating the asynchronous parallel load input (P�).
The terminal count up (T�U) and terminal count down (T�D) outputs are normally HIGH. When the circuit has
reached the maximum count state of 15, the next HIGH-to-LOW transition of CPU will cause T�U to go LOW. T�U
will stay LOW until CPU goes HIGH again, duplicating the count up clock Likewise, the T�D output will go LOW
when the circuit is in the zero state and the CPD goes LOW. The terminal count outputs can be used as the clock input
signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. Multistage
counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added.
The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the
parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the
conditions of the clock inputs when the parallel load (P�) input is LOW. A HIGH level on the master reset (MR) input
will disable the parallel load gates, override both clock inputs and set all outputs (Q0 to Q3) LOW. If one of the clock
inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be
interpreted as a legitimate signal and will be counted. Inputs include clamp diodes. This enables the use of current
limiting resistors to interface inputs to voltages in excess of VCC.
Features
Input levels:
For SN74HC192: CMOS level
For SN74HCT192: TTL level
Synchronous reversible counting
Asynchronous parallel load
Asynchronous reset
Expandable without external logic
Specified from -40℃ to +85℃
Packaging information: DIP16/SOP16/TSSOP16
XBLW version 1.0
文档仅供参考，实际应用测试为准
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第 1 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
ORDERING INFORMATION
DEVICE
Package Type
MARKING
Packing
Packing QTY
SN74HC192N
SN74HC192DTR
SN74HCT192DTR
SN74HCT192TDTR
DIP-16
SOP-16
SOP-16
TSSOP-16
74HC192N
74HC192
74HCT192
74HCT192
Tube
Tape
Tape
Tape
1000/Box
2500/Reel
2500/Reel
3000/Reel
Block Diagram And Pin Description
Block Diagram
Figure 1. Logic symbol
Figure 2. IEC Logic symbol
Figure 3. Functional diagram
Figure 4. Logic diagram
XBLW version 1.0
文档仅供参考，实际应用测试为准
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第 2 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
Figure 5. Typical clear, load and count sequence
Pin Configurations
XBLW version 1.0
文档仅供参考，实际应用测试为准
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第 3 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
Pin Description
Pin No.
Pin Name
Description
1
D1
2
Q1
3
Q0
4
CPD
5
CPU
6
Q2
7
Q3
8
GND
9
D3
10
D2
11
P�
12
T�U
13
T�D
14
MR
15
D0
16
VCC
Note: CPD, CPU is LOW-to-HIGH, edge triggered.
data input 1
flip-flop output 1
flip-flop output 0
count down clock input
count up clock input
flip-flop output 2
flip-flop output 3
ground(0V)
data input 3
data input 2
asynchronous parallel load input(active LOW)
terminal count up (carry)output(active LOW)
terminal count down (borrow)output(active LOW)
asynchronous master reset input(active HIGH)
data input 0
supply voltage
Function Table
Operating
mode
reset (clear)
parallel load
count up
count down
Note:
MR
H
H
L
L
L
L
L
L
P�
X
X
L
L
L
L
H
H
CPU
X
X
X
X
L
H
个
H
Input
CPD
D0
L
X
H
X
L
L
H
L
X
H
X
H
H
X
↑
X
D1
X
X
L
L
X
X
X
X
D2
X
X
L
L
X
X
X
X
D3
X
X
L
L
H
H
X
X
Output
Q0 Q1 Q2 Q3 T�U
L
I
L
L
H
I
L
L
L
H
L
L
L
L
H
L
I
L
L
H
Qn=Dn
L
Qn=Dn
H
count up
H
count down
H
T�D
L
H
L
H
H
H
H
H
[1] H=HIGH voltage level; L=LOW voltage level; X=don’t care; ↑=LOW-to-HIGH transition.
[2] T�U=CPU at terminal count up (HLLH).
[3] T�D=CPD at terminal count down (LLLL).
XBLW version 1.0
文档仅供参考，实际应用测试为准
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第 4 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
Electrical Parameter
Absolute Maximum Ratings (Voltages are referenced to GND (ground=0V), unless otherwise specified.)
Parameter
Symbol
Conditions
Min.
Max.
Unit
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VCC
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
-0.5
-65
-
+7.0
±20
±20
±25
50
-50
+150
500
V
mA
mA
mA
mA
mA
℃
mW
soldering temperature
TL
VI < -0.5V or VI > VCC+0.5V
VO < -0.5V or VO > VCC+0.5V
VO=-0.5V to (VCC+0.5V)
DIP
10s
SOP
245
250
℃
Note:
[1] For DIP16 packages: above 70℃ the value of Ptot derates linearly with 12mW/K.
[2] For SOP16 packages: above 70℃ the value of Ptot derates linearly with 8mW/K.
[3] For (T)SSOP16 packages: above 60℃ the value of Ptot derates linearly with 5.5mW/K.
Recommended Operating Conditions
Parameter
Symbol
supply voltage
input voltage
output voltage
VCC
VI
VO
input transition
rise and fall rate
Δt/ΔV
ambient temperature
Tamb
supply voltage
input voltage
output voltage
VCC
VI
VO
input transition
rise and fall rate
Δt/ΔV
ambient temperature
Tamb
XBLW version 1.0
Conditions
SN74HC192
VCC=2.0V
VCC=4.5V
VCC=6.0V
SN74HCT192
VCC=2.0V
VCC=4.5V
VCC=6.0V
-
Min.
Typ.
Max.
Unit
2.0
0
0
-40
5.0
1.67
-
6.0
VCC
VCC
625
139
83
+85
V
V
V
ns/V
ns/V
ns/V
℃
4.5
0
0
-40
5.0
1.67
-
5.5
VCC
VCC
139
+85
V
V
V
ns/V
ns/V
ns/V
℃
文档仅供参考，实际应用测试为准
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第 5 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
Electrical Characteristics
DC Characteristics 1 (Tamb=25℃, voltages are referenced to GND (ground=0V), unless otherwise specified.)
Parameter
Symbol
Conditions
HIGH-level
input voltage
VIH
LOW-level
input voltage
VIL
HIGH-level
output voltage
VOH
VI=VIH or VIL
LOW-level
output voltage
VOL
VI=VIH or VIL
SN74HC192
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
IO=-20uA;VCC=2.0V
IO=-20uA;VCC=4.5V
IO=-20uA;VCC=6.0V
IO=-4.0mA;VCC=4.5V
IO=-5.2mA;VCC=6.0V
IO=20uA;VCC=2.0V
IO=20uA;VCC=4.5V
IO=20uA;VCC=6.0V
IO=4.0mA;VCC=4.5V
IO=5.2mA;VCC=6.0V
Min.
Typ.
Max.
Unit
1.5
3.15
4.2
1.9
4.4
5.9
3.98
5.48
-
1.2
2.4
3.2
0.8
2.1
2.8
2.0
4.5
6.0
4.32
5.81
0
0
0
0.15
0.16
0.5
1.35
1.8
0.1
0.1
0.1
0.26
0.26
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
input leakage
current
supply current
II
VI=Vcc or GND;VCC=6.0V
-
-
±0.1
μA
ICC
VI=VCC or GND;IO=0A;VCC=6.0V
-
-
8.0
μA
input apacitance
CI
SN74HCT192
-
3.5
-
pF
VIH
VCC=4.5V to 5.5V
2.0
1.6
-
V
VIL
VCC=4.5V to 5.5V
-
1.2
0.8
V
4.4
3.98
-
4.5
4.32
0
0.15
0.1
0.26
V
V
V
V
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
LOW-level
output voltage
input leakage
current
supply current
Additional
Supply currend
input apacitance
XBLW version 1.0
VOH
VI=VIH or VIL
VCC=4.5V
VOL
VI=VIH or VIL
VCC=4.5V
IO=-20uA
IO=-4.0uA
IO=20uA
IO=4.0uA
II
VI=Vcc or GND;VCC=5.5V
-
-
±0.1
μA
ICC
VI=VCC or GND;IO=0A;VCC=5.5V
-
-
8.0
μA
pin Dn
-
35
126
μA
pins CPU,CPD
-
140
504
μA
pin P�
-
65
234
μA
pin MR
-
105
378
μA
-
3.5
-
pF
ΔICC
CI
per input pin;
VI=VCC-2.1V;
other inputs at VCC
or GND;IO=0V;
VCC=4.5V to 5.5V
-
文档仅供参考，实际应用测试为准
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第 6 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
DC Characteristics 2
(Tamb=-40℃ to +85℃, voltages are referenced to GND (ground=0V), unless otherwise specified.)
Parameter
Symbol
Conditions
HIGH-level
input voltage
VIH
LOW-level
input voltage
VIL
HIGH-level
output voltage
VOH
VI=VIH or VIL
LOW-level
output voltage
VOL
VI=VIH or VIL
SN74HC192
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
IO=-20uA;VCC=2.0V
IO=-20uA;VCC=4.5V
IO=-20uA;VCC=6.0V
IO=-4.0mA;VCC=4.5V
IO=-5.2mA;VCC=6.0V
IO=20uA;VCC=2.0V
IO=20uA;VCC=4.5V
IO=20uA;VCC=6.0V
IO=4.0mA;VCC=4.5V
IO=5.2mA;VCC=6.0V
Min.
Typ.
Max.
Unit
1.5
3.15
4.2
1.9
4.4
5.9
3.84
5.34
-
-
0.5
1.35
1.8
0.1
0.1
0.1
0.33
0.33
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
input leakage
current
supply current
II
VI=Vcc or GND;VCC=6.0V
-
-
±0.1
μA
ICC
VI=VCC or GND;IO=0A;VCC=6.0V
-
-
80
μA
input apacitance
CI
SN74HCT192
-
-
-
pF
VIH
VCC=4.5V to 5.5V
2.0
-
-
V
VIL
VCC=4.5V to 5.5V
-
-
0.8
V
4.4
3.84
-
-
0.1
0.33
V
V
V
V
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
LOW-level
output voltage
input leakage
current
supply current
Additional
Supply currend
input apacitance
XBLW version 1.0
VOH
VI=VIH or VIL
VCC=4.5V
VOL
VI=VIH or VIL
VCC=4.5V
IO=-20uA
IO=-4.0uA
IO=20uA
IO=4.0uA
II
VI=Vcc or GND;VCC=5.5V
-
-
±1.0
μA
ICC
VI=VCC or GND;IO=0A;VCC=5.5V
-
-
80
μA
pin Dn
-
-
157.5
μA
pins CPU,CPD
-
-
630
μA
pin P�
-
-
292.5
μA
pin MR
-
-
472.5
μA
-
-
-
pF
ΔICC
CI
per input pin;
VI=VCC-2.1V;
other inputs at VCC
or GND;IO=0V;
VCC=4.5V to 5.5V
-
文档仅供参考，实际应用测试为准
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第 7 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
AC Characteristics 1 (Tamb=25℃, GND =0V, tr=tf=6ns,CL=50pF,unless otherwise specified.)
Parameter
Symbol
Conditions
CPU,CPD to Qn;
see Figure7
CPU to T�U;
see Figure8
CPU to T�D;
see Figure8
P� to Qn;
see Figure9
Propagation
delay
tpd
MR to Qn;
see Figure10
Dn to Qn;
see Figure9
P� to T�U;
P� to T�D;
see Figure12
MR to T�U;
MR to T�D;
see Figure12
Dn to T�U;
Dn to T�D;
see Figure12
transition time
pulse width
XBLW version 1.0
tt
tw
see Figure10
up clock pulse
width HIGH or
LOW;see Figure7
down clock pulse
width HIGH or
LOW;see Figure7
SN74HC192
VCC=2.0V
VCC=4.5V
VCC=5.0V;CL=15pF
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
Min.
Typ.
Max.
Unit
120
24
20
140
28
24
66
23
24
19
33
12
10
39
14
11
69
25
20
63
23
18
91
33
26
102
37
30
96
35
28
83
30
24
19
7
6
39
14
11
50
18
14
215
43
37
125
25
21
125
25
21
215
43
37
200
40
34
275
55
47
315
63
54
285
57
48
290
58
49
75
15
13
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
文档仅供参考，实际应用测试为准
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第 8 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
master reset pulse
width HIGH;
see Figure10
parallel load
pulse width
LOW;
see Figure9
P� to CPU,CPD;
see Figure9
Recovery time
trec
MR to CPU,CPD;
see Figure10
Set-up time
Dn to P�;
see Figure11;note:
CPU=CPD=HIGH
tsu
Dn to P�
see Figure11
Hold time
th
Maximum
frequency
fMAX
power
dissipation
capacitance
CPD
CPU to CPD,
CPD to CPU;
see Figure13
CPU,CPD;
see Figure8
XBLW version 1.0
tpd
80
16
14
80
16
22
8
6
22
8
-
ns
ns
ns
ns
ns
VCC=6.0V
14
6
-
ns
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=5.0V;CL=15pF
VCC=6.0V
50
10
9
50
10
9
80
16
14
0
0
0
80
16
14
4.0
20
24
3
1
1
0
0
0
22
8
6
-14
-5
-4
19
7
6
12
36
40
43
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
-
24
-
pF
-
23
20
43
-
ns
ns
VCC=4.5V
-
16
30
ns
VCC=4.5V
-
17
30
ns
VCC=4.5V
-
28
46
ns
VCC=4.5V
-
24
40
ns
VCC=4.5V
-
36
62
ns
VCC=4.5V
-
36
64
ns
VI=GND to VCC
CPU,CPD to Qn;
see Figure7
Propagation
delay
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
CPU to T�U;
see Figure8
CPU to T�D;
see Figure8
P� to Qn;
see Figure9
MR to Qn;
see Figure10
Dn to Qn;
see Figure9
P� to T�U;
P� to T�D;
SN74HCT192
VCC=4.5V
VCC=5.0V;CL=15pF
文档仅供参考，实际应用测试为准
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第 9 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
transition time
pulse width
tt
tw
Recovery time
trec
Set-up time
tsu
Hold time
th
Maximum
frequency
fMAX
power
dissipation
capacitance
Note:
see Figure12
MR to T�U;
VCC=4.5V
MR to T�D;
see Figure12
Dn to T�U;
VCC=4.5V
Dn to T�D;
see Figure12
VCC=4.5V;see Figure10
up down clock pulse
width HIGH or LOW;
see Figure7
master reset pulse
VCC=4.5V
width HIGH;
see Figure10
parallel load pulse
width LOW;
see Figure9
P� to CPU,CPD;
see Figure9
VCC=4.5V
MR to CPU,CPD;
see Figure10
Dn to P�;see Figure11;
Note:CPU=CPD=HIGH;VCC=4.5V
Dn to P�
see Figure11
VCC=4.5V
CPU to CPD,
CPD to CPU;
see Figure13
VCC=4.5V
CPU,CPD;
see Figure7
VCC=5.0V;CL=15pF
CPD
VI=GND to VCC-1.5V
-
36
64
ns
-
33
58
ns
-
7
15
ns
25
14
-
ns
16
6
-
ns
20
10
-
ns
10
1
-
ns
10
2
-
ns
16
8
-
ns
0
-6
-
ns
20
9
-
ns
20
-
41
45
-
MHz
MHz
-
28
-
pF
[1]tpd is the same as tPLH and tPHL.
[2]tt is the same as tTHL and tTLH.
[3]CPD is used to determine the dynamic power dissipation (PD in uW).
PD=CPD×VCC2×fi×N+∑(CL×VCC2×fo) where:
fi=input frequency in MHz;
fo=output frequency in MHz;
CL=output load capacitance in pF;
VCC=supply voltage in V;
N=number of inputs switching;
∑(CL×VCC2×f`)=sum of outputs.
XBLW version 1.0
文档仅供参考，实际应用测试为准
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第 10 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
AC Characteristics 2 (Tamb=-40℃ to +85℃, GND =0V, tr=tf=6ns,CL=50pF,unless otherwise specified.)
Parameter
Symbol
Conditions
CPU,CPD to Qn;
see Figure7
CPU to T�U;
see Figure8
CPU to T�D;
see Figure8
P� to Qn;
see Figure9
Propagation
delay
tpd
MR to Qn;
see Figure10
Dn to Qn;
see Figure9
P� to T�U;
P� to T�D;
see Figure12
MR to T�U;
MR to T�D;
see Figure12
Dn to T�U;
Dn to T�D;
see Figure12
transition time
pulse width
XBLW version 1.0
tt
tw
see Figure10
up clock pulse
width HIGH or
LOW;see Figure7
down clock pulse
width HIGH or
LOW;see Figure7
SN74HC192
VCC=2.0V
VCC=4.5V
VCC=5.0V;CL=15pF
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
Min.
Typ.
Max.
Unit
150
30
26
175
35
30
-
270
54
46
155
31
26
155
31
26
270
54
46
25
50
43
345
69
59
395
79
67
355
71
60
365
73
62
95
19
16
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
文档仅供参考，实际应用测试为准
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第 11 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
master reset pulse
width HIGH;
see Figure10
parallel load
pulse width
LOW;
see Figure9
P� to CPU,CPD;
see Figure9
Recovery time
trec
MR to CPU,CPD;
see Figure10
Set-up time
Dn to P�;
see Figure11;note:
CPU=CPD=HIGH
tsu
Dn to P�
see Figure11
Hold time
th
Maximum
frequency
fMAX
power
dissipation
capacitance
CPD
CPU to CPD,
CPD to CPU;
see Figure13
CPU,CPD;
see Figure8
XBLW version 1.0
tpd
100
20
17
100
20
-
-
ns
ns
ns
ns
ns
VCC=6.0V
17
-
-
ns
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=5.0V;CL=15pF
VCC=6.0V
65
13
11
65
13
11
100
20
17
0
0
0
100
20
17
3.2
16
19
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
-
-
-
pF
-
-
54
-
ns
ns
VCC=4.5V
-
-
38
ns
VCC=4.5V
-
-
38
ns
VCC=4.5V
-
-
58
ns
VCC=4.5V
-
-
50
ns
VCC=4.5V
-
-
78
ns
VCC=4.5V
-
-
80
ns
VI=GND to VCC
CPU,CPD to Qn;
see Figure7
Propagation
delay
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
CPU to T�U;
see Figure8
CPU to T�D;
see Figure8
P� to Qn;
see Figure9
MR to Qn;
see Figure10
Dn to Qn;
see Figure9
P� to T�U;
P� to T�D;
SN74HCT192
VCC=4.5V
VCC=5.0V;CL=15pF
文档仅供参考，实际应用测试为准
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第 12 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
transition time
pulse width
tt
tw
Recovery time
trec
Set-up time
tsu
Hold time
th
Maximum
frequency
fMAX
power
dissipation
capacitance
Note:
see Figure12
MR to T�U;
VCC=4.5V
MR to T�D;
see Figure12
Dn to T�U;
VCC=4.5V
Dn to T�D;
see Figure12
VCC=4.5V;see Figure10
up down clock pulse
width HIGH or LOW;
see Figure7
master reset pulse
VCC=4.5V
width HIGH;
see Figure10
parallel load pulse
width LOW;
see Figure9
P� to CPU,CPD;
see Figure9
VCC=4.5V
MR to CPU,CPD;
see Figure10
Dn to P�;see Figure11;
Note:CPU=CPD=HIGH;VCC=4.5V
Dn to P�
see Figure11
VCC=4.5V
CPU to CPD,CPD to CPU;
see Figure13
VCC=4.5V
CPU,CPD;
see Figure7
VCC=5.0V;CL=15pF
CPD
VI=GND to VCC-1.5V
-
-
80
ns
-
-
73
ns
-
-
19
ns
31
-
-
ns
20
-
-
ns
25
-
-
ns
13
-
-
ns
13
-
-
ns
20
-
-
ns
0
-
-
ns
25
-
-
ns
16
-
-
-
MHz
MHz
-
-
-
pF
[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in uW).
PD=CPD×VCC2×fi+∑(CL×VCC2×f o) where:
fi=input frequency in MHz;
fo=output frequency in MHz;
CL=output load capacitance in pF;
VCC=supply voltage in V;
∑(CL×VCC 2×fo)=sum of outputs.
XBLW version 1.0
文档仅供参考，实际应用测试为准
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第 13 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
Testing Circuit
AC Testing Circuit
Figure 6. Test circuit for measuring switching times
Definitions for test circuit:
CL=Load capacitance including jig and probe capacitance.
RT=Termination resistance should be equal to the output impedance Zo of the pulse generator.
RL=Load resistance
S1=Test selection switch
AC Testing Waveforms
Figure 7. The clock (CPU, CPD) to output (Qn) propagation delays, the clock pulse width, and the
maximum clock pulse frequency
XBLW version 1.0
文档仅供参考，实际应用测试为准
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第 14 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
Figure 8. The clock (CPU, CPD) to terminal count output (T�U, T�D) propagation delays
Figure 9. The parallel load input (P�) and data (Dn) to Qn output propagation delays and P� removal
time to clock input (CPU, CPD)
XBLW version 1.0
文档仅供参考，实际应用测试为准
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第 15 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
Figure 10. The master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU, CPD removal
time and output transition times
Figure 11. The data input (Dn) to parallel load input (P�) set-up and hold times
XBLW version 1.0
文档仅供参考，实际应用测试为准
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第 16 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
Figure 12. The data input (Dn), parallel load input (P�) and the master reset input (MR) to the terminal
count outputs (T�U, T�D) propagation delays
Figure 13. The CPU to CPD or CPD to CPU hold times
XBLW version 1.0
文档仅供参考，实际应用测试为准
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第 17 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
Measurement Points
Input
Type
VI
GND to VCC
GND to 3V
SN74HC192
SN74HCT192
Output
VM
0.5×VCC
1.3V
VM
0.5×VCC
1.3V
Test Data
VI
tr,tf
CL
RL
S1 position
tPHL,tPLH
SN74HC192
VCC
6.0ns
15pF,50pF
1KΩ
open
SN74HCT192
3.0V
6.0ns
15pF,50pF
1KΩ
open
Type
XBLW version 1.0
Input
Load
文档仅供参考，实际应用测试为准
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第 18 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
Package Information
DIP16
Symbol
A
A1
A2
B
B1
C
D
E
E1
e
L
E2
XBLW version 1.0
Dimensions In Millimeters
Min
Max
3.710
4.310
0.510
3.200
3.600
0.380
0.570
1.524(BSC)
0.204
0.360
18.800
19.200
6.200
6.600
7.320
7.920
2.540(BSC)
3.000
3.600
8.400
9.000
Dimensions In Inches
Min
Max
0.146
0.170
0.020
0.126
0.142
0.015
0.022
0.060(BSC)
0.008
0.014
0.740
0.756
0.244
0.260
0.288
0.312
0.100(BSC)
0.118
0.142
0.331
0.354
文档仅供参考，实际应用测试为准
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第 19 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
SOP16
Symbol
A
A1
A2
b
C
D
E
E1
e
L
θ
XBLW version 1.0
Dimensions In Millimeters
Min
Max
1.350
1.750
0.100
0.250
1.350
1.550
0.330
0.510
0.170
0.250
9.800
10.200
3.800
4.000
5.800
6.200
1.270(BSC)
0.400
1.270
0°
8°
Dimens ons In Inches
Min
Max
0.053
0.069
0.004
0.010
0.053
0.061
0.013
0.020
0.007
0.010
0.386
0.402
0.150
0.157
0.228
0.244
0.050(BSC)
0.016
0.050
0°
文档仅供参考，实际应用测试为准
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8°
第 20 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
TSSOP16
SYMBOL
A
Al
A2
A3
b
bl
c
cl
D
E
E1
e
L
L1
θ
XBLW version 1.0
MILLIMETER
MIN NOM MAX
0.05
0.90
0.39
0.20
0.19
0.13
0.12
4.90
6.20
4.30
0.45
0
文档仅供参考，实际应用测试为准
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1.00
0.44
0.22
0.13
5.00
6.40
4.40
0.65BSC
0.60
1.00BSC
-
1.20
0.15
1.05
0.49
0.28
0.25
0.17
0.14
5.10
6.60
4.50
0.75
8°
第 21 页 共 22 页
XBLW 74HC/HCT192
Synchronous BCD Up/Down Counter
Statement：
Shenzhen xinbole electronics co., ltd. reserves the right to change the product specifications, without notice!
Before placing an order, the customer needs to confirm whether the information obtained is the latest version,
and verify the integrity of the relevant information.
Any semiconductor product is liable to fail or malfunction under certain conditions, and the buyer shall be
responsible for complying with safety standards in the system design and whole machine manufacturing using
Shenzhen xinbole electronics co., ltd products, and take appropriate security measures to avoid the potential risk
of failure may result in personal injury or property losses of the situation occurred!
Product performance is never ending, Shenzhen xinbole electronics co., ltd will be dedicated to provide
customers with better performance, better quality of integrated circuit products.
XBLW version 1.0
文档仅供参考，实际应用测试为准
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第 22 页 共 22 页
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