TI60F100S3F2C4L

Ti60 Data Sheet DSTi60-v2.0 April 2022 www.efinixinc.com Copyright © 2022. All rights reserved. Efinix, the Efinix logo, the Titanium logo, Quantum, Trion, and Efinity are trademarks of Efinix, Inc. All other trademarks and service marks are the property of their respective owners. All specifications subject to change without notice. Contents Introduction..................................................................................................................................... 3 Features............................................................................................................................................3 Available Package Options...................................................................................................................... 4 Device Core Functional Description................................................................................................5 XLR Cell.......................................................................................................................................................6 Embedded Memory..................................................................................................................................7 True Dual-Port Mode..................................................................................................................... 7 Simple Dual-Port Mode.................................................................................................................7 DSP Block................................................................................................................................................... 8 Clock and Control Network..................................................................................................................... 9 Clock Sources that Drive the Global and Regional Networks...............................................10 Driving the Global Network....................................................................................................... 11 Driving the Regional Network................................................................................................... 16 Driving the Local Network......................................................................................................... 17 Device Interface Functional Description....................................................................................... 19 Interface Block Connectivity.................................................................................................................. 19 GPIO.......................................................................................................................................................... 20 Features for HVIO and HSIO Configured as GPIO................................................................. 21 HVIO...............................................................................................................................................24 HSIO...............................................................................................................................................26 I/O Banks...................................................................................................................................... 41 Oscillator...................................................................................................................................................41 PLL............................................................................................................................................................. 42 Dynamic Phase Shift....................................................................................................................45 SPI Flash Memory....................................................................................................................................46 HyperRAM................................................................................................................................................ 47 Single-Event Upset Detection............................................................................................................... 48 Internal Reconfiguration Block.............................................................................................................. 48 Security Feature.............................................................................................................................48 Power Up Sequence...................................................................................................................... 51 Power Supply Current Transient............................................................................................................51 Configuration.................................................................................................................................52 Supported FPGA Configuration Modes.............................................................................................. 53 Characteristics and Timing............................................................................................................ 54 DC and Switching Characteristics.........................................................................................................54 HSIO Electrical and Timing Specifications.......................................................................................... 59 PLL Timing and AC Characteristics...................................................................................................... 62 Configuration Timing..............................................................................................................................63 Pinout Description.........................................................................................................................65 Ti60 Interface Floorplan................................................................................................................68 Efinity Software Support............................................................................................................... 68 Ordering Codes............................................................................................................................. 68 Revision History.............................................................................................................................69 Ti60 Data Sheet Introduction The Titanium Ti60 FPGA features the high-density, low-power Efinix® Quantum™ compute fabric wrapped with an I/O interface in a small footprint package for easy integration. Ti60 FPGAs are designed for highly integrated mobile and edge devices that need low power, a small footprint, and a multitude of I/Os. With ultra-low power Ti60 FPGAs, designers can build products that are always on, providing enhanced capabilities for applications such as mobile, edge, AI IoT, and sensor fusion. Features • High-density, low-power Quantum™ compute fabric • Built on TSMC 16 nm process • 10-kbit high-speed, embedded SRAM, configurable as single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM • High-performance DSP blocks for multiplication, addition, subtraction, accumulation, and up to 15-bit variable-right-shifting • Versatile on-chip clocking — Low-skew global network supporting 32 clock or control signals — Regional and local clock networks — PLL support • FPGA interface blocks — High-voltage I/O (HVIO) (1.8, 2.5, 3.3 V) — High-speed I/O (HSIO), configurable as: – LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional), up to 1.5 Gbps – MIPI lane I/O (DSI and CSI) in high-speed (HS) low-power (LP) modes, up to 1.5 Gbps – Single-ended and differential I/O — PLL — Oscillator • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain(1)) — JTAG interface — Supports internal reconfiguration • Single-event upset (SEU) detection feature • Fully supported by the Efinity® software, an RTL-to-bitstream compiler • Optional security feature — Asymmetric bitstream authentication using RSA-4096 — Bitstream encryption/decryption using AES-GCM Important: All specifications are preliminary and pending hardware characterization. (1) Daisy-chain is not supported in F100S3F2 package. www.efinixinc.com 3 Ti60 Data Sheet Table 1: Ti60 FPGA Resources Logic Elements (LEs) 62,016 eXchangeable Logic and Routing (XLR) Cells Total SRL8(2) 60,800 14,720 Global Clock and Control Signals Embedded Memory (Mbits) Embedded Memory Blocks (10 Kbits) Embedded DSP Blocks Up to 32 2.6 256 160 Table 2: Ti60 Package-Dependent Resources Resource W64 F100S3F2 F225 – – 23 HSIO (1.2, 1.5, 1.8 V LVCMOS, HSTL and SSTL) 35 61 140 HSIO (LVDS, Differential HSTL, SSTL, MIPI TX Data and Clock Lanes) 17 30 70 HSIO (MIPI RX Data Lanes) 8 21 58 HSIO (MIPI RX Clock Lanes) 2 3 12 Global clock or control signals from GPIO pins 3 8 15 PLLs 2 3 4 Single-ended GPIO HVIO (1.8, 2.5, 3.0, 3.3 V LVCMOS, 3.0, 3.3 V (Max) LVTTL) Differential GPIO (Max) Learn more: Refer to the Titanium Packaging User Guide for the package outlines and markings. Available Package Options Table 3: Available Packages Package (2) Dimensions (mm x mm) Pitch (mm) 64-ball WLCSP 3.5 x 3.4 0.4 100-ball FBGA 5.5 x 5.5 0.5 225-ball FBGA 10 x 10 0.65 Number of XLR that can be configured as shift register with 8 maximum taps. www.efinixinc.com 4 Ti60 Data Sheet Device Core Functional Description Ti60 FPGAs feature an eXchangeable Logic and Routing (XLR) cell that Efinix® has optimized for a variety of applications. Titanium FPGAs contain LEs that are constructed from XLR cells. Each FPGA in the Titanium family has a custom number of building blocks to fit specific application needs. As shown in the following figure, the FPGA includes I/O ports on all four sides, as well as columns of LEs, memory, and DSP blocks. A control block within the FPGA handles configuration. Figure 1: Ti60 FPGA Block Diagram Device Interface Quantum compute fabric DSP Blocks 10K Memory Blocks XLR cell for logic and routing DSP blocks are optimized for computing and AI Interface blocks for GPIO, LVDS, PLL and MIPI lane I/O. www.efinixinc.com 5 Ti60 Data Sheet XLR Cell The eXchangeable Logic and Routing (XLR) cell is the basic building block of the Quantum™ architecture. The Efinix® XLR cell combines logic and routing and supports both functions. This unique innovation greatly enhances the transistor flexibility and utilization rate, thereby reducing transistor counts and silicon area significantly. Learn more: For more detailed on the advantages the XLR cell brings to Titanium FPGAs, read the Why the XLR Cell is a Big Deal White Paper. The XLR cell functions as: • A 4-input LUT that supports any combinational logic function with four inputs. • A simple full adder. • An 8-bit shift register that can be cascaded. • A fracturable LUT or full adder. The logic cell includes an optional flipflop. You can configure multiple logic cells to implement arithmetic functions such as adders, subtractors, and counters. Figure 2: Logic Cell Functions 4-Input LUT Input[3:0] Clock Clock Enable 4-Input LUT LUT Out Flipflop Register Out Full Adder Input[1:0] Clock Clock Enable Carry In Sum Out Full Adder Flipflop Register Out Carry Out Fracturable LUT or Full Adder Input[3:0] Clock Clock Enable Carry In Input Clock Clock Enable Address[2:0] Carry In Fracturable LUT (1) or Full Adder Data Out Flipflop Register Out Flexible Carry Out Carry Out Propagate Out or Data Out 2 8-Bit Shift Register Data Out Shift Register Flipflop Register Out Cascade Out 1. The fracturable LUT is a combination of a 3-input LUT and a 2-input LUT. They share 2 of the same inputs. Learn more: Refer to the Quantum Titanium Primitives User Guide for details on the Titanium logic cell primitves. www.efinixinc.com 6 Ti60 Data Sheet Embedded Memory The core has 10-kbit high-speed, synchronous, embedded SRAM memory blocks. Memory blocks can operate as single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM. You can initialize the memory content during configuration. The Efinity® software includes a memory cascading feature to connect multiple blocks automatically to form a larger array. This feature enables you to instantiate deeper or wider memory modules. Note: The block RAM content is random and undefined if it is not initialized. The read and write ports support independently configured data widths, an address enable, and an output register reset. The simple dual-port mode also supports a write byte enable. Learn more: Refer to the Quantum Titanium Primitives User Guide for details on the RAM configuration. True Dual-Port Mode The memory read and write ports have the following modes for addressing the memory (depth x width): 1024 x 8 2048 x 4 4096 x 2 8192 x 1 1024 x 10 2048 x 5 Figure 3: RAM Block Diagram (True Dual-Port Mode) Write Data A [9:0] Address A [12:0] Embedded Memory Write Data B [9:0] Address B [12:0] Address Enable B Address Enable A Write Enable B Write Enable A Clock B Clock A Clock Enable B Clock Enable A Reset B Reset A Read Data B [9:0] Read Data A [9:0] Simple Dual-Port Mode The memory read and write ports have the following modes for addressing the memory (depth x width): 512 x 16 1024 x 8 2048 x 4 4096 x 2 8192 x 1 512 x 20 1024 x 10 2048 x 5 Figure 4: Simple Dual-Port Mode RAM Block Diagram (512 x 20 Configuration) Write Data [19:0] Write Address [12:0] Write Enable [1:0] Write Clock Write Clock Enable Write Address Enable Embedded Memory Read Data [19:0] Read Address [12:0] Read Enable Read Address Enable Read Clock Reset RAM output www.efinixinc.com 7 Ti60 Data Sheet DSP Block The Titanium FPGA has high-performance, complex DSP blocks that can perform multiplication, addition, subtraction, accumulation, and 4-bit variable right shifting. The 4-bit variable right shift supports one lane in normal mode, two lanes in dual mode and four lanes in quad mode. Each DSP block has four modes, which support the following multiplication operations: • Normal—One 19 x 18 integer multiplication with 48-bit addition/subtraction. • Dual—One 11 x 10 integer multiplication and one 8 x 8 integer multiplication with two 24-bit additions/subtractions. • Quad—One 7 x 6 integer multiplication and three 4 x 4 integer multiplications with four 12-bit additions/subtractions. • Float—One fused-multiply-add/subtract/accumulate (FMA) BFLOAT16 multiplication. The integer multipliers can represent signed or unsigned values based on the SIGNED parameter. When multiple EFX_DSP12 or EFX_DSP24 primitives are mapped to the same DSP block, they must have the same SIGNED value. The inputs to the multiplier are the A and B data inputs. Optionally, you can use the result of the multiplier in an addition or subtraction operation. Figure 5: DSP Block Diagram CASCOUT[47:0] A[18:0] A B[17:0] B 19 18 37 P pext M Signed 48 W >> O 16 C[17:0] CLK CE RST OP[1:0] cext C 48 >> 18¹ >>> 18² 0 1 O[47:0] OVFL N 16 OP Bypassable Shift 2 DSP Block 48 CASCIN[47:0] SHIFT_ENA 1. Logical right-shift-by-18. 2. Arithmetic right-shift-by-18. Learn more: Refer to the Quantum Titanium Primitives User Guide for more information about the Titanium DSP block primitives. www.efinixinc.com 8 Ti60 Data Sheet Clock and Control Network The clock and control network is distributed through the FPGA to provide clocking for the core's LEs, memory, DSP blocks, I/O blocks, and control signals. The FPGA has 32 global signals that can be used as either clocks or control signals. The global signals are balanced trees that feed the whole FPGA. The FPGA also has regional signals that can only reach certain FPGA regions, including the top or bottom edges. The FPGA has 4 regional networks for the core, right interface, and left interface blocks. The top and bottom interface blocks have 1 regional clock network each. You can drive the right and left sides of each region independently. Each region also has a local network of clock signals that can only be used in that region. The core's global buffer (GBUF) blocks drive the global and regional signals. Signals from the core and interface can drive the GBUF blocks. Each network has dedicated enable logic to save power by disabling the clock tree. The logic dynamically enables/disables the network and guarantees no glitches at the output. Figure 6: Global and Regional Clock Network Overview 8 Regional Signals 4 Global Signals 4 Interface Only Region 2 2 2 2 Core and Interface Regions 8 8 2 2 2 2 4 4 8 Global Signals Regional Signals Regions for Core and Interface Interface Only Region GBUF RBUF www.efinixinc.com 9 Ti60 Data Sheet Clock Sources that Drive the Global and Regional Networks The Titanium global and regional networks are highly flexible and configurable. Clock sources can come from interface blocks, such as GPIO or PLLs, or from the core fabric. Table 4: Clock Sources that Drive the Global and Regional Networks Source Description GPIO Supports GCLK, GCTRL, RCLK, RCTRL. (Only the P resources support this connection type). LVDS RX Supports GCLK and RCLK. MIPI RX Lane (configured as clock lane) Supports GCLK (default) and RCLK. You can only use resources that are identified as clocks. PLL Output clocks 0 - 3 connect to the global network. Output clock 4 only connects to the regional network in the top or bottom interface regions (depending on the location of the PLL) and can only drive interface blocks on the top or bottom of the FPGA. Refer to Driving the Regional Network on page 16. Oscillator Connects to global buffer. Core Signals from the core logic can drive the global or regional network. www.efinixinc.com 10 Ti60 Data Sheet Driving the Global Network You can access the global clock network using the global clock GPIO pins, PLL outputs, oscillator output, and core-generated clocks. Similarly, the FPGA has GPIO pins that you can configure as control inputs to access the high-fanout network connected to the LE's set, reset, and clock enable signals. A clock multiplexing network controls which interface blocks can drive the global and regional networks. Eight of the clock multiplexers are dynamic (two on each side of the FPGA), allowing you to change which clock drives the global signal in user mode. Learn more: Refer to the Titanium Interfaces User Guide for information on how to configure the global and regional clock networks. The following figure shows the global network clock sources graphically. GPIOL_P_07 GPIOL_P_08 GPIOL_P_09 GPIOL_P_10 CLKOUT0-3 4 3 4 CLKOUT0-3 GPIOT_PN_03 GPIOT_PN_09 GPIOT_PN_14 CLKOUT0-3 Oscillator Core 4 8 GPIOR_P_08 GPIOR_P_09 GPIOR_P_10 GPIOR_P_11 4 TL TR CLKOUT0-3 Core 4 4 I/O GPIO or LVDS 4 3 MIPI Clock Lane 4 MIPI Clock Lane GPIOT_P_07 GPIOT_P_08 GPIOT_P_09 GPIOT_P_10 GPIO or LVDS Figure 7: Clock Sources that Drive the Global Network PLL 4 8 4 Core CLKOUT0-3 BL BR GPIOL_PN_02 GPIOL_PN_09 GPIOL_PN_16 MIPI Clock Lane CLKOUT0-3 3 GPIO or LVDS GPIOB_P_07 GPIOB_P_08 GPIOB_P_09 GPIOB_P_10 4 3 Core 4 GPIO or LVDS MIPI Clock Lane 4 CLKOUT0-3 GPIOR_PN_02 GPIOR_PN_10 GPIOR_PN_17 8 4 8 4 4 Core CLKOUT0-3 GPIOB_PN_03 GPIOB_PN_09 GPIOB_PN_14 Note: The Ti60ES oscillator can only drive the core. www.efinixinc.com 11 Ti60 Data Sheet As the figure shows, numerous clock sources feed the global network. These signals are multiplexed together with static and dynamic clock multiplexers. The following figure shows the specific sources that drive each multiplexer. Figure 8: Clock Sources that Drive the Multiplexers: Top Mux 1 Mux 2 TL0 CLKOUT2 Oscillator GPIOT_PN_09 Mux 3 TL0 CLKOUT0 GPIOT_PN_14 Mux 4 GPIOT_PN_09 TR0 CLKOUT0 Mux 5 GPIOT_PN_03 GPIOT_PN_07 TR0 CLKOUT2 TL0 CLKOUT1 GPIOT_PN_08 TR0 CLKOUT3 TL0 CLKOUT2 TR0 CLKOUT2 GPIOT_PN_09 Core Clock 2 TL0 CLKOUT1 TR0 CLKOUT1 GPIOT_PN_08 Core Clock 1 TL0 CLKOUT0 TR0 CLKOUT0 GPIOT_PN_07 Core Clock 0 TL0 CLKOUT3 TR0 CLKOUT3 GPIOT_PN_10 Core Clock 3 TL0 CLKOUT2 TR0 CLKOUT2 GPIOT_PN_09 Core Clock 2 TL0 CLKOUT1 TR0 CLKOUT1 GPIOT_PN_08 Core Clock 1 TL0 CLKOUT0 TR0 CLKOUT0 GPIOT_PN_07 Core Clock 0 Mux 7 TL0 CLKOUT3 TR0 CLKOUT1 GPIOT_PN_10 Mux 6 Mux 0 TL0 CLKOUT3 TR0 CLKOUT3 GPIOT_PN_10 Core Clock 3 GPIO MIPI Clock Lane PLL CLKOUT Dynamic Multiplexer Static Multiplexer www.efinixinc.com 12 Ti60 Data Sheet Figure 9: Clock Sources that Drive the Multiplexers: Bottom Mux 1 Mux 2 BL0 CLKOUT2 N.C. GPIOB_PN_09 Mux 3 BL0 CLKOUT0 GPIOB_PN_14 Mux 4 GPIOB_PN_09 BR0 CLKOUT0 Mux 5 GPIOB_PN_03 GPIOB_PN_07 BR0 CLKOUT2 BL0 CLKOUT1 GPIOB_PN_08 BR0 CLKOUT3 BL0 CLKOUT2 BR0 CLKOUT2 GPIOB_PN_09 Core Clock 2 BL0 CLKOUT1 BR0 CLKOUT1 GPIOB_PN_08 Core Clock 1 BL0 CLKOUT0 BR0 CLKOUT0 GPIOB_PN_07 Core Clock 0 BL0 CLKOUT3 BR0 CLKOUT3 GPIOB_PN_10 Core Clock 3 BL0 CLKOUT2 BR0 CLKOUT2 GPIOB_PN_09 Core Clock 2 BL0 CLKOUT1 BR0 CLKOUT1 GPIOB_PN_08 Core Clock 1 BL0 CLKOUT0 BR0 CLKOUT0 GPIOB_PN_07 Core Clock 0 Mux 7 BL0 CLKOUT3 BR0 CLKOUT1 GPIOB_PN_10 Mux 6 Mux 0 BL0 CLKOUT3 BR0 CLKOUT3 GPIOB_PN_10 Core Clock 3 GPIO MIPI Clock Lane PLL CLKOUT Dynamic Multiplexer Static Multiplexer www.efinixinc.com 13 Ti60 Data Sheet Figure 10: Clock Sources that Drive the Multiplexers: Left Mux 1 Mux 2 BL0 CLKOUT2 N.C. GPIOL_PN_09 Mux 3 BL0 CLKOUT0 GPIOL_PN_16 Mux 4 GPIOL_PN_09 TL0 CLKOUT0 Mux 5 GPIOL_PN_02 GPIOL_PN_07 TL0 CLKOUT2 BL0 CLKOUT1 GPIOL_PN_08 TL0 CLKOUT3 BL0 CLKOUT2 TL0 CLKOUT2 GPIOL_PN_09 Core Clock 2 BL0 CLKOUT1 TL0 CLKOUT1 GPIOL_PN_08 Core Clock 1 BL0 CLKOUT0 TL0 CLKOUT0 GPIOL_PN_07 Core Clock 0 BL0 CLKOUT3 TL0 CLKOUT3 GPIOL_PN_10 Core Clock 3 BL0 CLKOUT2 TL0 CLKOUT2 GPIOL_PN_09 Core Clock 2 BL0 CLKOUT1 TL0 CLKOUT1 GPIOL_PN_08 Core Clock 1 BL0 CLKOUT0 TL0 CLKOUT0 GPIOL_PN_07 Core Clock 0 Mux 7 BL0 CLKOUT3 TL0 CLKOUT1 GPIOL_PN_10 Mux 6 Mux 0 BL0 CLKOUT3 TL0 CLKOUT3 GPIOL_PN_10 Core Clock 3 GPIO MIPI Clock Lane PLL CLKOUT Dynamic Multiplexer Static Multiplexer www.efinixinc.com 14 Ti60 Data Sheet Figure 11: Clock Sources that Drive the Multiplexers: Right Mux 1 Mux 2 BR0 CLKOUT2 N.C. GPIOR_PN_10 Mux 3 BR0 CLKOUT0 GPIOR_PN_17 Mux 4 GPIOR_PN_10 TR0 CLKOUT0 Mux 5 GPIOR_PN_02 GPIOR_PN_08 TR0 CLKOUT2 BR0 CLKOUT1 GPIOR_PN_09 TR0 CLKOUT3 BR0 CLKOUT2 TR0 CLKOUT2 GPIOR_PN_10 Core Clock 2 BR0 CLKOUT1 TR0 CLKOUT1 GPIOR_PN_09 Core Clock 1 BR0 CLKOUT0 TR0 CLKOUT0 GPIOR_PN_08 Core Clock 0 BR0 CLKOUT3 TR0 CLKOUT3 GPIOR_PN_11 Core Clock 3 BR0 CLKOUT2 TR0 CLKOUT2 GPIOR_PN_10 Core Clock 2 BR0 CLKOUT1 TR0 CLKOUT1 GPIOR_PN_09 Core Clock 1 BR0 CLKOUT0 TR0 CLKOUT0 GPIOR_PN_08 Core Clock 0 Mux 7 BR0 CLKOUT3 TR0 CLKOUT1 GPIOR_PN_11 Mux 6 Mux 0 BR0 CLKOUT3 TR0 CLKOUT3 GPIOR_PN_11 Core Clock 3 GPIO MIPI Clock Lane PLL CLKOUT Dynamic Multiplexer Static Multiplexer The dynamic multiplexers are configurable by the user at run-time. You can choose which clock source drives which input to the dynamic multiplexer. When you enable the dynamic multiplexer, you specify a select bus to choose which clock source is active. www.efinixinc.com 15 Ti60 Data Sheet Driving the Regional Network The following figure shows the regional network clock sources graphically. The PLL CLKOUT4 can only connect to the top (or bottom) interface. Figure 12: Clock Sources that Drive the Regional Network RBUF7 GPIOT_PN_10 RBUF6 GPIOT_PN_07 RBUF5 GPIOT_PN_09 RBUF4 GPIOT_PN_03 RBUF3 TR0 CLKOUT4 RBUF2 TL0 CLKOUT4 RBUF1 GPIOT_PN_09 RBUF0 GPIOT_PN_08 TL GPIOL_PN_07 GPIOL_PN_02 GPIOL_PN_08 GPIOL_PN_09 GPIOL_PN_09 GPIOL_PN_09 GPIOL_PN_10 GPIOL_PN_16 TR RBUF0 RBUF0 RBUF1 RBUF1 RBUF2 RBUF2 RBUF3 RBUF3 RBUF4 RBUF4 RBUF5 RBUF5 RBUF6 RBUF6 RBUF7 RBUF7 I/O PLL Oscillator GPIOR_PN_09 GPIOR_PN_10 GPIOR_PN_10 GPIOR_PN_10 GPIOR_PN_11 GPIOR_PN_17 RBUF7 RBUF6 RBUF5 RBUF4 RBUF3 RBUF2 RBUF1 GPIO or LVDS MIPI Clock Lane PLL CLKOUT4 GPIOR_PN_02 BR RBUF0 BL GPIOR_PN_08 GPIOB_PN_07 GPIOB_PN_10 GPIOB_PN_03 GPIOB_PN_09 BL0 CLKOUT4 GPIOB_PN_08 BR0 CLKOUT4 GPIOB_PN_09 www.efinixinc.com 16 Ti60 Data Sheet Driving the Local Network As described previously, the FPGA has horizontal clock regions. The top and bottom regions are only for the top and bottom interfaces. The other regions are for the core logic (XLR cells, DSP Blocks, and RAM) and the interfaces on the sides. Local Network for Core Logic As shown in the following figure, the regions that contain the core logic are 80 XLR cells tall, and the local network connects an area that is 40 XLR cells tall. Additionally, each column has it's own local network. For example, in the first column, XLR cells 1 - 40 are in the same local network and XLR cells 41 - 80 are in another local network. DSP Blocks and RAM also have their own local networks. This pattern of block/local network is repeated for each column in the die. Figure 13: Clock Sources for Logic, DSP Blocks, and RAM Set/Reset Clock Local Networks 20 RAM DSP Block 1 Clock Enable Clock Clock Region 21 Clock enable from local fabric Clock or control signals from local fabric 40 2 2 3 4 4 16 2 2 3 4 4 32 Global 16 from fabric in another region 4 or 8 Regional 41 60 61 Local network Clocks from local fabric 80 Clock Set/Reset Clock Clock XLR Cell ClockEnable www.efinixinc.com 17 Ti60 Data Sheet There are 16 signals that can feed the local networks. These signals can come from several sources: • The global network (32 possible signals) • The core fabric in another region (16 possible signals) • The regional network (4 or 8 possible signals). For the top and bottom regions 8 signals can come from the regional network. For the other regions, 4 signals can come from the regional network. (Refer back to Clock and Control Network on page 9.) Additionally, the local fabric can generate clock and control signals for the local network. The fabric can also drive the clock enable for the XLR cell directly, allowing each XLR cell to have a unique clock enable. Local Network for Interface Regions The following figure shows the local clock networks for the interface blocks. There are a limited number of unique clocks per local clock region. • The top and bottom regions can each support up to 16 unique clock signals; 14 from the global network and 2 from the fabric. • The left and right regions can each support up to 4 unique clock signals. Up to 2 can come from the routing fabric, the rest come from the global or regional buffers. Figure 14: Clock Sources that Drive the Interfaces Left PLL_TL Right 0 8 9 11 T0 3 18 17 4 (2) 17 14 4 (2) 13 12 4 (2) R7 19 4 (2) 18 L6 R6 18 4 (2) 15 L5 R5 14 4 (2) 13 L4 R4 12 4 (2) 10 8 7 4 (2) L3 R3 6 5 4 (2) L2 R2 4 (2) 1 0 4 (2) B0 0 0 20 L7 4 (2) 4 2 PLL_TR 12 16 (1) T1 16 (1) 11 9 2 PLL_BL 17 L1 R1 L0 R0 16 (1) 16 (1) 8 9 4 (2) 9 7 4 (2) 6 5 4 (2) 4 2 4 (2) 1 0 21 B1 29 17 Interface Only Region Each local region is 40 rows of XLR cells Local Clocks PLL HSIO HVIO Dimensions not to scale Interface Only Region PLL_BR Note: 1. 14 signals come from the global network; 2 come from the routing fabric. 2. Up to 2 signals can come from the routing fabric. The rest come from the regional/global buffer. www.efinixinc.com 18 Ti60 Data Sheet Device Interface Functional Description The device interface wraps the core and routes signals between the core and the device I/O pads through a signal interface. Because they use the flexible Quantum™ architecture, devices in the Titanium family support a variety of interfaces to meet the needs of different applications. Learn more: The following sections describe the available device interface features in Ti60 FPGAs. Refer to the Titanium Interfaces User Guide for details on the Efinity® Interface Designer settings. Interface Block Connectivity The FPGA core fabric connects to the interface blocks through a signal interface. The interface blocks then connect to the package pins. The core connects to the interface blocks using three types of signals: • Input—Input data or clock to the FPGA core • Output—Output from the FPGA core • Clock output—Clock signal from the core clock tree Figure 15: Interface Block and Core Connectivity FPGA Interface Block Interface Block Signal Interface Input Output Core Input Output Clock Output Clock Output Input Output Input Output Clock Output Clock Output Interface Block Interface Block GPIO GPIO blocks are a special case because they can operate in several modes. For example, in alternate mode the GPIO signal can bypass the signal interface and directly feed another interface block. So a GPIO configured as an alternate input can be used as a PLL reference clock without going through the signal interface to the core. When designing for Titanium FPGAs, you create an RTL design for the core and also configure the interface blocks. From the perspective of the core, outputs from the core are inputs to the interface block and inputs to the core are outputs from the interface block. The Efinity netlist always shows signals from the perspective of the core, so some signals do not appear in the netlist: • GPIO used as reference clocks are not present in the RTL design, they are only visible in the interface block configuration of the Efinity® Interface Designer. www.efinixinc.com 19 Ti60 Data Sheet • The FPGA clock tree is connected to the interface blocks directly. Therefore, clock outputs from the core to the interface are not present in the RTL design, they are only part of the interface configuration (this includes GPIO configured as output clocks). The following sections describe the different types of interface blocks in the Ti60. Signals and block diagrams are shown from the perspective of the interface, not the core. GPIO The Ti60 FPGA supports two types of GPIO: • High-voltage I/O (HVIO)—Simple I/O blocks that can support single-ended I/O standards. • High-speed I/O (HSIO)—Complex I/O blocks that can support single-ended and differential I/O functionality. The I/O logic comprises three register types: • Input—Capture interface signals from the I/O before being transferred to the core logic • Output—Register signals from the core logic before being transferred to the I/O buffers • Output enable—Enable and disable the I/O buffers when I/O used as output The HVIO supports the following I/O standards. Table 5: HVIO Supported Standards Standard VCCIO33 (V) When Configured As LVTTL 3.3 V 3.3 GPIO LVTTL 3.0 V 3.0 GPIO LVCMOS 3.3 V 3.3 GPIO LVCMOS 3.0 V 3.0 GPIO LVCMOS 2.5 V 2.5 GPIO LVCMOS 1.8 V 1.8 GPIO Important: Efinix recommends that you limit the number of 3.0/3.3 V HVIO as I/O or output to 6 per bank to avoid switching noise. The Efinity® software issues a warning if you exceed the recommended limit. www.efinixinc.com 20 Ti60 Data Sheet The HSIO supports the following I/O standards. Table 6: HSIO Supported I/O Standards Standard VCCIO (V) VCCAUX (V) VREF (V) When Configured As TX RX LVCMOS 1.8 V 1.8 1.8 1.8 – GPIO LVCMOS 1.5 V 1.5 1.5 1.8 – GPIO LVCMOS 1.2 V 1.2 1.2 1.8 – GPIO HSTL/Differential HSTL 1.8 V 1.8 1.8 1.8 0.9 GPIO HSTL/Differential HSTL 1.5 V 1.5 1.5, 1.8(3) 1.8 0.75 GPIO HSTL/Differential HSTL 1.2 V 1.2 1.2, 1.5, 1.8(3) 1.8 0.6 GPIO LVDS/RSDS/mini-LVDS 1.8 1.5, 1.8(3) 1.8 – LVDS Sub-LVDS 1.8 1.5, 1.8(3) 1.8 – LVDS MIPI Lane I/O /SLVS 1.2 1.2 1.8 – MIPI Lane SSTL/Differential SSTL 1.8 V SSTL/Differential SSTL 1.5 V SSTL/Differential SSTL 1.2 V The differential receivers are powered by VCCAUX, which gives you the flexibility to choose the VCCIO you want to use. Features for HVIO and HSIO Configured as GPIO The following table describes the features supported by HVIO and HSIO configured as GPIO. Table 7: Features for HVIO and HSIO Configured as GPIO Feature HVIO HSIO Configured as GPIO Double-data I/O (DDIO) Dynamic pull-up – Pull-up/Pull-down Slew-Rate Control – Variable Drive Strength Schmitt Trigger 1:4 Serializer/Deserializer (Full rate mode only) – Programmable Bus Hold – Static Programmable Delay Chains Dynamic Programmable Delay Chains (3) – To prevent pin leakage, you must ensure that the voltage at the pin does not exceed VCCIO. www.efinixinc.com 21 Ti60 Data Sheet Table 8: GPIO Modes GPIO Mode Input Description Only the input path is enabled; optionally registered. If registered, the input path uses the input clock to control the registers (positively or negatively triggered). Select the alternate input path to drive the alternate function of the GPIO. The alternate path cannot be registered. In DDIO mode, two registers sample the data on the positive and negative edges of the input clock, creating two data streams. Output Only the output path is enabled; optionally registered. If registered, the output path uses the output clock to control the registers (positively or negatively triggered). The output register can be inverted. In DDIO mode, two registers capture the data on the positive and negative edges of the output clock, multiplexing them into one data stream. Bidirectional The input, output, and OE paths are enabled; optionally registered. If registered, the input clock controls the input register, the output clock controls the output and OE registers. All registers can be positively or negatively triggered. Additionally, the input and output paths can be registered independently. The output register can be inverted. Clock output Clock output path is enabled. During configuration, all GPIO pins are configured in weak pull-up mode. During user mode, unused GPIO pins are tristated and configured in weak pull-up mode. You can change the default mode to weak pull-down in the Interface Designer. Double-Data I/O Ti60 FPGAs support double data I/O (DDIO) on input and output registers. In this mode, the DDIO register captures data on both positive and negative clock edges. The core receives 2 bit wide data from the interface. In normal mode, the interface receives or sends data directly to or from the core on the positive and negative clock edges. In resync and pipeline mode, the interface resynchronizes the data to pass both signals on the positive clock edge only. www.efinixinc.com 22 Ti60 Data Sheet Figure 16: DDIO Input Timing Waveform GPIO Input DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 Clock Normal Mode IN0 DATA1 IN1 DATA3 DATA5 DATA2 DATA4 DATA7 DATA6 DATA8 Resync Mode IN0 DATA1 DATA3 DATA5 DATA2 DATA4 DATA6 DATA8 IN0 DATA1 DATA3 DATA5 DATA7 IN1 DATA2 DATA4 DATA6 DATA8 IN1 DATA7 Pipeline Mode In resync mode, the IN1 data captured on the falling clock edge is delayed one half clock cycle. In the Interface Designer, IN0 is the HI pin name and IN1 is the LO pin name. Figure 17: DDIO Output Timing Waveform Normal Mode Clock OUT0 DATA1 OUT1 GPIO Output DATA3 DATA2 DATA1 DATA5 DATA4 DATA2 DATA3 DATA7 DATA6 DATA4 DATA5 DATA8 DATA6 DATA7 DATA8 Resync Mode Clock OUT0 DATA1 DATA3 DATA5 DATA7 OUT1 DATA2 DATA4 DATA6 DATA8 GPIO Output DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 In the Interface Designer, OUT0 is the HI pin name and OUT1 is the LO pin name. www.efinixinc.com 23 Ti60 Data Sheet Programmable Delay Chains The HSIO configured as GPIO supports programmable delay chain. In some cases you can use static and dynamic delays at the same time. Table 9: Programmable Delay Support Delay Type Static GPIO Type Description Single-ended 16 steps with approximately 60 ps of delay per step, both input and output paths. Differential RX 64 steps of approximately 25 ps delay per step. You cannot use the static and dynamic delay at the same time. Available only on P input of the HSIO pin pair. Dynamic Differential TX 64 steps with approximately 25 ps of delay per step. Single ended and differential 64 steps with approximately 25 ps of delay per step, input only. Only available on input (RX) delay; available only on P input of the HSIO pin pair. HVIO The HVIOs are grouped into banks. Each bank has its own VCCIO33 that sets the bank voltage for the I/O standard. Each HVIO consists of I/O logic and an I/O buffer. I/O logic connects the core logic to the I/O buffers. I/O buffers are located at the periphery of the device. Figure 18: HVIO Interface Block I/O Buffer I/O Logic ALT HVIO Block 1 IN0 0 IN 0 IN1 1 IN IN INCLK Pull-Up Resistor OE OE IO OUTCLK OUT 0 0 OUT1 OUT 1 OUT 1 OUT0 www.efinixinc.com 24 Ti60 Data Sheet Table 10: HVIO Signals (Interface to FPGA Fabric) Signal Direction Description IN[1:0] Output Input data from the HVIO pad to the core fabric. ALT Output Alternative input connection (in the Interface Designer, Register Option is none). HVIO only support pll_clkin as the alternative connection. IN0 is the normal input to the core. In DDIO mode, IN0 is the data captured on the positive clock edge (HI pin name in the Interface Designer) and IN1 is the data captured on the negative clock edge (LO pin name in the Interface Designer). OUT[1:0] Input Output data to HVIO pad from the core fabric. OE Input Output enable from core fabric to the I/O block. Can be registered. OUTCLK Input Core clock that controls the output and OE registers. This clock is not visible in the user netlist. INCLK Input Core clock that controls the input registers. This clock is not visible in the user netlist. OUT0 is the normal output from the core. In DDIO mode, OUT0 is the data captured on the positive clock edge (HI pin name in the Interface Designer) and OUT1 is the data captured on the negative clock edge (LO pin name in the Interface Designer). Table 11: HVIO Pads Signal IO Direction Bidirectional Description HVIO pad. www.efinixinc.com 25 Ti60 Data Sheet HSIO Each HSIO block uses a pair of I/O pins as one of the following: • Single-ended HSIO—Two single-ended I/O pins (LVCMOS, SSTL, HSTL) • Differential HSIO—One differential I/O pins: — Differential SSTL and HSTL — LVDS—Receiver (RX), transmitter (TX), or bidirectional (RX/TX) — MIPI lane I/O—Receiver (RX) or transmitter (TX) Figure 19: HSIO Buffer Block Diagram OE P Buffer Out P LVCMOS HSIO Buffer Buffer In P VREF OE D Buffer In D LVDS TX 100 Ω LVDS RX Buffer Out D OE N Buffer Out N LVCMOS Buffer In N VREF Important: When you are using an HSIO pin as a GPIO, LVDS, or MIPI lanes, make sure to leave at least 1 pair of unassigned HSIO pins between the HSIO pins used as GPIO, LVDS, or MIPI lanes and HSIO pins. This separation reduces noise. The Efinity software issues an error if you do not leave this separation. www.efinixinc.com 26 Ti60 Data Sheet HSIO Configured as GPIO You can configure each HSIO block as two GPIO (single-ended) or one GPIO (differential). Figure 20: I/O Interface Block HSIO Block Configured as GPIO 1 0 IN0 IN1 I/O Buffer I/O Logic ALT 0 1 Buffer In IN 0 0 1 1 IN IN INCLK Deserializer IN2 IN3 INFASTCLK OE/OEN Pull-Up Resistor Buffer OE OE OUTCLK Pull-Down Resistor OUT 0 0 OUT1 OUT 1 OUT OUT0 OUT2 OUT3 OUTFASTCLK 1 0 Serializer IO 1 Buffer Out www.efinixinc.com 27 Ti60 Data Sheet Table 12: HSIO Block Configured as GPIO Signals (Interface to FPGA Fabric) Signal IN[3:0] Direction Output Description Input data from the pad to the core fabric. IN0 is the normal input to the core. In DDIO mode, IN0 is the data captured on the positive clock edge (HI pin name in the Interface Designer) and IN1 is the data captured on the negative clock edge (LO pin name in the Interface Designer). When using the deserializer, the first bit is on IN0 and the last bit is on IN3. ALT Output Alternative input connection for GCLK, GCTRL, PLL_CLKIN, RCLK, RCTRL, PLL_EXTFB, and VREF. (In the Interface Designer, Register Option is none). OUT[3:0] Input Output data to GPIO pad from the core fabric. OUT0 is the normal output from the core. In DDIO mode, OUT0 is the data captured on the positive clock edge (HI pin name in the Interface Designer) and OUT1 is the data captured on the negative clock edge (LO pin name in the Interface Designer). When using the serializer, the first bit is on OUT0 and the last bit is on OUT3. OE/OEN Input Output enable from core fabric to the I/O block. Can be registered. DLY_ENA Input (Optional) Enable the dynamic delay control. DLY_INC Input (Optional) Dynamic delay control. When DLY_ENA = 1, DLY_RST Input (Optional) Reset the delay counter. OUTCLK Input Core clock that controls the output and OE registers. This clock is not visible in the user netlist. OUTFASTCLK Input Core clock that controls the output serializer. INCLK Input Core clock that controls the input registers. This clock is not visible in the user netlist. INFASTCLK Input Core clock that controls the input serializer. OEN is used in diffferential mode. Drive it with the same signal as OE. 1: Increments 0: Decrements Table 13: GPIO Pads Signal IO (P and N) Direction Bidirectional Description GPIO pad. The signal path from the pad through the I/O buffer changes depending on the I/O standard you are using. The following figures show the paths for the supported standards. The blue highlight indicates the path. www.efinixinc.com 28 Ti60 Data Sheet Figure 21: I/O Buffer Path for LVCMOS OE P HSIO Buffer Buffer Out P Buffer In P VREF P N OE N Buffer Out N Buffer In N VREF When using an HSIO with the HSTL or SSTL I/O standards, you must configure an I/O pad of the standard's input path as a VREF pin. There is one programmable VREF per I/O bank. Important: When configuring an I/O pad of the standard's input path as a VREF pin, you must use the VREF from the same physical I/O bank even when the I/O banks are merged to share a common VCCIO pin. Figure 22: I/O Buffer Path for HSTL and SSTL OE P HSIO Buffer Buffer Out P Buffer In P VREF P N OE N Buffer Out N Buffer In N VREF www.efinixinc.com 29 Ti60 Data Sheet When using an HSIO with the differential HSTL or differential SSTL standard, you must use both GPIO resources in the HSIO. You use the core interface pins associated with the P resource. Figure 23: I/O Buffer Path for Differential HSTL and SSTL OE P HSIO Buffer Buffer Out P VREF P Buffer In P N OEN P Buffer Out P VREF HSIO Configured as LVDS You can configure each HSIO block in RX, TX, or bidirectional LVDS mode. As LVDS, the HSIO has these features: • Programmable VOD, depending on the I/O standard used. • Programmable pre-emphasis. • Up to 1.5 Gbps. • Programmable 100 Ω termination to save power (you can enable or disable it at runtime). • LVDS input enable to dynamically enable/disable the LVDS input. • Support for full rate or half rate serialization. • Up to 10-bit serialization to support protocols such as 8b10b encoding. • Programmable delay chains. • Optional 8-word FIFO for crossing from the parallel (slow) clock to the user’s core clock to help close timing (RX only). • Dynamic phase alignment (DPA) that automatically eliminates skew for clock to data channels and data to data channels by adjusting a delay chain setting so that data is sampled at the center of the bit period. www.efinixinc.com 30 Ti60 Data Sheet Table 14: Full and Half Rate Serialization Mode Description Full rate clock Half rate clock Example In full rate mode, the fast clock runs at the same frequency as the data and captures data on the positive clock edge. Data rate: 800 Mbps In half rate mode, the fast clock runs at half the speed of the data and captures data on both clock edges. Data rate: 800 Mbps Serialization/Deserialization factor: 8 Slow clock frequency: 100 Mhz (800 Mbps / 8) Fast clock frequency: 800 Mhz Serialization / Deserialization factor: 8 Slow clock frequency: 100 Mhz (800 Mbps / 8) Fast clock frequency: 400 Mhz (800 / 2 ) You use a PLL to generate the serial (fast) and parallel (slow) clocks for the LVDS pins. The slow clock runs at the data rate divided by the serialization factor. Ti60 FPGAs do not have a dedicated LVDS clock tree; therefore, the fast and slow clocks must use global or regional clocks to feed the LVDS primitives. LVDS RX You can configure an HSIO block as one LVDS RX signal. Figure 24: LVDS RX Interface Block Diagram RST Core IN[n:0] LOCK PLL PLL SLOWCLK FASTCLK Alternate LVDS RX Deserializer FIFO DPA Up/ Down Counter Programmable Delay HSIO Buffer RXP RXN Configuration Setting www.efinixinc.com 31 Ti60 Data Sheet Table 15: LVDS RX Signals (Interface to FPGA Fabric) Signal Direction Clock Domain SLOWCLK Description IN[9:0] Output ALT Output Alternate input, only available for an LVDS RX resource in bypass mode (deserialization width is 1; alternate connection type). Alternate connections are PLL_CLKIN, PLL_EXTFB, GCLK, and RCLK. LOCK Output (Optional) When DPA is enabled, this signal indicates that the DPA has achieved training lock and data can be passed. FIFO_EMPTY Output FIFOCLK SLOWCLK Input – Parallel (slow) clock. FASTCLK Input – Serial (fast) clock. FIFOCLK Input – (Optional) Core clock to read from the FIFO. FIFO_RD Input FIFOCLK (Optional) Enables FIFO to read. RST Input FIFOCLK (Optional) Asynchronous. Resets the FIFO and serializer. If the FIFO is enabled, it is relative to FIFOCLK; otherwise it is relative to SLOWCLK. ENA Input – Dynamically enable or disable the LVDS input buffer. Can save power when disabled. SLOWCLK Parallel input data to the core. The width is programmable. (Optional) When FIFO is enabled, this signal indicates that the FIFO is empty. 1: Enabled 0: Disabled TERM Input – Enables or disables termination in dynamic termination mode. DLY_ENA Input SLOWCLK (Optional) Enable the dynamic delay control or the DPA circuit, depending on which one is enabled. DLY_INC Input SLOWCLK (Optional) Dynamic delay control. Cannot be used with DPA enabled. When DLY_ENA is 1: 1: Enabled 0: Disabled 1: Increments 0: Decrements DLY_RST Input SLOWCLK (Optional) Reset the delay counter or the DPA circuit, depending on which one is enabled. The following waveform shows the relationship between the fast clock, slow clock, RX data coming in from the pad, and byte-aligned data to the core. Figure 25: LVDS RX Timing Example Serialization Width of 8 (Half Rate) www.efinixinc.com 32 Ti60 Data Sheet LVDS TX You can configure an HSIO block as one LVDS TX signal. LVDS TX can be used in the serial data output mode or reference clock output mode. Figure 26: LVDS TX Interface Block Diagram LVDS TX OE RST Core Serializer OUT[n:0] HSIO Buffer TXP Programmable Delay TXN SLOWCLK FASTCLK PLL Table 16: LVDS TX Signals (Interface to FPGA Fabric) Signal Direction Clock Domain Description OUT[9:0] Input SLOWCLK SLOWCLK Input – Parallel (slow) clock. FASTCLK Input – Serial (fast) clock. RST Input SLOWCLK OE Input – Parallel output data from the core. The width is programmable. (Optional) Resets the serializer. (Optional) Output enable signal. The following waveform shows the relationship between the fast clock, slow clock, TX data going to the pad, and byte-aligned data from the core. Figure 27: LVDS Timing Example Serialization Width of 8 (Half Rate) TX Pad A 0 A A 1 2 A A 3 4 A A 5 6 A B 7 0 B B 1 2 B B 3 4 B B 5 6 B C 7 0 C C 1 2 C C 3 4 C C 5 6 C 7 FASTCLK SLOWCLK OUT[7:0] A[7:0] B[7:0] C[7:0] OUT is byte-aligned data passed from the core on the rising edge of SLOWCLK. www.efinixinc.com 33 Ti60 Data Sheet LVDS Bidirectional You can configure an HSIO block as one LVDS bidirectional signal. You must use the same serialization for the RX and TX. Figure 28: LVDS Bidirectional Interface Block Diagram RST IN[n:0] Core Deserializer LVDS RX FIFO Programmable Delay DPA LOCK HSIO Buffer RXP RXN Up/Down Counter Alternate PLL Configuration Setting SLOWCLK FASTCLK PLL OE RST Serializer OUT[n:0] LVDS TX TXP Programmable Delay TXN Table 17: LVDS Bidirectional Signals (Interface to FPGA Fabric) Signal Direction Clock Domain Description IN[9:0] Output SLOWCLK Parallel input data to the core. The width is programmable. LOCK Output – FIFO_EMPTY Output FIFOCLK INSLOWCLK Input – Parallel (slow) clock for RX. INFASTCLK Input – Serial (fast) clock for RX. FIFOCLK Input – (Optional) Core clock to read from the FIFO. FIFO_RD Input FIFOCLK (Optional) Enables FIFO to read. INRST Input FIFOCLK (Optional) Asynchronous. Resets the FIFO and RX serializer. If the FIFO is enabled, it is relative to FIFOCLK; otherwise it is relative to SLOWCLK. ENA Input SLOWCLK – (Optional) When DPA is enabled, this signal indicates that the DPA has achieved training lock and data can be passed. (Optional) When the FIFO is enabled, this signal indicates that the FIFO is empty. Dynamically enable or disable the LVDS input buffer. Can save power when disabled. 1: Enabled 0: Disabled TERM Input – Enables or disables termination in dynamic termination mode. 1: Enabled 0: Disabled www.efinixinc.com 34 Ti60 Data Sheet Signal Direction Clock Domain Description DLY_ENA Input SLOWCLK (Optional) Enable the dynamic delay control or the DPA circuit, depending on which one is enabled. DLY_INC Input SLOWCLK (Optional) Dynamic delay control. Cannot be used with DPA enabled. When DLY_ENA is 1, 1: Increments 0: Decrements DLY_RST Input SLOWCLK (Optional) Reset the delay counter or the DPA circuit, depending on which one is enabled. OUT[9:0] Input SLOWCLK Parallel output data from the core. The width is programmable. OUTSLOWCLK Input – Parallel (slow) clock for TX. OUTFASTCLK Input – Serial (fast) clock for TX. OUTRST Input SLOWCLK OE Input – (Optional) Resets the TX serializer. Output enable signal. LVDS Pads Table 18: LVDS Pads Signal Direction Description P Output Differential pad P. N Output Differential pad N. www.efinixinc.com 35 Ti60 Data Sheet HSIO Configured as MIPI Lane You can configure the HSIO block as a MIPI RX or TX lane. The block supports bidirectional data lane, unidirectional data lane, and unidirectional clock lane which can run at speeds up to 1.5 Gbps. The MIPI lane operates in high-speed (HS) and low-power (LP) modes. In HS mode, the HSIO block transmits or receives data with x8 serializer/deserializer. In LP mode, it transmits or receives data without deserializer/serializer. The MIPI lane block does not include the MIPI D-PHY core logic. A full MIPI D-PHY solution requires: • Multiple MIPI RX or TX lanes (at least a clock lane and a data lane) • Soft MIPI D-PHY IP core programmed into the FPGA fabric The MIPI D-PHY standard is a point-to-point protocol with one endpoint (TX) responsible for initiating and controlling communication. Often, the standard is unidirectional, but when implementing the MIPI DSI protocol, you can use one TX data lane for LP bidirectional communication. The protocol is source synchronous with one clock lane and 1, 2, 4, or 8 data lanes. The number of lanes available depends on which package you are using. A dedicated HSIO block is assigned on the RX interface as a clock lane while the clock lane for TX interface can use any of the HSIO block in the group. www.efinixinc.com 36 Ti60 Data Sheet MIPI RX Lane In RX mode, the HS (fast) clock comes in on the MIPI clock lane and is divided down to generate the slow clock. The fast and slow clocks are then passed to neighboring HSIO blocks to be used for the MIPI data lanes. The data lane fast and slow clocks must be driven by a clock lane in the same MIPI group (dedicated buses drive from the clock lane to the neighboring data lanes). The MIPI RX function is defined as: Table 19: MIPI RX Function MIPI RX Function Description RX_DATA_xy_zz MIPI RX Lane. You can use any data lanes within the same group to form multiple lanes of MIPI RX group. x = P or N y = 0 to 7 data lanes (Up to 8 data lanes) zz = I0 to I11 MIPI RX group (Up to 12 MIPI RX groups) RX_CLK_x_zz MIPI RX Clock Lane. x = P or N zz = I0 to I11 MIPI group Learn more: Refer to the Ti60 Pinout Pinout for more information about the MIPI RX function for each HSIO and for which pins are in the same MIPI group. Figure 29: MIPI RX Lane Block Diagram LP_P_OE HSIO Buffer LP_P_OUT LP_P_IN CLKOUT SLOWCLKOUT (1) FASTCLKOUT (1) HS_IN FIFO_EMPTY RD FIFO RST FIFOCLK (1) SLOWCLK (1) FASTCLK (1) DLY_ENA DLY_ENA DLY_RST LP_N_OE VREF Div4 Deserializer 100 Ω Programmable Delay Up/Down Counter PCR Bit LP_N_OUT LP_N_IN MIPI RX Lane I/O VREF 1. These signals are in the primitive, but the software automatically connects them for you. www.efinixinc.com 37 Ti60 Data Sheet Table 20: MIPI RX Lane Signals Interface to MIPI soft CSI/DSI controller with D-PHY in FPGA Fabric Signal Direction Clock Domain HS_IN[7:0] Output SLOWCLK LP_P_IN Output – Low-power input data from the P pad. LP_N_IN Output – Low-power input data from the N pad. LP_P_OUT Input – (Optional) Low-power output data from the core for the P pad. Used if the data lane is reversible. LP_N_OUT Input – (Optional) Low-power output data from the core for the N pad. Used if the data lane is reversible. FIFO_EMPTY Output FIFOCLK SLOWCLKOUT(4) Output – Divided down parallel (slow) clock from the pads. Can only drive RX DATA lanes. FASTCLKOUT(4) Output – Serial (fast) clock from the pads. Can only drive RX DATA lanes. CLKOUT Output – Divided down parallel (slow) clock from the pads that can drive the core clock tree. Used to drive the core logic implementing the rest of the D-PHY protocol. It should also connect to the FIFOCLK of the data lanes. SLOWCLK(4) Input – Parallel (slow) clock. FASTCLK(4) Input – Serial (fast) clock. FIFOCLK(4) Input – (Optional) Core clock to read from the FIFO. FIFO_RD Input FIFOCLK (Optional) Enables FIFO to read. RST Input FIFOCLK (Optional) Asynchronous. Resets the FIFO and serializer. If the FIFO is enabled, it is relative to FIFOCLK; otherwise it is relative to SLOWCLK. HS_ENA Input – Dynamically enable the differential input buffer when in high-speed mode. HS_TERM Input – Dynamically enables input termination high-speed mode. DLY_ENA Input SLOWCLK (Optional) Enable the dynamic delay control. DLY_INC Input SLOWCLK (Optional) Dynamic delay control. When DLY_ENA is 1, DLY_RST Input SLOWCLK (Optional) Reset the delay counter. (4) SLOWCLK Description High-speed parallel data input. (Optional) When the FIFO is enabled, this signal indicates that the FIFO is empty. 1: Increments 0: Decrements These signals are in the primitive, but the software automatically connects them for you. www.efinixinc.com 38 Ti60 Data Sheet The clock lane generates the fast clock and slow clock for the RX data lanes within the interface group. It also generates a clock that feeds the global network. The following figure shows the clock connections between the clock and data lanes. Figure 30: Connections for Clock and RX Data Lane in the Same MIPI RX Group To Global Network CLKOUT SLOWCLKOUT (1) FASTCLKOUT (1) Div4 Clock Lane Data Lane To Core From Global Network FIFOCLK (1) FIFO Deserializer Programmable Delay Programmable Delay From Buffer Configuration Setting From Buffer FASTCLK (1) SLOWCLK (1) Up/Down Counter Configuration Setting 1. The software automatically connects this signal for you. www.efinixinc.com 39 Ti60 Data Sheet MIPI TX Lane In TX mode, a PLL generates the parallel and serial clocks and passes them to the clock and data lanes. Figure 31: MIPI TX Lane Block Diagram LP_P_OE HSIO Buffer LP_P_OUT LP_P_IN VREF HS_OE PLL RST HS_OUT[7:0] SLOWCLK FASTCLK Serializer 100 Ω LP_N_OE LP_N_OUT LP_N_IN MIPI TX Lane I/O VREF Table 21: MIPI TX Lane Signals Interface to MIPI soft CSI/DSI controller with D-PHY in FPGA fabric Signal Direction Clock Domain Description HS_OUT[7:0] Input SLOWCLK LP_P_OUT Input – Low-power output data from the core for the P pad. LP_N_OUT Input – Low-power output data from the core for the N pad. LP_P_IN Output – (Optional) Low-power input data from the P pad. Used if data lane is reversible. LP_N_IN Output – (Optional) Low-power input data from the N pad. Used if data lane is reversible. SLOWCLK Input – Parallel (slow) clock. FASTCLK Input – Serial (fast) clock. RST Input SLOWCLK HS_OE Input – High-speed output enable signal. LP_P_OE Input – Low-power output enable signal for P pad. LP_N_OE Input – Low-power output enable signal for N pad. High-speed output data from the core. Always 8-bits wide. (Optional) Resets the serializer. www.efinixinc.com 40 Ti60 Data Sheet MIPI Lane Pads Table 22: MIPI Lane Pads Signal Direction Description P Output Differential pad P. N Output Differential pad N. I/O Banks Efinix FPGAs have input/output (I/O) banks for general-purpose usage. Each I/O bank has independent power pins. The number and voltages supported vary by FPGA and package. Some I/O banks are merged at the package level by sharing VCCIO pins. Merged banks have underscores (_) between banks in the name (e.g., 1B_1C means 1B and 1C are connected). Table 23: I/O Banks by Package Package I/O Banks Voltage (V) Dynamic Voltage Support W64 1A, 1B, 2A, 3B 1.2, 1.5, 1.8 – All 1A_4B, 1B_2A, 2A_3A_3B_4A F100S3F2 1A, 2A, 2B, 4B 1.8 – All 1A_4B, 2A_2B 1B, 3A, 3B, 4A 1.2, 1.5, 1.8 – All 3B_4A BL 1.8, 2.5, 3.0, 3.3 All – BL, TL, TR, BR, 1.8, 2.5, 3.0, 3.3 All – 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B 1.2, 1.5, 1.8 All – F225 – Banks with Merged Banks DDIO Support Oscillator The Ti60 has one low-frequency oscillator tailored for low-power operation. The oscillator runs at a nominal frequency of 10, 20, 40, or 80 MHz. You can use the oscillator to perform always-on functions with the lowest power possible. It's output clock is available to the core. You can enable or disable the oscillator to allow power savings when not in use. www.efinixinc.com 41 Ti60 Data Sheet PLL Titanium FPGAs have 4 PLLs to synthesize clock frequencies. The PLLs are located in the corners of the FPGA. You can use the PLL to compensate for clock skew/delay via external or internal feedback to meet timing requirements in advanced applications. The PLL reference clock has up to four sources. You can dynamically select the PLL reference clock with the CLKSEL port. (Hold the PLL in reset when dynamically selecting the reference clock source.) The PLL consists of a pre-divider counter (N counter), a feedback multiplier counter (M counter), a post-divider counter (O counter), and output dividers (C). Figure 32: PLL Block Diagram CLKIN[3] CLKIN[2] CLKIN[1] CLKIN[0] FIN PLL N Counter Charge Pump CLKSEL[1] CLKSEL[0] IOFBK FBK FPFD M Counter Loop Filter Phase Frequency Detector Voltage F VCO O Control Counter Oscillator FPLL Local feedback RSTN SHIFT[2:0] SHIFT_SEL[4:0] SHIFT_ENA Output Divider (C) Output Divider (C) Output Divider (C) Output Divider (C) Output Divider (C) Phase Shift Phase Shift Phase Shift Phase Shift Phase Shift LOCKED FOUT CLKOUT4 CLKOUT3 CLKOUT2 CLKOUT1 CLKOUT0 The counter settings define the PLL output frequency: Local and Core Feedback Mode FPFD = FIN / N FVCO = (FPFD x M x O x CFBK ) (5) FPLL = FVCO / O FOUT = (FIN x M x CFBK) / (N x C) Where: FVCO is the voltage control oscillator frequency FPLL is the post-divider PLL VCO frequency FOUT is the output clock frequency FIN is the reference clock frequency FPFD is the phase frequency detector input frequency O is the post-divider counter C is the output divider Note: Refer to the PLL Timing and AC Characteristics on page 62 for FVCO, FOUT. FIN, FPLL, and FPFD values. (5) (M x O x CFBK) must be ≤ 255. www.efinixinc.com 42 Ti60 Data Sheet Figure 33: PLL Interface Block Diagram FPGA PLL Block Core PLL Signals Reference Clock GPIO Block(s) Table 24: PLL Signals (Interface to FPGA Fabric) Signal Direction Description CLKIN[3:0] Input Reference clocks driven by I/O pads or core clock tree. CLKSEL[1:0] Input You can dynamically select the reference clock from one of the clock in pins. RSTN Input Active-low PLL reset signal. When asserted, this signal resets the PLL; when de-asserted, it enables the PLL. Connect this signal in your design to power up or reset the PLL. Assert the RSTN pin for a minimum pulse of 10 ns to reset the PLL. Assert RSTN when dynamically changing the selected PLL reference clock. FBK Input Connect to a clock out interface pin when the PLL is in core feedback mode. IOFBK Input Connect to a clock out interface pin when the PLL is in external I/O feedback mode. CLKOUT0 CLKOUT1 Output PLL output. You can route these signals as input clocks to the core's GCLK network. CLKOUT4 can only feed the top or bottom regional clocks. CLKOUT2 All PLL outputs lock on the negative clock edge. The Interface Designer inverts the clock polarity on the leaf cells by default (Invert Output Clock option unchecked). CLKOUT3 CLKOUT4 You can use CLKOUT0 only for clocks with a maximum frequency of 4x (integer) of the reference clock. If all your system clocks do not fall within this range, you should dedicate one unused clock for CLKOUT0. LOCKED SHIFT[2:0] Output Goes high when PLL achieves lock; goes low when a loss of lock is detected. Connect this signal in your design to monitor the lock status. Input (Optional) Dynamically change the phase shift of the output selected to the value set with this signal. Possible values from 000 (no phase shift) to 111 (3.5 FPLL cycle delay). Each increment adds 0.5 cycle delay. SHIFT_SEL[4:0] Input (Optional) Choose the output(s) affected by the dynamic phase shift. SHIFT_ENA Input (Optional) When high, changes the phase shift of the selected PLL(s) to the new value. www.efinixinc.com 43 Ti60 Data Sheet Table 25: PLL Reference Clock Resource Assignments (W64) PLL REFCLK0 REFCLK1 REFCLK2 External Feedback I/O PLL_TL Single-ended: GPIOL_P_18_PLLIN0 Unbonded(6) Unbonded(6) Single-ended: GPIOL_P_17_EXTFB Differential: GPIOL_P_18_PLLIN0, Differential: GPIOL_P_17_EXTFB, GPIOL_N_18 GPIOL_N_17 PLL_BR Single-ended: GPIOR_P_00_PLLIN0 Unbonded(6) Unbonded(6) Single-ended: GPIOR_P_01_EXTFB Differential: GPIOR_P_00_PLLIN0, Differential: GPIOR_P_01_EXTFB, GPIOR_N_00_CDI22 GPIOR_N_01_CDI23 Table 26: PLL Reference Clock Resource Assignments (F100S3F2) PLL REFCLK0 REFCLK1 REFCLK2 External Feedback I/O PLL_TL Single-ended: GPIOL_P_18_PLLIN0 Unbonded(6) Unbonded(6) Single-ended: GPIOL_P_17_EXTFB Differential: GPIOL_P_18_PLLIN0, Differential: GPIOL_P_17_EXTFB, GPIOL_N_18 GPIOL_N_17 PLL_TR Single-ended: GPIOR_P_19_PLLIN0 Unbonded(6) Unbonded(6) Unbonded(6) Differential: GPIOR_P_19_PLLIN0, GPIOR_N_19 PLL_BR Single-ended: GPIOR_P_00_PLLIN0 Unbonded(6) Unbonded(6) Single-ended: GPIOR_P_01_EXTFB Differential: GPIOR_P_00_PLLIN0, Differential: GPIOR_P_01_EXTFB, GPIOR_N_00_CDI22 GPIOR_N_01_CDI23 Table 27: PLL Reference Clock Resource Assignments (F225) PLL PLL_BL REFCLK0 Single-ended: GPIOB_P_00_PLLIN1 Unbonded(6) Single-ended: GPIOL_P_18_PLLIN0 Single-ended: GPIOT_P_00_PLLIN1 GPIOL_11_PLLIN2 Single-ended: GPIOR_P_19_PLLIN0 Single-ended: GPIOT_P_17_PLLIN1 Unbonded(6) Single-ended: GPIOR_P_00_PLLIN0 Single-ended: GPIOB_P_17_PLLIN1 GPIOR_29_PLLIN2 Differential: GPIOL_P_18_PLLIN0, GPIOL_N_18 PLL_TR Differential: GPIOR_P_19_PLLIN0, GPIOR_N_19 PLL_BR Differential: GPIOR_P_00_PLLIN0, GPIOR_N_00_CDI22 (6) REFCLK2 Single-ended: GPIOL_P_00_PLLIN0 Differential: GPIOL_P_00_PLLIN0, GPIOL_N_00 PLL_TL REFCLK1 Differential: GPIOB_P_00_PLLIN1, GPIOB_N_00 Single-ended: GPIOB_P_01_EXTFB Differential: GPIOB_P_01_EXTFB, GPIOB_N_01 Differential: GPIOT_P_00_PLLIN1 GPIOT_N_00 Single-ended: GPIOL_P_17_EXTFB Differential: GPIOL_P_17_EXTFB, GPIOL_N_17 Differential: GPIOT_P_17_PLLIN1, GPIOT_N_17 Differential: GPIOB_P_17_PLLIN1, GPIOB_N_17 External Feedback I/O Single-ended: GPIOT_P_16_EXTFB Differential: GPIOT_P_16_EXTFB, GPIOT_N_16 Single-ended: GPIOR_P_01_EXTFB Differential: GPIOR_P_01_EXTFB, GPIOR_N_01_CDI23 There is no dedicated pin assigned to this reference clock. www.efinixinc.com 44 Ti60 Data Sheet Dynamic Phase Shift Ti60 FPGAs support a dynamic phase shift where you can adjust the phase shift of each output dynamically in user mode by up to 3.5 FPLL cycles. For example, to phase shift a 400 MHz clock by 90-degree, configure the PLL to have a FPLL frequency of 800 MHz, set the output counter division to 2, and set SHIFT[2:0] to 001. Implementing Dynamic Phase Shift Use these steps to implement the dynamic phase shift: 1. Write the new phase setting into SHIFT[2:0]. 2. After 1 clock cycle of the targeted output clock that you want to shift, assert the SHIFT_SEL[n] and SHIFT_ENA signals. 3. Hold SHIFT_ENA and SHIFT_SEL[n] high for a minimum period of 4 clock cycles of the targeted output clock. 4. De-assert SHIFT_ENA and SHIFT_SEL[n]. Wait for at least 4 clock cycles of the targeted output clock before asserting SHIFT_ENA and SHIFT_SEL[n] again. Note: n in SHIFT_SEL[n] represents the output clock that you intend to add phase shift. The following waveforms describe the signals for a single phase shift and consecutive multiple phase shifts. Figure 34: Single Dynamic Phase Shift Waveform Example for CLKOUT1 SHIFT[2:0] 000 001 000 SHIFT_SEL[1] SHIFT_ENA CLKOUT0 CLKOUT1 4 cycles minimum Figure 35: Consecutive Dynamic Phase Shift Waveform Example for CLKOUT1 SHIFT[2:0] 000 001 010 SHIFT_SEL[1] SHIFT_ENA CLKOUT0 CLKOUT1 4 cycles minimum 4 cycles minimum www.efinixinc.com 45 Ti60 Data Sheet SPI Flash Memory Ti60 FPGAs in the F100S3F2 package include a SPI flash memory. The SPI flash memory has a density of 16 Mbits and a clock rate of up to 85 MHz. In active configuration mode, the FPGA is configured using the configuration bitstream in the SPI flash memory. Typically you can fit two compressed bitstream images into the F100S3F2 SPI flash. Important: You cannot enable the Ti60 FPGA security features when using compressed bitstreams. To use active programming mode for the Ti60 F100S3F2 with the SPI flash memory, you must use the SPI Active using JTAG Bridge configuration mode to configure the SPI flash memory. Learn more: Refer to the AN 033: Configuring Titanium FPGAs for information on programming the SPI flash memory. Figure 36: SPI Flash Memory Block Diagram SCLK MOSI SPI Flash Memory MISO WP_N HOLD_N CS_N Important: The SPI flash memory's VCC is connected to VCCIO1A_4B. If you are using the SPI flash memory, drive the VCCIO1A_4B with a 1.8 V supply. Table 28: SPI Flash Memory Signals (Interface to FPGA Fabric) Signal Direction Description SCLK Input Clock output to SPI flash memory. MOSI Input Data output to SPI flash memory. CS_N Input Active-low SPI flash memory chip select. WP_N Input Active-low write protect signal. HOLD_N Input Active-low hold signal. MISO Output Data input from SPI flash memory. www.efinixinc.com 46 Ti60 Data Sheet HyperRAM The Ti60 FPGA in F100S3F2 package includes a HyperRAM. The HyperRAM has a density of 256 Mbits and a clock rate of up to 200 MHz. The HyperRAM supports double-data rates of up to 400 Mbps and supports a 16 bit data bus. Figure 37: HyperRAM Block Diagram CLK HyperRAM CLK90 RWDS_OUT_HI [1:0] RWDS_OUT_LO [1:0] CLKCAL RWDS_OE [1:0] RST_N RWDS_IN_HI [1:0] CS_N RWDS_IN_LO [1:0] CK_P_HI DQ_OUT_HI [15:0] CK_P_LO DQ_OUT_LO [15:0] CK_N_HI DQ_OE [15:0] CK_N_LO DQ_IN_HI [15:0] DQ_IN_LO [15:0] Important: The HyperRAM's VCC is connected to VCCIO_2A_2B. If you are using the HyperRAM, drive the VCCIO_2A_2B with a 1.8 V supply. Table 29: HyperRAM Signals (Interface to FPGA Fabric) Signal Direction Description CLK Input HyperRAM controller clock. CLK90 Input 90 degree phase-shifted version of CLK. CLKCAL Input Calibration clock for input data. RST_N Input Active-low HyperRAM reset. CS_N Input Active-low HyperRAM chip select signal. CK_P_HI Input CK_P_LO Input CK_N_HI Input The clock provided to the HyperRAM. The clock is not required to be free-running. Registered in normal mode of DDIO. CK_N_LO Input RWDS_OUT_HI [1:0] Input RWDS_OUT_LO [1:0] Input Read/write data strobe input ports for data mask during write operation. Registered in normal mode/resync mode of DDIO. RWDS_OE [1:0] Input Read/write data strobe output enable port. RWDS_IN_HI [1:0] Output RWDS_IN_LO [1:0] Output DQ_OUT_HI [15:0] Input DQ_OUT_LO [15:0] Input DQ_OE [15:0] Input DQ_IN_HI [15:0] Output Read/write data strobe output ports for latency indication, also center-aligned reference strobe for read data. Registered in normal mode/resync mode of DDIO. DQ input ports for command, address and data. Registered in normal mode of DDIO. DQ output enable port. DQ output ports for data. www.efinixinc.com 47 Ti60 Data Sheet Signal DQ_IN_LO [15:0] Direction Description Output Single-Event Upset Detection The Ti60 FPGA has a hard block for detecting single-event upset (SEU). The SEU detection feature has two modes: • Auto mode—The Ti60 control block periodically runs SEU error checks and flags if it detects an error. You can configure the interval time between SEU checks. • Manual mode—The user design runs the check. In both modes, the user design is responsible for deciding whether to reconfigure the Ti60 when an error is detected. Learn more: For more information on using the SEU detection feature, refer to the Titanium Interfaces User Guide. Internal Reconfiguration Block The Ti60 FPGAs have built-in hardware that supports an internal reconfiguration feature. The Ti60 can reconfigure itself from a bitstream image stored in flash memory. Security Feature The Ti60 FPGA security feature includes: • Intellectual property protection using bitstream encryption with the AES-GCM-256 algorithm • Anti-tampering support using asymmetric bitstream authentication with the RSA-4096 algorithm Important: You cannot enable the Ti60 FPGA security features when using compressed bitstreams. You can enable encryption, authentication, or both. You enable the security features at the project level. www.efinixinc.com 48 Ti60 Data Sheet Figure 38: Security Flow Start Read Bitstream Bitstream Encrypted? no Read Key from Fuse yes RSA Signature AES Decryption RSA-4096 Verification Decryption Key SHA384 Hash Result Comparison Configuration Success yes Match? no Configuration Halts No User Mode End Download: Refer to the Securing Titanium Bitstreams section of the Configuring an FPGA chapter in the Efinity Software User Guide for instructions on how to enable these features. Bitstream Encryption Symmetric bitstream encryption uses a 256-bit key and the AES-GCM-256 algorithm. You create the key and then use it to encrypt the bitstream. You also need to store the key into the FPGA's fuses. During configuration, the Ti60 built-in AES-GCM-256 engine decrypts the encrypted configuration bitstream using the stored key. Without the correct key, the bitstream decryption process cannot recover the original bitstream. www.efinixinc.com 49 Ti60 Data Sheet Bitstream Authentication For bitstream authentication, you use a public/private key pair and the RSA-4096 algorithm. You create a public/private key pair and sign the bitstream with the private key. Then, you save a hashed version of the public key into fuses in the FPGA. During configuration, the FPGA validates the signature on the bitstream using the public key. If the signature is valid, the FPGA knows that the bitstream came from a trusted source and has not been altered by a third party. The FPGA continues configuring normally and goes into user mode. If the signature is invalid, the FPGA stops configuration and does not go into user mode. The private key remains on your computer and is not shared with anyone. The FPGA only has the public key: the bitstream contains the public key data and a signature, while the fuses contain a hashed public key. You can only sign the bitstream with the private key. An attacker cannot re-sign a tampered bitstream without the private key. Disabling JTAG Access Ti60 FPGA's support JTAG blocking, which disables JTAG access to the FPGA by blowing a fuse. Once the fuse is blown, you cannot perform any JTAG operation except for reading the FPGA IDCODE, reading DEVICE_STATUS, and enabling BYPASS mode. To fully secure the FPGA, you must blow the JTAG fuse. Important: Once you blow the fuse, however, you cannot use JTAG ever again in that FPGA (except for IDCODE, DEVICE_STATUS, and BYPASS). So blowing this fuse should be the very last step in your manufacturing process. www.efinixinc.com 50 Ti60 Data Sheet Power Up Sequence You must use the following power up sequence when powering Titanium FPGAs: 1. Power up VCC and VCCA_xx first. 2. When VCC and VCCA_xx are stable, power up all VCCIO and VCCAUX. There is no specific timing delay between the VCCIO pins. Important: Ensure the power ramp rate is within VCCIO/10 V/ms to 10 V/ms. 3. After all power supplies are stable, hold CRESET_N low for a duration of tCRESET_N before asserting CRESET_N from low to high to trigger active SPI programming (the FPGA loads the configuration data from an external flash device). Figure 39: Power Up Sequence VCC VCCA_xx All VCCIO VCCAUX CRESET_N tCRESET_N Max 10 ms Table 30: Connection Requirements for Unused Resources Unused Resource Pin Note HSIO Bank VCCIOxx Connect to either 1.2 V, 1.5 V, or 1.8 V. HVIO Bank VCCIO33 Connect to either 1.8 V, 2.5 V, 3.0 V, or 3.3 V. PLL VCCA_PLL Connect to VCC. Learn more: Refer to AN 030: Using the Titanium Power Estimator for detailed information on FPGA power estimation. Power Supply Current Transient You may observe an inrush current on the dedicated power rail during power-up. You must ensure that the power supplies selected in your board meets the current requirement during power-up and the estimated current during user mode. Use the Power Estimator to calculate the estimated current during user mode. Table 31: Minimum Power Supply Current Transient Power Supply VCC (7) Minimum Power Supply Current Transient Unit 500(7) mA Measured under the recommended power up sequence. For applications which require lower power, contact Efinix Support. www.efinixinc.com 51 Ti60 Data Sheet Configuration The Ti60 FPGA contains volatile Configuration RAM (CRAM). The user must configure the CRAM for the desired logic function upon power-up and before the FPGA enters normal operation. The FPGA's control block manages the configuration process and uses a bitstream to program the CRAM. The Efinity® software generates the bitstream, which is design dependent. You can configure the Ti60 FPGA(s) in active, passive, or JTAG mode. Figure 40: High-Level Configuration Options Board JTAG Interface SPI Flash Processor Microcontroller FPGA JTAG SPI Data JTAG Mode Controller SPI Active Mode Controller Control Block Configuration Manager User Logic SPI Passive Mode Controller In active mode, the FPGA controls the configuration process. The configuration clock can either be provided by an oscillator circuit within the FPGA or an external clock connected to the EXT_CONFIG_CLK pin. The bitstream is typically stored in an external serial flash device, which provides the bitstream when the FPGA requests it. The control block sends out the instruction and address to read the configuration data. First, it issues a release from power-down instruction to wake up the external SPI flash. Then, it waits for at least 30 μs before issuing a fast read command to read the content of SPI flash from address 24h’000000. In passive mode, the FPGA is the slave and relies on an external master to provide the control, bitstream, and clock for configuration. Typically the master is a microcontroller or another FPGA in active mode. The controller must wait for at least 32 μs after CRESET is deasserted before it can send the bitstream. In JTAG mode, you configure the FPGA via the JTAG interface. www.efinixinc.com 52 Ti60 Data Sheet Supported FPGA Configuration Modes Table 32: Ti60 Configuration Modes by Package Configuration Mode Active Width W64 F100S3F2 F225 X1 X2 X4 X8 Passive – – – X1 X2 X4 JTAG – X8 – – X16 – – (8) X32 – – (8) X1 Learn more: Refer to AN 033: Configuring Titanium FPGAs for more information. (8) Not supported when security mode is enabled. www.efinixinc.com 53 Ti60 Data Sheet Characteristics and Timing DC and Switching Characteristics Important: All specifications are preliminary and pending hardware characterization. Table 33: Absolute Maximum Ratings Conditions beyond those listed may cause permanent damage to the device. Device operation at the absolute maximum ratings for extended periods of time has adverse effects on the device. Symbol Description Min Max Units VCC Core power supply -0.5 1.05 V VCCIO HSIO bank power supply -0.5 1.98 V VCCA_PLL PLL analog power supply -0.5 1.05 V VCCAUX 1.8 V auxiliary power supply -0.5 1.98 V VCCIO33 HVIO bank power supply -0.5 3.6 V IIN Maximum current allowed through any I/O pin when the devices is not turned on or during power-up/down(10) – 10 mA VIN HVIO input voltage -0.5 3.63 V HSIO input voltage -0.5 1.98 V TJ Operating junction temperature -40 125 °C TSTG Storage temperature, ambient -55 150 °C (9) (10) Supply voltage specification applied to the voltage taken at the device pins with respect to ground, not at the power supply. Should not exceed a total of 100 mA per bank www.efinixinc.com 54 Ti60 Data Sheet Table 34: Recommended Operating Conditions (C3 and C4, and I3 Speed Grades)(9) Symbol Description Min Typ Max Units VCC Core power supply 0.92 0.95 0.98 V VCCIO 1.2 V I/O bank power supply 1.14 1.2 1.26 V 1.5 V I/O bank power supply 1.425 1.5 1.575 V 1.8 V I/O bank power supply 1.71 1.8 1.89 V 1.8 V I/O bank power supply 1.71 1.8 1.89 V 2.5 V I/O bank power supply 2.375 2.5 2.625 V 3.0 V I/O bank power supply 2.85 3.0 3.15 V 3.3 V I/O bank power supply 3.135 3.3 3.465 V VCCA_PLL PLL analog power supply 0.92 0.95 0.98 V VCCAUX 1.8 V auxiliary power supply 1.75 1.8 1.85 V TJCOM Operating junction temperature, commercial 0 – 85 °C TJIND Operating junction temperature, industrial -40 – 100 °C VCCIO33 Table 35: Recommended Operating Conditions (C3L, I3L, and C4L Speed Grades)(9) Symbol Description Min Typ Max Units VCC Core power supply 0.82 0.85 0.88 V VCCIO 1.2 V I/O bank power supply 1.14 1.2 1.26 V 1.5 V I/O bank power supply 1.425 1.5 1.575 V 1.8 V I/O bank power supply 1.71 1.8 1.89 V 1.8 V I/O bank power supply 1.71 1.8 1.89 V 2.5 V I/O bank power supply 2.375 2.5 2.625 V 3.0 V I/O bank power supply 2.85 3.0 3.15 V 3.3 V I/O bank power supply 3.135 3.3 3.465 V VCCA_PLL PLL analog power supply 0.82 0.85 0.88 V VCCAUX 1.8 V auxiliary power supply 1.75 1.8 1.85 V TJCOM Operating junction temperature, commercial 0 – 85 °C TJIND Operating junction temperature, industrial -40 – 100 °C VCCIO33 Table 36: Power Supply Ramp Rates Symbol tRAMP Description Power supply ramp rate for all supplies. Min Max Units VCCIO/10 10 V/ms www.efinixinc.com 55 Ti60 Data Sheet Table 37: HVIO DC Electrical Characteristics I/O Standard VIL (V) VIH (V) VOL (V) VOH (V) Min Max Min Max Max Min 3.3 V LVCMOS -0.3 0.8 2.1 3.465 0.2 VCCIO33 - 0.2 3.0 V LVCMOS -0.3 0.8 2.1 3.15 0.2 VCCIO33 - 0.2 3.3 V LVTTL -0.3 0.8 2.1 3.465 0.4 2.4 3.0 V LVTTL -0.3 0.8 2.1 3.15 0.4 2.4 2.5 V LVCMOS -0.3 0.45 1.7 2.625 0.4 2.0 1.8 V LVCMOS -0.3 0.58 1.27 1.89 0.45 VCCIO33 - 0.45 Table 38: HVIO DC Electrical Characteristics Voltage (V) Typical Hysteresis (mV) Input Leakage Current (μA) Tristate Output Leakage Current (μA) 3.3 250 ±10 ±10 2.5 (11) ±10 ±10 1.8 200 ±10 ±10 Table 39: Single-Ended I/O and Dedicated Configuration Pins Schmitt Trigger Buffer Characteristic Voltage (V) VT+ (V) Schmitt Trigger Low-toHigh Threshold VT- (V) Schmitt Trigger High-toLow Threshold Input Leakage Current (μA) Tri-State Output Leakage Current (μA) 3.3 1.73 1.32 ±10 ±10 2.5 1.37 1.01 ±10 ±10 1.8 1.05 0.71 ±10 ±10 Table 40: HSIO Pins Configured as Single-Ended I/O DC Electrical Characteristics I/O Standard VIL (V) VIH (V) VOL (V) VOH (V) Min Max Min Max Max Min 1.8 V LVCMOS -0.3 0.58 1.27 1.89 0.45 VCCIO - 0.45 1.5 V LVCMOS -0.3 0.35 * VCCIO 0.65 * VCCIO 1.575 0.25 * VCCIO 0.75 * VCCIO 1.2 V LVCMOS -0.3 0.35 * VCCIO 0.65 * VCCIO 1.26 0.25 * VCCIO 0.75 * VCCIO 1.8 V HSTL – VREF - 0.1 VREF + 0.1 – 0.4 VCCIO - 0.4 1.5 V HSTL – VREF - 0.1 VREF + 0.1 – 0.4 VCCIO - 0.4 1.2 V HSTL -0.15 VREF - 0.08 VREF + 0.08 VREF + 0.15 0.25 * VCCIO 0.75 * VCCIO 1.8 V SSTL -0.3 VREF - 0.125 VREF + 0.125 VCCIO + 0.3 VTT - 0.603 VTT + 0.603 1.5 V SSTL – VREF - 0.1 VREF + 0.1 – 0.2 * VCCIO 0.8 * VCCIO 1.2 V SSTL – VREF - 0.1 VREF + 0.1 – 0.2 * VCCIO 0.8 * VCCIO (11) Pending hardware characterization. www.efinixinc.com 56 Ti60 Data Sheet Table 41: HSIO Pins Configured as Single-Ended I/O DC Electrical Characteristics I/O Standard VREF (V) Vtt (V) Min Typ Max Min Typ Max 1.8 V HSTL 0.85 0.9 0.95 – 0.5 * VCCIO – 1.5 V HSTL 0.68 0.75 0.9 – 0.5 * VCCIO – 1.2 V HSTL 0.47 * VCCIO 0.5 * VCCIO 0.53 * VCCIO – 0.5 * VCCIO – 1.8 V SSTL 0.8333 0.9 0.969 VREF - 0.04 VREF VREF + 0.04 1.5 V SSTL 0.49 * VCCIO 0.5 * VCCIO 0.51 * VCCIO 0.49 * VCCIO 0.5 * VCCIO 0.51 * VCCIO 1.2 V SSTL 0.49 * VCCIO 0.5 * VCCIO 0.51 * VCCIO 0.49 * VCCIO 0.5 * VCCIO 0.51 * VCCIO Table 42: HSIO Pins Configured as Differential SSTL I/O Electrical Characteristics I/O Standard VSWING (DC) (V) VX(AC) (V) VSWING (AC) (V) Min Max Max Typ Max Min Max 1.8 V SSTL 0.25 VCCIO + 0.6 VCCIO/2 – 0.175 – VCCIO/2 + 0.175 0.5 VCCIO + 0.6 1.5 V SSTL 0.2 – VCCIO/2 – 0.15 – VCCIO/2 + 0.15 0.35 – 1.2 V SSTL 0.18 – VREF– 0.15 VCCIO /2 VREF + 0.15 -0.3 0.3 Table 43: HSIO Pins Configured as Differential HSTL I/O Electrical Characteristics I/O Standard VDIF (DC) (V) VX (AC) (V) VCM (DC) (V) VDIF (AC) (V) Min Max Min Typ Max Min Typ Max Min Max 1.8 V HSTL 0.2 – 0.78 – 1.12 0.78 – 1.12 0.4 – 1.5 V HSTL 0.2 – 0.68 – 0.9 0.68 – 0.9 0.4 – 1.2 V HSTL 0.16 VCCIO + 0.3 – 0.5 * VCCIO – 0.4 * VCCIO 0.5 * VCCIO 0.6 * VCCIO 0.3 VCCIO + 0.48 Table 44: HSIO Pins Configured as Single-Ended I/O DC Electrical Characteristics Voltage (V) Typical Hysteresis (mV) Input Leakage Current (μA) Tristate Output Leakage Current (μA) 1.8 200 ±10 ±10 1.5 160 ±10 ±10 1.2 140 ±10 ±10 www.efinixinc.com 57 Ti60 Data Sheet Table 45: Maximum Toggle Rate I/O I/O Standard Speed Grade Maximum Load (pF) Max Toggle Rate (Mbps) HVIO 3.0 V / 3.3 V LVTTL, 3.0 V / 3.3 V LVCMOS All 40 200 HVIO 2.5 V LVCMOS All 40 200 HVIO 1.8 V LVCMOS All 20 400 HSIO 1.8 V / 1.5 V / 1.2 V LVCMOS All 20 400 HSIO 1.8 V / 1.5 V / 1.2 V SSTL, 1.8 V / 1.5 V / 1.2 V HSTL All 5 800 HSIO LVDS I3, C4 5 1,500 C3 5 1,300 I3L, C4L 5 1,250 C3L 5 1,100 HSIO Sub-LVDS All 5 1,250 HSIO MIPI lane I3, C4 5 1,500 C3 5 1,300 I3L, C4L 5 1,250 C3L 5 1,100 Table 46: HVIO Internal Weak Pull-Up and Pull-Down Resistance I/O Standard Internal Pull-Up Internal Pull-Down Units Min Typ Max Min Typ Max 3.3 V LVTTL/LVCMOS 25 42 67 24 29 33 kΩ 3.0 V LVTTL/LVCMOS 25 42 67 24 29 33 kΩ 2.5 V LVCMOS 25 42 67 24 29 33 kΩ 1.8 V LVCMOS 25 35 45 24 29 33 kΩ Table 47: HSIO Internal Weak Pull-Up and Pull-Down Resistance CDONE and CRESET_N also have an internal weak pull-up with these values. I/O Standard Internal Pull-Up Internal Pull-Down Units Min Typ Max Min Typ Max 1.8 V LVCMOS/HSTL/SSTL 18 27 47 18 27 47 kΩ 1.5 V LVCMOS/HSTL/SSTL 22 38 65 22 38 65 kΩ 1.2 V LVCMOS/HSTL/SSTL 40 66 135 40 66 135 kΩ Table 48: Block RAM Characteristics Symbol fMAX Description Block RAM maximum frequency. Speed Grade Units C3, C4, I3 C3L, C4L, I3L 1,000 800 MHz www.efinixinc.com 58 Ti60 Data Sheet Table 49: DSP Block Characteristics Symbol fMAX Description Speed Grade Units C3, C4, I3 C3L, C4L, I3L 1,000 800 DSP block maximum frequency. MHz Table 50: Global Clock Buffer Block Characteristics Symbol fMAX Description Speed Grade Units C3, C4, I3 C3L, C4L, I3L 1,000 800 Global clock buffer block maximum frequency. MHz HSIO Electrical and Timing Specifications The HSIO pins comply with the LVDS EIA/TIA-644 electrical specifications. Important: All specifications are preliminary and pending hardware characterization. HSIO as LVDS, Sub-LVDS, Bus-LVDS, RSDS, Mini LVDS, and SLVS Table 51: HSIO Electrical Specifications when Configured as LVDS Parameter Description Test Conditions Min Typ Max Unit VCCIO LVDS transmitter voltage supply – 1.71 1.8 1.89 V VOD Output differential voltage RL = 100 Ω 200 350 450 mV Δ VOD Change in VOD – – – 50 mV VOCM Output common mode voltage – 1.125 1.2 1.375 V Δ VOCM Change in VOCM – – – 50 mV VID Input differential voltage – 100 – 600 mV VICM Input common mode voltage (fmax 1000 Mbps) – 700 – 1,400 mV Input voltage valid range – 0 – 1.89 V LVDS TX LVDS RX Vi Table 52: HSIO Timing Specifications when Configured as LVDS Parameter Description tLVDS_DT LVDS TX reference clock output duty cycle tLVDS_skew LVDS TX lane-to-lane skew Min Typ Max Unit 45 50 55 % – 200 – ps www.efinixinc.com 59 Ti60 Data Sheet Table 53: HSIO Electrical Specifications when Configured as Sub-LVDS Parameter Description Test Conditions Min Typ Max Unit VCCIO Sub-LVDS transmitter voltage supply – 1.71 1.8 1.89 V VOD Output differential voltage RL = 100 Ω 100 150 200 mV ΔVOD Change in VOD – – – 50 mV VOCM Output common mode voltage – 0.8 0.9 1.0 V ΔVOCM Change in VOCM – – – 50 mV Sub-LVDS TX Sub-LVDS RX VID Input differential voltage – 100 – 600 mV VICM Input common mode voltage – 100 – 1600 mV Vi Input voltage valid range – 0 – 1.89 V Table 54: HSIO Electrical Specifications when Configured as Bus-LVDS Parameter Description Test Conditions Min Typ Max Unit VCCIO Voltage supply for LVDS transmitter – 1.71 1.8 1.89 V VOD Differential output voltage RL = 27 Ω 200 250 300 mV ΔVOD Static difference of VOD (between 0 and 1) – – – 50 mV VOC Output common mode voltage – 1.125 1.2 1.375 V ΔVOC Output common mode voltage offset – – – 50 mV Bus-LVDS TX Bus-LVDS RX VID Differential input voltage – 100 – 600 mV VIC Differential input common mode – 100 – 1600 mV Vi Valid input voltage range – 0 – 1.89 V Table 55: HSIO Electrical Specifications when Configured as RSDS, Mini LVDS and SLVS IO standard VID (mV) VICM (mV) VOD (mV) VOCM (mV) Min Max Min Max Min Typ Max Min Typ Max RSDS 100 - 300 1400 100 200 600 500 1200 1400 Mini LVDS 200 600 400 1325 250 - 600 1000 1200 1400 SLVS 100 400 100 300 150 200 250 140 200 270 www.efinixinc.com 60 Ti60 Data Sheet HSIO as High–Speed and Low-Power MIPI Lane The MIPI transmitter and receiver lanes are compliant to the MIPI Alliance Specification for D-PHY Revision 1.1. Table 56: HSIO DC Specifications when Configured as High–Speed MIPI TX Lane Parameter Description Min Typ Max Unit VCCIO High–speed transmitter voltage supply 1.14 1.2 1.26 V VCMTX High–speed transmit static common– mode voltage 150 200 250 mV |ΔVCMTX| VCMTX mismatch when output is Differential–1 or Differential–0 – – 5 mV |VOD| High–speed transmit differential voltage 140 200 270 mV |ΔVOD| VOD mismatch when output is Differential–1 or Differential–0 – – 14 mV VOHHS High–speed output high voltage – – 360 mV VCMRX Common mode voltage for highspeed receive mode 70 – 330 mV Table 57: HSIO DC Specifications when Configured as Low–Power MIPI TX Lane Parameter Description Min Typ Max Unit VOH Thevenin output high level 1.1 1.2 1.3 V VOL Thevenin output low level -50 – 50 mV ZOLP Output impedance of low-power transmitter 110 – – Ω Table 58: HSIO DC Specifications when Configured as High–Speed MIPI RX Lane Parameter Description Min Typ Max Unit 70 – 330 mV VCMRX(DC) Common mode voltage high–speed receiver mode VIDTH Differential input high threshold – – 70 mV VIDTL Differential input low threshold -70 – – mV VIHHS Single-ended input high voltage – 460 mV VILHS Single-ended input low voltage – – mV -40 Table 59: HSIO DC Specifications when Configured as Low–Power MIPI RX Lane Parameter Description Min Typ Max Unit 880 – – mV VIH Logic 1 input voltage VIL Logic 0 input voltage, not in ULP state – – 550 mV VIL-ULPS Logic 0 input voltage, ULPS state – – 300 mV VHYST Input hysteresis 25 – – mV www.efinixinc.com 61 Ti60 Data Sheet PLL Timing and AC Characteristics The following tables describe the PLL timing and AC characteristics. Important: All specifications are preliminary and pending hardware characterization. Table 60: PLL Timing Symbol Parameter Min Typ Max Units 16 – 800 MHz FIN Input clock frequency. FOUT Output clock frequency. 0.1342 – 1,000 MHz FVCO PLL VCO frequency. 2,200 – 5,500 MHz FPLL Post-divider PLL VCO frequency. – – 4,000 MHz FPFD Phase frequency detector input frequency. 16 – 800 MHz Min Typ Max Units 45 50 55 % Table 61: PLL AC Characteristics(12) Symbol Parameter tDT Output clock duty cycle. tOPJIT (PK - PK) Output clock period jitter (PK-PK). – – 200 ps tOPJITN (PK PK)(14)(15) Output clock period jitter (PK-PK) with noisy input. – – 400 ps tINDT Input clock duty cycle. 45 – 55 % tLOCK PLL lock-in time. – 300 500 PFD(16) (13) (12) (13) (14) (15) (16) Test conditions at nominal voltage and room temperature. The output jitter specification applies to the PLL jitter when an input jitter of 20 ps is applied. The output jitter specification applies to the PLL jitter with maximum allowed input jitter of 800 ps. The period jitter is measured over 10,000 sample size with minimal core and I/O activity. PFD cycle equals to reference clock division divided by reference clock frequency. www.efinixinc.com 62 Ti60 Data Sheet Configuration Timing Important: All specifications are preliminary and pending hardware characterization. The Ti60 FPGA has the following configuration timing specifications. Note: Refer to AN 033: Configuring Titanium FPGAs for detailed configuration information. Timing Waveforms Figure 41: SPI Active Mode (x1) Timing Sequence CCK tCRESET_N CRESET_N SSL_N VCC CDI0 Read 24 bit Start Address Dummy Byte tH CDI1 Data tSU Figure 42: SPI Passive Mode (x1) Timing Sequence CCK tCRESET_N CRESET_N tCLK tDMIN SSL_N GND tCLKL tH CDI Header and Data tSU CDONE tUSER Figure 43: Boundary-Scan Timing Waveform TMS TDI tTMSSU tTDISU tTMSH TCK tTDIH TDO tTCKTDO www.efinixinc.com 63 Ti60 Data Sheet Timing Parameters Table 62: All Modes Symbol Parameter Min Typ Max Units tCRESET_N Minimum CRESET_N low pulse width required to trigger re-configuration. 1 – 100 μs tUSER Minimum configuration duration after CDONE goes high before entering user mode.(17)(18) 25 – – μs Test condition at 10 kΩ pull-up resistance and 10 pF output loading on CDONE pin. Table 63: Active Mode Symbol Frequency Min Typ Max Units DIV1 52 80 100 MHz DIV2 26 40 52 MHz DIV4 13 20 26 MHz DIV8 6.5 10 13 MHz fMAX_M_EXTCLK Active mode external configuration clock frequency. – – – 100 MHz tSU Setup time. Test condition at 1.8 V I/O standard and 0 pF output loading. – 3 – – ns tH Hold time. Test condition at 1.8 V I/O standard and 0 pF output loading. – 0 – – ns fMAX_M Parameter Active mode internal configuration clock frequency. Table 64: Passive Mode Symbol Parameter Min Typ Max Units – – 100 MHz fMAX_S Passive mode configuration clock frequency. tCLKH Configuration clock pulse width high. 4.8 – – ns tCLKL Configuration clock pulse width low. 4.8 – – ns tSU Setup time. 2 – – ns tH Hold time. 1 – – ns tDMIN Minimum time between deassertion of CRESET_N to first valid configuration data. 32 – – μs (17) (18) The FPGA may go into user mode before tUSER has elapsed. However, Efinix recommends that you keep the system interface to the FPGA in reset until tUSER has elapsed. For JTAG programming, the min tUSER configuration time is required after CDONE goes high and the FPGA receives the ENTERUSER instruction from the JTAG host (TAP controller in UPDATE_IR state). www.efinixinc.com 64 Ti60 Data Sheet Table 65: JTAG Mode Symbol Parameter Min Typ Max Units fTCK TCK frequency. – – 30 MHz tTDISU TDI setup time. 3.5 – – ns tTDIH TDI hold time. 2.5 – – ns tTMSSU TMS setup time. 3 – – ns tTMSH TMS hold time. 2.5 – – ns tTCKTDO TCK falling edge to TDO output. – – 10 ns Pinout Description The following tables describe the pinouts for power, ground, configuration, and interfaces. Table 66: Power and Ground Pinouts xx indicates the bank location. Function Description VCC Core power supply. VCCA_xx PLL analog power supply. VCCAUX 1.8 V auxiliary power supply. VCCIO33_xx HVIO bank power supply. VCCIOxx HSIO bank power supply. VCCIOxx_yy_zz Power for HSIO banks that are shorted together. xx, yy, and zz are the bank locations. For example: VCCIO1B_1C shorts banks 1B and 1C GND Ground. Table 67: GPIO Pinouts x indicates the location (T, B, L, or R); xx indicates the bank location; n indicates the number; yyyy indicates the function. Function Direction Description GPIOx_n I/O HVIO for user function. User I/O pins are single-ended. GPIOx_n_yyyy I/O HVIO or multi-function pin. GPIOx_N_n I/O HSIO transmitter, receiver, or both. GPIOx_N_n_yyyy I/O HSIO transmitter, receiver, both, or multi-function. GPIOx_P_n GPIOx_P_n_yyyy REF_RES_xx – REF_RES is a reference resistor to generate constant current for LVDS TX. Connect a 10 kΩ resistor with a tolerance of ±1% to the REF_RES pin with respect to ground. If none of the pins in a bank are used for LVDS, leave this pin floating. www.efinixinc.com 65 Ti60 Data Sheet Table 68: Alternate Function Pinouts n is the number. Function Direction Description CLKn Input Single ended input for global clock and control network resource. The number of inputs is package dependent. PLLINn Input PLL reference clock resource. The number of reference clock resources is package dependent. Table 69: Dedicated Configuration Pins These pins cannot be used as general-purpose I/O after configuration. Pins CDONE Direction Description Use External Weak PullUp During Configuration Bidirectional Configuration done status pin. CDONE is an open drain output; connect it to an external pull-up resistor to VCCIO. When CDONE = 1, configuration is complete. If you hold CDONE low, the device will not enter user mode. CRESET_N Input Initiates FPGA re-configuration (active low). Pulse CRESET_N low for a duration of tcreset_N before asserting CRESET_N from low to high to initiate FPGA re-configuration. This pin does not perform a system reset. TCK Input JTAG test clock input (TCK). The rising edge loads signals applied at the TAP input pins (TMS and TDI). The falling edge clocks out signals through the TAP TDO pin. TMS Input JTAG test mode select input (TMS). The I/O sequence on this input controls the test logic operation . The signal value typically changes on the falling edge of TCK. TMS is typically a weak pullup; when it is not driven by an external source, the test logic perceives a logic 1. TDI Input JTAG test data input (TDI). Data applied at this serial input is fed into the instruction register or into a test data register depending on the sequence previously applied at TMS. Typically, the signal applied at TDI changes state following the falling edge of TCK while the registers shift in the value received on the rising edge. Like TMS, TDI is typically a weak pull-up; when it is not driven from an external source, the test logic perceives a logic 1. TDO Output JTAG test data output (TDO). This serial output from the test logic is fed from the instruction register or from a test data register depending on the sequence previously applied at TMS. During shifting, data applied at TDI appears at TDO after a number of cycles of TCK determined by the length of the register included in the serial path. The signal driven through TDO changes state following the falling edge of TCK. When data is not being shifted through the device, TDO is set to an inactive drive state (e.g., high-impedance). (19) CDONE has a drive strength of 12 mA at 1.8 V. www.efinixinc.com 66 Ti60 Data Sheet Table 70: Dual-Purpose Configuration Pins In user mode (after configuration), you can use these dual-purpose pins as general I/O. Pins CBSEL[1:0] Direction Input Description Use External Weak PullUp During Configuration Optional multi-image selection input (if external multi-image configuration mode is enabled). CCK I/O Passive SPI input configuration clock or active SPI output configuration clock. CDIn I/O n is a number from 0 to 31 depending on the SPI configuration. (20) 0: Passive serial data input or active serial output. 1: Passive serial data output or active serial input. n: Parallel I/O. In multi-bit daisy chain connection, the CDIn (31:0) connects to the data bus in parallel. CSI Input Chip select. 0: The FPGA is not selected or enabled and will not be configured. 1: Selects the FPGA for configuration (SPI and JTAG configuration). CSO Output Chip select output. Selects the next device for cascading configuration. (21) N/A NSTATUS Output Status (active low). Indicates a configuration error. When the FPGA drives this pin low, it indicates an ID mismatch, the bitstream CRC check has failed, or remote update has failed. N/A Input Active-low configuration mode select. The FPGA senses the value of SSL_N when it comes out of reset (pulse CRESET_N low to high). SSL_N 0: Passive mode 1: Active mode In active configuration mode, SSL_N serves as a chip select to the flash device 1 (CDI0 - CDI3). SSU_N EXT_CONFIG_CLK TEST_N Input I/O Input In active configuration mode (dual quad mode), SSU_N serves as a chip select to the flash device 2 (CDI4 - CDI7). In active mode, EXT_CONFIG_CLK pin is connected from an external clock, to be used as a configuration clock. Active-low test mode enable signal. Set to 1 to disable test mode. During configuration, rely on the external weak pull-up or drive this pin high. (20) (21) Not applicable to single-image or remote update. Cascaded configuration is not supported in the F100S3F2 package. www.efinixinc.com 67 Ti60 Data Sheet Ti60 Interface Floorplan Note: The numbers in the floorplan figures indicate the HVIO and HSIO number ranges. Some packages may not have all HVIO or HSIO pins in the range bonded out. Figure 44: Floorplan Diagram for Ti60 Left Right 2A TL PLL_TL 0 2B 8 9 TR 17 11 PLL_TR 12 3 18 20 19 3A 1B Quantum Compute Fabric 9 10 I/O bank HVIO Dedicated blocks 9 PLL 3B 1A 8 0 HSIO 0 21 Dimensions not to scale 2 0 PLL_BL BL 29 0 4B 8 9 4A 17 BR PLL_BR Efinity Software Support The Efinity® software provides a complete tool flow from RTL design to bitstream generation, including synthesis, place-and-route, and timing analysis. The software has a graphical user interface (GUI) that provides a visual way to set up projects, run the tool flow, and view results. The software also has a command-line flow and Tcl command console. The Efinity® software supports simulation flows using the ModelSim, NCSim, or free iVerilog simulators. An integrated hardware Debugger with Logic Analyzer and Virtual I/O debug cores helps you probe signals in your design. The software-generated bitstream file configures the Ti60 FPGA. The software supports the Verilog HDL and VHDL languages. Ordering Codes Refer to the Titanium Selector Guide for the full listing of Ti60 ordering codes. www.efinixinc.com 68 Ti60 Data Sheet Revision History Table 71: Revision History Date April 2022 Version 2.0 Description Updated test condition load to maximum load in Maximum Toggle Rate Table. (DOC-781) Corrected description for differential TX static programmable delay. (DOC-786) Added notes about VCC requirements in SPI flash memory and HyperRAM for F100S3F2 packages. (DOC-773) Added PLL period jitter spec with noisy input clock specs and updated test condition note. (DOC-771) Updated HyperRAM clock rate and double data rate speed. (DOC-793) April 2022 1.9 Updated figure title for Connections for Clock and RX Data Lane in the Same MIPI RX Group. (DOC-739) Updated LVDS/RSDS/mini-LVDS RX supported VCCIO. (DOC-740) Updated Power Supply Current Transient and power sequence. (DOC-761) Corrected RD and RST signal directions in MIPI RX Lane Block Diagram. March 2022 1.8 Updated power supply ramp rate and power up sequence diagram. (DOC-631) Updated external pull-up requirement for dual-purpose configuration pins. (DOC-734) February 2022 1.7 Corrected tH and tSU parameter label in SPI Passive Mode (x1) Timing Sequence figure. Updated active and passive configuration timing specs. (DOC-708) Update 2.5 V LVCMOS VIH and VIL specs. (DOC-718) Added IIN and VIN specs. (DOC-652) Updated and improved clock and control network content and figures. (DOC-668) Updated MIPI and LVDS maximum toggle rate. Added note about the block RAM content is random and undefined if it is not initialized. (DOC-729) January 2022 1.6 Corrected Available Package Options. January 2022 1.5 Merged MIPI and LVDS data rate specs into Maximum Toggle Rate table. January 2022 1.4 I/O banks for HVIO pins support dynamic voltage shifting. (DOC-444) Added Schmitt Trigger input buffer specs. (DOC-606) Added PLL reference clock input duty cycle specs. (DOC-661) Updated HVIO maximum toggle rate specs. (DOC-689) Removed I4 and I4L speed grades. (DOC-681) Updated global clock buffer, DSP, BRAM, HSIO as LVDS, and HSIO as MIPI lane specs. (DOC-693) Added internal weak pull-up resistor and drive strength specs for CDONE and CRESET_N. (DOC-635) Added ambient storage temperature spec. (DOC-678) www.efinixinc.com 69 Ti60 Data Sheet Date Version November 2021 1.3 Description Updated REF_RES_xx description and resistor tolerance. (DOC-602, DOC-603, DOC-605) Added Ordering Codes topic. (DOC-637) Added SRL8 resource number. (DOC-596) Added global clock buffer block characteristics. (DOC-577) Updated power up sequence, updated power supply ramp rates, updated tCRESET_N and added power supply current transient specs. (DOC-643) November 2021 1.2 Added internal weak pull-up and pull-down specs for HVIO and HSIO. (DOC-561) Updated the SHIFT[2:0] description in PLL Signals table and Dynamic Phase Shift topic. (DOC-570) Updated note about leaving unassigned pins when using HSIO as GPIO, LVDS, or MIPI lanes. (DOC-581) Updated the Security Feature topic. (DOC-538) Added a note in the Single Event Upset Detection topic referring to the Titanium Interfaces User Guide for details on using this feature. Updated LVDS standard compliance which is TIA/EIA-644. (DOC-592) Updated F100 package name to F100S3F2. (DOC-593) October 2021 1.1 Updated the Security Feature topic. Updated DIV 2 active mode fMAX_M typical and maximum values. (DOC-509) Added FPLL specs and updated the PLL block diagram to include FPLL. (DOC-512) Added note stating that all PLL outputs lock on the negative clock edge. (DOC-511) Updated sub-LVDS maximum toggle rate. (DOC-541) Added description about CLKOUT0 limitation. (DOC-533) Updated HyperRAM double-data rates to up to 500 Mbps. (DOC-554) Added connection requirements for unused resources in Power Up Sequence topic. June 2021 1.0 Initial release. www.efinixinc.com 70