BUK9K13-40HX

BUK9K13-40H Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D 11 February 2021 Product data sheet 1. General description Dual, Logic level N-channel MOSFET in an LFPAK56D package, using Trench 9 TrenchMOS technology. This product has been designed and qualified to AEC-Q101 for use in high performance automotive applications 2. Features and benefits • • • • Fully automotive qualified to AEC-Q101 at 175 °C Trench 9 superjunction technology: • Low power losses, high power density LFPAK copper clip package technology: • High robustness and reliability • Gull wing leads for high manufacturability and AOI Repetitive avalanche rated 3. Applications • • • • 12 V, 24 V and 48 V automotive systems Motors, lamps and solenoid control Transmission control DC-to-DC conversion 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 40 V ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 - - 42 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 46 W VGS = 4.5 V; ID = 10 A; Tj = 25 °C; Fig. 11 9.8 14.1 16.9 mΩ ID = 10 A; VDS = 32 V; VGS = 5 V; Tj = 25 °C; Fig. 13; Fig. 14 - 1.8 4.2 nC IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V; [2] VDS = 20 V; Tj = 25 °C - 16.2 - nC [1] Static characteristics FET1 and FET2 RDSon drain-source on-state resistance Dynamic characteristics FET1 and FET2 QGD gate-drain charge Source-drain diode FET1 and FET2 Qr [1] [2] recovered charge 42A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. Includes capacitive recovery BUK9K13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D 5. Pinning information Table 2. Pinning information Pin Symbol Description 1 S1 source1 2 G1 gate1 3 S2 source2 4 G2 gate2 5 D2 drain2 6 D2 drain2 7 D1 drain1 8 D1 drain1 Simplified outline 8 7 6 Graphic symbol 5 D1 D1 S1 D2 D2 G1 S2 G2 mbk725 1 2 3 4 LFPAK56D; Dual LFPAK (SOT1205) 6. Ordering information Table 3. Ordering information Type number Package BUK9K13-40H Name Description Version LFPAK56D; Dual LFPAK plastic, single ended surface mounted package (LFPAK56D); 8 leads SOT1205 7. Marking Table 4. Marking codes Type number Marking code BUK9K13-40H 91340HK 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 40 V VGS gate-source voltage DC; Tj = 25 °C -20 20 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 46 W ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 - 42 A VGS = 10 V; Tmb = 100 °C; Fig. 2 - 30 A pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 [1] IDM peak drain current - 169 A Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Source-drain diode FET1 and FET2 IS source current Tmb = 25 °C - 42 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 169 A BUK9K13-40H Product data sheet All information provided in this document is subject to legal disclaimers. 11 February 2021 © Nexperia B.V. 2021. All rights reserved 2 / 12 BUK9K13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D Symbol Parameter Conditions Min Max Unit Avalanche Ruggedness FET1 and FET2 EDS(AL)S non-repetitive drainID = 39.9 A; Vsup ≤ 40 V; RGS = 50 Ω; source avalanche energy VGS = 10 V; Tj(init) = 25 °C; Fig. 4 [2] [3] - 10.6 mJ IAS non-repetitive avalanche Vsup = 40 V; VGS = 10 V; Tj(init) = 25 °C; current RGS = 50 Ω; Fig. 4 [4] - 39.9 A [1] [2] [3] [4] 42A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Refer to application note AN10273 for further information. Protected by 100% test 03aa16 120 ID (A) Pder (%) aaa-032436 50 40 80 30 20 40 10 0 Fig. 1. 0 50 100 150 Tmb (°C) 0 200 25 50 75 100 125 150 175 Tmb (°C) Normalized total power dissipation as a function of mounting base temperature Continuous drain current as a function of mounting base temperature, FET1 and FET2 aaa-032438 103 102 200 VGS ≥ 10 V 42A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. Fig. 2. ID (A) 0 Limit RDSon = VDS / ID tp = 10 µs 100 µs 10 DC 1 1 ms 10 ms 100 ms 10-1 10-1 Fig. 3. 1 10 VDS (V) 102 Safe operating area; continuous and peak drain current as a function of drain-source voltage, FET1 and FET2 BUK9K13-40H Product data sheet All information provided in this document is subject to legal disclaimers. 11 February 2021 © Nexperia B.V. 2021. All rights reserved 3 / 12 BUK9K13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D IAL (A) aaa-032437 102 (1) 10 (2) 1 (3) 10-1 10-2 10-3 10-2 10-1 1 tAL (ms) 10 (1) Tj (init) = 25 °C; (2) Tj (init) = 150 °C; (3) Repetitive Avalanche Fig. 4. Avalanche rating; avalanche current as a function of avalanche time, FET1 and FET2 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Rth(j-mb) Conditions thermal resistance from Fig. 5 junction to mounting base Min Typ Max Unit - 3 3.23 K/W aaa-032439 10 Zth(j-mb) (K/W) δ = 0.5 1 0.2 0.1 0.05 10-1 0.02 P single shot δ= Fig. 5. 10-5 10-4 10-3 10-2 T t tp 10-2 10-6 tp T 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration, FET1 and FET2 BUK9K13-40H Product data sheet All information provided in this document is subject to legal disclaimers. 11 February 2021 © Nexperia B.V. 2021. All rights reserved 4 / 12 BUK9K13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit ID = 250 µA; VGS = 0 V; Tj = 25 °C 40 43 - V ID = 250 µA; VGS = 0 V; Tj = -40 °C - 40.5 - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 36 40 - V ID = 1 mA; VDS=VGS; Tj = 25 °C; Fig. 9; Fig. 10 1.5 1.85 2.2 V ID = 1 mA; VDS=VGS; Tj = 175 °C; Fig. 10 0.7 - - V ID = 1 mA; VDS=VGS; Tj = -55 °C; Fig. 10 - - 2.6 V VDS = 40 V; VGS = 0 V; Tj = 25 °C - 0.01 5 µA VDS = 16 V; VGS = 0 V; Tj = 125 °C - 0.14 10 µA VDS = 40 V; VGS = 0 V; Tj = 175 °C - 26 500 µA VGS = -10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 16 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 10 V; ID = 10 A; Tj = 25 °C; Fig. 11 7.9 11.4 13.6 mΩ VGS = 10 V; ID = 10 A; Tj = 105 °C; Fig. 12 10.9 16 20.4 mΩ VGS = 10 V; ID = 10 A; Tj = 125 °C; Fig. 12 12 17.4 21.9 mΩ VGS = 10 V; ID = 10 A; Tj = 175 °C; Fig. 12 14.5 20.9 26.4 mΩ VGS = 4.5 V; ID = 10 A; Tj = 25 °C; Fig. 11 9.8 14.1 16.9 mΩ VGS = 4.5 V; ID = 10 A; Tj = 105 °C; Fig. 12 13.5 20 25.4 mΩ VGS = 4.5 V; ID = 10 A; Tj = 125 °C; Fig. 12 14.8 21.6 27.2 mΩ VGS = 4.5 V; ID = 10 A; Tj = 175 °C; Fig. 12 18 26.6 32.8 mΩ f = 1 MHz; Tj = 25 °C 0.7 1.8 4.2 Ω ID = 10 A; VDS = 32 V; VGS = 10 V; Tj = 25 °C; Fig. 13; Fig. 14 - 13 19.4 nC ID = 10 A; VDS = 32 V; VGS = 5 V; Tj = 25 °C; Fig. 13; Fig. 14 - 6.8 10.2 nC - 2.3 3.8 nC - 1.8 4.2 nC - 848 1160 pF - 280 420 pF - 39 84 pF - 6.5 - ns - 9.7 - ns - 10.1 - ns Static characteristics FET1 and FET2 V(BR)DSS VGS(th) IDSS IGSS RDSon RG drain-source breakdown voltage gate-source threshold voltage drain leakage current gate leakage current drain-source on-state resistance gate resistance Dynamic characteristics FET1 and FET2 QG(tot) total gate charge QGS gate-source charge QGD gate-drain charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) turn-off delay time BUK9K13-40H Product data sheet VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; Fig. 15 VDS = 32 V; RL = 3.2 Ω; VGS = 5 V; RG(ext) = 5 Ω; Tj = 25 °C All information provided in this document is subject to legal disclaimers. 11 February 2021 © Nexperia B.V. 2021. All rights reserved 5 / 12 BUK9K13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D Symbol Parameter tf fall time Conditions Min Typ Max Unit - 7.8 - ns Source-drain diode FET1 and FET2 VSD source-drain voltage IS = 10 A; VGS = 0 V; Tj = 25 °C; Fig. 16 - 0.81 1 V trr reverse recovery time - 21.5 - ns Qr recovered charge IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 20 V; Tj = 25 °C [1] - 16.2 - nC [1] Includes capacitive recovery ID (A) aaa-032440 60 10 V 48 aaa-032441 40 RDSon (mΩ) 4.5 V 3.5 V 30 36 20 24 VGS = 3 V 12 10 2.8 V 2.6 V 0 Fig. 6. ID (A) 0 1 2 3 VDS (V) 0 4 0 4 8 12 20 Tj = 25 °C Tj = 25 °C; ID = 10 A Output characteristics; drain current as a Fig. 7. function of drain-source voltage; typical values, FET1 and FET2 Drain-source on-state resistance as a function of gate-source voltage; typical values. FET1 and FET2 aaa-032442 60 aaa-029502 10-1 ID (A) 48 10-2 36 10-3 Min 175°C 12 0 Typ Max 10-4 24 10-5 Tj = -55°C 25°C 0 1 2 3 4 VGS (V) 10-6 5 VDS = 8 V Fig. 8. 16 VGS (V) Product data sheet 0.5 1 1.5 2 2.5 VGS (V) 3 Tj = 25 °C; VDS = 5 V Transfer characteristics; drain current as a function of gate-source voltage; typical values, FET1 and FET2 BUK9K13-40H 0 Fig. 9. Sub-threshold drain current as a function of gate-source voltage, FET1 and FET2 All information provided in this document is subject to legal disclaimers. 11 February 2021 © Nexperia B.V. 2021. All rights reserved 6 / 12 BUK9K13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D aaa-029503 3 VGS(th) (V) 2.5 aaa-032443 80 RDSon (mΩ) 2.8 V 64 Max 3V 2 48 Typ 1.5 Min 32 3.5 V 1 0.5 0 -60 -30 0 30 60 90 120 150 Tj (°C) 0 180 ID = 1 mA ; VDS = VGS 0 5 10 15 20 25 30 35 ID (A) 40 Fig. 11. Drain-source on-state resistance as a function of drain current; typical values, FET1 and FET2 aaa-029504 2 VGS (V) aaa-032444 10 1.7 8 VGS = 4.5 V 1.4 6 10 V 1.1 4 0.8 2 0.5 -60 VGS = 10 V Tj = 25 °C Fig. 10. Gate-source threshold voltage as a function of junction temperature, FET1 and FET2 a 4.5 V 16 -30 0 30 60 90 120 150 Tj (°C) 0 180 32 V VDS = 14 V 0 4 8 12 16 QG (nC) 20 Tj = 25 °C; ID = 10 A Fig. 12. Normalized drain-source on-state resistance factor as a function of junction temperature, FET1 and FET2 BUK9K13-40H Product data sheet Fig. 13. Gate-source voltage as a function of gate charge; typical values, FET1 and FET2 All information provided in this document is subject to legal disclaimers. 11 February 2021 © Nexperia B.V. 2021. All rights reserved 7 / 12 BUK9K13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D aaa-032445 104 C (pF) VDS ID 103 Ciss VGS(pl) Coss 102 VGS(th) VGS Crss QGS2 QGS1 QGS 10 10-1 QGD QG(tot) 10 VDS (V) 102 VGS = 0V; f = 1MHz 003aaa508 Fig. 14. Gate charge waveform definitions IS (A) 1 Fig. 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values, FET1 and FET2 aaa-032446 60 48 36 24 -55°C 12 0 175°C 0 0.2 0.4 Tj = 25°C 0.6 0.8 1 VSD (V) 1.2 VGS = 0 V Fig. 16. Source-drain (diode forward) current as a function of source-drain (diode forward) voltage; typical values FET1 and FET2 BUK9K13-40H Product data sheet All information provided in this document is subject to legal disclaimers. 11 February 2021 © Nexperia B.V. 2021. All rights reserved 8 / 12 BUK9K13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D 11. Package outline Plastic single ended surface mounted package LFPAK56D; 8 leads E SOT1205 A A b1 c1 L1 mounting base D H D1 D2 L 1 2 3 e b (8x) 4 w X c A E1 E2 A1 C θ Lp detail X 0 2.5 A max 1.05 nom min 1.02 mm 5 mm scale Dimensions Unit y C D(1) D1(1) D2 (ref) E(1) E1(1) 4.4 0.25 0.30 4.70 4.55 3.5 5.30 1.8 0.85 4.1 0.19 0.24 4.45 4.35 3.4 4.95 1.6 0.60 A1 b b1 0.1 0.50 0.0 0.35 c c1 E2 e 1.27 H L L1 Lp 6.2 1.3 0.55 0.85 5.9 0.8 0.30 0.40 w y 0.25 0.1 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. Outline version References IEC JEDEC JEITA θ 8° 0° sot1205_po European projection Issue date 14-08-21 14-10-28 SOT1205 Fig. 17. Package outline LFPAK56D; Dual LFPAK (SOT1205) BUK9K13-40H Product data sheet All information provided in this document is subject to legal disclaimers. 11 February 2021 © Nexperia B.V. 2021. All rights reserved 9 / 12 BUK9K13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D 12. Soldering Footprint information for reflow soldering of LFPAK56D package SOT1205 5.85 0.57 0.025 0.57 0.7 1.97 0.65 1.27 1.9 3.325 3.175 3.2 2.0 1.275 0.8 1.875 2.1 2.7 1.0 3.85 3.975 0.025 1.1 1.15 0.65 1.27 1.1 1.44 solder land solder land plus solder paste solder paste deposit solder resist occupied area Dimensions in mm Issue date 0.7 14-07-28 20-04-20 sot1205_fr Fig. 18. Reflow soldering footprint for LFPAK56D; Dual LFPAK (SOT1205) BUK9K13-40H Product data sheet All information provided in this document is subject to legal disclaimers. 11 February 2021 © Nexperia B.V. 2021. All rights reserved 10 / 12 BUK9K13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 13. Legal information Data sheet status Document status [1][2] Product status [3] Definition Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Applications — Applications that are described herein for any of these products are for illustrative purposes only. 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In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. 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Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or BUK9K13-40H Product data sheet All information provided in this document is subject to legal disclaimers. 11 February 2021 © Nexperia B.V. 2021. All rights reserved 11 / 12 BUK9K13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Quick reference data....................................................1 5. Pinning information......................................................2 6. Ordering information....................................................2 7. Marking.......................................................................... 2 8. Limiting values............................................................. 2 9. Thermal characteristics............................................... 4 10. Characteristics............................................................ 5 11. Package outline.......................................................... 9 12. Soldering................................................................... 10 13. Legal information......................................................11 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 11 February 2021 BUK9K13-40H Product data sheet All information provided in this document is subject to legal disclaimers. 11 February 2021 © Nexperia B.V. 2021. All rights reserved 12 / 12