PSMN029-100HLX

PSMN029-100HL N-channel 100 V, 29 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology 26 September 2022 Product data sheet 1. General description Dual logic level N-channel MOSFET in an LFPAK56D (Dual Power-SO8) package using TrenchMOS technology. 2. Features and benefits • • • • • High peak drain current IDM Copper clip and flexible Leads High operating junction temperature Tj = 175 °C Superior reliability Low body diode reverse recovery charge Qr 3. Applications • • • • • Synchronous rectifier Forward and flyback converter Industrial drive Power management system Uninterruptible Power Supply (UPS) 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 100 V ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 2 - - 30 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 68 W Tj junction temperature -55 - 175 °C VGS = 5 V; ID = 5 A; Tj = 25 °C; Fig. 12 - 25.1 29 mΩ VGS = 5 V; ID = 5 A; Tj = 175 °C; Fig. 12; Fig. 13 - 68 80 mΩ - 10.9 - nC - 29.6 - nC - - 83 mJ Static characteristics FET1 and FET2 RDSon drain-source on-state resistance Dynamic characteristics FET1 and FET2 QGD gate-drain charge QG(tot) total gate charge ID = 10 A; VDS = 80 V; VGS = 5 V; Tj = 25 °C; Fig. 14; Fig. 15 Avalanche ruggedness FET1 and FET2 EDS(AL)S non-repetitive drainsource avalanche energy ID = 30 A; Vsup ≤ 100 V; VGS = 5 V; Tj(init) = 25 °C; Fig. 4 [1] [2] PSMN029-100HL Nexperia N-channel 100 V, 29 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology Symbol Parameter Conditions Min Typ Max Unit IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 50 V; Tj = 25 °C - 50.1 - nC Source-drain diode FET1 and FET2 Qr [1] [2] recovered charge Refer to application note AN10273 for further information Single-pulse avalanche rating limited by maximum junction temperature of 175 °C 5. Pinning information Table 2. Pinning information Pin Symbol Description 1 S1 source1 2 G1 gate1 3 S2 source2 4 G2 gate2 5 D2 drain2 6 D2 drain2 7 D1 drain1 8 D1 drain1 Simplified outline 8 7 6 Graphic symbol 5 D1 D1 1 2 3 4 S1 D2 D2 G1 S2 G2 mbk725 LFPAK56D; Dual LFPAK (SOT1205) 6. Ordering information Table 3. Ordering information Type number Package PSMN029-100HL Name Description Version LFPAK56D; Dual LFPAK plastic, single ended surface mounted package (LFPAK56D); 8 leads SOT1205 7. Marking Table 4. Marking codes Type number Marking code PSMN029-100HL 29RL10H 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 100 V VDGR drain-gate voltage 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ - 100 V VGS gate-source voltage DC; Tj ≤ 175 °C -10 10 V -15 15 V Ptot total power dissipation - 68 W Pulsed; Tj ≤ 175 °C PSMN029-100HL Product data sheet Tmb = 25 °C; Fig. 1 All information provided in this document is subject to legal disclaimers. 26 September 2022 [1] [2] © Nexperia B.V. 2022. All rights reserved 2 / 12 PSMN029-100HL Nexperia N-channel 100 V, 29 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology Symbol Parameter Conditions Min Max Unit ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 2 - 30 A VGS = 5 V; Tmb = 100 °C; Fig. 2 - 21 A pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 IDM peak drain current - 118 A Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C Source-drain diode FET1 and FET2 IS source current Tmb = 25 °C - 30 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 118 A - 83 mJ Avalanche ruggedness FET1 and FET2 EDS(AL)S [1] [2] [3] [4] non-repetitive drainID = 30 A; Vsup ≤ 100 V; VGS = 5 V; source avalanche energy Tj(init) = 25 °C; Fig. 4 [3] [4] Accumulated Pulse duration up to 50 hours delivers zero defect ppm Significantly longer life times are achieved by lowering Tj and or VGS. Refer to application note AN10273 for further information Single-pulse avalanche rating limited by maximum junction temperature of 175 °C 03aa16 120 003aaj531 40 ID (A) Pder (%) 30 80 20 40 10 0 0 50 100 150 Tmb (°C) 0 200 0 50 100 150 Tmb (° C) 200 VGS ≥ 5 V Fig. 2. Fig. 1. Normalized total power dissipation as a function of mounting base temperature PSMN029-100HL Product data sheet Continuous drain current as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. 26 September 2022 © Nexperia B.V. 2022. All rights reserved 3 / 12 PSMN029-100HL Nexperia N-channel 100 V, 29 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology ID (A) 003aaj530 103 Limit RDSon = VDS / ID 102 tp = 10 us 100 us 10 DC 1 10-1 1 ms 10 ms 100 ms 1 102 10 VDS (V) 103 Tmb = 25 °C; IDM is a single pulse Fig. 3. Safe operating area; continuous and peak drain current as a function of drain-source voltage 003aaj659 104 IAL (A) 103 102 10 (1) (2) 1 10-1 (3) 10-2 10-3 10-2 10-1 1 tAL (ms) 10 (1) Tj (init) = 25 °C; (2) Tj (init) = 150 °C; (3) Repetitive Avalanche Fig. 4. Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time, FET1 and FET2 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from Fig. 5 junction to mounting base - - 2.21 K/W Rth(j-a) thermal resistance from Minimum footprint; mounted on a junction to ambient printed circuit board - 95 - K/W PSMN029-100HL Product data sheet All information provided in this document is subject to legal disclaimers. 26 September 2022 © Nexperia B.V. 2022. All rights reserved 4 / 12 PSMN029-100HL Nexperia N-channel 100 V, 29 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology 003aaj584 10 Zth(j-mb) (K/W) δ = 0.5 1 0.2 0.1 0.05 10-1 0.02 P 10-2 δ= single shot tp 10-3 Fig. 5. tp T 10-6 10-5 10-4 10-3 10-2 t T 10-1 1 tp (s) Transient thermal impedance from junction to mounting base as a function of pulse duration 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C 90 - - V ID = 250 µA; VGS = 0 V; Tj = 25 °C 100 - - V gate-source threshold voltage ID = 1 mA; VDS=VGS; Tj = 25 °C; Fig. 10; Fig. 11 1.4 1.7 2.1 V ID = 1 mA; VDS=VGS; Tj = 175 °C; Fig. 10; Fig. 11 0.5 - - V ID = 1 mA; VDS=VGS; Tj = -55 °C; Fig. 10; Fig. 11 - - 2.45 V VDS = 100 V; VGS = 0 V; Tj = 25 °C - 0.02 1 µA VDS = 100 V; VGS = 0 V; Tj = 175 °C - - 500 µA VGS = -10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 5 V; ID = 5 A; Tj = 25 °C; Fig. 12 - 25.1 29 mΩ VGS = 5 V; ID = 5 A; Tj = 175 °C; Fig. 12; Fig. 13 - 68 80 mΩ VGS = 10 V; ID = 5 A; Tj = 25 °C; Fig. 12 - 22.7 27 mΩ - 29.6 - nC - 5.6 - nC - 10.9 - nC - 2727 3637 pF - 169 203 pF - 106 145 pF - 13.4 - ns - 18.7 - ns Static characteristics FET1 and FET2 V(BR)DSS VGS(th) IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Dynamic characteristics FET1 and FET2 QG(tot) total gate charge QGS gate-source charge QGD gate-drain charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time PSMN029-100HL Product data sheet ID = 10 A; VDS = 80 V; VGS = 5 V; Tj = 25 °C; Fig. 14; Fig. 15 VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; Fig. 16 VDS = 80 V; RL = 8 Ω; VGS = 5 V; RG(ext) = 5 Ω; Tj = 25 °C All information provided in this document is subject to legal disclaimers. 26 September 2022 © Nexperia B.V. 2022. All rights reserved 5 / 12 PSMN029-100HL Nexperia N-channel 100 V, 29 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology Symbol Parameter td(off) tf Conditions Min Typ Max Unit turn-off delay time - 48 - ns fall time - 36 - ns Source-drain diode FET1 and FET2 VSD source-drain voltage IS = 15 A; VGS = 0 V; Tj = 25 °C; Fig. 17 - 0.78 1.2 V trr reverse recovery time - 32.7 - ns Qr recovered charge IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 50 V; Tj = 25 °C - 50.1 - nC 003aaj520 150 gfs (S) 003aaj521 160 ID (A) 120 120 90 80 60 30 0 0 10 20 30 ID (A) 0 40 Tj = 25 °C; VDS = 15 V Fig. 6. Tj = 175 °C 40 Fig. 7. 003aaj523 4.5 ID (A) 10 2 4 6 VGS (V) VDS = 10 V Forward transconductance as a function of drain current; typical values 45 0 Tj = 25 ° C Transfer characteristics: drain current as a function of gate-source voltage; typical values 003aaj522 100 3.5 RDSon (mΩ ) VGS (V) = 2.8 3 75 30 50 2.6 15 25 2.4 2.2 0 Fig. 8. 0 1 2 3 VDS(V) 0 4 0 10 20 V GS (V) 30 Tj = 25 °C Tj = 25 °C; ID = 5 A Output characteristics: drain current as a Fig. 9. function of drain-source voltage; typical values Drain-source on-state resistance as a function of gate-source voltage; typical values PSMN029-100HL Product data sheet All information provided in this document is subject to legal disclaimers. 26 September 2022 © Nexperia B.V. 2022. All rights reserved 6 / 12 PSMN029-100HL Nexperia N-channel 100 V, 29 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology 003aah025 3 VGS(th) (V) 2.5 003aah026 10-1 ID (A) 10-2 max 2 min 10-3 typ typ max 1.5 10-4 min 1 10-5 0.5 0 -60 0 60 120 Tj (° C) 10-6 180 ID = 1 mA; VDS = VGS 80 V GS (V) 3 003aaj820 3 a V GS (V) = 2.8 2.4 1.8 60 40 3 20 30 1.2 3.5 4.5 10 0 10 2 Fig. 11. Sub-threshold drain current as a function of gate-source voltage 003aaj528 100 2.6 1 Tj = 25 °C; VDS = 5 V Fig. 10. Gate-source threshold voltage as a function of junction temperature RDSon (mΩ ) 0 40 ID (A) 0.6 0 -60 50 0 60 120 Tj ( °C) 180 Tj = 25 °C Fig. 12. Drain-source on-state resistance as a function of drain current; typical values PSMN029-100HL Product data sheet Fig. 13. Normalized drain-source on-state resistance factor as a function of junction temperature All information provided in this document is subject to legal disclaimers. 26 September 2022 © Nexperia B.V. 2022. All rights reserved 7 / 12 PSMN029-100HL Nexperia N-channel 100 V, 29 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology 003aaj525 10 VDS VGS (V) 8 ID VDS =80 V 6 VGS(pl) 14 V 4 VGS(th) VGS 2 QGS2 QGS1 QGS 0 QGD QG(tot) 003aaa508 Fig. 14. Gate charge waveform definitions 15 30 45 QG (nC) 60 Tj = 25 °C; ID = 10 A Fig. 15. Gate-source voltage as a function of gate charge; typical values 003aaj526 104 C (pF) 0 Ciss 003aaj527 60 IS (A) 103 40 Coss 102 20 Tj = 175° C Crss 10 10-1 1 10 VDS (V) 102 0 0 0.3 Tj = 25 °C 0.6 0.9 VSD (V) 1.2 VGS = 0 V; f = 1 MHz VGS = 0 V Fig. 16. Input, output and reverse transfer capacitances Fig. 17. Source current as a function of source-drain as a function of drain-source voltage; typical voltage; typical values values PSMN029-100HL Product data sheet All information provided in this document is subject to legal disclaimers. 26 September 2022 © Nexperia B.V. 2022. All rights reserved 8 / 12 PSMN029-100HL Nexperia N-channel 100 V, 29 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology 11. Package outline Plastic single ended surface mounted package LFPAK56D; 8 leads E SOT1205 A A b1 c1 L1 mounting base D H D1 D2 L 1 2 3 e b (8x) 4 w X c A E1 E2 A1 C θ Lp detail X 0 2.5 mm 5 mm scale Dimensions Unit y C A max 1.05 nom min 1.02 D(1) D1(1) D2 (ref) E(1) E1(1) 4.4 0.25 0.30 4.70 4.55 3.5 5.30 1.8 0.85 4.1 0.19 0.24 4.45 4.35 3.4 4.95 1.6 0.60 A1 b b1 0.1 0.50 0.0 0.35 c c1 E2 e 1.27 H L L1 Lp 6.2 1.3 0.55 0.85 5.9 0.8 0.30 0.40 w y 0.25 0.1 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. Outline version References IEC JEDEC JEITA θ 8° 0° sot1205_po European projection Issue date 14-08-21 14-10-28 SOT1205 Fig. 18. Package outline LFPAK56D; Dual LFPAK (SOT1205) PSMN029-100HL Product data sheet All information provided in this document is subject to legal disclaimers. 26 September 2022 © Nexperia B.V. 2022. All rights reserved 9 / 12 PSMN029-100HL Nexperia N-channel 100 V, 29 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology 12. Soldering Footprint information for reflow soldering of LFPAK56D package SOT1205 5.85 0.57 0.025 0.57 0.7 1.97 0.65 1.27 1.9 3.325 3.175 3.2 2.0 1.275 0.8 1.875 2.1 2.7 1.0 3.85 3.975 0.025 1.1 1.15 0.65 1.27 1.1 1.44 solder land solder land plus solder paste solder paste deposit solder resist occupied area Dimensions in mm Issue date 0.7 14-07-28 20-04-20 sot1205_fr Fig. 19. Reflow soldering footprint for LFPAK56D; Dual LFPAK (SOT1205) PSMN029-100HL Product data sheet All information provided in this document is subject to legal disclaimers. 26 September 2022 © Nexperia B.V. 2022. All rights reserved 10 / 12 PSMN029-100HL Nexperia N-channel 100 V, 29 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology 13. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. 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The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. 26 September 2022 © Nexperia B.V. 2022. All rights reserved 11 / 12 PSMN029-100HL Nexperia N-channel 100 V, 29 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Quick reference data....................................................1 5. Pinning information......................................................2 6. Ordering information....................................................2 7. Marking.......................................................................... 2 8. Limiting values............................................................. 2 9. Thermal characteristics............................................... 4 10. Characteristics............................................................ 5 11. Package outline.......................................................... 9 12. Soldering................................................................... 10 13. Legal information......................................................11 © Nexperia B.V. 2022. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 26 September 2022 PSMN029-100HL Product data sheet All information provided in this document is subject to legal disclaimers. 26 September 2022 © Nexperia B.V. 2022. All rights reserved 12 / 12