BUK9V13-40HX

BUK9V13-40H Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) 9 May 2023 Product data sheet 1. General description Dual, logic level N-channel MOSFET in an LFPAK56D package (half-bridge configuration), using Trench 9 TrenchMOS technology. This product has been designed and qualified to AEC-Q101. An internal connection is made between the source (S1) of the highside FET to the drain (D2) of the low-side FET, making the device ideal to use as a half-bridge switch in high-performance automotive PWM applications. D1 G1 S1, D2 G2 S2 aaa-028081 2. Features and benefits • • • • LFPAK56D package with half-bridge configuration enables: • Reduced PCB layout complexity • PCB shrinkage through reduced component footprint for 3-phase motor drive • Improved system level Rth(j-amb) due to optimized package design • Lower parasitic inductance to support higher efficiency • Footprint compatibility with LFPAK56D Dual package Advanced AEC-Q101 grade Trench 9 silicon technology: • Low power losses, high power density • Superior avalanche performance • Repetitive avalanche rated LFPAK copper clip packaging provides high robustness and reliability Gull wing leads support high manufacturability and Automated Optical Inspection (AOI) 3. Applications • • • • • 12 V automotive systems Powertrain, chassis, body and infotainment applications Brushless or brushed DC motor drive DC-to-DC systems LED lighting 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit - - 40 V - - 42 A - - 46 W Limiting values FET1 and FET2 VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 Ptot total power dissipation Tmb = 25 °C; Fig. 1 [1] BUK9V13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) Symbol Parameter Conditions Min Typ Max Unit VGS = 10 V; ID = 10 A; Tj = 25 °C; Fig. 11 7.9 11.35 13.6 mΩ ID = 10 A; VDS = 32 V; VGS = 5 V; Tj = 25 °C; Fig. 13; Fig. 14 - 2.1 4.2 nC IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V; [2] VDS = 20 V; Tj = 25 °C - 16.2 - nC Static characteristics FET1 and FET2 RDSon drain-source on-state resistance Dynamic characteristics FET1 and FET2 QGD gate-drain charge Source-drain diode FET1 and FET2 Qr [1] [2] recovered charge 42A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. includes capacitive recovery 5. Pinning information Table 2. Pinning information Pin Symbol Description 1 S2 source2 2 G2 gate2 3 S1, D2 source1, drain2 4 G1 gate1 5 D1 drain1 6 D1 drain1 7 S1, D2 source1, drain2 8 S1, D2 source1, drain2 Simplified outline 8 7 6 Graphic symbol 5 D1 G1 S1, D2 G2 1 2 3 4 LFPAK56D; Dual LFPAK (SOT1205) S2 aaa-028081 6. Ordering information Table 3. Ordering information Type number Package BUK9V13-40H Name Description Version LFPAK56D; Dual LFPAK plastic, single ended surface mounted package (LFPAK56D); 8 leads SOT1205 7. Marking Table 4. Marking codes Type number Marking code BUK9V13-40H 9V1340H BUK9V13-40H Product data sheet All information provided in this document is subject to legal disclaimers. 9 May 2023 © Nexperia B.V. 2023. All rights reserved 2 / 13 BUK9V13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Limiting values FET1 and FET2 VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 40 V VGS gate-source voltage DC; Tj = 25 °C -20 20 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 46 W ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 - 42 A VGS = 10 V; Tmb = 100 °C; Fig. 2 - 30 A pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 - 169 A [1] IDM peak drain current Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Source-drain diode FET1 and FET2 IS source current Tmb = 25 °C - 42 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 169 A Avalanche ruggedness FET1 and FET2 EDS(AL)S non-repetitive drainID = 39.9 A; Vsup ≤ 40 V; RGS = 50 Ω; source avalanche energy VGS = 10 V; Tj(init) = 25 °C; Fig. 4 [2] [3] - 10.6 mJ IAS non-repetitive avalanche Vsup = 40 V; VGS = 10 V; Tj(init) = 25 °C; current RGS = 50 Ω; Fig. 4 [4] - 39.9 A [1] [2] [3] [4] 42A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Refer to application note AN10273 for further information. Protected by 100% test 03aa16 120 ID (A) Pder (%) aaa-032340 50 40 80 30 20 40 10 0 Fig. 1. 0 50 100 150 Tmb (°C) 0 200 Fig. 2. Product data sheet 25 50 75 100 125 150 175 Tmb (°C) 200 VGS ≥ 10 V 42A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. Normalized total power dissipation as a function of mounting base temperature BUK9V13-40H 0 Continuous drain current as a function of mounting base temperature, FET1 and FET2 All information provided in this document is subject to legal disclaimers. 9 May 2023 © Nexperia B.V. 2023. All rights reserved 3 / 13 BUK9V13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) ID (A) aaa-032342 103 Limit RDSon = VDS / ID 102 tp = 10 µs 100 µs 10 DC 1 1 ms 10 ms 100 ms 10-1 10-1 1 10 VDS (V) 102 Tmb = 25 °C; IDM is a single pulse Fig. 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage, FET1 and FET2 IAL (A) aaa-032341 102 (1) 10 (2) 1 (3) 10-1 10-2 10-3 10-2 10-1 1 tAL (ms) 10 (1) Tj (init) = 25 °C; (2) Tj (init) = 150 °C; (3) Repetitive Avalanche Fig. 4. Avalanche rating; avalanche current as a function of avalanche time, FET1 and FET2 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Rth(j-mb) Conditions thermal resistance from Fig. 5 junction to mounting base BUK9V13-40H Product data sheet All information provided in this document is subject to legal disclaimers. 9 May 2023 Min Typ Max Unit - 3 3.23 K/W © Nexperia B.V. 2023. All rights reserved 4 / 13 BUK9V13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) aaa-032343 10 Zth(j-mb) (K/W) δ = 0.5 1 0.2 0.1 0.05 10-1 0.02 P single shot δ= Fig. 5. 10-5 10-4 10-3 10-2 T t tp 10-2 10-6 tp T 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration, FET1 and FET2 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit ID = 250 µA; VGS = 0 V; Tj = 25 °C 40 43 - V ID = 250 µA; VGS = 0 V; Tj = -40 °C - 40.5 - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 36 40 - V ID = 1 mA; VDS=VGS; Tj = 25 °C; Fig. 9; Fig. 10 1.5 1.85 2.2 V ID = 1 mA; VDS=VGS; Tj = 175 °C; Fig. 10 0.7 - - V ID = 1 mA; VDS=VGS; Tj = -55 °C; Fig. 10 - - 2.6 V VDS = 40 V; VGS = 0 V; Tj = 25 °C - 0.01 5 µA VDS = 16 V; VGS = 0 V; Tj = 125 °C - 0.14 10 µA VDS = 40 V; VGS = 0 V; Tj = 175 °C - 26 500 µA VGS = 16 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = -10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA Static characteristics FET1 and FET2 V(BR)DSS VGS(th) IDSS IGSS drain-source breakdown voltage gate-source threshold voltage drain leakage current gate leakage current BUK9V13-40H Product data sheet All information provided in this document is subject to legal disclaimers. 9 May 2023 © Nexperia B.V. 2023. All rights reserved 5 / 13 BUK9V13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) Symbol Parameter Conditions Min Typ Max Unit RDSon drain-source on-state resistance VGS = 10 V; ID = 10 A; Tj = 25 °C; Fig. 11 7.9 11.35 13.6 mΩ VGS = 10 V; ID = 10 A; Tj = 105 °C; Fig. 12 10.9 16.87 20.4 mΩ VGS = 10 V; ID = 10 A; Tj = 125 °C; Fig. 12 12 18.2 21.9 mΩ VGS = 10 V; ID = 10 A; Tj = 175 °C; Fig. 12 14.5 21.97 26.4 mΩ VGS = 4.5 V; ID = 10 A; Tj = 25 °C; Fig. 11 9.8 14.04 16.9 mΩ VGS = 4.5 V; ID = 10 A; Tj = 105 °C; Fig. 12 13.5 20.6 25.4 mΩ VGS = 4.5 V; ID = 10 A; Tj = 125 °C; Fig. 12 14.8 22.24 27.2 mΩ VGS = 4.5 V; ID = 10 A; Tj = 175 °C; Fig. 12 18 26.65 32.8 mΩ f = 1 MHz; Tj = 25 °C 0.7 1.7 4.2 Ω ID = 10 A; VDS = 32 V; VGS = 10 V; Tj = 25 °C; Fig. 13; Fig. 14 - 13.9 19.4 nC ID = 10 A; VDS = 32 V; VGS = 5 V; Tj = 25 °C; Fig. 13; Fig. 14 - 7.3 10.2 nC - 2.5 3.8 nC - 2.1 4.2 nC - 829 1160 pF - 280 420 pF - 38 84 pF - 5.6 - ns - 8.1 - ns RG gate resistance Dynamic characteristics FET1 and FET2 QG(tot) total gate charge QGS gate-source charge QGD gate-drain charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) turn-off delay time - 9.1 - ns tf fall time - 6.5 - ns VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; Fig. 15 VDS = 30 V; RL = 3 Ω; VGS = 5 V; RG(ext) = 5 Ω; Tj = 25 °C Source-drain diode FET1 and FET2 VSD source-drain voltage IS = 10 A; VGS = 0 V; Tj = 25 °C; Fig. 16 - 0.84 1 V trr reverse recovery time - 21.5 - ns Qr recovered charge IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 20 V; Tj = 25 °C [1] - 16.2 - nC [1] includes capacitive recovery BUK9V13-40H Product data sheet All information provided in this document is subject to legal disclaimers. 9 May 2023 © Nexperia B.V. 2023. All rights reserved 6 / 13 BUK9V13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) ID (A) aaa-032344 60 10 V 4.5 V 48 aaa-032345 30 RDSon (mΩ) 25 3.5 V 20 36 15 24 VGS = 3 V 10 2.8 V 5 12 2.6 V 0 Fig. 6. ID (A) 0 1 2 3 VDS (V) 0 4 0 4 8 12 20 Tj = 25 °C Tj = 25 °C; ID = 10 A Output characteristics; drain current as a Fig. 7. function of drain-source voltage; typical values, FET1 and FET2 Drain-source on-state resistance as a function of gate-source voltage; typical values, FET1 and FET2 aaa-032346 60 aaa-029502 10-1 ID (A) 48 10-2 36 10-3 Min 12 0 Typ Max 10-4 24 175°C 0 1 2 25°C 3 10-5 Tj = -55°C 4 VGS (V) 10-6 5 VDS = 8 V Fig. 8. 16 VGS (V) Product data sheet 0.5 1 1.5 2 2.5 VGS (V) 3 Tj = 25 °C; VDS = 5 V Transfer characteristics; drain current as a function of gate-source voltage; typical values, FET1 and FET2 BUK9V13-40H 0 Fig. 9. Sub-threshold drain current as a function of gate-source voltage, FET1 and FET2 All information provided in this document is subject to legal disclaimers. 9 May 2023 © Nexperia B.V. 2023. All rights reserved 7 / 13 BUK9V13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) aaa-029503 3 VGS(th) (V) 2.5 aaa-032347 80 RDSon (mΩ) 2.8 V 3V 64 Max 2 48 Typ 1.5 Min 32 3.5 V 1 4.5 V 16 0.5 VGS = 10 V 0 -60 -30 0 30 60 90 120 150 Tj (°C) 0 180 ID = 1 mA ; VDS = VGS 6 12 18 24 30 ID (A) 36 Tj = 25 °C Fig. 10. Gate-source threshold voltage as a function of junction temperature, FET1 and FET2 Fig. 11. Drain-source on-state resistance as a function of drain current; typical values, FET1 and FET2 aaa-029504 2 a 0 VGS (V) 1.7 aaa-032348 10 8 VGS = 4.5 V 1.4 6 10 V 1.1 32 V 4 VDS = 14 V 0.8 0.5 -60 2 -30 0 30 60 90 120 150 Tj (°C) 0 180 0 4 8 12 16 QG (nC) 20 Tj = 25 °C; ID = 10 A Fig. 12. Normalized drain-source on-state resistance factor as a function of junction temperature, FET1 and FET2 BUK9V13-40H Product data sheet Fig. 13. Gate-source voltage as a function of gate charge; typical values, FET1 and FET2 All information provided in this document is subject to legal disclaimers. 9 May 2023 © Nexperia B.V. 2023. All rights reserved 8 / 13 BUK9V13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) aaa-032349 104 C (pF) VDS ID 103 Ciss VGS(pl) Coss 102 VGS(th) VGS Crss Q GS2 QGS1 Q GS 10 10-1 QGD QG(tot) 10 VDS (V) 102 VGS = 0 V; f = 1 MHz 003aaa508 Fig. 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values, FET1 and FET2 Fig. 14. Gate charge waveform definitions IS (A) 1 aaa-032350 60 48 36 24 -55°C 12 175°C Tj = 25°C 0 0 0.2 0.4 0.6 0.8 1 VSD (V) 1.2 VGS = 0 V Fig. 16. Source-drain (diode forward) current as a function of source-drain (diode forward) voltage; typical values, FET1 and FET2 BUK9V13-40H Product data sheet All information provided in this document is subject to legal disclaimers. 9 May 2023 © Nexperia B.V. 2023. All rights reserved 9 / 13 BUK9V13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) 11. Package outline Plastic single ended surface mounted package LFPAK56D; 8 leads E SOT1205 A A b1 c1 L1 mounting base D H D1 D2 L 1 2 3 e b (8x) 4 w X c A E1 E2 A1 C θ Lp detail X 0 2.5 A max 1.05 nom min 1.02 mm 5 mm scale Dimensions Unit y C D(1) D1(1) D2 (ref) E(1) E1(1) 4.4 0.25 0.30 4.70 4.55 3.5 5.30 1.8 0.85 4.1 0.19 0.24 4.45 4.35 3.4 4.95 1.6 0.60 A1 b b1 0.1 0.50 0.0 0.35 c c1 E2 e 1.27 H L L1 Lp 6.2 1.3 0.55 0.85 5.9 0.8 0.30 0.40 w y 0.25 0.1 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. Outline version References IEC JEDEC JEITA θ 8° 0° sot1205_po European projection Issue date 14-08-21 14-10-28 SOT1205 Fig. 17. Package outline LFPAK56D; Dual LFPAK (SOT1205) BUK9V13-40H Product data sheet All information provided in this document is subject to legal disclaimers. 9 May 2023 © Nexperia B.V. 2023. All rights reserved 10 / 13 BUK9V13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) 12. Soldering Footprint information for reflow soldering of LFPAK56D package SOT1205 5.85 0.57 0.025 0.57 0.7 1.97 0.65 1.27 1.9 3.325 3.175 3.2 2.0 1.275 0.8 1.875 2.1 2.7 1.0 3.85 3.975 0.025 1.1 1.15 0.65 1.27 1.1 1.44 solder land solder land plus solder paste solder paste deposit solder resist occupied area Dimensions in mm Issue date 0.7 14-07-28 20-04-20 sot1205_fr Fig. 18. Reflow soldering footprint for LFPAK56D; Dual LFPAK (SOT1205) BUK9V13-40H Product data sheet All information provided in this document is subject to legal disclaimers. 9 May 2023 © Nexperia B.V. 2023. All rights reserved 11 / 13 BUK9V13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 13. Legal information Data sheet status Document status [1][2] Product status [3] Definition Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. 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Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or BUK9V13-40H Product data sheet All information provided in this document is subject to legal disclaimers. 9 May 2023 © Nexperia B.V. 2023. All rights reserved 12 / 13 BUK9V13-40H Nexperia Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Quick reference data....................................................1 5. Pinning information......................................................2 6. Ordering information....................................................2 7. Marking.......................................................................... 2 8. Limiting values............................................................. 3 9. Thermal characteristics............................................... 4 10. Characteristics............................................................ 5 11. Package outline........................................................ 10 12. Soldering................................................................... 11 13. Legal information......................................................12 © Nexperia B.V. 2023. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 9 May 2023 BUK9V13-40H Product data sheet All information provided in this document is subject to legal disclaimers. 9 May 2023 © Nexperia B.V. 2023. All rights reserved 13 / 13