nPM1100
Product Specification
v1.2
4445_367 v1.2 / 2022-10-07
nPM1100
nPM1100 is an integrated Power Management IC (PMIC) with a linear-mode lithium-ion/lithium-polymer
battery charger in a compact 2.1x2.1 mm WLCSP package. It has a highly efficient DC/DC buck regulator
with configurable dual mode output.
nPM1100 is an extremely compact PMIC device, created for space constrained applications that have
a small lithium-ion or lithium-polymer battery. It is compatible with all nRF52 and nRF53 Series SoCs,
supports charging batteries at up to 400 mA through USB, and delivers up to 150 mA of current to power
external components with regulated voltage.
A minimum of five passive components are required for operation. It is the perfect companion for nRF52
and nRF53 multiprotocol SoCs in battery powered designs and the device functions without a control
interface. Low quiescent current (IQ) extends battery life for shipping and storage with Ship mode, or in
operation using auto-controlled hysteretic buck mode for high efficiency down to 1 µA loads. Charge and
error indication LED drivers are built in. Charge profile limits are configurable and VBUS current limits can
be fixed or auto-controlled with on-chip USB port detection.
•
•
•
•
Ultra-high efficiency prolongs battery life or allows for use of smaller and less costly batteries
Small solution size leaves space for additional features without increasing product size
No software control
Automatic USB port detection minimizes development time
VBUS
DD+
ISET
SYSREG
VINT
VSYS
System
regulator
DEC
SW
VBAT
VOUTB
BUCK
NTC
DC/DC
converter
+
AVSS
BATTERY PACK
VTERMSET
ICHG
VOUTBSET1
MODE
PVSS
CHARGER
400 mA Li-Ion
charger
CHG
ERR
SHPACT
SHPHLD
Figure 1: nPM1100 block diagram
4445_367 v1.2
VOUTBSET0
ii
Feature list
Features:
•
400 mA linear battery charger
•
1.8 V to 3.0 V, 150 mA step-down buck regulator
•
Linear charger for lithium-ion/lithium-polymer batteries
•
Step-down buck regulator with up to 92% efficiency
•
Adjustable charge current from 20 mA to 400 mA
•
Automatic transition between hysteretic and pulse width
•
Selectable termination voltage of 4.1 V or 4.2 V
•
Automatic trickle, constant current, and constant voltage charging
•
Forced PWM mode for clean power operation
•
Battery thermal protection
•
Pin-selectable output voltage (1.8 V, 2.1 V, 2.7 V, 3.0 V)
•
Discharge current limitation
•
Soft start-up
•
JEITA compliant
modulation (PWM) modes
•
LED drivers for charger state indication
•
Li-ion/Li-polymer USB battery charger with a high efficiency buck regulator
•
5 mA low side LED driver for charging indication
•
800 nA - Typical quiescent current
•
5 mA low side LED driver for error indication
•
460 nA - Shipping mode quiescent current
•
2.3 V to 4.35 V battery operating input range
•
Thermal protection
•
2.1x2.1 mm WLCSP package
•
Input regulator
•
USB compatible current limit of 100 mA and 500 mA
•
4.1 V to 6.7 V input voltage range for normal operation
•
20 V overvoltage protection
•
Reverse current protection
•
3.0 V to 5.5 V system voltage output
•
USB port detection supporting the following types:
•
SDP
•
CDP/DCP
•
Suitable for two layer PCB design
Applications:
•
Advanced wearables
•
•
•
Health/fitness sensor and monitor devices
Advanced computer peripherals and I/O devices
•
Mouse
•
Keyboard
•
Multi-touch trackpad
4445_367 v1.2
iii
Interactive entertainment devices
•
Remote controls
•
Gaming controllers
Contents
nPM1100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ii
Feature list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
1
Revision history.
6
2
About this document.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
2.1 Document status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Core component chapters. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
7
Product overview.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
3.1 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 In circuit configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 System description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Power-on reset (POR) and brownout reset (BOR). . . . . . . . . . . . . . . . . . .
3.4 DPPM — Dynamic power-path management. . . . . . . . . . . . . . . . . . . . .
3.5 Using Ship mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Thermal protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Battery considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Charging and Error LED drivers. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 System electrical parameters. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 System efficiency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
8
9
10
10
10
11
11
11
11
12
4
Absolute maximum ratings.
13
5
Recommended operating conditions.
3
6
. . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .
14
5.1 Dissipation ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 WLCSP light sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
Core components.
15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 SYSREG — System regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.1 USB port detection and VBUS current limiting. . . . . . . . . . . . . . . . . . .
6.1.2 SYSREG resistance and output voltage. . . . . . . . . . . . . . . . . . . . . .
6.1.3 VBUS overvoltage and undervoltage protection. . . . . . . . . . . . . . . . . .
6.1.4 VBUS disconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.5 Electrical specification. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.6 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 CHARGER — Battery charger. . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.1 Charging cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.2 Termination voltage (VTERMSET). . . . . . . . . . . . . . . . . . . . . . . .
6.2.3 Termination and trickle charge current. . . . . . . . . . . . . . . . . . . . . .
6.2.4 Charge current limit (ICHG). . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.5 Battery thermal protection using NTC thermistor (NTC). . . . . . . . . . . . . . .
6.2.6 Charger thermal regulation. . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.7 Charger error conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.8 Charging indication (CHG) and charging error indication (ERR). . . . . . . . . . . .
6.2.9 DPPM — Dynamic power-path management. . . . . . . . . . . . . . . . . . .
6.2.10 Electrical specification. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4445_367 v1.2
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15
15
16
16
16
16
17
19
19
20
21
21
21
22
22
22
23
24
7
8
9
6.2.11 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 BUCK — Buck regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.1 Output voltage selection (VOUTBSET0, VOUTBSET1). . . . . . . . . . . . . . . .
6.3.2 BUCK mode selection (MODE). . . . . . . . . . . . . . . . . . . . . . . . .
6.3.3 Component selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.4 Electrical specification. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.5 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
28
29
29
29
30
31
Application.
39
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Supplying from BUCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 USB port negotiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 Charging and error states. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 Termination voltage and current. . . . . . . . . . . . . . . . . . . . . . . . . .
7.6 NTC configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7 Ship mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8 Battery monitoring and low battery indication. . . . . . . . . . . . . . . . . . . .
39
39
40
40
40
40
40
41
Hardware and layout.
42
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 Ball assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Mechanical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.1 WLCSP 2.075x2.075 mm package. . . . . . . . . . . . . . . . . . . . . . . .
8.3 Reference circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.1 Configuration 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.2 Configuration 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.3 Configuration 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.4 PCB guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.5 PCB layout example. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
43
43
44
45
46
46
47
47
Ordering information.
49
9.1
9.2
9.3
9.4
9.5
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
IC marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Box labels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Order code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Code ranges and values. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 Legal notices.
4445_367 v1.2
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v
49
49
50
51
52
54
1
Revision history
Date
October 2022
Version
Description
1.2
The following has been added or updated:
• Capacitor on VBAT in the following chapters:
• Block diagram on page 8
• Schematic on page 39
• Reference circuitry on page 44
• Absolute Maximum Ratings – MSL value
• Editorial
June 2022
1.1
The following has been added or updated:
• Ordering code for latest revision in Product
options on page 52, build code C00 no
longer supported
• Editorial
May 2021
4445_367 v1.2
1.0
First release
6
2
About this document
This document is organized into chapters that are based on the modules available in the IC.
2.1 Document status
The document status reflects the level of maturity of the document.
Document name
Description
Objective Product Specification (OPS)
Applies to document versions up to 1.0.
This document contains target specifications for
product development.
Product Specification (PS)
Applies to document versions 1.0 and higher.
This document contains final product
specifications. Nordic Semiconductor ASA reserves
the right to make changes at any time without
notice in order to improve design and supply the
best possible product.
Table 1: Defined document names
2.2 Core component chapters
Every core component has a unique capitalized name or an abbreviation of its name, e.g. LED, used for
identification and reference. This name is used in chapter headings and references, and it will appear in
the C-code header file to identify the component.
The core component instance name, which is different from the core component name, is constructed
using the core component name followed by a numbered postfix, starting with 0, for example, LED0.
A postfix is normally only used if a core component can be instantiated more than once. The core
component instance name is also used in the C-code header file to identify the core component instance.
The chapters describing core components may include the following information:
• A detailed functional description of the core component
• Register configuration for the core component
• Electrical specification tables, containing performance data which apply for the operating conditions
described in Recommended operating conditions on page 14.
4445_367 v1.2
7
3
Product overview
This chapter contains an overview of the main features found in nPM1100.
3.1 Block diagram
The block diagram illustrates the overall system.
VBUS
DD+
ISET
SYSREG
VINT
VSYS
System
regulator
DEC
SW
VBAT
VOUTB
BUCK
NTC
DC/DC
converter
+
AVSS
BATTERY PACK
VTERMSET
ICHG
VOUTBSET0
VOUTBSET1
MODE
PVSS
CHARGER
400 mA Li-Ion
charger
CHG
ERR
SHPACT
SHPHLD
Figure 2: Block diagram
3.1.1 In circuit configurations
The device is configurable for different applications and battery characteristics through input pins.
Static input pins must be configured before power-on reset. Dynamic input pins may be modified during
operation under conditions described in references. For the full list of pins, see Pin assignments on page
42.
4445_367 v1.2
8
Product overview
Pin
Function
Input type
VTERMSET
Sets termination voltage Static (H/L)
Battery dependent
Usage reference
Termination voltage
(VTERMSET) on page
20
ICHG
Charge current limit
Static (resistor)
Charge current limit
(ICHG) on page 21
ISET
VBUS current limit
Dynamic (H/L)
VBUS current limit ISET
MODE
BUCK PWM mode
override
Dynamic (H/L)
BUCK mode selection
(MODE) on page 29
VOUTBSET[n]
Two pin VOUTB voltage
configuration
Static (H/L)
Output voltage
selection (VOUTBSET0,
VOUTBSET1) on page
29
SHPACT
Enables Ship mode
Dynamic (H/L)1
Using Ship mode on
page 10
SHPHLD
Disables Ship mode
Dynamic (H/L)1
Using Ship mode on
page 10
Table 2: In circuit configurations
1
These pins are level and hold-time controlled.
3.2 System description
The device has the following core components that are described in detail in the respective chapters.
• SYSREG — System regulator on page 15
• CHARGER — Battery charger on page 19
• BUCK — Buck regulator on page 28
The system regulator (SYSREG) is a 5 V LDO supplied by VBUS. It generates VINT when enabled. VINT is the
internal supply for the device and available on an external pin, VSYS. SYSREG supports a wide operating
voltage range on VBUS, tolerates transient voltages up to 20 V, and implements overvoltage protection.
SYSREG also implements configurable current limiting from VBUS, and USB port detection. When VBUS
is disconnected, SYSREG ensures the device enters Ultra-Low Power mode to minimize quiescent current.
Reverse current protection is enabled when VBUS VBAT(V) + VDROPOUT_VBUS. If this condition is not met the charge cycle stops.
4445_367 v1.2
19
Core components
VBUS connect event
Battery detection
Battery detected
Trickle charging
VBAT ≥ V TRICKLEFAST
Fast charging
VBAT ≥ V TERM
Constant voltage charging
IBAT ≤ I TERM
Charging complete
VBAT < V RECHARGE
Figure 9: Charging cycle flow chart
V
I
VTERM
VTRICKLE_FAST
ICHGLIM
ITRICKLE
ITERM
t
Trickle
charge
Fast charge
Constant voltage charge Charging complete
Figure 10: Charging cycle
6.2.2 Termination voltage (VTERMSET)
The termination voltage, VTERM, is set using VTERMSET to support two values of battery charging
termination voltage.
4445_367 v1.2
20
Core components
VTERMSET
VTERM threshold
LOW
4.1 V
HIGH
4.2 V
Table 10: VTERMSET
6.2.3 Termination and trickle charge current
Termination current and trickle charge current are set to a percentage of the charge current limit (ICHGLIM).
See Electrical specification on page 24 for the limits.
6.2.4 Charge current limit (ICHG)
The charge current limit is set between 20 mA and 400 mA by connecting the RICHG resistor to the ICHG
and AVSS pins.
The following equation gives the resistance to be connected based on the ICHGLIM.
The following apply when the RICHG resistor is between 0 Ω and 30 kΩ.
• ICHGLIM is the fast charge current limit in Amps
• RICHG is the resistance to be connected between the ICHG and AVSS pins in Ω
Common values are provided in the following table.
RICHG resistor value
Nominal charge current limit,
ICHGLIM
Error
0 (short to AVSS)
400 mA
± ICHGACC%
1.5 kΩ
200 mA
± (ICHGACC + RICHGACC)%
4.7 kΩ
100 mA
± (ICHGACC + RICHGACC)%
11 kΩ
50 mA
± (ICHGACC + RICHGACC)%
30 kΩ
20 mA
± (ICHGACC + RICHGACC)%
Table 11: Common charge current values
Note: ICHGLIM must be set at or below the safe charge current limit of the battery according to the
battery specification.
6.2.5 Battery thermal protection using NTC thermistor (NTC)
Battery thermal protection is implemented in the following two ways.
• Using a battery pack with an integrated NTC thermistor
• Connecting a thermistor between the NTC pin and the AVSS pin
The thermistor needs to have thermal contact with the battery and preferably within the battery pack.
Recommended values for the NTC thermistor are found in the following table.
4445_367 v1.2
21
Core components
Parameter
Value
Unit
Nominal resistance at 25°C
10
kΩ
Resistance accuracy
1
%
B25/50 constant
3380
Kelvin
B25/85 constant
3434 to 3435
Kelvin
1
%
B constant accuracy
Table 12: Recommended NTC thermistor values
If the thermal protection feature is not used, then a 10 kΩ, ≤20% accuracy resistor should be connected
between NTC and AVSS pins.
To provide JEITA compliant thermal protection, the charge current limit and termination voltage are
adjusted according to the NTC thermistor measurement.
Temperature region
Battery temperature
Charging current
Termination voltage
Cold
T < 0°C
0 (OFF)
NA
Cool
0°C < T < 10°C
IREDUCED
VTERM
Nominal
10°C < T < 45°C
ICHGLIM
VTERM
Warm
45°C < T < 60°C
ICHGLIM
VTERM-VTHIGH_DELTA
Hot
T > 60°C
0 (OFF)
NA
Table 13: Battery temperature ranges
6.2.6 Charger thermal regulation
If the device junction temperature exceeds THIGH and CHARGER is in Fast Charge mode, the charge current
is reduced to IREDUCED.
6.2.7 Charger error conditions
A CHARGER error condition occurs when one of the following are present:
•
•
•
•
•
A battery short (VBAT to AVSS)
Battery voltage lower than VBATCHARGEMIN after battery detection due to a fault with the battery
Trickle charge timeout; see TOUTTRICKLE
Constant voltage charge/fast charge timeout; see TOUTCHARGE
Device internal error occurs when CHARGER is self-checking
After an error is detected, CHARGER is disabled, the charging error indication is activated, and the charging
indication is deactivated. Error conditions are cleared when VBUS is disconnected and reconnected again.
Note: The constant voltage/fast charge timeout is the combined time spent in both constant
voltage charge and fast charge, TOUTCHARGE.
6.2.8 Charging indication (CHG) and charging error indication (ERR)
The charging indication pin CHG and charging error indication pin ERR sink 5 mA of current when active.
They are high impedance when disabled. This is suitable for driving LEDs or connecting to host GPIOs in a
weak pull-up configuration.
4445_367 v1.2
22
Core components
VSYS
CHG
ERR
Figure 11: Configuration for connecting to LEDs
VOUTB
HOST
CHG
ERR
Figure 12: Configuration for connecting to a host
Note: To configure both LED indication and connection to a host, the GPIO input voltage range
tolerance must be met, or an external circuit may be required. See Reference circuitry on page
44.
The charging indication pin, CHG, is active while the battery is charging.
The charging error indication pin, ERR, is activated when an error occurs, see Charger error conditions on
page 22.
6.2.9 DPPM — Dynamic power-path management
CHARGER manages battery current flow to maintain VINT voltage.
The system load requirements are prioritized over battery charge current when VBUS is connected and
the battery is charging. The battery is isolated when VBUS is connected and the battery is fully charged.
SYSREG supplies the load unless the load exceeds SYSREG limits. When VBUS is disconnected, CHARGER
switches to battery supply.
During charging, if the combined current load ILOAD on VINT (including BUCK input current) and VBAT
(ICHG) exceeds the current provided by SYSREG (ILIM), the battery charge current decreases to maintain the
VINT voltage. The battery charger reduces the current to maintain the internal voltage: VINT = V(VBAT )+
VDROPOUT_CHARGER. If more current is required, CHARGER enters Supplement mode, switching to provide
current from the battery, up to IBATLIM.
If a charge cycle ends and ILOAD exceeds ILIM, CHARGER connects the battery and enters Supplement mode
to maintain VINT.
When VBUS and the battery are connected, the maximum supported load is ILIM + IBATLIM.
4445_367 v1.2
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Core components
When VBUS is disconnected, CHARGER sources current for VINT from the battery. In Supplement mode, or
when VBUS is disconnected, VINT voltage is the same as the battery voltage.
VBUS
Battery
connected connected
Load
CHARGER
VINT supply
VINT voltage
Yes
Yes
(ILOAD + ICHGLIM) < ILIM
Charging
VBUS
V(VBUS)
Yes
Yes
(ILOAD + ICHGLIM) > ILIM
Charging
ILOAD < ILIM
(ICHG reduced)
Yes
Yes
ILOAD > ILIM
Supplement
mode
Yes
No
ILOAD < ILIM
N/A
No
Yes
ILOAD ≤ IBATLIM
N/A
VBUS
V(VBAT) +
VDROPOUTCHARGER
VBUS and
VBAT
V(VBAT)1
VBUS
V(VBUS)
VBAT
V(VBAT)1
Table 14: Battery supply
1
CHARGER has a resistance of RONCHARGER between VBAT and VINT. The voltage drop from VBAT to VINT
is IBAT x RONCHARGER, where IBAT is the current being drawn from the battery.
6.2.10 Electrical specification
Symbol
Description
Min.
ICHGACC
Fast Charge current accuracy, 0.1% accuracy
external resistor
VTERM0
Termination voltage, VTERMSET = LOW
Typ.
Max.
±10
Unit
%
-
4.1
-
V
VTERM1
Termination voltage, VTERMSET = HIGH
-
4.2
-
V
VTERMACC0
Termination voltage accuracy
-1
-
+1
%
VTHIGH_DELTA
VTERM voltage reduction at high temperature
ITERM
Termination current
ITRICKLE
Trickle charge current
IREDUCED
Fast charge current when device junction
temperature is above THIGH or battery
temperature is below TNTCCOOL
-
50
-
% of
ICHG
THIGH
High temperature threshold
-
100
-
°C
THIGHHYST
High temperature hysteresis
-
10
-
°C
VTRICKLE_FAST
Trickle to Fast Charge threshold
-
2.9
-
V
VRECHARGE
Recharge threshold
-
97
-
% of
VTERM
VBATCHARGEMIN
Minimum voltage during charge
-
2.1
-
V
4445_367 v1.2
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8
10
mV
12
10
24
% of
ICHG
% of
ICHG
Core components
Symbol
Description
Min.
Typ.
Max.
Unit
TOUTTRICKLE
Trickle charging timeout
-
10
-
min
TOUTCHARGE
Timeout for Fast charging and constant current
charging
-
7
-
hour
VDROPOUT_CHARGER
VINT - VBAT voltage for charging
-
50
-
mV
VDROPOUT_VBUS
Minimum VBUS - VBAT voltage for charging
-
140
-
mV
TREDETECT
Period between detection events
-
500
-
ms
IBATLIM
Output current limit from battery in discharge
-
660
-
mA
RONCHARGER
CHARGER resistance between VBAT and VINT in
Discharge, VBAT = 3.7 V
-
130
230
mΩ
VBATPOR
Power-on reset release voltage for VBAT
-
2.7
-
V
VBATBOR
Brownout reset trigger voltage for VBAT 1
-
2.5
-
V
ISINK
DC current (CHG and ERR)
-
5
-
mA
TNTCCOLD
JEITA cold temperature threshold (Thermistor: 10
kΩ, B25/50=3380 K)
-
0
-
°C
RNTCCOLD_FALLING
Resistance threshold from cool to cold
25.53
27.28
29.13
kΩ
RNTCCOLD_RISING
Resistance threshold from cold to cool
23.10
26.00
28.20
kΩ
TNTCCOOL
JEITA cool temperature threshold (Thermistor: 10
kΩ, B25/50=3380 K)
-
10
-
°C
RNTCCOOL_FALLING
Resistance threshold from nom. to cool
16.80
18.00
19.20
kΩ
RNTCCOOL_RISING
Resistance threshold from cool to nom.
15.50
17.10
18.60
kΩ
TNTCWARM
JEITA warm temperature threshold (Thermistor:
10 kΩ, B25/50=3380 K)
-
45
-
°C
RNTCWARM_FALLING
Resistance threshold from warm to nom.
4.86
5.13
5.43
kΩ
RNTCWARM_RISING
Resistance threshold from nom. to warm
4.68
4.92
5.17
kΩ
TNTCHOT
JEITA hot temperature threshold (Thermistor: 10
kΩ, B25/50=3380 K)
-
60
-
°C
RNTCHOT_FALLING
Resistance threshold from hot to warm
3.04
3.19
3.35
kΩ
RNTCHOT_RISING
Resistance threshold from warm to hot
2.90
3.02
3.15
kΩ
Table 15: CHARGER electrical specification
1
Device enters BOR only if (V(VBUS) < VBUSBOR) AND (V(VBAT) < VBATBOR).
6.2.11 Electrical characteristics
The following graphs show CHARGER electrical characteristics.
4445_367 v1.2
25
Core components
Figure 13: CHARGER RDS(ON) vs. VBAT voltage
Figure 14: Quiescent VBAT current vs. VBAT voltage
4445_367 v1.2
26
Core components
Figure 15: CHARGER RDS(ON) vs. temperature
Figure 16: Quiescent VBAT current vs. temperature
4445_367 v1.2
27
Core components
Figure 17: VTERM vs. temperature
Figure 18: Charge profile with ISET=1
6.3 BUCK — Buck regulator
BUCK is a step-down DC/DC voltage regulator with the following features:
•
•
•
•
High efficiency (low IQ) and low noise operation
PWM and Hysteretic modes with automatic switching based on load
MODE control pin for forcing PWM mode to minimize output voltage ripple
Configurable output voltage between 1.8 V and 3.0 V
4445_367 v1.2
28
Core components
When VINT is above VINTBUCKMIN, BUCK is enabled and its output voltage is available at VOUTB.
Hysteretic mode offers efficiency for the full range of supported load currents. PWM mode provides a
clean supply operation due to a constant switching frequency, FBUCK. This provides optimal coexistence
with RF circuits. BUCK can automatically change between Hysteretic and PWM modes. Modes are
controlled by the MODE pin. The state of the MODE pin can be changed at any time.
6.3.1 Output voltage selection (VOUTBSET0, VOUTBSET1)
BUCK output voltage selection pins VOUTBSET0 and VOUTBSET1 should be hardwired to DEC, VSYS, or
AVSS. Do not toggle these pins during operation.
VOUTBSET1
VOUTBSET0
VOUTB voltage
LOW
LOW
1.8 V
LOW
HIGH
2.1 V
HIGH
LOW
2.7 V
HIGH
HIGH
3.0 V
Table 16: Output voltage selection
For BUCK to supply the desired output voltage, VINT must be VDROPOUT_BUCK greater than the voltage on
VOUTB.
When supplied from battery, the following equation gives the VINT, where IBAT is the current being drawn
from the battery:
VINT = VBAT – IBAT x RONCHARGER
6.3.2 BUCK mode selection (MODE)
In Automatic mode, BUCK selects Hysteretic mode for low load currents, and PWM mode for high load
currents.
This maximizes efficiency over the full range of supported load currents. In PWM mode, BUCK provides
a clean supply operation due to constant switching frequency and lower voltage ripple. This allows for
optimal coexistence with RF circuits. The MODE pin can be changed at any time.
MODE
BUCK operation mode
LOW
Automatic selection between Hysteretic and PWM
modes
HIGH
PWM mode
Table 17: BUCK mode selection
6.3.3 Component selection
Recommended values for the inductor are shown in the following table.
4445_367 v1.2
29
Core components
Parameter
Value
Units
Nominal inductance
2.2
μH
Inductor tolerance
≤ 20
%
DC resistance (DCR)
≤ 400
mΩ
Saturation current (lsat)
≥ 350
mA
Maximum current (lmax)
≥ 350
mA
Table 18: Inductor selection
The following table shows the minimum and maximum effective capacitance at VOUTB.
Recommended nominal capacitor
Min.
Max.
10 µF
6 µF
20 µF
Table 19: Output capacitor selection
6.3.4 Electrical specification
Symbol
Description
Min.
Typ.
VOUTBACC
Max.
Unit
VOUTB accuracy under static conditions; no change
in supply voltage, load current, or Buck operating
mode
-2
-
8
%
IOUTBSHORT
Short circuit current limit
-
-
400
mA
IPWMTHRES
Load current threshold from Hysteretic to PWM
mode (MODE = LOW)
90
mA
IHYSTTHRES
Load current threshold from PWM to Hysteretic
mode (MODE = LOW)
40
mA
VOUTBRIPPLE_HYST VOUTB ripple, MODE = HIGH or load current above
IPWMTHRES
-
-
10
mVpp
VOUTBRIPPLE_HYST VOUT ripple, MODE = LOW and load current below
IPWMTHRES
-
-
80
mVpp
-
%
EFFBUCK
Efficiency, VOUTBSET = 11 (VOUTB = 3.0 V), VINT =
3.7 V, IOUTB = 100 mA
-
93.5
VDROPOUT_BUCK
Dropout voltage, V(VOUTB) - VINT
-
0.41
FBUCK
Switching frequency for PWM mode
-
3.6
-
MHz
TPWMMODE
Hysteretic to PWM mode transition time on MODE
pin toggle
-
-
55
μs
THYSTMODE
PWM to Hysteretic mode transition time on MODE
pin toggle
-
-
25
μs
TPWM
Hysteretic to PWM mode transition time
-
-
90
μs
4445_367 v1.2
30
V
Core components
Symbol
Description
Min.
Typ.
Max.
Unit
THYST
PWM to Hysteretic mode transition time
-
-
35
μs
TSETTLE
Settling time to within 1% after load transient of 0
A to 100 mA
-
-
20
μs
VINTBUCKMIN
Minimum VINT voltage for enabling BUCK
-
2.8
-
V
Table 20: BUCK electrical specification
6.3.5 Electrical characteristics
The following graphs show BUCK electrical characteristics.
Figure 19: VOUTB=3.0 system efficiency, MODE=AUTO
4445_367 v1.2
31
Core components
Figure 20: VOUTB=3.0 system efficiency, MODE=PWM
Figure 21: VOUTB=3.0: VOUTB vs. temperature (VBAT=4.2)
4445_367 v1.2
32
Core components
Figure 22: VOUTB=2.7 system efficiency, MODE=AUTO
Figure 23: VOUTB=2.7 system efficiency, MODE=PWM
4445_367 v1.2
33
Core components
Figure 24: VOUTB=2.1 system efficiency, MODE=AUTO
Figure 25: VOUTB=2.1 system efficiency, MODE=PWM
4445_367 v1.2
34
Core components
Figure 26: VOUTB=1.8 system efficiency, MODE=AUTO
Figure 27: VOUTB=1.8 system efficiency, MODE=PWM
4445_367 v1.2
35
Core components
Figure 28: VOUTB=1.8 VOUTB vs. temperature (VBAT=4.2)
Figure 29: Startup with no load, soft start, Vout=1.8 V, VBAT=3.8 V
4445_367 v1.2
36
Core components
Figure 30: BUCK load transition in auto mode (MODE=0), Iout=10
mA → 150 mA → 10 mA (1 µs step), Vout=1.8 V, VBAT=3.8 V
Figure 31: BUCK Mode transition, MODE pin 0 → 1, Vout=1.8 V Iout=10 mA
4445_367 v1.2
37
Core components
Figure 32: BUCK Mode transition, MODE pin 1 → 0, Vout=1.8 V Iout=10 mA
Figure 33: BUCK load transition in PWM mode (MODE=1), Iout=10
mA → 150 mA → 10 mA (1 µs step), Vout=1.8 V, VBAT=3.8 V
4445_367 v1.2
38
7
Application
The following application example uses nPM1100 and an nRF5x wireless System on Chip (SoC). Any nRF52
or nRF53 series device with USB can be configured in the same way as this application. When using a
device without USB, or for other configurations, see Reference circuitry on page 44.
The example application is for a design with the following configuration and features:
•
•
•
•
•
•
•
nPM1100 BUCK regulator supplies the nRF5x device
USB current limit negotiation
Charging status monitoring using SoC GPIOs
ICHG and VTERM configuration
NTC thermistor in the battery pack
Ship mode
Battery monitoring circuit and low battery indication LED (this requires the device to sample the
battery voltage; software is not described here)
7.1 Schematic
J2
U
S
B
VBUS
USB
B1
B2
A1
A2
C1
2.2µF
VBAT
D1
D2
E1
J1
+
Battery pack
U1
VBUS
VBUS
DD+
VSYS
VSYS
DEC
VOUTBSET0
VOUTBSET1
VOUTB
nPM1100
VSYS
R_ICHG
1k5
C3
E2
C4
C5
A5
VSYS
B4
B3
C4
10µF
PVSS
VBAT
VBAT
NTC
C5
1.0µF
C1
C2
A3
SW
VTERM
ICHG
MODE
ISET
ERR
CHG
SHPACT
SHPHLD
AVSS
AVSS
PVSS
B5
E5
D5
E3
E4
D4
D3
C3
10µF
TP1
nPM1100-CAAx
PVSS
VDD
VDDH
C2
10µF
PVSS
SHPHLD
R1
100k
VBUS
DD+
VDD_nRF
L1
2.2µH
A4
U2
D_N
D_P
SW1
PB SW
MODE
ISET
ERR
CHG
SHPACT
LOW_BATT
BAT_MON_EN
BAT_MON
R6
150R
LD3
L0603R
Q2
FDV303N
Battery monitoring circuit
(optional)
P0.xx
P0.xx
P0.xx
P0.xx
P0.xx
P0.xx
P0.xx
P0.xx
VSS
nRF5x
R7
1M0
R3
1M0
Q1B
DMC2400UV
Low battery indication
(optional)
Q1A
DMC2400UV
R2
1M0
R4
1M5
R5
220k
Figure 34: Application example
7.2 Supplying from BUCK
nRF5x is supplied by nPM1100 VOUTB at 1.8 V. BUCK mode (MODE) is controlled with a GPIO.
4445_367 v1.2
39
nRF5x
Application
An application should not be supplied directly from VBAT because it can disturb the battery charging
process and may cause incorrect behavior from the charger. Instead, VOUTB and/or VSYS should be used
to supply an application.
7.3 USB port negotiation
nRF5x can connect to a USB host.
Port negotiation can be performed after nPM1100 port detection. The nRF5x device and nPM1100 are
both connected to USB in the application example. nPM1100 detects SDP or CDP/DCP. If SDP is detected,
the USB device can negotiate with the USB host for higher current from VBUS.
• D+ and D- pins are connected to both nPM1100 and nRF5x. The nRF5x SoC must wait until nPM1100
completes port detection before enabling its USB port. See USB port detection and VBUS current
limiting on page 15 for port detection time after VBUS connection.
• An nRF5x GPIO is connected to the ISET pin and sets the VBUS current limit after negotiation. If CDP
or DCP is detected, then a 500 mA limit is automatically set regardless of ISET state.
• VBUS is supplied to both nPM1100 and nRF5x to supply nPM1100 SYSREG and the nRF5x VBUS
regulator.
See USB port detection and VBUS current limiting on page 15 for a detailed description.
7.4 Charging and error states
Pins CHG and ERR indicate charging and error states. See Charging indication (CHG) and charging error
indication (ERR) on page 22 and Charger error conditions on page 22.
7.5 Termination voltage and current
The termination voltage is configured to 4.2 V through the VTERMSET pin. See Termination voltage
(VTERMSET) on page 20.
Charge current is configured to 200 mA (±10%) using a 1.5 kΩ (1%) resistor to ground on the ICHG pin.
See Charge current limit (ICHG) on page 21.
7.6 NTC configuration
The NTC pin is connected to an external NTC thermistor which should be placed with thermal coupling
to the battery pack. See Battery thermal protection using NTC thermistor (NTC) on page 21 for more
information.
7.7 Ship mode
Ship mode is enabled at production time through an off-board circuit with a probe point on the SHIPACT
pin.
An external button is in the circuit to exit Ship mode. If another circuit is present instead of a button, any
signal that is able to pull the SHIPHLD pin low for the required period can be connected to that net. See
Using Ship mode on page 10 for more information.
4445_367 v1.2
40
Application
7.8 Battery monitoring and low battery indication
The battery monitoring circuit allows the battery voltage to be sampled by the nRF5x ADC.
The transistors enable battery voltage sensing through a resistive divider. When not sampling, the
transistors prevent current leakage to ground. The circuit is designed to ensure the voltage range on an
analog input pin over the battery voltage is within the limits required by the nRF5x GPIO and ADC. A
battery voltage of 2.8 V to 4.2 V is scaled down to 360 mV to 540 mV at P0.xx for sampling.
If software on nRF5x determines that the battery on nPM1100 is low, the Low Bat LED can be switched on
through GPIO. This circuit sources the LED current from VSYS. VSYS will not be supplied after VBAT drops
below VBATBOR because CHARGER will isolate the battery when a brownout reset occurs. See Power-on
reset (POR) and brownout reset (BOR) on page 10.
4445_367 v1.2
41
8
Hardware and layout
8.1 Ball assignments
The ball assignment figure and table describe the assignments for this variant of the chip.
Figure 35: WLCSP ball assignments
Pin
Name
Function
Description
A1
D-
Analog input
USB D- data line
Analog input
USB D+ data line
Power
System decoupling capacitor
A2
A3
D+
DEC
A4
SW
Power
BUCK converter output (to
inductor)
A5
PVSS
Power
Ground (DC/DC)
Power
Input supply
Power
Input supply
B1
B2
VBUS
VBUS
Recommended
usage
B3
VOUTBSET1
Digital I/O
BUCK regulator output voltage
selection
Toggle only when the
device is in Power
OFF
B4
VOUTBSET0
Digital I/O
BUCK regulator output voltage
selection
Toggle only when the
device is in Power
OFF
B5
VOUTB
Power
BUCK regulator output
C1
VSYS
Power
System voltage output;
automatically enabled after poweron reset
C2
VSYS
Power
System voltage output;
automatically enabled after poweron reset
4445_367 v1.2
42
Hardware and layout
Pin
Name
Function
Description
Recommended
usage
C3
VTERMSET
Digital I/O
Battery charging termination
voltage selection:
Toggle only when the
device is in Power
OFF
0 to 4.10 V
1 to 4.20 V
AVSS
C4
AVSS
C5
D1
D2
D3
D4
D5
VBAT
VBAT
SHPHLD
SHPACT
ISET
Power
Ground
Power
Ground
Power
Battery
Power
Battery
Digital I/O
Shipping mode hold
Digital I/O
Shipping mode activate
Digital I/O
VBUS current limit selection:
0 mA to 100 mA (SDP mode only)
1 mA to 500 mA
NTC
E1
ICHG
E2
Analog input
NTC resistor
Analog input
Charge current limiting resistor
E3
ERR
Digital OUT
Open-drain LED driver; enabled
when error condition in charging
E4
CHG
Digital OUT
Open-drain LED driver; enabled
when battery is charging
E5
MODE
Digital I/O
0 - automatic
1 - Forced PWM
Table 21: Pin assignments
Note: VOUTBSET1 and VOUTBSET0 balls are located close to AVSS, DEC, and VSYS to allow
connection to tracks on the PCB without any via holes.
8.2 Mechanical specifications
The mechanical specifications for the package shows the dimensions in millimeters.
8.2.1 WLCSP 2.075x2.075 mm package
Dimensions in millimeters for the WLCSP 2.075x2.075 mm package.
4445_367 v1.2
43
Hardware and layout
Figure 36: WLCSP 2.075x2.075 mm package
A
A1
A2
b
Min.
0.406
0.14
0.266 0.195
Nom.
0.464
Max.
0.522
0.294
0.2
D
E
D2
E2
d
e
2.075 2.075 1.6
1.6
0.4
0.4
K
L
0.322 0.255
Table 22: WLCSP dimensions in millimeters
8.3 Reference circuitry
Documentation for the different package reference circuits, including Altium Designer files, PCB layout
files, and PCB production files can be downloaded from www.nordicsemi.com.
The following reference circuits for nPM1100 show the schematics and components to support different
configurations in a design.
4445_367 v1.2
44
Hardware and layout
Description
Configuration 1
Configuration 2
Configuration 3
Minimal configuration
Minimal configuration
Normal configuration
Fixed 100 mA VBUS limit Fixed 500 mA VBUS limit USB port detection
BUCK
Not used
Not used
Configured
Ship mode
Not used
Not used
Configured
Battery NTC
Not used
Not used
Configured
VTERM
4.1 V
4.1 V
4.2 V
ISET
AVSS
VSYS
AVSS
D-
AVSS
D+
ICHG
AVSS
USB
NC
NC
USB
4.7 kΩ
0Ω
1.5 kΩ
1%
GND
GND
VOUTB
-
-
2V1
Table 23: PCB application configuration
8.3.1 Configuration 1
VBUS
B1
B2
A1
A2
C1
2.2µF
VBAT
J1
+
Battery pack
C3
1.0µF
D1
D2
E1
R1
10k
VBUS
VBUS
DD+
VSYS
VSYS
DEC
VOUTBSET0
VOUTBSET1
VBAT
VBAT
NTC
VOUTB
nPM1100
C3
E2
R_ICHG
4k7
U1
C4
C5
A5
SW
VTERM
ICHG
MODE
ISET
ERR
CHG
SHPACT
SHPHLD
AVSS
AVSS
PVSS
nPM1100-CAAx
4445_367 v1.2
45
C1
C2
A3
VOUT
B4
B3
C2
22µF
B5
Optional
LD1
L0603R
A4
E5
D5
E3
E4
D4
D3
ERR
CHG
LD2
L0603G
Hardware and layout
Designator
Value
Description
Footprint
C1
2.2 µF
Capacitor, X5R, 25 V, ±20%
0603
C2
22 µF
Capacitor, X5R, 6.3 V, ± 20%
0603
C3
1.0 µF
Capacitor, X5R, 10 V, ± 20%
0201
J1
Battery pack
Battery pack
TP_2x1mm_TH
LD1
L0603R
LED, SMD, RED
0603
LD2
L0603G
LED, SMD, GREEN
0603
R1
10 kΩ
Resistor, 0.05 W, ±1%
0201
R_ICHG
4.7 kΩ
Resistor, 0.05 W, ±1%
0201
U1
nPM1100-CAAx Li-ion/Li-poly USB battery charger with high
efficiency buck regulator
WLCSP-25
Table 24: Configuration 1 reference circuitry
8.3.2 Configuration 2
VBUS
B1
B2
A1
A2
C1
2.2µF
VBAT
J1
+
C3
1.0µF
Battery pack
D1
D2
E1
R1
10k
U1
VBUS
VBUS
DD+
VSYS
VSYS
DEC
VOUTBSET0
VOUTBSET1
VBAT
VBAT
NTC
VOUTB
nPM1100
C3
E2
C4
C5
A5
SW
VTERM
ICHG
MODE
ISET
ERR
CHG
SHPACT
SHPHLD
AVSS
AVSS
PVSS
C1
C2
A3
VOUT
B4
B3
C2
22µF
B5
Optional
LD1
L0603R
A4
E5
D5
E3
E4
D4
D3
LD2
L0603G
ERR
CHG
nPM1100-CAAx
Designator
Value
Description
Footprint
C1
2.2 µF
Capacitor, X5R, 25 V, ±20%
0603
C2
22 µF
Capacitor, X5R, 6.3 V, ±20%
0603
C3
1.0 µF
Capacitor, X5R, 10 V, ±20%
0201
J1
Battery pack
Battery pack
TP_2x1mm_TH
LD1
L0603R
LED, SMD, RED
0603
LD2
L0603G
LED, SMD, GREEN
0603
R1
10 kΩ
Resistor, 0.05 W, ±1%
0201
U1
nPM1100-CAAx Li-ion/Li-poly USB battery charger with a high
efficiency buck regulator
Table 25: Configuration 2 reference circuitry
8.3.3 Configuration 3
4445_367 v1.2
46
WLCSP-25
Hardware and layout
VBUS
Optional
R3
1k
C1
2.2µF
D_N
D_P
B1
B2
A1
A2
U1
VBUS
VBUS
DD+
VSYS
VSYS
DEC
VOUTBSET0
VOUTBSET1
LD3
L0603R
VBAT
D1
D2
E1
J1
+
Battery pack
VOUTB
nPM1100
VSYS
R_ICHG
1k5
C3
E2
C4
C5
A5
B4
B3
VSYS
C4
10µF
PVSS
VBAT
VBAT
NTC
C5
1.0µF
C1
C2
A3
SW
VTERM
ICHG
MODE
ISET
ERR
CHG
SHPACT
SHPHLD
AVSS
AVSS
PVSS
B5
A4
E5
D5
E3
E4
D4
D3
C3
10µF
VOUT
L1
2.2µH
MODE
ISET
ERR
CHG
SHPACT
SHPHLD
Optional
C2
10µF
LD1
L0603R
LD2
L0603G
PVSS
nPM1100-CAAx
PVSS
Designator
Value
Description
Footprint
C1
2.2 µF
Capacitor, X5R, 25 V, ±20%
0603
C2, C3, C4
10 µF
Capacitor, X5R, 6.3 V, ±20%
0603
C5
1.0 µF
Capacitor, X5R, 10 V, ±20%
0201
J1
Battery pack
Battery pack with NTC
TP_3x1mm_TH
L1
2.2 µH
Inductor ±20%
0806
LD1, LD3
L0603R
LED, SMD, RED
0603
LD2
L0603G
LED, SMD, GREEN
0603
R3
1 kΩ
Resistor, 0.05 W, ±1%
0201
R_ICHG
1.5 kΩ
Resistor, 0.05 W, ±1%
0201
U1
nPM1100-CAAx Li-ion/Li-poly USB battery charger with a high
efficiency buck regulator
WLCSP-25
Table 26: Configuration 3 reference circuitry
8.3.4 PCB guidelines
A well designed PCB is necessary to achieve good performance. A poor layout can lead to loss in
performance or functionality.
To ensure functionality, it is essential to follow the schematics and layout references closely.
A PCB with a minimum of two layers, including a ground plane, is recommended for optimal performance.
The DC supply voltage should be decoupled with high performance capacitors as close as possible to the
supply pins. See the reference schematic in Configuration 1 on page 45 for recommended decoupling
capacitor values.
Long power supply lines on the PCB should be avoided. All device grounds, VDD connections, and VDD
bypass capacitors must be connected as close as possible to the device.
8.3.5 PCB layout example
The PCB layout shown here is a reference layout for the WLCSP25 package.
For all available reference layouts, see the Reference Layout section on the Downloads tab for nPM1100
on www.nordicsemi.com.
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Hardware and layout
Figure 37: Top silk layer
Figure 38: Top layer
Figure 39: Bottom layer
Note: No components in the bottom layer.
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9
Ordering information
This chapter contains information on IC marking, ordering codes, and container sizes.
9.1 IC marking
The nPM1100 PMIC package is marked as shown in the following figure.
N
P
M
1
1
0
0
Figure 40: IC marking
9.2 Box labels
The following figures define the box labels used for the nPM1100.
PART NO.: (1P)
TRACE CODE: (1T)
TRACE CODE QUANTITY:
TOTAL QUANTITY: (Q)
Figure 41: Inner box label
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Pb
eX
Ordering information
FROM:
TO:
PART NO: (1P)
CUSTOMER PO NO: (K)
Pb
SALES ORDER NO: (14K)
SHIPMENT ID.: 2K
QUANTITY: (Q)
COUNTRY OF ORIGIN.: 4L
CARTON NO:
x/n
DELIVERY NO.: (9K)
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