PSMN013-60HLX

PSMN013-60HL N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology 30 September 2022 Product data sheet 1. General description Dual logic level N-channel MOSFET in an LFPAK56D (Dual Power-SO8) package using TrenchMOS technology. 2. Features and benefits • • • • • Dual MOSFET Repetitive avalanche rated High reliability LFPAK56D package Copper-clip, solder die attach Qualified to 175 °C 3. Applications • • • • Brushless DC motor control DC-to-DC converters High-performance synchronous rectification High performance and high efficiency server power supply 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 60 V ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 2 - - 40 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 64 W Tj junction temperature -55 - 175 °C VGS = 5 V; ID = 10 A; Tj = 25 °C; Fig. 11 - 10 12.5 mΩ VGS = 5 V; ID = 10 A; Tj = 175 °C; Fig. 11; Fig. 12 - 22 28.3 mΩ - 7.9 - nC - 22.4 - nC - - 82 mJ [1] Static characteristics FET1 and FET2 RDSon drain-source on-state resistance Dynamic characteristics FET1 and FET2 QGD gate-drain charge QG(tot) total gate charge ID = 10 A; VDS = 48 V; VGS = 5 V; Tj = 25 °C; Fig. 13; Fig. 14 Avalanche Ruggedness FET1 and FET2 EDS(AL)S non-repetitive drainsource avalanche energy ID = 40 A; Vsup ≤ 60 V; RGS = 50 Ω; VGS = 5 V; Tj(init) = 25 °C; unclamped; Fig. 4 [2] [3] PSMN013-60HL Nexperia N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology Symbol Parameter Conditions Min Typ Max Unit IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 30 V; Tj = 25 °C - 18.9 - nC Source-drain diode FET1 and FET2 Qr [1] [2] [3] recovered charge Continuous current is limited by package Refer to application note AN10273 for further information Single-pulse avalanche rating limited by maximum junction temperature of 175 °C 5. Pinning information Table 2. Pinning information Pin Symbol Description 1 S1 source1 2 G1 gate1 3 S2 source2 4 G2 gate2 5 D2 drain2 6 D2 drain2 7 D1 drain1 8 D1 Simplified outline 8 7 6 Graphic symbol 5 D1 D1 1 drain1 2 3 4 S1 D2 D2 G1 S2 G2 mbk725 LFPAK56D; Dual LFPAK (SOT1205) 6. Ordering information Table 3. Ordering information Type number Package PSMN013-60HL Name Description Version LFPAK56D; Dual LFPAK plastic, single ended surface mounted package (LFPAK56D); 8 leads SOT1205 7. Marking Table 4. Marking codes Type number Marking code PSMN013-60HL 13RL60H 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 60 V VDGR drain-gate voltage RGS = 20 kΩ - 60 V VGS gate-source voltage DC; Tj ≤ 175 °C -10 10 V -15 15 V - 64 W Pulsed; Tj ≤ 175 °C Ptot PSMN013-60HL Product data sheet total power dissipation Tmb = 25 °C; Fig. 1 All information provided in this document is subject to legal disclaimers. 30 September 2022 [1] [2] © Nexperia B.V. 2022. All rights reserved 2 / 12 PSMN013-60HL Nexperia N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology Symbol Parameter Conditions Min Max Unit ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 2 - 40 A VGS = 5 V; Tmb = 100 °C; Fig. 2 - 33 A pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 [3] IDM peak drain current - 190 A Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C - 40 A - 190 A - 82 mJ Source-drain diode FET1 and FET2 IS source current Tmb = 25 °C [3] ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C Avalanche Ruggedness FET1 and FET2 EDS(AL)S [1] [2] [3] [4] [5] non-repetitive drainID = 40 A; Vsup ≤ 60 V; RGS = 50 Ω; source avalanche energy VGS = 5 V; Tj(init) = 25 °C; unclamped; Fig. 4 [4] [5] Accumulated Pulse duration up to 50 hours delivers zero defect ppm Significantly longer life times are achieved by lowering Tj and or VGS. Continuous current is limited by package Refer to application note AN10273 for further information Single-pulse avalanche rating limited by maximum junction temperature of 175 °C 03aa16 120 ID (A) Pder (%) 003aak109 50 40 (1) 80 30 20 40 10 0 0 50 100 150 Tmb (°C) 0 200 0 25 50 75 100 125 150 175 Tmb (°C) 200 (1) Capped at 40 A due to package VGS ≥ 5 V Fig. 1. Normalized total power dissipation as a function of mounting base temperature PSMN013-60HL Product data sheet Fig. 2. Continuous drain current as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. 30 September 2022 © Nexperia B.V. 2022. All rights reserved 3 / 12 PSMN013-60HL Nexperia N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology ID (A) 003aak108 103 Limit RDSon = VDS / ID 102 tp = 10 us 100 us 10 DC 1 ms 1 10 ms 100 ms 10-1 10-1 1 102 10 VDS (V) 103 Tmb = 25 °C; IDM is a single pulse Fig. 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage IAL (A) 003aak110 102 (1) 10 (2) 1 (3) 10-1 10-3 10-2 10-1 1 tAL (ms) 10 (1) Tj (init) = 25 °C; (2) Tj (init) = 150 °C; (3) Repetitive Avalanche Fig. 4. Avalanche rating; avalanche current as a function of avalanche time 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from Fig. 5 junction to mounting base - - 2.36 K/W Rth(j-a) thermal resistance from Minimum footprint; mounted on a junction to ambient printed circuit board - 95 - K/W PSMN013-60HL Product data sheet All information provided in this document is subject to legal disclaimers. 30 September 2022 © Nexperia B.V. 2022. All rights reserved 4 / 12 PSMN013-60HL Nexperia N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology 003aaj748 10 Zth(j-mb) (K/W) δ = 0.5 1 0.2 0.1 0.05 10-1 P 0.02 δ= single shot Fig. 5. 10-5 10-4 10-3 10-2 T t tp 10-2 10-6 tp T 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C 54 - - V ID = 250 µA; VGS = 0 V; Tj = 25 °C 60 - - V gate-source threshold voltage ID = 1 mA; VDS=VGS; Tj = 25 °C; Fig. 9; Fig. 10 1.4 1.7 2.1 V ID = 1 mA; VDS=VGS; Tj = 175 °C; Fig. 9 0.5 - - V ID = 1 mA; VDS=VGS; Tj = -55 °C; Fig. 9 - - 2.45 V VDS = 60 V; VGS = 0 V; Tj = 25 °C - 0.02 1 µA VDS = 60 V; VGS = 0 V; Tj = 175 °C - - 500 µA VGS = -10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 5 V; ID = 10 A; Tj = 25 °C; Fig. 11 - 10 12.5 mΩ VGS = 5 V; ID = 10 A; Tj = 175 °C; Fig. 11; Fig. 12 - 22 28.3 mΩ VGS = 10 V; ID = 10 A; Tj = 25 °C; Fig. 11 - 9 11.2 mΩ - 22.4 - nC - 5.2 - nC - 7.9 - nC - 2215 2953 pF - 225 270 pF - 116 159 pF - 13 - ns - 22.1 - ns - 30.5 - ns Static characteristics FET1 and FET2 V(BR)DSS VGS(th) IDSS drain leakage current IGSS gate leakage current RDSon drain-source on-state resistance Dynamic characteristics FET1 and FET2 QG(tot) total gate charge QGS gate-source charge QGD gate-drain charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) turn-off delay time PSMN013-60HL Product data sheet ID = 10 A; VDS = 48 V; VGS = 5 V; Tj = 25 °C; Fig. 13; Fig. 14 VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; Fig. 15 VDS = 48 V; RL = 5 Ω; VGS = 5 V; RG(ext) = 5 Ω; Tj = 25 °C All information provided in this document is subject to legal disclaimers. 30 September 2022 © Nexperia B.V. 2022. All rights reserved 5 / 12 PSMN013-60HL Nexperia N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology Symbol Parameter tf fall time Conditions Min Typ Max Unit - 21.8 - ns Source-drain diode FET1 and FET2 VSD source-drain voltage IS = 15 A; VGS = 0 V; Tj = 25 °C; Fig. 16 - 0.8 1.2 V trr reverse recovery time - 22.7 - ns Qr recovered charge IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 30 V; Tj = 25 °C - 18.9 - nC ID (A) 003aak102 40 10 V 4.5 V 003aak101 50 RDSon (mΩ) 2.8 V 32 40 VGS = 2.6 V 24 30 16 20 2.4 V 8 10 2.2 V 0 Fig. 6. 0 1 2 3 VDS (V) 0 4 0 2 4 6 8 VGS (V) 10 Tj = 25 °C; tp = 300 μs Tj = 25 °C; ID = 10 A Output characteristics; drain current as a Fig. 7. function of drain-source voltage; typical values Drain-source on-state resistance as a function of gate-source voltage; typical values aaa-016783 120 ID (A) 100 003aah025 3 VGS(th) (V) 2.5 max 2 80 typ 60 1.5 40 1 175°C Tj = 25°C 20 0 0 1 2 3 4 VGS (V) 0.5 0 -60 5 VDS = 10 V Fig. 8. Product data sheet 0 60 120 Tj (° C) 180 ID = 1 mA; VDS = VGS Transfer characteristics; drain current as a function of gate-source voltage; typical values PSMN013-60HL min Fig. 9. Gate-source threshold voltage as a function of junction temperature All information provided in this document is subject to legal disclaimers. 30 September 2022 © Nexperia B.V. 2022. All rights reserved 6 / 12 PSMN013-60HL Nexperia N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology 003aah026 10-1 ID (A) 10 003aak107 50 RDSon (mΩ) -2 2.6 V 2.8 V 40 min 10-3 typ max 30 10-4 20 10-5 10 3V 4.5 V VGS = 10 V 10-6 0 1 2 V GS (V) 0 3 0 5 10 15 20 25 30 35 ID (A) 40 Tj = 25 °C; tp = 300 μs Tj = 25 °C; VDS = 5 V Fig. 10. Sub-threshold drain current as a function of gate-source voltage Fig. 11. Drain-source on-state resistance as a function of drain current; typical values 003aaj816 2.4 VDS a ID 1.6 VGS(pl) 0.8 VGS(th) VGS QGS2 0 -60 QGS1 0 60 120 Tj ( °C) QGS 180 QGD QG(tot) 003aaa508 Fig. 13. Gate charge waveform definitions Fig. 12. Normalized drain-source on-state resistance factor as a function of junction temperature PSMN013-60HL Product data sheet All information provided in this document is subject to legal disclaimers. 30 September 2022 © Nexperia B.V. 2022. All rights reserved 7 / 12 PSMN013-60HL Nexperia N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology VGS (V) 003aak104 10 8 003aak105 104 C (pF) Ciss VDS = 14 V 103 6 Coss 4 48 V 102 Crss 2 0 0 10 20 30 40 QG (nC) 10 10-1 50 Tj = 25 °C; ID = 10 A 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig. 14. Gate-source voltage as a function of gate charge; typical values IS (A) Fig. 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aak106 40 30 20 10 0 175°C 0 0.2 0.4 Tj = 25°C 0.6 0.8 1 VSD (V) 1.2 VGS = 0 V Fig. 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values PSMN013-60HL Product data sheet All information provided in this document is subject to legal disclaimers. 30 September 2022 © Nexperia B.V. 2022. All rights reserved 8 / 12 PSMN013-60HL Nexperia N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology 11. Package outline Plastic single ended surface mounted package LFPAK56D; 8 leads E SOT1205 A A b1 c1 L1 mounting base D H D1 D2 L 1 2 3 e b (8x) 4 w X c A E1 E2 A1 C θ Lp detail X 0 2.5 A max 1.05 nom min 1.02 mm 5 mm scale Dimensions Unit y C D(1) D1(1) D2 (ref) E(1) E1(1) 4.4 0.25 0.30 4.70 4.55 3.5 5.30 1.8 0.85 4.1 0.19 0.24 4.45 4.35 3.4 4.95 1.6 0.60 A1 b b1 0.1 0.50 0.0 0.35 c c1 E2 e 1.27 H L L1 Lp 6.2 1.3 0.55 0.85 5.9 0.8 0.30 0.40 w y 0.25 0.1 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. Outline version References IEC JEDEC JEITA θ 8° 0° sot1205_po European projection Issue date 14-08-21 14-10-28 SOT1205 Fig. 17. Package outline LFPAK56D; Dual LFPAK (SOT1205) PSMN013-60HL Product data sheet All information provided in this document is subject to legal disclaimers. 30 September 2022 © Nexperia B.V. 2022. All rights reserved 9 / 12 PSMN013-60HL Nexperia N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology 12. Soldering Footprint information for reflow soldering of LFPAK56D package SOT1205 5.85 0.57 0.025 0.57 0.7 1.97 0.65 1.27 1.9 3.325 3.175 3.2 2.0 1.275 0.8 1.875 2.1 2.7 1.0 3.85 3.975 0.025 1.1 1.15 0.65 1.27 1.1 1.44 solder land solder land plus solder paste solder paste deposit solder resist occupied area Dimensions in mm Issue date 0.7 14-07-28 20-04-20 sot1205_fr Fig. 18. Reflow soldering footprint for LFPAK56D; Dual LFPAK (SOT1205) PSMN013-60HL Product data sheet All information provided in this document is subject to legal disclaimers. 30 September 2022 © Nexperia B.V. 2022. All rights reserved 10 / 12 PSMN013-60HL Nexperia N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology 13. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". 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Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. 30 September 2022 © Nexperia B.V. 2022. All rights reserved 11 / 12 PSMN013-60HL Nexperia N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Quick reference data....................................................1 5. Pinning information......................................................2 6. Ordering information....................................................2 7. Marking.......................................................................... 2 8. Limiting values............................................................. 2 9. Thermal characteristics............................................... 4 10. Characteristics............................................................ 5 11. Package outline.......................................................... 9 12. Soldering................................................................... 10 13. Legal information......................................................11 © Nexperia B.V. 2022. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 30 September 2022 PSMN013-60HL Product data sheet All information provided in this document is subject to legal disclaimers. 30 September 2022 © Nexperia B.V. 2022. All rights reserved 12 / 12