24C128BN

XBLW 24C128 General Description The 24C128 series are 131,072 bits of serial Electrical Erasable and Programmable Read Only Memory, commonly known as EEPROM. They are organized as 16,384 words of 8 bits (one byte) each. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead MSOP, 8-lead TSSOP, and 8-lead DFN packages. A standard 2-wire serial interface is used to address all read and write functions. Our extended VCC range (1.8V to 5.5V) devices enables wide spectrum of applications. Features               Low voltage and low power operations: • 24C128: VCC = 1.8V to 5.5V 64 bytes page write mode. Partial page write operation allowed. Internally organized: 16,384 ×8 (128K). Standard 2-wire bi-directional serial interface. Schmitt trigger, filtered inputs for noise protection. Self-timed write cycle (5ms maximum). 1 MHz (2.5-5.5V), 400 kHz (1.8V) Compatibility. Automatic erase before write operation. Write protect pin for hardware data protection. High reliability: typically 1,000,000 cycles endurance. 100 years data retention. Industrial temperature range (-40C to 85C). Standard 8-lead DIP/SOP/MSOP/TSSOP/UDFN Pb-free packages. Ordering Information DEVICE 24C128N 24C128BN 24C128MDTR 24C128TDTR 24C128UDTR Package Type DIP-8 SOP-8 MSOP-8 TSSOP-8 UDFN-8 MARKING 24C128N 24C128BN 24C128BM 24C128BT 24C128BU Packing Tube Tape Tape Tape Tape Packing QTY 2000/Box 4000/Reel 3000/Reel 3000/Reel 3000/Reel Pin Configuration Pin Name A2, A1, A0 Pin Function Device Address Inputs SDA Serial Data Input / Open Drain Output SCL Serial Clock Input WP Write Protect NC No-Connect All these packaging types come in Pb-free certified. XBLWversion1.0 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第 1 页 共 15 页 XBLW 24C128 Absolute Maximum Ratings Industrial operating temperature: - 4 0 C to 8 5 C Storage temperature: - 50 C to 12 5 C Input voltage on any pin relative to ground: Maximum voltage: ESD Protection on all pins: -0.3V to VCC + 0.3V 8V >4000V * Stresses exceed those listed under “ Absolute Maximum Rating” may cause permanent damage to the device. Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality. PIN DESCRIPTIONS XBLWversion1.0 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第 2 页 共 15 页 XBLW 24C128 (A) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0) These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to either VIH or VIL . If left unconnected, they are internally recognized as VIL . (B) SERIAL CLOCK (SCL) The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to clock data out of the EEPROM device. (C) SERIAL DATA LINE (SDA) SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-OR with other open-drain output devices. (D) WRITE PROTECT (WP) The 24C128 devices have a WP pin to protect the whole EEPROM array from programming. Programming operations are allowed if WP pin is left un-connected or input to VIL . Conversely all programming functions are disabled if WP pin is connected to VIH or VCC . Read operations is not affected by the WP pin’s input level. Memory Organization The 24C128 devices have 2 5 6 pages. Since each page has 6 4 bytes, random word addressing to 24C128 will require 14 bits data word addresses. Device Operation (A) SERIAL CLOCK AND DATA TRANSITIONS The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock SCL is at VIL . Any SDA signal transition may interpret as either a START or STOP condition as described below. (B) START CONDITION With SCL ≥ VIH , a SDA transition from high to low is interpreted as a START condition. commands must begin with a START condition. All valid (C) STOP CONDITION With SCL ≥ VIH , a SDA transition from low to high is interpreted as a STOP condition. All valid read or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command. A STOP condition after page or byte write command will trigger the chip into the STANDBY mode after the self-timed internal programming finish (see Figure 1). (D) ACKNOWLEDGE The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM acknowledges the data or address by outputting a "0 " after receiving each word. The ACKNOWLEDGE signal occurs on the 9 th serial clock after each word. (E) STANDBY MODE The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read mode, or after completing a self-time internal programming operation. XBLWversion1.0 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第 3 页 共 15 页 XBLW 24C128 Device Addressing The 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke a valid read or write command. The first four most significant bits of the device address must be 1 0 1 0 , which is common to all serial EEPROM devices. The next three bits are device address bits. These three device address bits (5 th , 6 th and 7 th) are to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8 th read/ write bit, otherwise the chip will go into STANDBY mode. However, matching may not be needed for some or all device address bits (5 th , 6 th and 7 th) as noted below. The last or 8th bit is a read/write command bit. If the 8th bit is at VIH then the chip goes into read mode. If a “0” is detected, the device enters programming mode. XBLWversion1.0 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第 4 页 共 15 页 XBLW 24C128 Write Operations (A) BYTE WRITE A write operation requires two 8- bit data word address following the device address word and ACKNOWLEDGE signal. Upon receipt of this address, the EEPROM will respond with a “ 0 ” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will again output a “ 0 ” . The addressing device, such as a microcontroller, must terminate the write sequence with a STOP condition. At this time the EEPROM enters into an internally- timed write cycle state. All inputs are disabled during this write cycle and the EEPROM will not respond until the writing is completed (Figure 3). (B) PAGE WRITE The128K EEPROM are capable of 64-byte page write. A page write is initiated the same way as a byte write, but the microcontroller does not send a STOP condition after the first data word is clocked in. The microcontroller can transmit up to 6 3 more data words after the EEPROM acknowledges receipt of the first data word. The EEPROM will respond with a “0” after each data word is received. The microcontroller must terminate the page write sequence with a STOP condition (see Figure 4). The lower six bits of the data word address are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. If more than 64 data words are transmitted to the EEPROM, the data word address will “ roll over” and the previous data will be overwritten. (C) ACKNOWLEDGE POLLING ACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal programming. By issuing a valid read or write address command, the EEPROM will not acknowledge at the 9 th clock cycle if the device is still in the self-timed programming mode. However, if the programming completes and the chip has returned to the STANDBY mode, the device will return a valid ACKNOWLEDGE signal at the 9 th clock cycle. Read Operations The read command is similar to the write command except the 8 th read/write bit in address word is set to “1” . The three read operation modes are described as follows: (A) CURRENT ADDRESS READ The EEPROM internal address word counter maintains the last read or write address plus one if the power supply to the device has not been cut off. To initiate a current address read operation, the microcontroller issues a START bit and a valid device address word with the read/write bit (8 th) set to “1” . The EEPROM will response with an ACKNOWLEDGE signal on the 9 th serial clock cycle. An 8-bit data word will then be serially clocked out. The internal address word counter will then automatically increase by one. For current address read the micro-controller will not issue an ACKNOWLEDGE signal on the 18 th clock cycle. The micro-controller issues a valid STOP bit after the 18 th clock cycle to terminate the read operation. The device then returns to STANDBY mode (see Figure 5). (B) SEQUENTIAL READ The sequential read is very similar to current address read. The micro-controller issues a START bit and a valid device address word with read/write bit (8 th) set to “1” . The EEPROM will response with an ACKNOWLEDGE signal on the 9 th serial clock cycle. An 8-bit data word will then be serially clocked out. Meanwhile the internally address word counter will then automatically increase by one.nlike current address read, the micro- controller sends an ACKNOWLEDGE signal on the 1 8 th clock cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the ACKNOWLEDGE signal, the EEPROM will serially clocked out an 8-bit data word based on the incremented internal address counter. If the micro-controller needs another data, it sends out an ACKNOWLEDGE signal on the 27 th clock cycle. Another 8-bit data word will then be serially clocked out. This sequential read continues as long as the micro- controller sends an ACKNOWLEDGE signal after receiving a new data word. When the internal address counter reaches its maximum valid address, it rolls over to the beginning of the memory array address. Similar to current address read, the micro- controller can terminate the sequential read by not acknowledging the last data word received, but sending a STOP bit afterwards instead (Figure 6). (C) RANDOM READ XBLWversion1.0 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第 5 页 共 15 页 XBLW 24C128 Random read is a two- steps process. The first step is to initialize the internal address counter with a target read address using a “dummy write” instruction. The second step is a current address read. To initialize the internal address counter with a target read address, the micro-controller issues a START bit first, follows by a valid device address with the read/write bit (8 th) set to “0” . The EEPROM will then acknowledge. The micro-controller will then send two address words. Again the EEPROM will acknowledge. Instead of sending a valid written data to the EEPROM, the micro- controller performs a current address read instruction to read the data. Note that once a START bit is issued, the EEPROM will reset the internal programming process and continue to execute the new instruction - which is to read the current address (Figure7). XBLWversion1.0 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第 6 页 共 15 页 XBLW 24C128 Electrical Specifications (A) Power-Up Requirements During a power-up sequence, the VCC supplied to the device should monotonically rise from GND to the minimum VCC level, with a slew rate no faster than 0.05 V/ ps and no slower then 0.1 V/ms. A decoupling cap should be connected to the VCC PAD which is no smaller than 10nF. (B) Device Reset To prevent inadvertent write operations or any other spurious events from occurring during a power- up sequence, this device includes a Power- on Reset ( POR) circuit. Upon power- up, the device will not respond to any commands until the VCC level crosses the internal voltage threshold ( VPOR) that brings XBLWversion1.0 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第 7 页 共 15 页 XBLW 24C128 the device out of Reset and into Standby mode. The system designer must ensure the instructions are not sent to the device until the VCC supply has reached a stable value greater than or equal to the minimum VCC level. Figure 11: Power on and Power down If an event occurs in the system where the VCC level supplied to the device drops below the maximum VPOR level specified, it is recommended that a full power cycle sequence be performed by first driving the VCC pin to GND, waiting at least the minimum tPOFF time and then performing a new power-up sequence in compliance with the requirements defined in this section. Ac Characteristics Symbol fSCL tLOW tHIGH tI tAA tBUF tHD. STA tSU. STA tHD. DAT tSU. DAT tR tF tSU. STO tDH tPWR, R tPUP tPOFF 1.8V Parameter Min Clock frequency, SCL Max Min Clock pulse width high (1 ) Max Unit 1.3 0.6 kHz µs 0.6 0.3 µs 400 Clock pulse width low 1000 Noise suppression time 100 50 Clock low to data out valid 0.9 0.55 ns µs Time the bus must be free before a new transmission can start( 1 ) 1.3 0.5 µs START hold time 0.6 0.25 µs START set-up time 0.6 0.25 µs 0 0 µs 100 100 ns µs Data in hold time Data in set-up time Input rise time (1) 0.3 0.3 300 100 STOP set-up time 0.6 0.25 ns µs Date out hold time Vcc slew rate at power up 50 50 ns Input fall time (1) 0.1 Time required after VCC is stable before the device can accept commands Minimum time at Vcc= 0 V between power cycles tW R Write cycle time (1) 25oC, Page Mode, 3.3V Endurance 2.5-5.5V 50 0.1 50 V/ms 100 100 µs 500 500 ms 5 5 1,000,000 ms Write Cycles Notes: 1. This Parameter is expected by characterization but are not fully screened by test. 2. AC Measurement conditions: RL (Connects to Vcc): 1.3KQ Input Pulse Voltages: 0. 3 Vcc to 0. 7Vcc Input and output timing reference Voltages: 0 . 5 Vcc XBLWversion1.0 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第 8 页 共 15 页 XBLW 24C128 Dc Characteristics VCC1 24C×× A supply VCC ICC1 Supply read current VCC @ 5.5V SCL = 100 kHz ICC2 Supply write current ISB1 1.8 5.5 V 0.4 1.0 mA VCC @ 5.5V SCL = 100 kHz 2.0 3.0 mA Supply current VCC @ 1.8V, VIN = VCC or VSS < 1.0 µA ISB2 Supply current VCC @ 2.5V, VIN = VCC or VSS < 1.0 µA ISB3 Supply current VCC @ 5.5V, VIN = VCC or VSS < 1.0 µA IIL Input leakage current VIN = VCC or VSS 3.0 µA ILO Output leakage current VIN = VCC or VSS 3.0 µA VIL Input low level VIH Input high level VOL1 Output low level VCC @ 1.8V, IOL = 0.15 mA 0.4 V VOL2 Output low level VCC @ 3.0V, IOL = 2.1 mA 0.4 V XBLWversion1.0 -0.6 VCC × 0.7 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 VCC ×0.3 V VCC + 0.5 V 第 9 页 共 15 页 XBLW 24C128 DIP8 Package Outline Dimensions Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 3.710 4.310 0.146 0.170 A1 0.510 A2 3.200 3.600 0.126 0.142 B 0.380 0.570 0.015 0.022 B1 0.020 1.524 (BSC) 0.060 (BSC) C 0.204 0.360 0.008 0.014 D 9.000 9.400 0.354 0.370 E 6.200 6.600 0.244 0.260 E1 e 7.320 7.920 0.288 0.312 L 3.000 3.600 0.118 0.142 E2 8.400 9.000 0.331 0.354 XBLWversion1.0 2.540 (BSC) 0.100 (BSC) 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第 10 页 共 15 页 XBLW 24C128 SOP8 Package Outline Dimensions Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 1.350 1.750 0.053 0.069 A1 0.100 0.250 0.004 0.010 A2 1.350 1.550 0.053 0.061 b c 0.330 0.510 0.013 0.020 0.170 0.250 0.006 0.010 D 4.700 5.100 0.185 0.200 E 3.800 4.000 0.150 0.157 E1 e 5.800 6.200 0.228 L 0.400 1.270 0.016 0.050 θ 0° 8° 0° 8° XBLWversion1.0 0.244 0.050 (BSC) 1.270 (BSC) 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第 11 页 共 15 页 XBLW 24C128 MSOP8 Package Outline Dimensions Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.820 1.100 0.320 0.043 A1 0.020 0.150 0.001 0.006 A2 0.750 0.950 0.030 0.037 b c 0.250 0.380 0.010 0.015 0.090 0.230 0.004 0.009 D e 2.900 3.100 0.114 0.122 0.026 (BSC) 0.65 (BSC) E 2.900 3.100 0.114 0.122 E1 4.750 5.050 0.187 0.199 L 0.400 0.800 0.016 0.031 θ 0° 6° 0° 6° XBLWversion1.0 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第 12 页 共 15 页 XBLW 24C128 TSSOP8 Package Outline Dimensions Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max D 2.900 3.100 0.114 0.122 E 4.300 4.500 0.169 0.177 b c 0.190 0.300 0.007 0.012 0.090 0.200 0.004 0.008 E1 6.250 6.550 0.246 0.258 A 1.100 0.043 A2 0.800 1.000 0.031 0.039 A1 e 0.020 0.150 0.001 0.006 L 0.500 H θ XBLWversion1.0 0.026 (BSC) 0.65 (BSC) 0.700 0.020 1° 0.028 0.01 (TYP) 0.25 (TYP) 7° 1° 7° 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第 13 页 共 15 页 XBLW 24C128 UDFN8 Package Outline Dimensions Symbol Dimensions In Millimeters Min Max A 0.450 0.550 Min 0.017 A1 0.000 0.050 0.000 0.002 b 0.180 0.300 0.007 0.039 Max 0.021 0.006REF b1 c 0.100 0. 160REF 0.200 0.004 0.008 D 1.900 2.100 0.075 0.083 D2 e 1.400 1.600 0.055 0.062 Nd XBLWversion1.0 Dimensions In Inches 0.500BSC 0.020BSC 1.500BSC 0.059BSC E 2.900 3.100 0.114 0.122 E2 1.500 1.700 0.059 0.067 0.020 0.12 L 0.300 0.500 0.012 h 0.200 0.300 0.066 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第 14 页 共 15 页 XBLW 24C128 Statement：  Shenzhen xinbole electronics co., ltd. reserves the right to change the product specifications, without notice! Before placing an order, the customer needs to confirm whether the information obtained is the latest version, and verify the integrity of the relevant information.  Any semiconductor product is liable to fail or malfunction under certain conditions, and the buyer shall be responsible for complying with safety standards in the system design and whole machine manufacturing using Shenzhen xinbole electronics co., ltd products, and take appropriate security measures to avoid the potential risk of failure may result in personal injury or property losses of the situation occurred!  Product performance is never ending, Shenzhen xinbole electronics co., ltd will be dedicated to provide customers with better performance, better quality of integrated circuit products. XBLWversion1.0 文档仅供参考，实际应用测试为准 www.xinboleic.com 技术支持热线：4009682003 第 15 页 共 15 页