XBLW SN74HC/HCT163
4-BIT SYNCHRONOUS BINARY COUNTERS
General Description
The SN74HC/HCT163 is a synchronous presettable binary counter with an internal look-head carry.
Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going
edge of the clock (CP). The outputs (Q0 to Q3) of the counters maybe preset to a HIGH or LOW. A LOW
at the parallel enable input (PE) disables the counting action. It causes the data at the data inputs (D0 to D3)
to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the
levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW
after the next positive-going transition on the clock input (CP). This action occurs regardless of the levels
at input pins PE, CET and CEP. This synchronous reset feature enables the designer to modify the maximum
count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both
CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC).
The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output
of Q0. This pulse can be used to enable the next cascaded stage. Inputs include clamp diodes. This enables the
use of current limiting resistors to interface inputs to voltages in excess of VCC.
The CP to TC propagation delay and CEP to CP set-up time determine the maximum clock frequency for the
cascaded counters according to the following formula:
fmax=1/(tP(max)(CP to TC)+tSU(CEP to CP))
Features
Input levels:
For SN74HC163: CMOS level
For SN74HCT163: TTL level
Synchronous counting and loading
2 count enable inputs for n-bit cascading
Synchronous reset
Positive-edge triggered clock
Specified from -40℃ to +125℃
Packaging information: DIP16/SOP16/TSSOP16
Ordering Information
Product Model
XBLW SN74HC163N
XBLW SN74HC163DTR
XBLW SN74HC163TDTR
XBLW SN74HCT163N
XBLW SN74HCT163DTR
XBLW SN74HCT163TDTR
XBLWversion1.0
Package Type
DIP-16
SOP-16
TSSOP-16
DIP-16
SOP-16
TSSOP-16
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Marking
74HC163N
74HC163
74HC163
74HCT163N
74HCT163
74HCT163
Packing
Tube
Tape
Tape
Tube
Tape
Tape
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Packing Qty
1000Pcs/Box
2500Pcs/Reel
3000Pcs/Reel
1000Pcs/Box
2500Pcs/Reel
3000Pcs/Reel
1 / 18
XBLW SN74HC/HCT163
4-BIT SYNCHRONOUS BINARY COUNTERS
Block Diagram And Pin Description
Block Diagram
Figure 1. Logic symbol
Figure 2. IEC logic symbol
Figure 3.Functional diagram
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XBLW SN74HC/HCT163
4-BIT SYNCHRONOUS BINARY COUNTERS
Figure 4. Logic diagram
Figure 5. State diagram
Figure 6. Typical timing sequence
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XBLW SN74HC/HCT163
4-BIT SYNCHRONOUS BINARY COUNTERS
Pin Configurations
Pin Description
Pin No.
Pin Name
Description
1
MR
asynchronous master reset (active LOW)
2
CP
clock input (LOW-to-HIGH, edge triggered)
3
D0
data input
4
D1
data input
5
D2
data input
6
D3
data input
7
CEP
count enable input
8
GND
ground (0V)
9
PE
parallel enable input (active LOW)
10
CET
count enable carry input
11
Q3
flip-flop output
12
Q2
flip-flop output
13
Q1
flip-flop output
14
Q0
15
TC
flip-flop output
terminal count output
16
VCC
supply voltage
Function Table
Operating mode
reset (clear)
parallel load
count
hold (do nothing)
XBLWversion1.0
Input
Output
MR
l
CP
CEP
CET
↑
Dn
Qn
TC
X
PE
X
X
h
↑
X
L
L
h
↑
X
X
l
l
L
L
h
↑
X
X
l
h
H
L
h
X
h
h
h
X
count
[2]
l
X
h
X
qn
L
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XBLW SN74HC/HCT163
4-BIT SYNCHRONOUS BINARY COUNTERS
h
X
X
l
X
h
L
qn
Note:
[1] H=HIGH voltage level; L=LOW voltage level; X=don’t care; ↑=LOW-to-HIGH clock transition;
l=LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
h=HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
q=lower case letters indicate the state of the referenced output one set-up time prior to the LOWto-HIGH CP transition.
[2] The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH).
Electrical Parameter
Absolute Maximum Ratings
(Voltages are referenced to GND(ground=0V), unless otherwise specified.)
Parameter
Symbol
Conditions
-
Min.
-0.5
Max.
+7.0
Unit
supply voltage
VCC
input clamping
current
IIK
VI < -0.5V or VI > VCC+0.5V
-
±20
mA
output clamping
current
IOK
VO < -0.5V or VO > VCC+0.5V
-
±20
mA
-0.5V < VO < VCC+0.5V
-
±25
mA
+50
mA
-
mA
V
output current
IO
supply current
ICC
ground current
storage
temperature
-
IGND
-
-50
Tstg
-
-65
+150
℃
total power
dissipation
Ptot
-
-
500
mW
Soldering
temperatur
e
TL
3.2
245
260
DIP
SOP/TSSOP
10s
℃
Recommended Operating Conditions
Conditions
Parameter
Symbol
supply voltage
VCC
input voltage
-
VI
-
Min.
Typ.
Max.
Unit
2.0
5.0
6.0
V
0
-
VCC
V
-
VCC
V
625
ns/V
139
ns/V
ns/V
SN74HC163
output voltage
VO
input transition
rise and fall rate
Δt/ΔV
ambient
temperature
Tamb
VCC=2.0V
0
VCC=4.5V
-
1.67
VCC=6.0V
-
-
83
-
-40
-
+125
℃
4.5
5.0
5.5
V
0
-
VCC
V
-
VCC
V
-
SN74HCT163
supply voltage
VCC
-
input voltage
VI
output voltage
VO
input transition
rise and fall rate
-
0
Δt/ΔV
VCC=4.5V
-
1.67
139
ns/V
ambient
temperature
Tamb
-
-40
-
+125
℃
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XBLW SN74HC/HCT163
4-BIT SYNCHRONOUS BINARY COUNTERS
DC Characteristics 1
(Tamb=25℃, voltages are referenced to GND (ground=0V), unless otherwise specified.)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
-
V
SN74HC163
HIGH-level
input voltage
VIH
LOW-level
input voltage
VIL
HIGH-level
output voltage
LOW-level
output voltage
VOH
VCC=2.0V
1.5
1.2
VCC=4.5V
3.15
2.4
VCC=6.0V
4.2
3.2
VCC=2.0V
-
supply current
input
capacitance
V
0.8
0.5
V
2.1
1.35
V
-
VCC=6.0V
2.8
1.8
V
IO=-20uA; VCC=2.0V
1.9
2.0
4.4
4.5
-
V
IO=-20uA; VCC=4.5V
IO=-20uA; VCC=6.0V
5.9
6.0
IO=-4.0mA; VCC=4.5V
3.98
4.32
IO=-5.2mA; VCC=6.0V
5.48
5.81
IO=20uA; VCC=2.0V
-
VI = VIH or VIL
IO=20uA; VCC=6.0V
VI = VIH or VIL
IO=4.0mA; VCC=4.5V
IO=5.2mA; VCC=6.0V
input leakage
current
V
VCC=4.5V
IO=20uA; VCC=4.5V
VOL
-
-
V
V
-
V
V
0
0.1
V
0
0.1
V
0
0.1
V
0.15
0.26
V
-
0.16
0.26
V
-
II
VI=VCC or GND; VCC=6.0V
-
-
±1.0
uA
ICC
VI=VCC or GND; IO=0A; VCC=6.0V
-
-
8.0
uA
-
3.5
-
pF
CI
SN74HCT163
HIGH-level
input voltage
VIH
VCC=4.5V to 5.5V
2.0
1.6
-
V
LOW-level
input voltage
VIL
VCC=4.5V to 5.5V
-
1.2
0.8
V
HIGH-level
output voltage
VOH
VI = VIH or VIL;
VCC=4.5V
IO=-20uA
4.4
4.5
V
IO=-4.0mA
3.98
4.32
-
V
LOW-level
output voltage
VOL
VI = VIH or VIL;
VCC=4.5V
IO=20uA
-
0
0.1
V
IO=4.0mA
0.26
V
input leakage
current
-
0.15
II
VI=VCC or GND; VCC=5.5V
-
-
±1.0
uA
supply current
ICC
VI=VCC or GND; IO=0A; VCC=5.5V
-
-
8.0
uA
-
-
342
uA
-
-
396
uA
-
-
90
uA
-
-
270
uA
-
-
108
uA
-
3.5
-
pF
—
additional
supply current
input
capacitance
XBLWversion1.0
ΔICC
CI
pin MR
pin CP
per input pin;
VI=VCC-2.1V;
other inputs at VCC
or GND; IO=0A;
VCC=4.5V to 5.5V
pin CEP and Dn
pin CET
pin PE
-
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XBLW SN74HC/HCT163
4-BIT SYNCHRONOUS BINARY COUNTERS
DC Characteristics 2
(Tamb=-40℃ to +85℃, voltages are referenced to GND (ground=0V), unless otherwise specified.)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
VCC=2.0V
1.5
3.15
-
V
VCC=4.5V
-
4.2
-
-
V
VCC=6.0V
-
V
VCC=2.0V
-
-
0.5
V
-
-
1.35
V
-
V
IO=-20uA; VCC=2.0V
1.9
1.8
IO=-20uA; VCC=4.5V
-
-
V
4.4
IO=-20uA; VCC=6.0V
5.9
-
-
IO=-4.0mA; VCC=4.5V
3.84
-
-
IO=-5.2mA; VCC=6.0V
-
-
V
5.34
-
-
0.1
V
IO=20uA; VCC=2.0V
-
V
-
-
0.1
V
-
-
0.1
V
-
-
0.33
V
-
-
0.33
V
SN74HC163
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
LOW-level
output voltage
VIH
VCC=4.5V
VIL
VCC=6.0V
VOH
VI = VIH or VIL
IO=20uA; VCC=4.5V
VOL
IO=20uA; VCC=6.0V
VI = VIH or VIL
IO=4.0mA; VCC=4.5V
IO=5.2mA; VCC=6.0V
V
V
input leakage
current
II
VI=VCC or GND; VCC=6.0V
-
-
±1.0
uA
supply current
ICC
VI=VCC or GND; IO=0A; VCC=6.0V
-
-
80
uA
SN74HCT163
HIGH-level
input voltage
VIH
VCC=4.5V to 5.5V
2.0
-
-
V
LOW-level
input voltage
VIL
VCC=4.5V to 5.5V
-
-
0.8
V
HIGH-level
output voltage
VOH
VI = VIH or VIL;
VCC=4.5V
IO=-20uA
4.4
-
V
IO=-4.0mA
3.84
-
V
LOW-level
output voltage
VOL
VI = VIH or VIL;
VCC=4.5V
IO=20uA
-
-
0.1
V
IO=4.0mA
-
V
input leakage
current
-
0.33
II
VI=VCC or GND; VCC=5.5V
-
-
±1.0
uA
supply current
ICC
VI=VCC or GND; IO=0A; VCC=5.5V
-
-
80
uA
pin MR
pin CP
-
-
427.5
uA
-
495
uA
pin CEP and Dn
-
-
-
additional
supply current
XBLWversion1.0
ΔICC
per input pin;
VI=VCC-2.1V;
other inputs at VCC
or GND; IO=0A;
VCC=4.5V to 5.5V
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pin CET
pin PE
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112.5
uA
-
337.5
uA
-
135
uA
7 / 18
XBLW SN74HC/HCT163
4-BIT SYNCHRONOUS BINARY COUNTERS
DC Characteristics 3
(Tamb=-40℃ to +125℃, voltages are referenced to GND (ground=0V), unless otherwise specified.)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
VCC=2.0V
1.5
VCC=4.5V
-
-
V
3.15
4.2
-
V
VCC=6.0V
-
-
-
0.5
V
VCC=2.0V
-
V
-
-
1.35
V
-
1.8
V
IO=-20uA; VCC=2.0V
1.9
4.4
-
-
V
IO=-20uA; VCC=4.5V
IO=-20uA; VCC=6.0V
5.9
-
-
IO=-4.0mA; VCC=4.5V
3.7
-
-
5.2
-
-
V
IO=-5.2mA; VCC=6.0V
-
V
IO=20uA; VCC=2.0V
-
-
0.1
V
-
-
0.1
V
-
-
0.1
V
-
-
0.4
V
-
-
0.4
V
SN74HC163
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
LOW-level
output voltage
VIH
VIL
VCC=4.5V
VCC=6.0V
VOH
VI = VIH or VIL
IO=20uA; VCC=4.5V
VOL
IO=20uA; VCC=6.0V
VI = VIH or VIL
IO=4.0mA; VCC=4.5V
IO=5.2mA; VCC=6.0V
V
V
input leakage
current
II
VI=VCC or GND; VCC=6.0V
-
-
±1.0
uA
supply current
ICC
VI=VCC or GND; IO=0A; VCC=6.0V
-
-
160
uA
SN74HCT163
HIGH-level
input voltage
VIH
VCC=4.5V to 5.5V
2.0
-
-
V
LOW-level
input voltage
VIL
VCC=4.5V to 5.5V
-
-
0.8
V
HIGH-level
output voltage
VOH
VI = VIH or VIL;
VCC=4.5V
IO=-20uA
4.4
-
V
IO=-4.0mA
3.7
-
LOW-level
output voltage
VOL
VI = VIH or VIL;
VCC=4.5V
-
V
IO=4.0mA
-
0.1
V
IO=20uA
-
V
input leakage
current
-
0.4
II
VI=VCC or GND; VCC=5.5V
-
-
±1.0
uA
supply current
ICC
VI=VCC or GND; IO=0A; VCC=5.5V
-
-
160
uA
pin MR
pin CP
-
-
465.5
uA
-
-
-
-
-
additional
supply current
XBLWversion1.0
ΔICC
per input pin;
VI=VCC-2.1V;
other inputs at VCC
or GND; IO=0A;
VCC=4.5V to 5.5V
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pin CEP and Dn
pin CET
pin PE
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539
uA
122.5
uA
-
367.5
uA
-
147
uA
8 / 18
XBLW SN74HC/HCT163
4-BIT SYNCHRONOUS BINARY COUNTERS
AC Characteristics 1
(Tamb=25℃, GND=0V, CL=50pF, unless otherwise specified.)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
SN74HC163
55
185
ns
20
37
ns
17
ns
16
31
69
215
ns
25
43
ns
21
37
ns
20
36
120
ns
13
24
ns
11
20
ns
10
19
75
ns
7
15
ns
13
ns
VCC=2.0V
80
6
17
16
6
-
ns
VCC=4.5V
14
5
-
ns
VCC=6.0V
ns
VCC=2.0V
80
22
-
16
8
-
ns
VCC=4.5V
ns
VCC=6.0V
14
6
-
ns
VCC=2.0V
80
17
ns
VCC=4.5V
16
6
-
VCC=6.0V
5
-
ns
14
175
58
-
ns
VCC=2.0V
ns
VCC=4.5V
35
21
-
30
17
-
ns
VCC=6.0V
0
-14
-
ns
VCC=2.0V
ns
VCC=4.5V
0
-5
-
VCC=6.0V
-4
-
ns
0
5
15
-
VCC=2.0V
ns
MHz
VCC=4.5V
27
46
32
51
-
VCC=2.0V
CP to Qn;
see Figure 8
VCC=4.5V
VCC=5.0V; CL=15pF
VCC=6.0V
VCC=2.0V
propagation
delay
tpd
CP to TC;
see Figure 8
VCC=4.5V
VCC=5.0V; CL=15pF
VCC=6.0V
VCC=2.0V
CET to TC;
see Figure 9
VCC=4.5V
VCC=5.0V; CL=15pF
VCC=6.0V
transition time
pulse width
tt
tW
see Figure 8
and Figure
9
CP HIGH or LOW;
see Figure 8
R, Dn to CP;
see Figure 10,
11
set-up time
tsu
PE to CP;
see Figure 10
CEP, CET to CP;
see Figure 12
—
Dn, PE, CEP, CET,
hold time
maximum
frequency
th
fmax
MR to CP;
see Figure 10, 11,
12
CP; see Figure 8
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=5.0V; CL=15pF
VCC=6.0V
power
dissipation
capacitanc
e
CPD
f i=1MHz; VCC=5.0V; VI=GND to VCC
-
55
-
ns
ns
ns
MHz
MHz
-
MHz
33
-
pF
23
39
ns
20
49
ns
32
ns
SN74HCT163
propagation
delay
tpd
CP to Qn;
see Figure 8
VCC=4.5V
VCC=5.0V; CL=15pF
-
CP to TC;
see Figure 8
VCC=4.5V
-
29
VCC=5.0V; CL=15pF
-
25
CET to TC;
see Figure 9
VCC=4.5V
VCC=5.0V; CL=15pF
transition time
tt
VCC=4.5V; see Figure 8, 9
pulse width
tW
CP HIGH or LOW; VCC=4.5V; see Figure 8
XBLWversion1.0
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-
-
17
ns
ns
-
14
20
15
ns
7
6
-
ns
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ns
9 / 18
XBLW SN74HC/HCT163
4-BIT SYNCHRONOUS BINARY COUNTERS
—
set-up time
MR, Dn to CP; VCC=4.5V; see Figure 10, 11
20
9
-
ns
PE to CP; VCC=4.5V; see Figure 10
20
11
-
ns
CEP, CET to CP; VCC=4.5V;see Figure 12
40
24
-
ns
0
-5
-
ns
26
45
-
MHz
-
50
-
tsu
—
hold time
th
maximum
frequency
fmax
power
dissipation
capacitanc
e
CPD
—
Dn, PE, CEP, CET, MR to CP;
VCC=4.5V; see Figure 10, 11, 12
CP; see Figure 8
VCC=4.5V
VCC=5.0V; CL=15pF
-
MHz
35
-
pF
Min.
Typ.
Max.
Unit
-
-
230
ns
-
-
46
ns
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCC=2.0V
100
VCC=4.5V
20
f i=1MHz; VCC=5.0V; VI=GND to VCC- 1.5V
Note:
[1] tpd is the same as tPLH and tPHL.
[2] tt is the sameastTHL and tTLH.
[3] CPD isused to determine the dynamic power dissipation (PD in uW).
PD=CPD ×VCC2 ×fi×N+Σ(CL×VCC2 ×fo) where:
f i=input frequency in MHz;
fo=output frequency in MHz;
CL=output load capacitance in pF;
VCC=supply voltage in V;
N=number of inputs switching;
Σ(CL×VCC2 ×fo)=sum of outputs.
AC Characteristics 2
(Tamb=-40℃ to +85℃, GND=0V, CL=50pF, unless otherwise specified.)
Parameter
Symbol
Conditions
SN74HC163
CP to Qn;
see Figure 8
propagation
delay
tpd
CP to TC;
see Figure 8
CET to TC;
see Figure 9
transition time
pulse width
tt
tW
see Figure 8
and Figure
9
CP HIGH or LOW;
see Figure 8
R, Dn to CP;
see Figure 10,
11
set-up time
XBLWversion1.0
tsu
PE to CP;
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VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=6.0V
17
VCC=2.0V
100
VCC=4.5V
20
VCC=6.0V
17
VCC=2.0V
100
VCC=4.5V
20
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39
ns
270
ns
54
ns
46
ns
150
ns
30
ns
26
ns
95
ns
19
ns
-
16
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
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XBLW SN74HC/HCT163
4-BIT SYNCHRONOUS BINARY COUNTERS
see Figure 10
CEP, CET to CP;
see Figure 12
Dn, PE, CEP, CET
hold time
maximum
frequency
th
MR to CP;
see Figure 10, 11, 12
CP; see Figure 8
fmax
VCC=6.0V
17
VCC=2.0V
220
VCC=4.5V
44
VCC=6.0V
37
VCC=2.0V
0
VCC=4.5V
0
VCC=6.0V
0
VCC=2.0V
4
VCC=4.5V
22
VCC=6.0V
26
SN74HCT163
propagation
delay
tpd
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
-
-
ns
MHz
-
-
-
-
MHz
MHz
CP to Qn;
see Figure 8
VCC=4.5V
-
-
49
ns
CP to TC;
see Figure 8
VCC=4.5V
-
-
61
ns
CET to TC;
see Figure 9
VCC=4.5V
-
-
44
ns
transition time
pulse width
tt
VCC=4.5V; see Figure 8, 9
25
19
ns
CP HIGH or LOW; VCC=4.5V; see Figure 8
-
tW
-
-
ns
set-up time
tsu
MR, Dn to CP; VCC=4.5V; see Figure 10, 11
25
-
-
ns
PE to CP; VCC=4.5V; see Figure 10
25
-
-
ns
CEP, CET to CP; VCC=4.5V;see Figure 12
50
-
-
ns
0
-
-
ns
21
-
-
MHz
Min.
Typ.
Max.
Unit
-
-
280
ns
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
—
hold time
th
maximum
frequency
fmax
—
Dn, PE, CEP, CET, MRto CP;
VCC=4.5V; see Figure 10, 11, 12
CP; see Figure 8
VCC=4.5V
Note:
[1] tpd is the same as tPLH and tPHL.
[2] tt is the sameastTHL and tTLH.
AC Characteristics 3
(Tamb=-40℃ to +125℃, GND=0V, CL=50pF, unless otherwise specified.)
Parameter
Symbol
Conditions
SN74HC163
CP to Qn;
see Figure 8
propagation
delay
tpd
CP to TC;
see Figure 8
CET to TC;
see Figure 9
transition time
XBLWversion1.0
tt
see Figure 8
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VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
Technical Support:4009682003
56
ns
48
ns
320
ns
65
ns
55
ns
180
ns
36
ns
31
ns
110
ns
22
ns
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XBLW SN74HC/HCT163
4-BIT SYNCHRONOUS BINARY COUNTERS
and Figure
9
pulse width
tW
CP HIGH or LOW;
see Figure 8
R, Dn to CP;
see Figure 10,
11
set-up time
PE to CP;
see Figure 10
tsu
CEP, CET to CP;
see Figure 12
maximum
frequency
th
-
-
19
ns
VCC=2.0V
120
24
-
-
ns
VCC=4.5V
20
-
ns
VCC=6.0V
-
-
ns
VCC=2.0V
120
-
24
-
-
ns
VCC=4.5V
20
-
ns
VCC=6.0V
-
-
ns
VCC=2.0V
120
-
ns
VCC=4.5V
24
-
20
-
-
ns
VCC=6.0V
265
-
ns
VCC=2.0V
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
-
-
ns
MHz
-
-
-
-
MHz
VCC=4.5V
53
VCC=6.0V
45
Dn, PE, CEP, CET
VCC=2.0V
0
MR to CP;
see Figure 10, 11, 12
VCC=4.5V
0
VCC=6.0V
0
VCC=2.0V
4
VCC=4.5V
18
VCC=6.0V
21
—
hold time
VCC=6.0V
—
CP; see Figure 8
fmax
SN74HCT163
propagation
transition time
pulse width
set-up time
VCC=4.5V
-
-
59
ns
CP to TC;
see Figure 8
VCC=4.5V
-
-
74
ns
CET to TC;
see Figure 9
VCC=4.5V
-
-
48
ns
CP to Qn;
tpd
delay
MHz
see Figure 8
tt
VCC=4.5V; see Figure 8, 9
30
22
ns
CP HIGH or LOW; VCC=4.5V; see Figure 8
-
tW
-
-
ns
MR, Dn to CP; VCC=4.5V; see Figure 10, 11
30
-
-
ns
PE to CP; VCC=4.5V; see Figure 10
30
-
-
ns
CEP, CET to CP; VCC=4.5V;see Figure 12
60
-
-
ns
0
-
-
ns
17
-
-
MHz
—
tsu
—
hold time
th
maximum
frequency
fmax
—
Dn, PE, CEP, CET, MRto CP;
VCC=4.5V; see Figure 10, 11, 12
CP; see Figure 8
VCC=4.5V
Note:
[1] tpd is the same as tPLH and tPHL.
[2] tt is the sameastTHL and tTLH.
XBLWversion1.0
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XBLW SN74HC/HCT163
4-BIT SYNCHRONOUS BINARY COUNTERS
Testing Circuit
AC Testing Circuit
Figure 7. Test circuit for measuring switching times
Definitions for test circuit:
CL=Load capacitance including jig and probe capacitance.
RT=Termination resistance should be equal to the output impedance Zo of the pulse generator.
RL=Load resistance.
S1=Test selection switch
AC Testing Waveforms
Figure 8. The clock (CP) to outputs (Qn, TC) propagation delays, pulse width, output transition times and maximum
frequency
XBLWversion1.0
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XBLW SN74HC/HCT163
4-BIT SYNCHRONOUS BINARY COUNTERS
Figure 9. The count enable carry input (CET) to terminal count output (TC) propagation delays and output transition
times
—
Figure 10. The data input (Dn) and parallel enable input (PE) set-up and hold times
Measurement Points
Input
Type
Output
SN74HC163
VI
VM
VM
GND to VCC
0.5×VCC
0.5×VCC
SN74HCT163
GND to 3V
1.3V
1.3V
Test Data
Type
Input
Load
S1 position
VI
CL
RL
tPHL, tPLH
SN74HC163
t r ,t f
VCC
6ns
15pF, 50pF
1kΩ
open
SN74HCT163
3V
6ns
15pF, 50pF
1kΩ
open
XBLWversion1.0
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XBLW SN74HC/HCT163
4-BIT SYNCHRONOUS BINARY COUNTERS
Package Information
DIP16
XBLWversion1.0
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XBLW SN74HC/HCT163
4-BIT SYNCHRONOUS BINARY COUNTERS
SOP16
XBLWversion1.0
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XBLW SN74HC/HCT163
4-BIT SYNCHRONOUS BINARY COUNTERS
TSSOP16
XBLWversion1.0
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Technical Support:4009682003
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XBLW SN74HC/HCT163
4-BIT SYNCHRONOUS BINARY COUNTERS
Statement:
Shenzhen xinbole electronics co., ltd. reserves the right to change the product specifications, without notice!
Before placing an order, the customer needs to confirm whether the information obtained is the latest version,
and verify the integrity of the relevant information.
Any semiconductor product is liable to fail or malfunction under certain conditions, and the buyer shall be
responsible for complying with safety standards in the system design and whole machine manufacturing using
Shenzhen xinbole electronics co., ltd products, and take appropriate security measures to avoid the potential risk
of failure may result in personal injury or property losses of the situation occurred!
This document is for referenceonly,and the actual use should be based on the application test results.
Product performance is never ending, Shenzhen xinbole electronics co., ltd will be dedicated to provide
customers with better performance, better quality of integrated circuit products.
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