NS2510/NS2520/NS2530
HD Video Transmitter
Revision 0.90
September 11, 2017
HD Video Transmitter
Copyright 2014-2017 Norel Systems Limited
All rights reserved.
No part of this document may be reproduced, stored, or transmitted, in any form or by any means without
the prior written permission of Norel Systems.
Data contained in this document is subject to change without notice. Norel Systems makes no warranties of
any kind, of functionality or suitability. Norel Systems assumes no responsibility for any errors that may
appear in this document.
Norel Systems assumes no responsibility or liability for any use of the information contained herein.
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Table of Contents
1.
2.
3.
Introduction .............................................................................................................................................. 6
1.1.
Related Documents ...................................................................................................................... 6
1.2.
Applications ................................................................................................................................. 6
1.3.
Features ........................................................................................................................................ 7
Pin Assignment and Description .............................................................................................................. 9
2.1.
Pin Assignment ............................................................................................................................ 9
2.2.
Pin Descriptions ......................................................................................................................... 10
Functional Description ........................................................................................................................... 13
3.1.
AVT Technologies ..................................................................................................................... 13
3.2.
Pixel Interface ............................................................................................................................ 13
3.3.
4.
5.
3.2.1.
BT.656 YCbCr 4:2:2 ..................................................................................................... 13
3.2.2.
BT.1120 YCbCr 4:2:2 ................................................................................................... 15
3.2.3.
DVP YCbCr 4:2:2 ......................................................................................................... 17
3.2.4.
Supported Video Formats YCbCr 4:2:2 ........................................................................ 18
Audio Embedding and Control .................................................................................................. 20
3.3.1.
Pass-through Mode ........................................................................................................ 20
3.3.2.
Appending Mode ........................................................................................................... 20
3.3.3.
Replacing Mode ............................................................................................................ 20
3.3.4.
Eliminating Mode .......................................................................................................... 20
3.4.
Audio Interface .......................................................................................................................... 20
3.5.
I2C and UART Interface............................................................................................................ 22
3.6.
SPI Flash Interface ..................................................................................................................... 22
3.7.
Boot, Firmware Loading and Update......................................................................................... 22
3.8.
Reset and Clock Output ............................................................................................................. 23
Electrical Characteristics ........................................................................................................................ 24
4.1.
Absolute Maximum Ratings ...................................................................................................... 24
4.2.
Recommended Operating Conditions ........................................................................................ 24
4.3.
Clock Requirements ................................................................................................................... 24
4.4.
DC Characteristics for Digital IO .............................................................................................. 25
4.5.
Power Up and Reset Timing ...................................................................................................... 25
Package Information .............................................................................................................................. 27
5.1.
50 pin QFN (7x5.5) package...................................................................................................... 27
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List of Figures
Figure 1. Functional Block Diagram ................................................................................................................ 6
Figure 2. QFN50 Package Pin Assignment ...................................................................................................... 9
Figure 3. BT.656 Htotal Encoding.................................................................................................................. 14
Figure 4. BT.656 Hactive Encoding YCbCr 4:2:2.......................................................................................... 14
Figure 5. 8/10-bit BT.1120 Htotal Encoding .................................................................................................. 16
Figure 6. 16-bit BT.1120 Htotal Encoding ..................................................................................................... 16
Figure 7. 16-bit BT.1120 Hactive Encoding YCbCr 4:2:2 ............................................................................. 16
Figure 8. DVP Frame Definition .................................................................................................................... 18
Figure 9. Audio Interface Topologies ............................................................................................................. 22
Figure 10. Power Up and Reset Timing.......................................................................................................... 25
Figure 11. 50pin QFN Package Mechanical Data........................................................................................... 27
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List of Tables
Table 1. NS2510/NS2520/NS2530 Features .................................................................................................... 7
Table 2. Pin Type Definitions ......................................................................................................................... 10
Table 3. Pin Descriptions ................................................................................................................................ 10
Table 4. Pin Mapping for 8-bit BT.656, 8-bit BT.1120 and 8-bit DVP .......................................................... 15
Table 5. Pin Mapping for 10-bit BT.656, 10-bit BT.1120 and 10-bit DVP .................................................... 15
Table 6. Pin Mapping for 16-bit BT.1120 ...................................................................................................... 17
Table 7. Supported Video Formats YCbCr 4:2:2 ........................................................................................... 19
Table 8. Audio interface signals ..................................................................................................................... 21
Table 9. Absolute Maximum Ratings ............................................................................................................. 24
Table 10. Recommended Operating Conditions ............................................................................................. 24
Table 11. Clock Requirements........................................................................................................................ 24
Table 12. DC Characteristics for Digital IO ................................................................................................... 25
Table 13. Power Up and Reset Timing Requirement ..................................................................................... 26
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1. Introduction
NS2510/NS2520/NS2530 are HD video transmitters supporting Advanced Video Transport (AVT)
technology with visually lossless digital video compression. They also support uncompressed video
transmission and are compatible with SMPTE SD-SDI, HD-SDI and 3G-SDI.
NS2510 supports up to HD 720p30 and HD 1080p15, NS2520 supports up to HD 720p60 and HD 1080p30.
NS2530 also supports HD 1080p50/60.
NS2510/NS2520/NS2530 employ Norelsys’ advanced video compression and serial data adaptation
technologies. It can extend the reach of HD video over 500 meters on 75-3 coaxial cable. Norelsys’
advanced digital video compression technologies achieve better video quality at less than half of the data
rate required by MJPEG. The chips also include Norelsys’ serial data adaptation engine which automatically
adjusts data equalization, transfer rate and compression ratio based on cable quality and cable length. A
programmable Reed-Solomon FEC block is implemented for increased reliability.
NS2510/NS2520/NS2530
PLL with Low
Noise VCO
Real-time Compression,
Audio Embedding &
Ancillary Data Insertion
Video Data
Audio Data
Video Capture
Logic
Serial
Cable Driver
SDO
8B/10B Encoder,
Scrambler & Serializer
Reed-Solomon FEC
Audio Logic
SPI, I2C,
UART & GPIO
SDO
Host Interface
Configuration
Registers
Power
Management
Figure 1. Functional Block Diagram
NS2510/NS2520/NS2530 implement advanced features such as transmission of downstream (camera to
DVR) audio/control and upstream (DVR to Camera) audio/control over the same cable.
NS2510/NS2520/NS2530 support both coaxial cable and STP cable.
1.1. Related Documents
EDN-5076, NS2511/NS2521/NS2531 Dual-port HD Video Receiver
EDN-5077, NS2532 Dual-port Full HD Video Receiver
1.2. Applications
Automotive camera and video
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Video surveillance
Industrial camera and video
1.3. Features
Table 1. NS2510/NS2520/NS2530 Features
NS2510
NS2520
NS2530
AVT Serial Interface
Serial data rate
AVT compressed video:
AVT compressed video:
AVT compressed video:
- 30Mbps-270Mbps
- 30Mbps-270Mbps
- 30Mbps-371.25Mbps
Uncompressed video:
Uncompressed video:
Uncompressed video:
- 270Mbps, 742.5Mbps
- 270Mbps, 742.5Mbps,
- 270Mbps, 742.5Mbps,
1.485Gbps
1.485Gbps, 2.970Gbps
Video formats
Selective video formats
Selective video formats
Selective video formats
(NS2510/NS2520/NS2530 support an
AVT compressed mode:
AVT compressed mode:
AVT compressed mode:
extensive selection of video formats, for
- HD 720p 24/25/30, HD
- HD 720p 24/25/30/50/60,
- HD 720p 24/25/30/50/60,
more details, see section 3.2.4)
1080p 12/12.5/15
Uncompressed video mode:
- SD-SDI, HD@742.5Mbps
HD 1080p
HD 1080p
12/12.5/15/24/25/30
12/12.5/15/24/25/30, HD
Uncompressed video mode:
1080p 50/60
- SD-SDI, HD@742.5Mbps,
Uncompressed mode:
HD-SDI
- SD-SDI, HD@742.5Mbps,
HD-SDI, 3G-SDI
Compression ratio
2 to 30
Automatic adaptation of compression
Yes
ratio
Support forward error correction for
Yes, Reed-Solomon
compressed video
Embedded audio and AUX data
Yes
forwarding from Pixel Interface
Support loss of cable detection
Yes
Supported cable types
Single-ended coaxial cable
Shielded twisted pair cable
Pixel Interface
Pixel interface width
8/10/16 bits
Pixel clock
Up to 148.5MHz
Pixel interface sampling
SDR, sampled by pixel clock rising or falling edge; Setup/hold time programmable
Pixel interface format
BT.656, BT.1120, DVP (Omnivision)
YCbCr4:2:2
RGB (uncompressed video only)
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Pixel interface voltage
1.8/2.7/3.3V
Audio Interface
Support bi-directional audio
Yes
Audio interface and format
Downstream (camera to DVR):
- I2S master/slave, SPDIF slave
- 2 channels
- 8/16/24/32/44.1/48/96K samples per second
- 16/20/24 bits per sample
Upstream (DVR to camera):
- I2S master/slave
- 1 channel
- 8K samples per second
- 16 bits per sample
Support forward error correction for
Yes, ECC
downstream (camera to DVR) audio
I2C and UART Interfaces
Support bi-directional control
Yes, I2C and UART
I2C port
1 port, master or slave
UART port
Tx and Rx
SPI Flash Interface
Support in-system programming of SPI
Yes
Flash
Support sharing SPI Flash with ISP or
Yes
other chips
Other
Support clock output
Programmable 6/12/18/24/27/30/54/74.5MHz
Support RESETN output
Controlled by on-chip MCU
External crystal
27MHz, 300ppm
ESD
HBM pin 32 and 33 +/-8KV, other pins +/-4KV
CDM
+/-1KV
Package
QFN50, 7x5.5mm
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2. Pin Assignment and Description
VDDC
CLK_OUT
PCLK
D19
D18
D17
D16
D15
D14
D13
D12
25
24
23
22
21
20
19
18
17
16
15
2.1. Pin Assignment
VDDA
26
14
VDDBT
XO
27
13
D9
XI
28
12
D8
RSET
29
11
D7
VDDA33
30
10
D6
RESEARVED
31
NS2510/NS2520/NS2530 9
D5
SDO_N
32
8
D4
SDO_P
33
7
D3
VDDR
34
6
D2
UART_RX
35
5
VDDC
UART_TX
36
4
DE
RESETN
37
3
VSYNC
GPIO2
38
2
RESETN_OUT
NSPI_DO
39
1
INT
46
47
48
49
50
I2S_AD_OUT
I2S_AD_IN
WCLK
ACLK
44
VDDC33
I2C_CK
43
VDDC
45
42
NSPI_CS
I2C_DATA
41
NSPI_CK
NSPI_DI
40
QFN50
Figure 2. QFN50 Package Pin Assignment
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2.2. Pin Descriptions
Table 2. Pin Type Definitions
Type
Description
I
Input
O
Output
I/O
Input/output
OD
Open drain driver
Hi-Z
Output in Hi-Z state
PH
Pull high resistor, nominal 100K
PL
Pull low resistor, nominal 100K
Off
PH and/or PL resistors are off
PH/PL/Off
Programmable PH on, PL on or both are off
Table 3. Pin Descriptions
Pin Type
Pin
During operation
At reset
Power
RESETN=HIGH
RESETN=LOW
Supply
Type
PH/PL
Type
PH/PL
Pin Name
Description
AVT Serial Interface
32
SDO_N
O
-
O
-
-
33
SDO_P
O
-
O
-
-
AVT Serial Interface signals.
Pixel Interface
6
D2
I
PH/PL/Off
I
Off
VDDBT
7
D3
I
PH/PL/Off
I
Off
VDDBT
8
D4
I
PH/PL/Off
I
Off
VDDBT
9
D5
I
PH/PL/Off
I
Off
VDDBT
10
D6
I
PH/PL/Off
I
Off
VDDBT
11
D7
I
PH/PL/Off
I
Off
VDDBT
12
D8
I
PH/PL/Off
I
Off
VDDBT
13
D9
I
PH/PL/Off
I
Off
VDDBT
15
D12
I
PH/PL/Off
I
Off
VDDBT
16
D13
I
PH/PL/Off
I
Off
VDDBT
17
D14
I
PH/PL/Off
I
Off
VDDBT
18
D15
I
PH/PL/Off
I
Off
VDDBT
19
D16
I
PH/PL/Off
I
Off
VDDBT
20
D17
I
PH/PL/Off
I
Off
VDDBT
21
D18
I
PH/PL/Off
I
Off
VDDBT
22
D19
I
PH/PL/Off
I
Off
VDDBT
3
VSYNC
I
PH/PL/Off
I
Off
VDDBT
Pixel interface vertical sync.
4
DE
I
PH/PL/Off
I
Off
VDDBT
Pixel interface data enable.
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Pixel interface data input.
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23
PCLK
I
PH/PL/Off
I
Off
VDDBT
Pixel clock.
Clock
out
(VDDBT
power
supply).
Frequency is programmable to one of the
24
CLK_OUT
O
PH/PL/Off
Hi-Z
Off
VDDBT
following: 6, 12, 18, 24, 27, 30, 54,
74.25MHz.
1
INT
I/O
PH/PL/Off
I
Off
VDDBT
2
RESETN_OUT
I/O
PH/PL/Off
I
Off
VDDBT
Interrupt output or GPIO.
RESETN output (VDDBT power supply) or
GPIO.
Audio Interface
47
I2S_ AD_OUT
I/O
PH
I
PH
VDDC33
I2S_AD_OUT or GPIO.
48
I2S_ AD_IN
I/O
PH
I
PH
VDDC33
I2S_AD_IN or SPDIF_AD_IN or GPIO.
49
WCLK
I/O
PH
I
PH
VDDC33
I2S WCLK or GPIO.
50
ACLK
I/O
PH
I
PH
VDDC33
I2S ACLK or GPIO.
I2C and UART Interface
UART_RX or RESETN_OUT33 or GIPO.
UART_RX: UART Rx input.
RESETN_OUT33:
When
set
to
RESETN_OUT33, this pin is similar to
RESETN_OUT
35
UART_RX
I/O
PL
I
PL
with
the
following
VDDC33
differences (1) the internal PL is turned on
for
this
pin
during
chip
reset
(RESETN=LOW) (2) this pin is powered by
VDDC33 while RESETN_OUT is powered
by VDDBT.
36
UART_TX
I/O
PH
I
PH
VDDC33
UART_TX or GPIO.
45
I2C_DATA
I/O, OD
-
I
-
VDDC33
I2C_DATA or GPIO.
46
I2C_CK
I/O, OD
-
I
-
VDDC33
I2C_CK or GPIO.
Data output to SPI Flash or GPIO.
SPI Flash Interface
39
NSPI_DO
I/O
PH
I
PH
VDDC33
40
NSPI_DI
I/O
PH
I
PH
VDDC33
Data input from SPI Flash or LED0 or
GPIO.
Clock output to SPI Flash or LED1 or
41
NSPI_CK
I/O
PH
I
PH
VDDC33
GPIO.
42
NSPI_CS
I/O
PH
I
PH
VDDC33
Chip select to SPI Flash or GPIO.
RESETN
I
-
I
-
VDDC33
Chip RESETN input. Active low.
Other
37
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GPIO2 or CLK_OUT33 (VCC33 power
supply).
When set
to CLK_OUT33, this pin is
similar to CLK_OUT, the only difference
38
GPIO2
I/O
PH
I
PH
VDDC33
is that this pin is powered by VDDC33
while CLK_OUT is powered by VDDBT.
Frequency is programmable to one of the
following: 6, 12, 18, 24, 27, 30, 54,
74.25MHz.
Analog Signals
27
XO
O
-
O
-
VDDA33
Crystal output.
28
XI
I
-
I
-
VDDA33
Crystal input.
29
RSET
I
-
I
-
VDDA33
Analog input, a 750Ohm resistor should be
connected between RSET and VDDA33.
31
Reserved
-
-
I
-
-
Reserved.
1.2V digital power supply.
Power and Ground
5, 25, 43
VDDC
Power
-
Power
-
-
14
VDDBT
Power
-
Power
-
-
Digital power supply for pixel interface. It
can be set to 1.8/2.7/3.3V.
26
VDDA
Power
-
Power
-
-
1.2V analog power supply.
30
VDDA33
Power
-
Power
-
-
3.3V analog power supply.
34
VDDR
Power
-
Power
-
-
1.2V digital power supply for serial
interface.
44
VDDC33
Power
-
Power
-
-
3.3V digital power supply.
51
GND
GND
-
GND
-
-
Ground pad.
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3. Functional Description
3.1. AVT Technologies
AVT (Advanced Video Transport) is a visual lossless compression and transmission technology, and it
employs a low delay intra-frame video compression, using Norelsys proprietary algorithm. The required
transmission bandwidth is only half of MJPEG algorithm in order to obtain the same image quality.
Furthermore, the AVT technology supports configurable compression ratio to obtain the best image quality.
NS2510/NS2520/NS2530 not only makes use of the AVT technology but also integrates an on-chip FEC
(forward error correction) module, using the Reed-solomon algorithm to correct the occurrence of
transmission errors. NS2510/NS2520/NS2530 also integrates a serializer and a cable driver, supports from
30Mbps to 2.97Gbps transmission rate. In uncompressed mode, NS2510 is compatible with SD-SDI
standard, NS2520 is compatible with SD/HD-SDI standard, while NS2530 is also compatible with 3G-SDI
standard.
NS2510/NS2520/NS2530 supports reverse audio and control data transmission, and integrates a reverse
direction signal receiving circuit, which makes it capable to transmit video, audio and control signals in
forward direction (downstream) while receiving reverse (upstream) audio and control signals transferred on
the same cable and at the same time. In addition I2C, UART TX/RX and audio input/output pins are also
provided to communicate with the external devices.
3.2. Pixel Interface
The parallel video interface (Pixel Interface) supports RGB (uncompressed mode) and YCbCr 4:2:2
(compressed mode or uncompressed mode) color space, and supports BT.656, BT.1120 and OmniVision
DVP input formats. The parallel video interface is 16-bit wide, which can receive 8/10/16 bits input video
data. The Pixel Interface is powered by VDDBT and the voltage can be 3.3V, 2.7V or 1.8V.
The Pixel Interface contains D2~D9, D12~D19, a total of 16 data pins, a vertical synchronous signal
VSYNC, a data enable signal DE, and a video clock signal PCLK. When the synchronization signal is
embedded in the video data (for example, BT.656/BT.1120), VSYNC and DE are not used. When the input
video employs an external synchronization mode (for example, DVP), the synchronization is based on
VSYNC and DE.
The video input data, D2~D9, D12~D19, VSYNC and DE, are sampled by PCLK in single data rate (SDR)
mode and the highest clock frequency of PCLK is 148.5MHz. The rising edge or falling edge of PCLK can
be selected to capture input data. In addition, the specific sampling position (relative to the PCLK rising
edge or falling edge) can also be finely tuned to provide maximum timing compatibility with the video
source chip (Sensor or ISP, etc.).
In the example timing diagram of this chapter, the rising edge of PCLK is used to sampling data.
3.2.1.
BT.656 YCbCr 4:2:2
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In BT.656 format, the synchronization signal is embedded in the video stream. SAV and EAV are used to
indicate the start and the end of active video in each line and occupy for 4 clock cycles. The space between
EAV and SAV is the horizontal blanking area. The timing diagram is shown in Figure 3.
HTOTAL
HACTIVE
HBLANK
PCLK
DATA
...
FF
00
00
..
...
XY
FF
00
00
...
XY
SAV
EAV
Figure 3. BT.656 Htotal Encoding
The timing diagram of active video area in each line is shown in Figure 4.
HACTIVE
PCLK
DATA
...
Cb0
Y0
Cr0
pixel#0
Y1
pixel#1
Cb2
Y2
Cr2
pixel#2
Y3
pixel#3
Cb4
Cr
(N-1) YN
...
Pixel#(N-1)
pixel#N
Figure 4. BT.656 Hactive Encoding YCbCr 4:2:2
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In addition, NS2510/NS2520/NS2530 includes versatile pin-mapping features which provide maximum
flexibility for users, as shown in Table 4 and Table 5.
Table 4. Pin Mapping for 8-bit BT.656, 8-bit BT.1120 and 8-bit DVP
8bit Bus-swap[1]
8bit Default
Pin
Name
Pixel#0
Pixel#1
Pixel#0
8bit Bit-swap
Pixel#1
Pixel#0
Pixel#1
Edge1
Edge2
Edge1
Edge2
Edge1
Edge2
Edge1
Edge2
Edge1
Edge2
Edge1
Edge2
D12
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
Y0[0]
Cb0[0]
Y1[0]
Cr0[0]
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
D13
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
Y0[1]
Cb0[1]
Y1[1]
Cr0[1]
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
D14
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
Y0[2]
Cb0[2]
Y1[2]
Cr0[2]
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
D15
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
Y0[3]
Cb0[3]
Y1[3]
Cr0[3]
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
D16
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
Y0[4]
Cb0[4]
Y1[4]
Cr0[4]
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
D17
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
Y0[5]
Cb0[5]
Y1[5]
Cr0[5]
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
D18
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
Y0[6]
Cb0[6]
Y1[6]
Cr0[6]
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
D19
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
Y0[7]
Cb0[7]
Y1[7]
Cr0[7]
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
Notes:
1、 With 8-bit width, bus-swap is only supported in compressed mode and is only supported in BT.656 and DVP formats.
2、 Bus-swap and bit-swap can be chosen at the same time.
Table 5. Pin Mapping for 10-bit BT.656, 10-bit BT.1120 and 10-bit DVP
10bit Bus-swap[1]
10bit Default
Pin
Name
Pixel#0
Pixel#1
Pixel#0
10bit Bit-swap
Pixel#1
Pixel#0
Pixel#1
Edge1
Edge2
Edge1
Edge2
Edge1
Edge2
Edge1
Edge2
Edge1
Edge2
Edge1
Edge2
D8
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
Y0[0]
Cb0[0]
Y1[0]
Cr0[0]
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
D9
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
Y0[1]
Cb0[1]
Y1[1]
Cr0[1]
Cb0[8]
Y0[8]
Cr0[8]
Y1[8]
D12
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
Y0[2]
Cb0[2]
Y1[2]
Cr0[2]
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
D13
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
Y0[3]
Cb0[3]
Y1[3]
Cr0[3]
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
D14
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
Y0[4]
Cb0[4]
Y1[4]
Cr0[4]
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
D15
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
Y0[5]
Cb0[5]
Y1[5]
Cr0[5]
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
D16
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
Y0[6]
Cb0[6]
Y1[6]
Cr0[6]
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
D17
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
Y0[7]
Cb0[7]
Y1[7]
Cr0[7]
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
D18
Cb0[8]
Y0[8]
Cr0[8]
Y1[8]
Y0[8]
Cb0[8]
Y1[8]
Cr0[8]
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
D19
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
Y0[9]
Cb0[9]
Y1[9]
Cr0[9]
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
Notes:
1、 With 10-bit width, bus-swap is only supported in compressed mode and is only supported in BT.656 and DVP formats.
2、 Bus-swap and bit-swap can be chosen at the same time.
3.2.2.
BT.1120 YCbCr 4:2:2
BT.1120 format is similar to BT.656 format, except that SAV and EAV in each line occupy for 8 clock
cycles. The timing diagram of 8/10-bit BT.1120 is shown in Figure 5.
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HTOTAL
HBLANK
PCLK
DATA
HACTIVE
..
FF
FF
00
00
00
00
XY
...
..
XY
FF
FF
00
00
00
EAV
00
XY
...
XY
SAV
Figure 5. 8/10-bit BT.1120 Htotal Encoding
For BT.1120 format, NS2510/NS2520/NS2530 also supports various pin-mapping modes, as shown in
above Table 4 and Table 5, except that 8/10-bit BT.1120 format does not support bus-swap function.
The timing diagram of 16-bit BT.1120 is shown in Figure 6.
HTOTAL
HBLANK
PCLK
HACTIVE
...
D[19:12] FF
00
00
XY
D[9:2]
00
00
XY
FF
...
...
FF
00
00
XY
FF
00
00
XY
...
SAV
EAV
Figure 6. 16-bit BT.1120 Htotal Encoding
The timing diagram of active video area in each line is shown in Figure 7.
HACTIVE
PCLK
...
D[19:12]
Y0
Y1
Y2
Y3
Y4
Y5
...
D[9:2]
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
...
YN-1
YN
Cb
Cr
(N-1) (N-1)
Figure 7. 16-bit BT.1120 Hactive Encoding YCbCr 4:2:2
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The pin-mapping modes supported by 16-bit BT.1120 format in shown in Table 6.
Table 6. Pin Mapping for 16-bit BT.1120
16bit Default
Pin
Name
16bit Bus-swap
16bit Bit-swap
Pixel#0
Pixel#1
Pixel#0
Pixel#1
Pixel#0
Pixel#1
D2
Cb0[0]
Cr0[0]
Y0[0]
Y1[0]
Cb0[7]
Cr0[7]
D3
Cb0[1]
Cr0[1]
Y0[1]
Y1[1]
Cb0[6]
Cr0[6]
D4
Cb0[2]
Cr0[2]
Y0[2]
Y1[2]
Cb0[5]
Cr0[5]
D5
Cb0[3]
Cr0[3]
Y0[3]
Y1[3]
Cb0[4]
Cr0[4]
D6
Cb0[4]
Cr0[4]
Y0[4]
Y1[4]
Cb0[3]
Cr0[3]
D7
Cb0[5]
Cr0[5]
Y0[5]
Y1[5]
Cb0[2]
Cr0[2]
D8
Cb0[6]
Cr0[6]
Y0[6]
Y1[6]
Cb0[1]
Cr0[1]
D9
Cb0[7]
Cr0[7]
Y0[7]
Y1[7]
Cb0[0]
Cr0[0]
D12
Y0[0]
Y1[0]
Cb0[0]
Cr0[0]
Y0[7]
Y1[7]
D13
Y0[1]
Y1[1]
Cb0[1]
Cr0[1]
Y0[6]
Y1[6]
D14
Y0[2]
Y1[2]
Cb0[2]
Cr0[2]
Y0[5]
Y1[5]
D15
Y0[3]
Y1[3]
Cb0[3]
Cr0[3]
Y0[4]
Y1[4]
D16
Y0[4]
Y1[4]
Cb0[4]
Cr0[4]
Y0[3]
Y1[3]
D17
Y0[5]
Y1[5]
Cb0[5]
Cr0[5]
Y0[2]
Y1[2]
D18
Y0[6]
Y1[6]
Cb0[6]
Cr0[6]
Y0[1]
Y1[1]
D19
Y0[7]
Y1[7]
Cb0[7]
Cr0[7]
Y0[0]
Y1[0]
Notes:
1、 Bus-swap and bit-swap can be chosen at the same time.
3.2.3.
DVP YCbCr 4:2:2
For DVP format, a new frame is indicated by a long period of high level for VSYNC, and the active video is
indicated by the high level for DE. The polarity of VSYNC and DE can also be changed with register
control . The timing diagram of DVP format is shown in Figure 8.
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Frame
VSYNC
...
HTOTAL
DE
...
HACTIVE
VIDEO
DATA
...
Invalid
Figure 8. DVP Frame Definition
The timing diagram of active video area (HACTIVE) in each line for DVP format is shown in Figure 4.
For DVP format, various pin-mapping modes are also available，specifically reference to the above Table 4
and Table 5.
3.2.4.
Supported Video Formats YCbCr 4:2:2
Table 7 lists the common video formats and the corresponding parameters supported by the YCbCr 4:2:2
color space. The main configurable parameters include the clock frequency of PCLK, compression ratio,
Htotal, Vtotal, Hactive, Vactive and so on. NS2510/NS2520/NS2530 also supports more video formats that
are not listed in the table.
In uncompressed mode, NS2510 is compatible with SD-SDI standard, NS2520 is compatible with
SD/HD-SDI standard, while NS2530 is also compatible with 3G-SDI standard.
NS2510/NS2520/NS2530 supports more video formats in compressed mode but does not support interlaced
video format.
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Table 7. Supported Video Formats YCbCr 4:2:2
PCLK(MHz)
Type
Frame
Htotal
Vtotal
Hactive
Vactive
Rate
(pixel）
(pixel)
(pixel)
(pixel)
Format
NS2510
8/10
NS2520
NS2530
16 bits
bits
compressed
uncompressed
compressed
uncompressed
compressed
uncompressed
59.94
858
525
720
480
27
-
●
●
●
59.94
858
525
720
487
27
-
●
●
●
59.94
858
525
720
507
27
-
●
●
●
625i
50
864
625
720
576
27
-
●
●
●
-
720p25RHB
25
1980
750
1280
720
74.25
37.125
●
●
●
●
●
●
-
720p30RHB
30
1650
750
1280
720
74.25
37.125
●
●
●
●
●
●
720p24
24
4125
750
1280
720
148.5
74.25
●
●
●
●
●
720p25
25
3960
750
1280
720
148.5
74.25
●
●
●
●
●
720p30
30
3300
750
1280
720
148.5
74.25
●
●
●
●
●
720p50
50
1980
750
1280
720
148.5
74.25
●
●
●
●
720p60
60
1650
750
1280
720
148.5
74.25
●
●
●
●
-
1920x1080p12
12
2750
1125
1920
1080
74.25
37.125
●
●
●
●
●
●
-
1920x1080p12.5
12.5
2640
1125
1920
1080
74.25
37.125
●
●
●
●
●
●
-
1920x1080p15
15
2200
1125
1920
1080
74.25
37.125
●
●
●
●
●
●
1080p24
24
2750
1125
1920
1080
148.5
74.25
●
●
●
●
1080p25
25
2640
1125
1920
1080
148.5
74.25
●
●
●
●
1080p30
30
2200
1125
1920
1080
148.5
74.25
●
●
●
●
1080i50
50i
2640
1125
1920
1080
148.5
74.25
●
●
1080i60
60i
2200
1125
1920
1080
148.5
74.25
●
●
1080p50
50
2640
1125
1920
1080
-
148.5
●
●
1080p60
60
2200
1125
1920
1080
-
148.5
●
●
-
1280x960p12.5
12.5
2160
1000
1280
960
54
27
●
●
●
-
1280x960p15
15
1800
1000
1280
960
54
27
●
●
●
-
1280x1024p15
15
1688
1066
1280
1024
54
27
●
●
●
-
1280x960p25
25
2160
1000
1280
960
108
54
●
●
-
1280x960p30
30
1800
1000
1280
960
108
54
●
●
-
1280x1024p30
30
1688
1066
1280
1024
108
54
●
●
1280x960p50
50
2160
1000
1280
960
-
108
●
1280x960p60
60
1800
1000
1280
960
-
108
●
1280x1024p60
60
1688
1066
1280
1024
-
108
●
525i
SD-SDI [1]
HD-SDI
HD-SDI
3G-SDI
VESA
VESA
Note: [1] Pixel Interface should be set to 8/10 bits BT.656 for SD formats.
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3.3. Audio Embedding and Control
NS2510/NS2520/NS2530 support audio embedding and control packets transmission in horizontal and
vertical blanking region of digital video through AVT serial link. The embedded audio and control packets
are compatible with SMPTE 272, SMPTE 299 and SMPTE 291 standard.
In non-compression case, there are four operation modes in which audio and control packets can be
manipulated described as below.
3.3.1.
Pass-through Mode
In pass-through mode, audio and control packets in the video stream will remain unchanged. Altering or
inserting new audio and control packets is not permitted.
3.3.2.
Appending Mode
In appending mode, the original embedded audio and control packets in the video stream will not be altered,
furthermore, new embedded audio and control packets can be superimposed on this basis. Except for that if
the audio packets already exists in the video stream, the embedded audio packets cannot be superimposed.
3.3.3.
Replacing Mode
In replacing mode, the original embedded audio and control packets in the video stream will be deleted, and
the audio data from the audio interface is packaged which conforms to the SMPTE 272 or SMPTE 299
standard. The control information that needs to be sent is also packaged which conforms to the SMPTE 291
standard. Then the audio and control packets will be embedded in the video stream.
3.3.4.
Eliminating Mode
The eliminating mode is similar to the replacing mode, except that no packets will be inserted after the
original embedded audio and control packets in the video stream are removed.
In compression case, the embedded audio and control packet operations are in the same way as in
non-compression case. However, because the bandwidth of the blanking region in the AVT serial link is
much smaller than that of the parallel video interface, the user should pay attention to the bandwidth
consumed by the embedded audio and control packets is not exceeding the limitation of the AVT serial link.
3.4. Audio Interface
NS2510/NS2520/NS2530 supports I2C and SPDIF interfaces. The I2C interface supports audio input and
output and can be configured as master or slave mode. The SPDIF interface only supports audio input and
shares the data pin with I2C interface.
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Table 8. Audio interface signals
Signal Name
Description
I2S_AD_OUT
I2S data output.
I2S_AD_IN
I2S data input or SPDIF data input.
WCLK
ACLK
Left/Right channel clock. This signal is input in I2S slave mode or output in I2S
master mode.
Bit clock. This signal is input in I2S slave mode or output in I2S master mode.
I2S_AD_IN is the audio input pin of forward transmission channel, which can be configured as I2C or
SPDIF input, and supports two channel audio, 8/16/24/32/44.1/48/96KHz sampling rate, 16/20/24 bits
sampling accuracy, left-justified/right-justified data format and configurable WCLK polarity.
I2S_AD_OUT is the audio output pin of reverse transmission channel, which supports only mono audio up
to 8KHz sampling rate, 16bits sampling accuracy, left-justified/right-justified data format and configurable
WCLK polarity.
Four typical audio configuration modes are shown in Figure 9.
Mode1: audio input/output configured as I2S interface, master mode.
Mode2: audio input/output configured as I2S interface, slave mode.
Mode3: audio input configured as SPDIF interface, and audio output configured as I2S interface,
master mode.
Mode4: audio input configured as SPDIF interface, and audio output configured as I2S interface, slave
mode.
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I2S_AD_IN
ADC
NS2510
/NS2520
/NS2530
WCLK
ACLK
I2S_AD_OUT
NS2510
/NS2520
/NS2530
DAC
ADC
&
DAC
WCLK
ACLK
I2S_AD_OUT
Mode-2
Mode-1
I2S_AD_IN(SPDIF)
NS2510
/NS2520
/NS2530
I2S_AD_IN
I2S_AD_IN(SPDIF)
ADC
NS2510
/NS2520
/NS2530
WCLK
ACLK
I2S_AD_OUT
DAC
WCLK
ACLK
I2S_AD_OUT
ADC
DAC
Mode-4
Mode-3
Figure 9. Audio Interface Topologies
3.5. I2C and UART Interface
NS2510/NS2520/NS2530 supports a standard I2C interface which is in slave mode after power on. The
firmware can then configure it as master or slave mode. NS2510/NS2520/NS2530 also supports a standard
UART TX and UART RX interface.
NS2510/NS2520/NS2530 supports the transmission of bidirectional control signals. The I2C and UART RX
interface can be used as the initiator of the forward control flow, transmitting commands through the AVT
serial link to the receiving end of the video stream, to configure the I2C/UART/GPIO/Register or other
functions of the receiving end. The I2C interface and UART TX can also be used as the executer of the
reverse control flow to receive and execute commands from the receiving end of the video stream.
3.6. SPI Flash Interface
NS2510/NS2520/NS2530 contains an SPI Flash Interface to connect external SPI Flash devices in which the
firmware code can be stored. NS2510/NS2520/NS2530 also supports the sharing of external SPI Flash with
other chips (such as Sensor or ISP chips) to reduce system costs and reduce PCB area.
3.7. Boot, Firmware Loading and Update
After power on and reset operation, the bootloader inside NS2510/NS2520/NS2530 will first attempt to load
firmware code from the external SPI Flash. If the external SPI Flash does not exist, or if there is no valid
firmware, then bootloader will wait to receive firmware from I2C interface. After the effective firmware is
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loaded to the on-chip SRAM, bootloader will switch control to firmware, and complete firmware loading
process.
NS2510/NS2520/NS2530 supports accessing external SPI Flash and updating firmware through I2C
interface. This function can be used to realize initial burning of firmware to external SPI Flash.
NS2510/NS2520/NS2530 also supports accessing external SPI Flash and updating firmware through the
reverse transmission channel. This function can be used to realize remote firmware update.
3.8. Reset and Clock Output
NS2510/NS2520/NS2530 provides reset and clock output signals in order to improve the system integration.
RESETN_OUT and CLK_OUT are powered by VDDBT, the voltage can be 3.3V, 2.7V or 1.8V. These two
pins also can be configured as GPIOs when not used as reset and clock output signals.
When used as reset output signal, the RESETN_OUT pin requires an external pull-down resistor which
provides an active low reset signal to other chips such as Sensor or ISP. After the firmware runs, the
RESETN_OUT can be driven high at the appropriate time to remove Sensor or ISP resets.
When used as clock output signal, the CLK_OUT can be configured to output one of the following
frequencies: 6/12/18/24/27/30/54/74.25MHz.
NS2510/NS2520/NS2530 also provides another set of reset and clock output signals RESETN_OUT33 and
CLK_OUT33 which are powered by VDDC33, fixed at 3.3V voltage.
RESETN_OUT33 can be used as UART_RX or GPIO function. The RESETN_OUT33 pin has a built-in
pull-down resistor, so there is no need to add an external resistor. CLK_OUT33 also can be used as GPIO
function. When configured as clock output, its function is the same as CLK_OUT.
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4. Electrical Characteristics
4.1. Absolute Maximum Ratings
Table 9. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
VDDC/VDDA/VDDR
1.2V supply voltage
-0.3 to 1.5
V
VDDA33/VDDC33
3.3V supply voltage
-0.3 to 4.0
V
VDDBT
Pixel interface supply voltage 1.8V/2.7V/3.3V
-0.3 to 4.0
V
TSTORAGE
Storage temperature
-65 to 150
℃
TJ
Junction temperature
-40 to 125
℃
4.2. Recommended Operating Conditions
Table 10. Recommended Operating Conditions
Symbol
Parameter
Min
Type
Max
Unit
VDDC/VDDA/VDDR
1.2V supply voltage
1.14
1.2
1.32
V
VDDA33/VDDC33
3.3V supply voltage
3.0
3.3
3.6
V
1.8V supply voltage
1.7
1.8
1.9
2.7V supply voltage
2.5
2.7
2.9
3.3V supply voltage
3.0
3.3
3.6
V
-40
-
105
℃
Min
Type
Max
Unit
-
27
-
MHz
-300
-
300
ppm
PCLK frequency
-
-
148.5
MHz
PCLK duty cycle
40
-
60
%
VDDBT
TA
Operating free-air temperature range
4.3. Clock Requirements
Table 11. Clock Requirements
Parameter
Crystal frequency
Crystal frequency tolerance
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4.4. DC Characteristics for Digital IO
Table 12. DC Characteristics for Digital IO
Symbol
Parameter
Min
Type
Max
Unit
VIH18
Input high level for 1.8V digital IO
1.1
-
-
V
VIL18
Input low level for 1.8V digital IO
-
-
0.4
V
VOH18
Output high level for 1.8V digital IO
1.3
-
-
V
VOL18
Output low level for 1.8V digital IO
-
-
0.2
V
VIH27
Input high level for 2.7V digital IO
1.6
-
-
V
VIL27
Input low level for 2.7V digital IO
-
-
0.6
V
VOH27
Output high level for 2.7V digital IO
2.0
-
-
V
VOL27
Output low level for 2.7V digital IO
-
-
0.3
V
VIH33
Input high level for 3.3V digital IO
2.0
-
-
V
VIL33
Input low level for 3.3V digital IO
-
-
0.8
V
VOH33
Output high level for 3.3V digital IO
2.4
-
-
V
VOL33
Output low level for 3.3V digital IO
-
-
0.4
V
4.5. Power Up and Reset Timing
The Power Up and Reset Timing rules are defined in this section. Designers should follow all the rules for
external power designs. Detailed explanations are listed below:
1.8/2.7/3.3V
VDDBT
VDDA33
VDDC33
80%
T1
1.2V
VDDC
VDDA
VDDR
T2
3.3V
2.0V
RESET#
T3
Figure 10. Power Up and Reset Timing
T1: Rise time for VDDBT/VDDA33/VDDC33 power rail form 0V to 80% of target voltages
T2: Rise time for VDDC/VDDA/VDDR power rail form 0V to 1.2V
T3: Rise time for RESET# signal from 0V to 2.0V
The recommended power sequence and timing requirements are listed in Table 13.
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Table 13. Power Up and Reset Timing Requirement
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Time
Min
Max
T1
0.01ms
1ms
T2
0.01ms
1ms
T3
15ms
-
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5. Package Information
5.1. 50 pin QFN (7x5.5) package
Figure 11. 50pin QFN Package Mechanical Data
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