SIT8008BI-11-YYS-24.000000

SiT8008B Low Power Programmable Oscillator Features ow Power, Standard Frequency Oscillator ◼ ◼ ◼ ◼ ◼ ◼ ◼ ◼ ◼ ◼ ◼ ◼ ◼ Applications Any frequency between 1 MHz and 110 MHz accurate to 6 decimal places 100% pin-to-pin drop-in replacement to quartz-based XO Excellent total frequency stability as low as ±20 ppm Operating temperature from -40°C to 85°C. For 125°C and/or -55°C options, refer to SiT1618, SiT8918, SiT8920 Low power consumption of 3.5 mA typical at 1.8 V Qualify just one device with 1.62 V to 3.63 V continuous supply voltage option Standby mode for longer battery life Fast startup time of 5 ms LVCMOS/HCMOS compatible output Industry-standard packages: 2.0 x 1.6, 2.5 x 2.0, 3.2 x 2.5, 5.0 x 3.2, 7.0 x 5.0 mm x mm Instant samples with Time Machine II and Field Programmable Oscillators RoHS and REACH compliant, Pb-free, Halogen-free and Antimony-free For AEC-Q100 oscillators, refer to SiT8924 and SiT8925 ◼ ◼ Ideal for DSC, DVC, DVR, IP CAM, Tablets, e-Books, SSD, GPON, EPON, etc Ideal for high-speed serial protocols such as: USB, SATA, SAS, Firewire, 100M / 1G / 10G Ethernet, etc. Related products for automotive applications. For aerospace and defense applications SiTime recommends using only Endura™ SiT8944. Electrical Characteristics All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise stated. Typical values are at 25°C and nominal supply voltage. Table 1. Electrical Characteristics Parameters Symbol Min. Typ. Max. Unit Condition Frequency Range Output Frequency Range f 1 – 110 MHz Frequency Stability and Aging Frequency Stability F_stab -20 – +20 ppm -25 – +25 ppm -50 – +50 ppm Inclusive of initial tolerance at 25°C, 1st year aging at 25°C, and variations over operating temperature, rated power supply voltage and load. Operating Temperature Range Operating Temperature Range T_use -20 – +70 °C Extended Commercial -40 – +85 °C Industrial Supply Voltage and Current Consumption Supply Voltage Options Current Consumption Vdd_1.8 1.62 1.8 1.98 V Vdd_2.5 2.25 2.5 2.75 V Vdd_2.8 2.52 2.8 3.08 V Vdd_3.0 2.7 3.0 3.3 V Vdd_3.3 2.97 3.3 3.63 V Vdd_XX 2.25 – 3.63 V Vdd_YY 1.62 – 3.63 V Idd – 3.8 4.5 mA No load condition, f = 20 MHz, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX, Vdd_YY – 3.7 4.2 mA No load condition, f = 20 MHz, Vdd_2.5 – 3.5 4.1 mA No load condition, f = 20 MHz, Vdd_1.8 – – 4.2 mA Vdd_2.5, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX, Vdd_YY. OE = GND, Output in high-Z state – – 4.0 mA Vdd_1.8. OE = GND, Output in high-Z state – 2.1 4.3 A ST = GND, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX, Vdd_YY. Output is weakly pulled down – 1.1 2.5 A ST = GND, Vdd_2.5, Output is weakly pulled down – 0.2 1.3 A ST = GND, Vdd_1.8, Output is weakly pulled down OE Disable Current I_OD Standby Current I_std 1.08 1 January 2023 Contact SiTime for 1.5 V support www.sitime.com SiT8008B Low Power Programmable Oscillator Table 1. Electrical Characteristics (continued) Parameters Symbol Min. Typ. Max. Unit Condition LVCMOS Output Characteristics DC 45 – 55 % All Vdds. See Duty Cycle definition in Figure 3 and Footnote 6 Tr, Tf – 1 2 ns 20% - 80% Vdd_2.5, Vdd_2.8, Vdd_3.0, Vdd_3.3 – 1.3 2.5 ns 20% - 80% Vdd_1.8 – – 2 ns 20% - 80% Vdd_XX – – 2.7 ns 20% - 80% Vdd_YY Duty Cycle Rise/Fall Time Output High Voltage VOH 90% – – Vdd Output Low Voltage VOL – – 10% Vdd Input High Voltage VIH 70% – – Vdd Pin 1, OE or ST Input Low Voltage VIL – – 30% Vdd Pin 1, OE or ST Input Pull-up Impedance Z_in 50 87 150 k Pin 1, OE logic high or logic low, or ST logic high 2 – – M Pin 1, ST logic low IOH = -4 mA (Vdd_3.0 and Vdd_3.3) IOH = -3 mA (Vdd_2.8 and Vdd_ 2.5) IOH = -2 mA (Vdd _1.8) IOL = 4 mA (Vdd_3.0 and Vdd_3.3) IOL = 3 mA (Vdd_2.8 and Vdd_2.5) IOL = 2 mA (Vdd_1.8) Input Characteristics Startup and Resume Timing Startup Time T_start – – 5 ms Measured from the time Vdd reaches its rated minimum value T_oe – – 130 ns f = 110 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles T_resume – – 5 ms Measured from the time ST pin crosses 50% threshold Enable/Disable Time Resume Time Jitter RMS Period Jitter T_jitt Peak-to-peak Period Jitter T_pk RMS Phase Jitter (random) T_phj – 1.8 3 ps – – 3.3 ps f = 75 MHz, Vdd_1.8, Vdd_2.5, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX, f = 75 MHz, Vdd_YY – 12 25 ps f = 75 MHz, Vdd_2.5, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX, Vdd_YY – 14 30 ps f = 75 MHz, Vdd_1.8 – 0.5 0.9 ps – 1.3 2 ps – – 1.4 ps f = 75 MHz, Integration bandwidth = 900 kHz to 7.5 MHz. Vdd_1.8, Vdd_2.5, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX f = 75 MHz, Integration bandwidth = 12 kHz to 20 MHz. Vdd_1.8, Vdd_2.5, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX f = 75 MHz, Integration bandwidth = 900 kHz to 7.5 MHz. Vdd_YY – – 2.3 ps f = 75 MHz, Integration bandwidth = 12 kHz to 20 MHz. Vdd_YY Table 2. Pin Description Pin 1 Symbol OE/ST, ̅ ̅ ̅ /NC Top View Functionality Output Enable H[1]: specified frequency output L: output is high impedance. Only output driver is disabled. Standby H[1]: specified frequency output L: output is low (weak pull down). Device goes to sleep mode. Supply current reduces to I_std. No Connect OE/ST, ̅ ̅ ̅ /NC Any voltage between 0 and Vdd or Open[1]: Specified frequency output. Pin 1 has no function. 2 GND Power Electrical ground 3 OUT Output Oscillator output 4 VDD Power Power supply voltage[2] Figure 1. Pin Assignments Notes: 1. In OE or ST, ̅ ̅ ̅ mode, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use the NC option. 2. A capacitor of value 0.1 µF or higher between Vdd and GND is required. 1.08 Page 2 of 18 www.sitime.com SiT8008B Low Power Programmable Oscillator Table 3. Absolute Maximum Limits Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings. Min. Max. Unit Storage Temperature Parameter -65 150 °C Vdd -0.5 4 V Electrostatic Discharge – 2000 V Soldering Temperature (follow standard Pb free soldering guidelines) Junction Temperature[3] – 260 °C – 150 °C Note: 3. Exceeding this temperature for extended period of time may damage the device. Table 4. Thermal Consideration[4] JA, 4 Layer Board JA, 2 Layer Board JC, Bottom 5032 97 199 24 3225 109 212 27 2520 117 222 26 2016 152 252 36 Package (°C/W) 142 7050 (°C/W) 273 (°C/W) 30 Note: 4. Refer to JESD51 for JA and JC definitions, and reference layout used to determine the JA and JC values in the above table. Table 5. Maximum Operating Junction Temperature[5] Max Operating Temperature (ambient) Maximum Operating Junction Temperature 70°C 80°C 85°C 95°C Note: 5. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature. Table 6. Environmental Compliance Parameter Condition/Test Method Mechanical Shock MIL-STD-883F, Method 2002 Mechanical Vibration MIL-STD-883F, Method 2007 Temperature Cycle JESD22, Method A104 Solderability MIL-STD-883F, Method 2003 Moisture Sensitivity Level MSL1 @ 260°C 1.08 Page 3 of 18 www.sitime.com SiT8008B Low Power Programmable Oscillator Test Circuit and Waveform[6] Vdd Vout Test Point tr 4 Power Supply 3 80% Vdd 15pF (including probe and fixture capacitance) 0.1 uF 2 1 tf 50% 20% Vdd High Pulse (TH) Vdd OE/ST Function Low Pulse (TL) Period 1 kΩ Figure 2. Waveform Figure 1. Test Circuit Note: 6. Duty Cycle is computed as Duty Cycle = TH/Period. Timing Diagrams 90% Vdd Vdd Vdd 50% Vdd Pin 4 Voltage T_start [7] No Glitch during start up T_resume ST Voltage CLK Output CLK Output HZ HZ T_start: Time to start from power-off T_resume: Time to resume from ST Figure 3. Startup Timing (OE/ST, ̅ ̅ ̅ Mode) Figure 4. Standby Resume Timing (ST, ̅ ̅ ̅ Mode Only) Vdd Vdd 50% Vdd OE Voltage OE Voltage T_oe 50% Vdd T_oe CLK Output CLK Output HZ HZ T_oe: Time to re-enable the clock output T_oe: Time to put the output in High Z mode Figure 5. OE Enable Timing (OE Mode Only) Figure 6. OE Disable Timing (OE Mode Only) Note: 7. SiT8008 has “no runt” pulses and “no glitch” output during startup or resume. 1.08 Page 4 of 18 www.sitime.com SiT8008B Low Power Programmable Oscillator Performance Plots[8] 1.8 2.5 2.8 3.0 3.3 6.0 DUT2 DUT3 DUT4 DUT5 DUT6 DUT7 DUT8 DUT9 DUT10 20 15 Frequency (ppm) 5.5 5.0 Idd (mA) DUT1 4.5 4.0 3.5 10 5 0 -5 -10 -15 -20 3.0 0 10 20 30 40 50 60 70 80 90 100 -40 110 -30 -20 -10 Figure 7. Idd vs Frequency 2.5 V 2.8 V 3.0 V 10 20 30 40 50 60 70 80 Temperature (°C) Frequency (MHz) 1.8 V 0 Figure 8. Frequency vs Temperature 3.3 V 1.8 V 2.5 V 2.8 V 3.0 V 3.3 V 55 RMS period jitter (ps) 54 53 ty cyc ( 52 51 50 49 48 47 46 45 0 Frequency (MHz) 20 30 40 50 60 70 80 90 100 110 Frequency (MHz) Figure 9. RMS Period Jitter vs Frequency Figure 10. Duty Cycle vs Frequency Temperature (°C) Temperature (°C) Figure 11. 20%-80% Rise Time vs Temperature 1.08 10 Page 5 of 18 Figure 12. 20%-80% Fall Time vs Temperature www.sitime.com SiT8008B Low Power Programmable Oscillator Performance Plots[8] 1.8 V 2.5 V 2.8 V 3.0 V 3.3 V 0.9 0.8 IPJ (ps) 0.7 0.6 0.5 0.4 10 30 50 70 90 10 110 30 50 70 90 110 Frequency (MHz) Frequency (MHz) Figure 14. RMS Integrated Phase Jitter Random (900 kHz to 20 MHz) vs Frequency[9] Figure 13. RMS Integrated Phase Jitter Random (12 kHz to 20 MHz) vs Frequency[9] Notes: 8. All plots are measured with 15 pF load at room temperature, unless otherwise stated. 9. Phase noise plots are measured with Agilent E5052B signal source analyzer. Integration range is up to 5 MHz for carrier frequencies below 40 MHz. 1.08 Page 6 of 18 www.sitime.com SiT8008B Low Power Programmable Oscillator Programmable Drive Strength The SiT8008 includes a programmable drive strength feature to provide a simple, flexible tool to optimize the clock rise/fall time for specific applications. Benefits from the programmable drive strength feature are: ◼ Improves system radiated electromagnetic interference (EMI) by slowing down the clock rise/fall time. ◼ Improves the downstream clock receiver’s (RX) jitter by decreasing (speeding up) the clock rise/fall time. ◼ Ability to drive large capacitive loads while maintaining full swing with sharp edge rates. For more detailed information about rise/fall time control and drive strength selection, see the SiTime Application Notes section. EMI Reduction by Slowing Rise/Fall Time Figure 15 shows the harmonic power reduction as the rise/fall times are increased (slowed down). The rise/fall times are expressed as a ratio of the clock period. For the ratio of 0.05, the signal is very close to a square wave. For the ratio of 0.45, the rise/fall times are very close to neartriangular waveform. These results, for example, show that the 11th clock harmonic can be reduced by 35 dB if the rise/fall edge is increased from 5% of the period to 45% of the period. trise=0.05 trise=0.1 trise=0.15 trise=0.2 trise=0.25 trise=0.3 trise=0.35 trise=0.4 trise=0.45 10 Harmonic amplitude (dB) 0 -10 -20 The SiT8008 can support up to 60 pF or higher in maximum capacitive loads with drive strength settings. Refer to the Rise/Fall Time Tables (Table 7 to 11) to determine the proper drive strength for the desired combination of output load vs. rise/fall time. SiT8008 Drive Strength Selection Tables 7 through 11 define the rise/fall time for a given capacitive load and supply voltage. 1. Select the table that matches the SiT8008 nominal supply voltage (1.8 V, 2.5 V, 2.8 V, 3.0 V, 3.3 V) 2. Select the capacitive load column that matches the application requirement (5 pF to 60 pF) 3. Under the capacitive load column, select the desired rise/fall times. 4. The left-most column represents the part number code for the corresponding drive strength. 5. Add the drive strength code to the part number for ordering purposes. Calculating Maximum Frequency Any given rise/fall time in Table 7 through 11 dictates the maximum frequency under which the oscillator can operate with guaranteed full output swing over the entire operating temperature range. This max frequency can be calculated as the following: Max Frequency = 1 5 x Trf_20/80 -30 where Trf_20/80 is the typical value for 20%-80% rise/fall time. -40 -50 Example 1 -60 Calculate fMAX for the following condition: -70 -80 1 3 5 7 9 11 Harmonic number ◼ ◼ Figure 15. Harmonic EMI reduction as a Function of Slower Rise/Fall Time ◼ ◼ Jitter Reduction with Faster Rise/Fall Time Power supply noise can be a source of jitter for the downstream chipset. One way to reduce this jitter is to speed up the rise/fall time of the input clock. Some chipsets may also require faster rise/fall time in order to reduce their sensitivity to this type of jitter. Refer to the Rise/Fall Time Tables (Table 7 to Table 11) to determine the proper drive strength. Vdd = 1.8 V (Table 7) Capacitive Load: 30 pF Desired Tr/f time = 3 ns (rise/fall time part number code = E) fMAX = 66.666660 Part number for the above example: SiT8008BIE12-18E-66.666660 Drive strength code is inserted here. Default setting is “-”. High Output Load Capability The rise/fall time of the input clock varies as a function of the actual capacitive load the clock drives. At any given drive strength, the rise/fall time becomes slower as the output load increases. As an example, for a 3.3 V SiT8008 device with default drive strength setting, the typical rise/fall time is 1 ns for 15 pF output load. The typical rise/fall time slows down to 2.6 ns when the output load increases to 45 pF. One can choose to speed up the rise/fall time to 1.83 ns by then increasing the drive strength setting on the SiT8008. 1.08 Page 7 of 18 www.sitime.com SiT8008B Low Power Programmable Oscillator Rise/Fall Time (20% to 80%) vs CLOAD Tables Table 7. Vdd = 1.8 V (Vdd_1.8) Rise/Fall Times for Specific CLOAD Table 8. Vdd = 2.5 V (Vdd_2.5) Rise/Fall Times for Specific CLOAD Rise/Fall Time Typ (ns) Rise/Fall Time Typ (ns) Drive Strength \ CLOAD 5 pF 15 pF 30 pF 45 pF 60 pF Drive Strength \ CLOAD 5 pF 15 pF 30 pF 45 pF 60 pF L A R B T E U F or "‐": default 6.16 3.19 2.11 1.65 0.93 0.78 0.70 0.65 11.61 6.35 4.31 3.23 1.91 1.66 1.48 1.30 22.00 11.00 7.65 5.79 3.32 2.94 2.64 2.40 31.27 16.01 10.77 8.18 4.66 4.09 3.68 3.35 39.91 21.52 14.47 11.08 6.48 5.74 5.09 4.56 L A R B T E or "‐": default U F 4.13 2.11 1.45 1.09 0.62 8.25 4.27 2.81 2.20 1.28 12.82 7.64 5.16 3.88 2.27 21.45 11.20 7.65 5.86 3.51 27.79 14.49 9.88 7.57 4.45 0.54 0.43 0.34 1.00 0.96 0.88 2.01 1.81 1.64 3.10 2.79 2.54 4.01 3.65 3.32 Table 10. Vdd = 3.0 V (Vdd_3.0) Rise/Fall Times for Specific CLOAD Table 9. Vdd = 2.8 V (Vdd_2.8) Rise/Fall Times for Specific CLOAD Rise/Fall Time Typ (ns) Rise/Fall Time Typ (ns) Drive Strength \ CLOAD L A R B T 5 pF 3.77 1.94 1.29 0.97 0.55 15 pF 7.54 3.90 2.57 2.00 1.12 30 pF 12.28 7.03 4.72 3.54 2.08 45 pF 19.57 10.24 7.01 5.43 3.22 60 pF 25.27 13.34 9.06 6.93 4.08 E or "‐": default U F 0.44 0.34 0.29 1.00 0.88 0.81 1.83 1.64 1.48 2.82 2.52 2.29 3.67 3.30 2.99 Drive Strength \ CLOAD L A R B T or "‐": default E U F 5 pF 3.60 1.84 1.22 0.89 0.51 0.38 0.30 0.27 15 pF 7.21 3.71 2.46 1.92 1.00 0.92 0.83 0.76 30 pF 11.97 6.72 4.54 3.39 1.97 1.72 1.55 1.39 45 pF 18.74 9.86 6.76 5.20 3.07 2.71 2.40 2.16 60 pF 24.30 12.68 8.62 6.64 3.90 3.51 3.13 2.85 Table 11. Vdd = 3.3 V (Vdd_3.3) Rise/Fall Times for Specific CLOAD Rise/Fall Time Typ (ns) Drive Strength \ CLOAD L A R B 5 pF 3.39 1.74 1.16 0.81 15 pF 6.88 3.50 2.33 1.82 30 pF 11.63 6.38 4.29 3.22 45 pF 17.56 8.98 6.04 4.52 60 pF 23.59 12.19 8.34 6.33 T or “‐”: default E U F 0.46 0.33 0.28 0.25 1.00 0.87 0.79 0.72 1.86 1.64 1.46 1.31 2.60 2.30 2.05 1.83 3.84 3.35 2.93 2.61 1.08 Page 8 of 18 www.sitime.com SiT8008B Low Power Programmable Oscillator Pin 1 Configuration Options (OE, ST, ̅ ̅ ̅ , or NC) Pin 1 of the SiT8008 can be factory-programmed to support three modes: Output Enable (OE), standby (ST, ̅ ̅ ̅ ) or No Connect (NC). These modes can also be programmed with the Time Machine using field programmable devices. Output Enable (OE) Mode In the OE mode, applying logic Low to the OE pin only disables the output driver and puts it in Hi-Z mode. The core of the device continues to operate normally. Power consumption is reduced due to the inactivity of the output. When the OE pin is pulled High, the output is typically enabled in