芯
洲
科
SCT2A23A
技
Silicon Content Technology
Rev.1.1
4.5V-100V Vin, 1.2A, Step-down DCDC Converter
FEATURES
DESCRIPTION
The SCT2A23A is 1.2A Step-down DCDC converter
with wide input voltage, ranging from 4.5V to 100V,
which integrates an 600mΩ high-side MOSFET and a
300mΩ low-side MOSFET. The SCT2A23A, adopting
the constant-on time (COT) mode control, supports the
PFM mode with typical 160uA low quiescent current
which assists the converter on achieving high efficiency
at light load or standby condition.
Wide Input Range: 4.5V-100V
1.2A Continuous Output Current
2.75A peak current limit
Integrated 600mΩ High-Side and 300mΩ LowSide Power MOSFETs
15uA Quiescent Current with VCC diode
160uA Quiescent Current without VCC diode
Selectable PFM, USM and FPWM Operation
Modes
1.2V ±2% Feedback Reference Voltage
4.3ms Internal Soft-start Time
Fixed Switching Frequency at 300KHz
COT Control Mode
FPWM mode support Iso-buck Topology
Precision Enable Threshold for Programmable
Input Voltage Under-Voltage Lock Out Protection
(UVLO) Threshold and Hysteresis
Cycle-by-Cycle Current Limit
Over-Voltage Protection
Over-Temperature Protection
Available in an ESOP-8 Package
The SCT2A23A features selectable operation mode at
light load, which provides the flexibility to select Pulse
Frequency Modulation (PFM) to achieve high efficiency
at the light-load, Ultrasonic Mode (USM) to keep the
switching frequency above audible frequency areas
during light-load conditions, and forced Pulse Width
Modulation (FPWM) to achieve smaller output ripple
and support isolation buck topology.
The SCT2A23A offers cycle-by-cycle current limit
protection, thermal shutdown protection, output overvoltage protection and over temperature protection.
The device is available in an 8-pin thermally enhanced
ESOP-8 package.
APPLICATIONS
GPS tracker
E-bike, Scooter
BMS
TYPICAL APPLICATION
100
90
L1
SW
C4
C2
VIN
VIN
D1
BST
SCT2A23A
R1
EN
R4
C5
C6
C3
VCC
R2
MODE
80
FB
R3
Efficiency(%)
GND
C1
VOUT
70
60
50
40
30
PFM
20
R5
FCCM
10
USM
0
0.001
0.01
0.1
1
Iload(A)
Efficiency, Vin=48V, Vout=12V
4.5V-100V, Buck Converter
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1
SCT2A23A
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Revision 1.0: Release to production
Revision 1.1: Update typo(I2) in Figure 7.
DEVICE ORDER INFORMATION
PART NUMBER
PACKAGE MARKING
PACKAGE DISCRIPTION
SCT2A23ASTE
A23A
8-Lead Plastic ESOP
1）For Tape & Reel, Add Suffix R (e.g. SCT2A23ASTER).
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
Over operating free-air temperature unless otherwise noted(1)
DESCRIPTION
MIN
MAX
UNIT
VIN, EN
-0.3
105
V
BOOT
-0.3
110
V
SW
-1
105
V
VCC, MODE
-0.3
30
V
BOOT-SW
-0.3
6
V
FB
-0.3
6
V
Operating junction temperature TJ(2)
-40
150
°C
Storage temperature TSTG
-65
150
°C
(1)
(2)
GND
1
VIN
2
EN
3
MODE
4
Thermal
PAD
9
8
SW
7
BST
6
VCC
5
FB
Figure 1. 8-Lead Plastic E-SOP
Stresses beyond those listed under Absolute Maximum Rating may cause device permanent damage. The device is not guaranteed to
function outside of its Recommended Operation Conditions.
The IC includes over temperature protection to protect the device during overload conditions. Junction temperature will exceed 150°C
when over temperature protection is active. Continuous operation above the specified maximum operating junction temperature will
reduce lifetime.
PIN FUNCTIONS
NAME
NO.
PIN FUNCTION
GND
1
VIN
2
EN
3
MODE
4
Ground
Input supply voltage.
Connect a local bypass capacitor from VIN pin to GND pin. Path from VIN pin to high
frequency bypass capacitor and GND must be as short as possible.
Enable pin to the regulator with internal pull-up current source.
a) Float or connect to VIN to enable the converter.
b) Pull below 1.23V to disable the converter.
c) Resistor divider from VIN to GND connecting EN pin can adjust the input voltage
lockout threshold.
PFM, USM and PWM mode selection.
a) Connect the pin to VCC by a resistor will force the device in Forced Pulse Width
Modulation (FPWM mode).
b) Ground the pin to operate the device in Pulse Frequency Modulation (PFM mode)
c) Floating the pin to operate the device in Ultrasonic Modulation (USM mode).
2
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SCT2A23A
FB
5
VCC
6
BST
7
SW
8
Thermal Pad
9
Inverting input of the internal PWM comparator.
The tap of external feedback resistor divider from the output to GND sets the output
voltage. The device regulates FB voltage to the internal reference value of 1.2V typical.
Output from the Internal High Voltage Regulator.
The internal VCC regulator provides bias supply for the gate drivers and other internal
circuitry. A larger than 1.0 μF decoupling capacitor is recommended.
Power supply bias for high-side power MOSFET gate driver.
Connect a 0.1uF capacitor from BOOT pin to SW pin. Bootstrap capacitor is charged
when low-side power MOSFET is on or SW voltage is low.
Regulator switching output.
Connect SW to an external power inductor
Heat dissipation path of die.
Electrically connection to GND pin. Must be connected to ground plane on PCB for
proper operation and optimized thermal performance.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range unless otherwise noted
PARAMETER
DEFINITION
VIN
VOUT
TJ
Input voltage range
Output voltage range
Operating junction temperature
MIN
MAX
UNIT
4.5
1.2
-40
100
30
125
V
V
°C
MIN
MAX
UNIT
-1
+1
kV
-0.5
+0.5
kV
ESD RATINGS
PARAMETER
VESD
DEFINITION
Human Body Model(HBM), per ANSI-JEDEC-JS-001-2014
specification, all pins(1)
Charged Device Model(CDM), per ANSI-JEDEC-JS-0022014 specification, all pins(2)
(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.
THERMAL INFORMATION
PARAMETER
RθJA
RθJC
RθJB
THERMAL METRIC
Junction to ambient thermal resistance(1)
resistance(1)
Junction to case thermal
Junction to board thermal resistance
ESOP-8L
UNIT
41.1
37.3
30.6
°C/W
(1) SCT provides RθJA and RθJC numbers only as reference to estimate junction temperatures of the devices. RθJA and RθJC are not a
characteristic of package itself, but of many other system level characteristics such as the design and layout of the printed circuit
board (PCB) on which the SCT2A23A is mounted, thermal pad size, and external environmental factors. The PCB board is a heat
sink that is soldered to the leads and thermal pad of the SCT2A23A. Changing the design or configuration of the PCB board
changes the efficiency of the heat sink and therefore the actual RθJA and RθJC.
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3
SCT2A23A
ELECTRICAL CHARACTERISTICS
VIN=48V, TJ=-40°C~125°C, typical value is tested under 25°C.
SYMBOL
PARAMETER
TEST CONDITION
Power Supply
VIN
Operating input voltage
VCC
MIN
4.5
VCC Regulator Output
VCC_UVLO
TYP
VCC UVLO Threshold
VIN rising
100
UNIT
V
7.3
V
4.1
V
250
mV
IVCC_LIM
VCC internal LDO current limit
VCC short to ground
30
mA
ISHDN
Shutdown current from VIN pin
EN=0, no load
PFM mode, EN floating, no load,
non-switching, BOOT-SW=5V
Force VCC>8V
PFM mode, EN floating, no load,
non- switching, BOOT-SW=5V
VCC floating
3
μA
15
μA
160
uA
600
mΩ
300
mΩ
IQ
Hysteresis
MAX
Quiescent current from VIN pin
Power MOSFETs
RDSON_H
High-side MOSFET on-resistance
RDSON_L
VBOOT-VSW=5V
Low-side MOSFET on-resistance
Reference and Control Loop
VREF
Reference voltage of FB
TJ=25°C
1.176
1.2
1.224
V
Enable and Soft-startup
VEN_H
Enable high threshold
1.24
V
VEN_L
Enable low threshold
1.23
V
IEN_L
Enable pin current
EN=0V
0.35
μA
IEN_H
Enable pin current
EN=1.5V
17
uA
Tss
Internal soft start time
4.3
ms
Switching Frequency Timing
FSW
Switching frequency
VOUT=12V
TOFF_MIN
Minimum off-time
VIN=12V
Operation Mode
PWM mode input logic high
VMD_PWM
threshold
PFM mode with USM logic
VMD_USM
threshold
PFM mode input logic low
VMD_PFM
threshold
VCC floating
LS zero cross current threshold
ILIM_LSROC
LS reverse current limit
300
kHz
ns
4.65
2.3
From source to drain for PSM
mode
From drain to source for FCCM
mode
330
200
V
1.5
Current Limit and Over Current Protection
ILIM_HS
HS MOSFET current limit
Izc
270
2.75
3.5
V
0.5
V
3.3
A
50
mA
3.4
A
120
%
Protection
VFB/VREF rising
4
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SCT2A23A
SYMBOL
VOVP
VUVP
TSD
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Feedback overvoltage with
VFB/VREF falling
115
%
Feedback under voltage with
VFB/VREF rising
80
%
respect to reference voltage
VFB/VREF falling
75
%
TJ rising
173
°C
Hysteresis
25
°C
respect to reference voltage
Thermal shutdown threshold*
*Derived from bench characterization
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5
SCT2A23A
TYPICAL CHARACTERISTICS
90
80
80
70
70
Efficiency(%)
100
90
Efficiency(%)
100
60
50
40
30
60
50
40
30
PFM
20
10
0.001
0.01
0.1
Iload(A)
FCCM
10
USM
0
PFM
20
FCCM
USM
0
0.001
1
100
100
90
90
80
80
70
70
60
50
40
30
PFM
20
0.001
0.01
0.1
Iload(A)
1
60
50
40
30
PFM
FCCM
10
USM
0
0.1
20
FCCM
10
Iload(A)
Figure 3. Efficiency, Vin=72V, Vout=12V
Efficiency(%)
Efficiency(%)
Figure 2. Efficiency, Vin=48V, Vout=12V
0.01
USM
0
1
Figure 5. Efficiency with VCC diode, Vin=48V, Vout=12V
0.001
0.01
Iload(A)
0.1
1
Figure 6. Efficiency with VCC diode, Vin=72V, Vout=12V
11.95
310
11.9
305
11.85
300
11.75
11.7
FSW(KHz)
Vout (V)
11.8
290
11.65
PFM
11.6
FCCM
285
USM
280
11.55
11.5
11.45
0.001
275
0.201
0.401
0.601
0.801
1.001
Iload(A)
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20
40
60
80
VIN(V)
Figure 4. Load Regulation, Vin=48V, Vout=12V
6
295
Figure 5. Switching Frequency VS Vin, Vout=12V
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100
SCT2A23A
FUNCTIONAL BLOCK DIAGRAM
VIN
0.35uA
17uA
Thermal
Shutdown
+
EN
VCC
LDO
EN LOGIC
VIN UVLO
Reference
1.24V
VCC
PVDD
LDO
VREF
EN_OK
PVDD
Current Limit
and Off Timer
Boot
Charge
Soft-start
Timer
BST
DC Error
Correction
1.2V
Boot
UVLO
+ PWM
+
+
FB
Ramp
Compensation
Control
Logic
ON Timer
Generator
+
SW
OVP
PVDD
LS
120%VREF
MODE
HS
MODE
Selection
GND
Figure 6. Functional Block Diagram
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7
SCT2A23A
OPERATION
Overview
The SCT2A23A is a 4.5V-100V input, 1.2A output, Step-down DCDC converter with built-in 600mΩ Rdson highside and 300mΩ Rdson low-side power MOSFETs. It implements constant on time control to regulate output voltage,
providing excellent line and load transient response, and internal error amplifier also could improve the line/load
regulation.
The device features three different operation modes at light loading: Pulse Frequency Modulation (PFM) mode,
Ultra-Sonic Modulation (USM) mode and force Pulse Width Modulation (FPWM). In PFM mode, SCT2A23A
provides high light load efficiency, because SCT2A23A design sleep control at light load for improve efficiency. In
USM SCT2A23A keeps the switching frequency above audible frequency areas to avoid audible noise. In FPWM
SCT2A23A achieves low output ripple and support Iso-buck topology.
The SCT2A23A features an internal 4.3ms soft-start time to avoid large inrush current and output voltage overshoot
during startup. The switching frequency is fixed at 300KHz. The device also supports monolithic startup with prebiased output condition for PSM mode and USM mode.
The SCT2A23A has a default input start-up voltage of 4.1V with 250mV hysteresis. The EN pin is a high-voltage
pin with a precision threshold that can be used to adjust the input voltage lockout thresholds with two external
resistors to meet accurate higher UVLO system requirements. Floating EN pin enables the device with the internal
pull-up current to the pin. Connecting EN pin to VIN directly or by a resistor will start up the device automatically.
The SCT2A23A full protection features include the VCC input under-voltage lockout, the output over-voltage
protection, over current protection with cycle-by-cycle current limit, output hard short protection and thermal
shutdown protection.
Constant On-Time Mode Control
The SCT2A23A employs constant on-time (COT) Mode control providing fast transient with pseudo fixed switching
frequency. At the beginning of each switching cycle, since the feedback voltage (VFB) is lower than the internal
reference voltage (VREF), the high-side MOSFET (Q1) is turned on during one on-time and the inductor current
rises to charge up the output voltage. The on-time is determined by the input voltage and output voltage. After the
on-time, the high-side MOSFET (Q1) turns off and the low-side MOSFET (Q2) turns on after dead time duration.
The inductor current drops and the output capacitors are discharged. When the output voltage decreases and the
VFB decreased below the VREF or SS, the Q1 turns on again after another dead time duration. This repeats on
cycle-by-cycle.
The SCT2A23A works with an internal compensation, so customer could use the device easily, but adding
feedforward cap Cf also provides flexibility for optimizing the loop stability and transient response.
Enable and Under Voltage Lockout Threshold
The SCT2A23A is enabled when the VCC pin voltage rises about 4.1V and the EN pin voltage exceeds the enable
threshold of 1.24V. The device is disabled when the VCC pin voltage falls below 3.88V or when the EN pin voltage
is below 1.23V. Internal pull up current source to EN pin allows the device enable when EN pin floats.
EN pin is a high voltage pin that can be connected to VIN directly or by a resistor to start up the device.
For a higher system UVLO threshold, connect an external resistor divider (R3 and R4) shown in Figure 9 from VIN
to EN. The UVLO rising and falling threshold can be calculated by Equation 1 and Equation 2 respectively.
8
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SCT2A23A
𝑉𝐼𝑁_𝑟𝑖𝑠𝑒 = 𝑉𝐸𝑁 ∗
𝑅3 + 𝑅4
𝑅4
VIN
(1)
I2
17uA
I1
0.35uA
(2)
𝑉𝐼𝑁_ℎ𝑦𝑠 = 𝐼2 ∗ 𝑅3
R3
EN
Where
VIN_rise: Vin rise threshold to enable the device
+
EN
1.24V
R4
VIN_hys: Vin hysteresis threshold
I1=0.35uA : neglect in calculation
I2=17uA
VEN=1.24V, assume VEN_r = VEN_f =1.24V
Figure 7. System UVLO by enable divide
Output Voltage
The SCT2A23A regulates the internal reference voltage at 1.2V with 2% tolerance over the operating temperature
and voltage range. The output voltage is set by a resistor divider from the output node to the FB pin. It is
recommended to use 1% tolerance or better resistors. Use Equation 3 to calculate resistance of resistor dividers.
To improve efficiency at light loads, larger value resistors are recommended. However, if the values are too high,
the regulator will be more susceptible to noise affecting output voltage accuracy.
𝑉𝑂𝑈𝑇
𝑅𝐹𝐵_𝑇𝑂𝑃 = (
− 1) ∗ 𝑅𝐹𝐵_𝐵𝑂𝑇
𝑉𝑅𝐸𝐹
(3)
where
RFB_TOP is the resistor connecting the output to the FB pin.
RFB_BOT is the resistor connecting the FB pin to the ground.
Internal Soft-Start
The SCT2A23A integrates an internal soft-start circuit that ramps the reference voltage from zero volts to 1.2V
reference voltage in 4.3ms. If the EN pin is pulled below 1.23V, switching stops and the internal soft-start resets.
The soft-start also resets during shutdown due to thermal overloading.
Mode Selection
The SCT2A23A features three different operation modes at light load by easily programming the MODE pin. The
programming information is listed in following table. The mode setting is latched at each power up or enable and is
not be able to be modified during operation.
Table 1. MODE Pin config for different operation mode
MODE Pin config
Connect to VCC by a resistor
Floating
Connect to GND
Operation Mode
FPWM
USM
PFM
Bootstrap Voltage Regulator
An external bootstrap capacitor between BOOT pin and SW pin powers the floating gate driver to high-side power
MOSFET. The bootstrap capacitor voltage is charged from an integrated voltage regulator when high-side power
MOSFET is off and low-side power MOSFET is on.
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9
SCT2A23A
Over Current Limit
The inductor current is monitored during high-side MOSFET turn on. The SCT2A23A implements over current
protection with cycle-by-cycle limiting high-side MOSFET peak current during unexpected overload or output hard
short condition.
SCT2A23A also provide a HS current limit off timer for making the IC safer when trigger over current condition.
Once trigger HS over current, the present on-time period is immediately terminated, and will force LS turn on a nonresettable off timer for avoiding the inductor current run away. The length of off time is controlled by FB voltage and
VIN voltage and could be calculated by the following equation.
𝑉𝐼𝑁
𝑇𝑜𝑓𝑓 = 1.5 ∗ (
) 𝑢𝑠
20 ∗ 𝑉𝐹𝐵 + 4.35
(4)
Over voltage Protection
The SCT2A23A implements the Over-voltage Protection OVP circuitry to minimize output voltage overshoot during
load transient, recovering from output fault condition or light load transient. The overvoltage comparator in OVP
circuit compares the FB pin voltage to the internal reference voltage. When FB voltage exceeds 120% of internal
1.2V reference voltage, the high-side MOSFET turns off to avoid output voltage continue to increase, and low-side
MOSFET will turn on to discharge the output voltage. When the FB pin voltage falls below 115% of the 1.2V
reference voltage, the high-side MOSFET can turn on again.
Thermal Shutdown
The SCT2A23A protects the device from the damage during excessive heat and power dissipation conditions. Once
the junction temperature exceeds 173°C, the internal thermal sensor stops power MOSFETs switching. When the
junction temperature falls below 148°C, the device restarts with internal soft start phase.
10
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SCT2A23A
APPLICATION INFORMATION
Typical Application1
L1 68uH
VOUT=12V IOUT =1.2A
GND
C1
10uF
SW
C2
0.1uF
VIN
VIN=24~100V
R1
300K
R2
20K
D1
100V
C4
0.1uF
R4
271K
BST
SCT2A23A
EN
C5
68pF
C6
22uF
C3
2.2uF
VCC
MODE
FB
R3
5K
R5
30K
Figure 8. SCT2A23A Design Example, 12V Output with Programmable UVLO, PSM Mode
Design Parameters
Design Parameters
Example Value
Input Voltage
48V Normal， 24V to 100V
Output Voltage
12V
Output Current
1.2A
Switching Frequency
300 KHz
Output voltage ripple (peak to peak)
50mV
Transient Response 10mA to 600mA load step
∆Vout = 80mV
Transient Response 10mA to 1A load step
∆Vout = 200mV
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11
SCT2A23A
Typical Application2: Low Iq application
L1 68uH
VOUT =12V IOUT=1.2A
GND
C1
10uF
SW
C2
0.1uF
C4
0.1uF
VIN
VIN=12V~100V
R1
100K
BST
C6
22uF
C3
2.2uF
SCT2A23A
EN
D1
100V
R4
271K
C5
68pF
VCC
D2
MODE
FB
R3
5K
R5
30K
Figure 11. SCT2A23A Design Example, 12V Output with VCC diode, PSM Mode and low Iq application
Design Parameters
12
Design Parameters
Example Value
Input Voltage
48V Normal， 24V to 100V
Output Voltage
12V
Output Current
1.2A
Switching Frequency
300 KHz
Output voltage ripple (peak to peak)
50mV
Transient Response 10mA to 600mA load step
∆Vout = 80mV
Transient Response 10mA to 1A load step
∆Vout = 200mV
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SCT2A23A
Output Voltage
The output voltage is set by an external resistor divider
R4 and R5 in typical application schematic.
Recommended R5 resistance is 30KΩ. Use equation 5
to calculate R4.
𝑉𝑂𝑈𝑇
𝑅4 = (
− 1) ∗ 𝑅5
𝑉𝑅𝐸𝐹
where:
(5)
Table 1. R1, R2Value for Common Output Voltage
(Room Temperature)
VOUT
R4
R5
5V
95 KΩ
30 KΩ
12V
271 KΩ
30 KΩ
24V
576 KΩ
30 KΩ
VREF is the feedback reference voltage of 1.2V
Under Voltage Lock-Out
An external voltage divider network of R3 from the input to EN pin and R4 from EN pin to the ground can set the
input voltage’s Under Voltage Lock-Out (UVLO) threshold. The UVLO has two thresholds, one for power up when
the input voltage is rising and the other for power down or brown outs when the input voltage is falling. For the
example design, the supply should turn on and start switching once the input voltage increases above 19.84V (start
or enable). After the regulator starts switching, it should continue to do so until the input voltage falls below 14.74V
(stop or disable). Use Equation 6 and Equation 7 to calculate the values 300 kΩ and 20 kΩ of R1 and R2 resistors.
𝑉𝐼𝑁𝑟𝑖𝑠𝑒 = 𝑉𝐸𝑁_𝐻 ∗
𝑅1 + 𝑅2
𝑅2
𝑉𝐼𝑁_ℎ𝑦𝑠 = 𝐼2 ∗ 𝑅1
(6)
(7)
Where
VIN_rise: Vin rise threshold to enable the device
VIN_hys: Vin hysteresis threshold
I2=17uA
VEN_H=1.24V
Inductor Selection
There are several factors should be considered in selecting inductor such as inductance, saturation current, the
RMS current and DC resistance(DCR). Larger inductance results in less inductor current ripple and therefore leads
to lower output voltage ripple. However, the larger value inductor always corresponds to a bigger physical size,
higher series resistance, and lower saturation current. A good rule for determining the inductance to use is to allow
the inductor peak-to-peak ripple current to be approximately 20%~40% of the maximum output current.
The peak-to-peak ripple current in the inductor ILPP can be calculated as in Equation 8.
𝐼𝐿𝑃𝑃 =
Where
𝑉𝑂𝑈𝑇 ∗ (𝑉𝐼𝑁 − 𝑉𝑂𝑈𝑇 )
𝑉𝐼𝑁 ∗ 𝐿 ∗ 𝑓𝑆𝑊
(8)
ILPP is the inductor peak-to-peak current
L is the inductance of inductor
fSW is the switching frequency
VOUT is the output voltage
VIN is the input voltage
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13
SCT2A23A
Since the inductor-current ripple increases with the input voltage, so the maximum input voltage in application is
always used to calculate the minimum inductance required. Use Equation 9 to calculate the inductance value.
𝐿𝑀𝐼𝑁 =
Where
𝑉𝑂𝑈𝑇
𝑉𝑂𝑈𝑇
∗ (1 −
)
𝑓𝑆𝑊 ∗ 𝐿𝐼𝑅 ∗ 𝐼𝑂𝑈𝑇(𝑚𝑎𝑥)
𝑉𝐼𝑁(𝑚𝑎𝑥)
(9)
LMIN is the minimum inductance required
fsw is the switching frequency
VOUT is the output voltage
VIN(max) is the maximum input voltage
IOUT(max) is the maximum DC load current
LIR is coefficient of ILPP to IOUT
The total current flowing through the inductor is the inductor ripple current plus the output current. When selecting
an inductor, choose its rated current especially the saturation current larger than its peak operation current and
RMS current also not be exceeded. Therefore, the peak switching current of inductor, ILPEAK and ILRMS can be
calculated as in equation 10 and equation 11.
𝐼𝐿𝑃𝐸𝐴𝐾 = 𝐼𝑂𝑈𝑇 +
𝐼𝐿𝑃𝑃
2
𝐼𝐿𝑅𝑀𝑆 = √(𝐼𝑂𝑈𝑇 )2 +
Where
(10)
1
∗ (𝐼𝐿𝑃𝑃 )2
12
(11)
ILPEAK is the inductor peak current
IOUT is the DC load current
ILPP is the inductor peak-to-peak current
ILRMS is the inductor RMS current
In overloading or load transient conditions, the inductor peak current can increase up to the switch current limit of
the device which is typically 2.75A. The most conservative approach is to choose an inductor with a saturation
current rating greater than 2.75A. Because of the maximum ILPEAK limited by device, the maximum output current
that the SCT2A23A can deliver also depends on the inductor current ripple. Thus, the maximum desired output
current also affects the selection of inductance. The smaller inductor results in larger inductor current ripple leading
to a lower maximum output current.
Diode Selection
The SCT2A23A requires an external catch diode between the SW pin and GND. The selected diode must have a
reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be greater than
the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due to their low
forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.
Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of
100-V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the SCT2A23A.
For the example design, the SS510 Schottky diode is selected for its lower forward voltage and good thermal
characteristics compared to smaller devices. The typical forward voltage of the SS510 is 0.7 volts at 5 A.
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by the
forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher switching
frequencies, the ac losses of the diode need to be taken into account. The ac losses of the diode are due to the
14
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SCT2A23A
charging and discharging of the junction capacitance and reverse recovery charge. Equation 12 is used to calculate
the total power dissipation, including conduction losses and ac losses of the diode.
The SS510 diode has a junction capacitance of 300 pF. Using Equation 12, the total loss in the diode at the
maximum input voltage is 1.24 W.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
𝑃𝐷 =
(𝑉𝐼𝑁_𝑀𝐴𝑋 − 𝑉𝑂𝑈𝑇 ) × 𝐼𝑂𝑈𝑇 × 𝑉𝑑 𝐶𝑗 × 𝑓𝑆𝑊 × (𝑉𝐼𝑁 + 𝑉𝑑 )2
+
𝑉𝐼𝑁_𝑀𝐴𝑋
2
(12)
Input Capacitor Selection
The input current to the step-down DCDC converter is discontinuous, therefore it requires a capacitor to supply the
AC current to the step-down DCDC converter while maintaining the DC input voltage. Use capacitors with low ESR
for better performance. Ceramic capacitors with X5R or X7R dielectrics are usually suggested because of their low
ESR and small temperature coefficients, and it is strongly recommended to use another lower value capacitor (e.g.
0.1uF) with small package size (0603) to filter high frequency switching noise. Place the small size capacitor as
close to VIN and GND pins as possible.
The voltage rating of the input capacitor must be greater than the maximum input voltage. And the capacitor must
also have a ripple current rating greater than the maximum input current ripple. The RMS current in the input
capacitor can be calculated using Equation 13.
ICINRMS = IOUT ∗ √
VOUT
VOUT
∗ (1 −
)
VIN
VIN
(13)
The worst case condition occurs at VIN=2*VOUT, where:
(14)
ICINRMS = 0.5 ∗ IOUT
For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load
current.
When selecting ceramic capacitors, it needs to consider the effective value of a capacitor decreasing as the DC
bias voltage across a capacitor increasing.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 15 and the maximum input voltage ripple occurs at 50% duty cycle.
∆VIN =
IOUT
VOUT
VOUT
∗
∗ (1 −
)
fSW ∗ CIN VIN
VIN
(15)
For this example, one 10μF, X7R ceramic capacitors rated for 100 V in parallel are used. And a 0.1 μF for highfrequency filtering capacitor is placed as close as possible to the device pins.
Bootstrap Capacitor Selection
A 0.1μF ceramic capacitor must be connected between BOOT pin and SW pin for proper operation. A ceramic
capacitor with X5R or better grade dielectric is recommended. The capacitor should have a 10V or higher voltage
rating.
Output Capacitor Selection
The selection of output capacitor will affect output voltage ripple in steady state and load transient performance.
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SCT2A23A
The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going through
the Equivalent Series Resistance ESR of the output capacitors and the other is caused by the inductor current ripple
charging and discharging the output capacitors. To achieve small output voltage ripple, choose a low-ESR output
capacitor like ceramic capacitor. For ceramic capacitors, the capacitance dominates the output ripple. For
simplification, the output voltage ripple can be estimated by Equation 16 desired.
∆VOUT =
Where
𝑉𝑂𝑈𝑇 ∗ (𝑉𝐼𝑁 − 𝑉𝑂𝑈𝑇 )
(16)
8 ∗ 𝑓𝑆𝑊 2 ∗ 𝐿 ∗ 𝐶𝑂𝑈𝑇 ∗ 𝑉𝐼𝑁
ΔVOUT is the output voltage ripple
fSW is the switching frequency
L is the inductance of inductor
COUT is the output capacitance
VOUT is the output voltage
VINis the input voltage
Due to capacitor’s degrading under DC bias, the bias voltage can significantly reduce capacitance. Ceramic
capacitors can lose most of their capacitance at rated voltage. Therefore, leave margin on the voltage rating to
ensure adequate effective capacitance. Typically, two 22μF ceramic output capacitors work for most applications.
Table 2 lists typical values of external components for some standard output voltages.
Table 2: Component List with Typical Output Voltage BOM list
16
Vout
L1
COUT
R4
R5
C5
5V
33uH
2*22uF
95K
30K
68pF
12V
68uH
2*22uF
271K
30K
150pF
24V
100uH
2*22uF
576k
30K
220pF
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Application Waveforms
Vin=48V, Vout=12V, unless otherwise noted
Figure 12. Power up (Iload=2A)
Figure 13. Power down (Iload=1.2A)
Figure 14. Enable toggle Iload=1.2A)
Figure 15. Output Hard Short Protection
Figure 16. Output Hard Short Release
Figure 17. Load Transient (0.3A to 0.9A, 1.6A/us)
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17
SCT2A23A
Application Waveforms(Continued)
Vin=48V, Vout=12V, unless otherwise noted
18
Figure 18. Load Transient 0A to 2.3A (400ms)
Figure 19. Output Ripple (Iload=0A, FCCM)
Figure 20. Output Ripple (Iload=0A, USM)
Figure 21. Output Ripple (Iload=0A, PFM)
Figure 22. Output Ripple (Iload=1.2A)
Figure 23. Thermal, 48VIN, 12Vout, 1.2A
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SCT2A23A
Typical Application3: Iso-Buck Application
C7
22uF
D1
R6
0 ohm
VOUT2=5V IOUT2=0.5A
L1=68uH
N =2.1:1
GND
C1
10uF
SW
C2
0.1uF
VIN
VIN=36~72V
R1
100K
BST
SCT2A23A
EN
MODE
VCC
VOUT1=12V IOUT1=0.6A
D1
100V
C4
0.1uF
R4
270K
C5
68pF
C6
22uF
C3
2.2uF
VCC
FB
R3
5K
R2
300K
R5
30K
Figure 24. SCT2A23A Design Example, Iso-BUCK application with 5V isolation Output
Design Parameters
Design Parameters
Example Value
Input Voltage
48V Normal， 36V to 72V
Output Voltage
12V/5V
Maximum Output Current
Iout1=0.6A/Iout2=0.5A
Voltage drop of VD1
0.7V
Inductor /Transformer Turns Ratio (N)
L1=68uH /N=2.1:1
Switching Frequency
300 KHz
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19
SCT2A23A
Design of Iso-BUCK
Selection of VOUT and Turns Ratio
The primary output voltage in a Iso-Buck converter should be no more than one half of the minimum input voltage.
For example, at the minimum VIN of 36 V, the primary output voltage (VOUT1) should be no higher than 18V. The
isolated output voltage VOUT2 is set by selecting a transformer with a turns ratio (N1:N2 = NPRI:NSEC). Using this
turns ratio, the required primary output voltage VOUT1 is calculated by the following equation:
𝑉𝑜𝑢𝑡1 =
𝑉𝑜𝑢𝑡2 + 𝑉𝑑1
𝑁2/𝑁1
(17)
The 0.7 V (Vd1) represents the forward voltage drop of the secondary rectifier diode. By setting the primary output
voltage VOUT1 by selecting the correct feedback resistors, the secondary voltage is regulated at VOUT2 nominally.
Adjustment of the primary side VOUT1 may be required to compensate for voltage errors due to the leakage
inductance of the transformer, the resistance of the transformer windings, the diode drop in the power path on the
secondary side.
Secondary Rectifier Diode
The secondary side rectifier diode must block the maximum input voltage reflected at secondary side switch node.
The minimum diode reverse voltage VRD1 rating is given below
𝑉𝑅𝐷1 = (𝑉𝐼𝑁(𝑚𝑎𝑥) − 𝑉𝑜𝑢𝑡1) ∗
𝑁2
+ 𝑉𝑜𝑢𝑡2
𝑁1
(18)
A diode with higher reverse voltage rating must be selected in this application. If the input voltage (V IN) has
transients above the normal operating maximum input voltage, then the worst-case transient input voltage must
be used in calculation while selecting the secondary side rectifier diode.
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Iso-Buck Application Waveforms
Vin=48V, Vout=12V, Viso=5V, unless otherwise noted
Figure 25. Power up(Io=0.6A,Iiso=0.5A)
Figure 26. Power down(IO=0.6A,Iiso=0.5A)
Figure 27. Steady State(Io=0.6A,Iiso=0.5A)
Figure 28. Load Transient 0.3A to 0.9A (isoload)
Figure 29. Secondary-Side Short(Io=1.2A)
Figure 30. Secondary-Side Short Release (Io=1.2A)
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SCT2A23A
Layout Guideline
Proper PCB layout is a critical for SCT2A23A’s stable and efficient operation. The traces conducting fast switching
currents or voltages are easy to interact with stray inductance and parasitic capacitance to generate noise and
degrade performance. For better results, follow these guidelines as below:
1. Power grounding scheme is very critical because of carrying power, thermal, and glitch/bouncing noise
associated with clock frequency. The thumb of rule is to make ground trace lowest impendence and power are
distributed evenly on PCB. Sufficiently placing ground area will optimize thermal and not causing over heat area.
2. Place a low ESR ceramic capacitor as close to VIN pin and the ground as possible to reduce parasitic effect.
3. For operation at full rated load, the top side ground area must provide adequate heat dissipating area. Make
sure top switching loop with power have lower impendence of grounding.
4. The bottom layer is a large ground plane connected to the ground plane on top layer by vias. The power pad
should be connected to bottom PCB ground planes using multiple vias directly under the IC. The center thermal
pad should always be soldered to the board for mechanical strength and reliability, using multiple thermal vias
underneath the thermal pad. Improper soldering thermal pad to ground plate on PCB will cause SW higher ringing
and overshoot besides downgrading thermal performance. It is recommended 8mil diameter drill holes of thermal
vias, but a smaller via offers less risk of solder volume loss. On applications where solder volume loss thru the vias
is of concern, plugging or tenting can be used to achieve a repeatable process.
5. Output inductor should be placed close to the SW pin. The area of the PCB conductor minimized to prevent
excessive capacitive coupling.
6. UVLO adjust, VCC capacitor and feedback components should connect to small signal ground which must return
to the GND pin without any interleaving with power ground.
7. For achieving better thermal performance, a four-layer layout is strongly recommended.
VOUT
Inductor
Output capacitors
GND
Top layer ground area
1
Input bypass
capacitor
VIN
GND
SW
VIN
BST
BST Capacitor
Programmable
UVLO resistors
VCC
EN
Thermal VIA
MODE
GND
22
FB
Via
Via
Feedback resistors
Top layer ground area
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SCT2A23A
PACKAGE INFORMATION
ESOP8/PP(95x130) Package Outline Dimensions
Symbol
A
A1
A2
b
c
D
D1
E
E1
E2
e
L
Dimensions in Millimeters
Min.
Max.
1.300
1.700
0.000
0.100
1.350
1.550
0.330
0.510
0.170
0.250
4.700
5.100
3.050
3.250
3.800
4.000
5.800
6.200
2.160
2.360
1.270(BSC)
Dimensions in Inches
Min.
Max.
0.051
0.067
0.000
0.004
0.053
0.061
0.013
0.020
0.007
0.010
0.185
0.201
0.120
0.128
0.150
0.157
0.228
0.244
0.085
0.093
0.050(BSC)
0.400
0°
0.016
0°
1.270
8°
0.050
8°
NOTE:
1.
2.
3.
4.
5.
6.
Drawing proposed to be made a JEDEC package outline MO-220 variation.
Drawing not to scale.
All linear dimensions are in millimeters.
Thermal pad shall be soldered on the board.
Dimensions of exposed pad on bottom of package do not include mold flash.
Contact PCB board fabrication for minimum solder mask web tolerances between the pins.
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SCT2A23A
TAPE AND REEL INFORMATION
Orderable Device
SCT2A23ASTER
24
Package Type
ESOP
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Pins
8
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