NJU8713V-TE1

NJU8713 2V Operation Switching Driver for Class D Amplifier PACKAGE OUTLINE GENERAL DESCRIPTION The NJU8713 is a Switching Driver for a class D Amplifier including Separated Power Source terminals between Input and Output, BEEP and BPZ (Bipolar Zero) output circuits. It converts 1bit digital signal input, such as PWM or PDM signal, to an analog signal output through a simple external LC low-pass filter. The NJU8713 realizes very high power-efficiency because of the class D operation. Therefore, it is suitable for portable audio set and others. NJU8713V PIN CONFIGURATION FEATURES 2-channel 1bit Audio Signal Input Standby(Hi-Z), BPZ Control Internal BPZ Charger Beep Function Operating Voltage : 1.7V to 2.7V Driving Voltage : 1.7V to VDD CMOS Technology Package Outline : SSOP14 MCK VSS IN1 EN1 VSSO OUT1 VDDO 14 13 12 11 10 9 8 1 2 3 4 5 6 7 BEEP VDD IN2 EN2 VSSO OUT2 VDDO BLOCK DIAGRAM VDD VSS VDDO VSSO BPZ Output OUT1 IN1 BEEP OUT2 IN2 Output Control MCK Ver.2004-06-02 EN1 BPZ Output EN2 -1- NJU8713 TERMINAL DESCRIPTION No. 13 2 SYMBOL VDD VSS I/O - 7 8 VDDO - 5 10 VSSO - 1 MCK I 4 11 3 12 EN1 EN2 IN1 IN2 14 BEEP I 6 9 OUT1 OUT2 O I I Function Operation Power Supply, VDD=2V Operation Power GND, VSS=0V Driving Power Supply, VDDO=2V Terminal No.7 and No.8 should be connected to the same electric potential. Driving Power GND, VSSO=0V Terminal No.5 and No.10 should be connected to the same electric potential. Master Clock Input Terminal The condition of the data input terminal is fetched with the rising edge of this signal. Output Control Terminal Output circuit is selected by the condition of this terminal. Audio Signal Input Terminal 1-bit Audio Signal inputs into this terminal. Beep Signal Input Terminal Beep signal inputs into this terminal. Output Terminal • When Output Terminal selects Audio Signal, IN1 terminal input data outputs from OUT1 terminal and IN2 terminal input data outputs from OUT2 terminal. • When Output Terminal selects Beep Signal, BEEP terminal input data outputs from OUT1 and OUT2 terminals. INPUT TERMINAL STRUCTURE VDD Input Terminal Inside Circuit VSS -2- Ver.2004-06-02 NJU8713 NJU3555 FUNCTIONAL DESCRIPTION (1) Signal Output PWM signals of L channel and R output from OUT1 and OUT2 terminals respectively. These signals are converted to analog signal by external 2nd-order or over LC filter. The output driver power supplied from VDDO and VSSO are required high response power supply against voltage fluctuation like as switching regulator because Output T.H.D is effected by power supply stability. (2) Master Clock Master clock (MCK) synchronizes the Audio signal inputs (IN1 and IN2). The setup time and the hold time should be kept in the AC characteristics because IN1 and IN2 are fetched with the rising edge of MCK. MCK requires jitter-free or jitter as small as possible because the jitter downs S/N ratio. OUT1 and OUT2 occur the pop noise when MCK is stopped in operation without standby mode. Therefore, the standby mode should be set before MCK stop. (3) Output Control Output circuit is selected by the conditions of EN1 and EN2 terminals. EN2 EN1 0 0 Standby(High impedance) 0 1 Audio Signal Output 1 0 BPZ Output 1 1 Beep Signal Output Output State of OUT1 & OUT2 (4) Beep Function The beep signal must be input before the rising edge of EN2 signal and must be stopped after the falling edge of EN2 signal. EN1 EN2 MCK BEEP Audio Signal Output Ver.2004-06-02 Beep Signal Output Audio Signal Output -3- NJU8713 (5) BPZ Function BPZ Function operates to charge the external AC coupling capacitor for the BPZ level which is a point of the analog signal common. Be sure to input sound-less data to IN1 and IN2 in busy of the BPZ function. At this time, the sound-less signal must be input before the rising edge of EN2 signal and must be continue after the falling edge of EN2 signal. The charging time is in proportion to the capacity value of the external AC coupling capacitor. EN1 EN2 MCK IN1, IN2 Standby -4- Sound-less Data Audio Data BPZ Output Audio Signal Output Standby Ver.2004-06-02 NJU8713 NJU3555 ABSOLUTE MAXIMUM RATINGS PARAMETER (Ta=25°C) UNIT SYMBOL RATING Operation Supply Voltage VDD -0.3 to +4.0 V Driving Supply Voltage VDDO -0.3 to +2.7 V Input Voltage Vin -0.3 to VDD+0.3 V Operating Temperature Topr -40 to +85 °C Storage Temperature Tstg -40 to +125 °C PD 300 mW - VDD ≥ VDDO V Power Dissipation SSOP14 Power Supply Voltage Condition Note 1) All voltage values are specified as VSS=VSSO=0V. Note 2) If the LSI is used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the electrical characteristics conditions will cause malfunction and poor reliability. Note 3) Decoupling capacitors should be connected between VDD-VSS and VDDO-VSSO due to the stabilized operation. ELECTRICAL CHARACTERISTICS (Ta=25°C, VDD=VDDO=2.0V, VSS=VSSO=0.0V, Load Impedance=32Ω, fS=44.1kHz, unless otherwise noted) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT VDD Supply Voltage VDD 1.7 2.0 2.7 V VDDO Supply Voltage VDDO 1.7 2.0 VDD V BPZ Driving Voltage VBPZ VDDO /2-0.2 VDDO /2 VDDO /2+0.2 V Output Driver High side Resistance Output Driver Low side Resistance Beep High side Current Beep Low side Current Operating Current At Standby Operating Current At no input signal load operating MCK=256fS IN1, IN2=32fS Duty50% RH VOUT=VDDO-0.1V - 1.5 2 Ω RL VOUT=0.1V - 1.5 2 Ω IBH VOUT=VDDO-1V 20 50 150 uA IBL VOUT=1V 20 50 150 uA - - 1 uA - 0.05 0.1 - 0.6 1.2 VIH 0.7VDD - VDD V VIL 0 - 0.3VDD V ILK - - ±1 uA IST IDD IDDO Stopping MCK, IN1, IN2, BEEP No-load operating IN1, IN2=32fS MCK=256fS mA Input Voltage Input Leakage Current Ver.2004-06-02 -5- NJU8713 TIMING CHARACTERISTICS Audio Signal Input • tMCKH tMCKL MCK tMCKI IN1, IN2 tDS PARAMETER tDH (Ta=25°C, VDD=VDDO=2.0V, VSS=VSSO=0.0V, unless otherwise noted) CONDITIONS MIN. TYP. MAX. UNIT SYMBOL MCK Frequency fMCKI 8 - 25 MHz MCK Pulse Width (H) tMCKH 12 - - ns MCK Pulse Width (L) tMCKL 12 - - ns IN1,IN2 Setup Time tDS 20 - - ns IN1,IN2 Hold Time tDH 20 - - ns BEEP Frequency fBEEP 0.1 - 20 kHz Note 4) tMCKI shows the cycle of the MCK signal. Output Control Signal Input • EN1 tED 0.9VDD 0.5VDD 0.1VDD tEr EN2 0.9VDD 0.5VDD 0.1VDD tEf PARAMETER SYMBOL (Ta=25°C, VDD=VDDO=2.0V, VSS=VSSO=0.0V, unless otherwise noted) CONDITIONS MIN. TYP. MAX. UNIT Rise Time tEr - - 50 ns Fall Time tEf - - 50 ns Switching Time tED 100 ns Note 5) All timings are based on 30% and 70% voltage level of VDD. -6- Ver.2004-06-02 NJU8713 NJU3555 APPLICATION CIRCUIT 4 Output Control 11 Master Clock Logic Power 1 10uF 2.2uF 13 2 BEEP EN1 EN2 OUT2 9 VDDO MCK VSSO VDD VDDO VSS VSSO 100uH 2.2uF 7 12 14 4 Output Control 11 Master Clock Logic Power 1 10uF 2.2uF 13 2 2.2uF 100uF 5 Switching Regulator 2.2uF 8 10 •A914BY-101M is manufactured by TOKO, INC. For further information, please refer to its technical papers. A914BY-101M IN1 OUT1 6 100uH IN2 100uH BEEP EN1 EN2 NJU8713 3 1kΩ Headphone 220uF A914BY-101M channel BTL application example Audio Signal 32Ω 1kΩ 14 0.22uF Beep Signal 100uH IN2 OUT2 32Ω Speaker 0.22uF 12 OUT1 6 0.22uF Audio Signal 220uF A914BY-101M IN1 0.22uF 3 •1 •A914BY-101M is manufactured by TOKO, INC. For further information, please refer to its technical papers. OTL application example NJU8713 • Stereo 9 A914BY-101M VDDO MCK VSSO VDD VDDO VSS VSSO 2.2uF 7 5 2.2uF 100uF Switching Regulator 2.2uF 8 10 Note 6) De-coupling capacitors must be connected between each power supply pin and GND pin. Note 7) The power supply for VDDO requires fast driving response performance such as a switching regulator for T.H.D. Note 8) The bigger capacitor value of external AC-coupling capacitors realize better low frequency response characteristics. In addition, ESR(Equivalent Series Resistance) should be low. Note 9) The above circuit shows only application example and does not guarantee the any electrical characteristics. Therefore, please consider and check the circuit carefully to fit your application. Ver.2004-06-02 -7- NJU8713 [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. -8- Ver.2004-06-02