W681513
5V SINGLE-CHANNEL VOICEBAND CODEC FOR USB
APPLICATIONS
Data Sheet
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Publication Release Date: October, 2005
Revision A11
W681513
1. GENERAL DESCRIPTION
The W681513 is a single channel PCM CODEC with pin-selectable μ-Law or A-Law companding
dedicated to the USB accessory market by supporting a derivative 2MHz clock. The device is
compliant with the ITU G.712 specification. It operates from a single +5V power supply and is
available in 20-pin SOP package option. Functions performed include digitization and reconstruction
of voice signals, and band limiting and smoothing filters required for PCM systems. The filters are
compliant with ITU G.712 specification. W681513 performance is specified over the industrial
temperature range of –40°C to +85°C.
The W681513 includes an on-chip precision voltage reference and an additional power amplifier,
capable of driving 300Ω loads differentially up to a level of 6.3V peak-to-peak. The analog section is
fully differential, reducing noise and improving the power supply rejection ratio. The data transfer
protocol supports both long-frame and short-frame synchronous communications for PCM
applications, and IDL and GCI communications for ISDN applications. W681513 accepts 2MHz
master clock rate, and an on-chip pre-scaler automatically determines the division ratio for the
required internal clock.
Applications
2. FEATURES
•
Single +5V power supply
•
Typical power dissipation of 30 mW,
power-down mode of 0.5 μW
•
Fully-differential analog circuit design
•
On-chip precision reference of 1.575 V for
a 0 dBm TLP at 600 Ω (775mVRMS)
•
Push-pull power amplifiers with external
gain adjustment with 300 Ω load capability
•
Master clock rate supports 2.000MHz
clock for USB applications
•
Pin-selectable
μ-Law
and
A-Law
companding (compliant with ITU G.711)
•
CODEC A/D and D/A filtering compliant
with ITU G.712
•
Industrial temperature range (–40°C to
+85°C)
•
Package: 20-pin SOP (SOG)
•
Pb-Free / RoHS package option available
•
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Soft phones running on a PC (VoInternet):
o
USB Phones
o
USB to PSTN Gateway
•
USB Microphones
•
USB Headset for PC and Game Consoles
W681513
3. BLOCK DIAGRAM
Re
Int
PC
cei
erf
M
ve
ace
Receive
PCM
Interface
BCLKR
FSR
PCMR
G.712 CODEC
G.711 μ/A -Law
Tra Int
ns PC erf
mitM ace
Transmit
PCM
Interface
BCLKT
FST
PCMT
PAO+
PAOPAI
RO
RO+
AO
AI+
AI-
μ/A-Law
512 kHz
256 kHz
Voltage reference
V AG
8 kHz
PUI
Power Conditioning
VDD
2000 kHz,
Pre -Scaler
-scaler
VSS
MCLK
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Publication Release Date: October, 2005
Revision A11
W681513
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2
2. FEATURES ......................................................................................................................................... 2
3. BLOCK DIAGRAM .............................................................................................................................. 3
4. TABLE OF CONTENTS ...................................................................................................................... 4
5. PIN CONFIGURATION ....................................................................................................................... 6
6. PIN DESCRIPTION ............................................................................................................................. 7
7. FUNCTIONAL DESCRIPTION............................................................................................................ 8
7.1. Transmit Path ................................................................................................................................ 8
7.2. Receive Path ................................................................................................................................. 9
7.3. Power Management..................................................................................................................... 10
7.3.1. Analog and Digital Supply ..................................................................................................... 10
7.3.2. Analog Ground Reference Voltage Outpt ............................................................................. 10
7.4. PCM Interface .............................................................................................................................. 10
7.4.1. Long Frame Sync.................................................................................................................. 10
7.4.2. Short Frame Sync ................................................................................................................. 11
7.4.3. General Circuit Interface (GCI) ............................................................................................. 11
7.4.4. Interchip Digital Link (IDL)..................................................................................................... 12
7.4.5. System Timing ...................................................................................................................... 12
8. TIMING DIAGRAMS.......................................................................................................................... 13
9. ABSOLUTE MAXIMUM RATIINGS................................................................................................... 20
9.1. Absolute Maximum Ratings ......................................................................................................... 20
9.2. Operating Conditions ................................................................................................................... 20
10. ELECTRICAL CHARACTERISTICS ............................................................................................... 21
10.1. General Parameters .................................................................................................................. 21
10.2. Analog Signal Level and Gain Parameters ............................................................................... 22
10.3. Analog Distortion and Noise Parameters .................................................................................. 23
10.4. Analog Input and Output Amplifier Parameters......................................................................... 24
10.5. Digital I/O ................................................................................................................................... 26
10.5.1. μ-Law Encode Decode Characteristics............................................................................... 26
10.5.2. A-Law Encode Decode Characteristics .............................................................................. 27
10.5.3. PCM Codes for Zero and Full Scale ................................................................................... 28
10.5.4. PCM Codes for 0dBm0 Output ........................................................................................... 28
11. TYPICAL APPLICATION CIRCUITS .............................................................................................. 29
12. PACKAGE SPECIFICATION .......................................................................................................... 32
12.2. 20L SOP (SOG)-300mil ............................................................................................................. 32
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W681513
13. ORDERING INFORMATION........................................................................................................... 33
14. VERSION HISTORY ....................................................................................................................... 34
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Publication Release Date: October, 2005
Revision A11
W681513
5. PIN CONFIGURATION
RO+
RO+
PAI
PAOPAO+
VDD
FSR
PCMR
BCLKR
PUI
1
20
2
19
3
18
4
17
5
6
7
SINGLE
CHANNEL
CODEC
16
15
14
8
13
9
12
10
11
SOP
-6-
VAG
AI+
AIAO
/A
μ/A-Law
VSS
FST
PCMT
BCLKT
MCLK
W681513
6. PIN DESCRIPTION
Pin
Name
Pin
No.
Functionality
RO+
1
Non-inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to
1.575 volt peak referenced to the analog ground level.
RO+
2
Non-inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to
1.575 volt peak referenced to the analog ground level.
PAI
3
This pin is the inverting input to the power amplifier. Its DC level is at the VAG voltage.
PAO-
4
Inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt peak referenced
to the VAG voltage level.
PAO+
5
Non-inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt peak
referenced to the VAG voltage level.
VDD
6
Power supply. This pin should be decoupled to VSS with a 0.1μF ceramic capacitor.
FSR
7
8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or
channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit
and receive are synchronous operations.
PCMR
8
PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins.
BCLKR
9
PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is
selected when this pin is tied to VSS. The IDL mode is selected when this pin is tied to VDD.
This pin can also be tied to the BCLKT when transmit and receive are synchronous operations.
PUI
10
Power up input signal. When this pin is tied to VDD, the part is powered up. When tied to VSS,
the part is powered down.
MCLK
11
System master clock input supporting 2000 kHz only.
BCLKT
12
PCM transmit bit clock input pin.
PCMT
13
PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins.
FST
14
8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes.
VSS
15
This is the supply ground. This pin should be connected to 0V.
μ/A-Law
16
Compander mode select pin. μ-Law companding is selected when this pin is tied to VDD. A-Law
companding is selected when this pin is tied to VSS.
AO
17
Analog output of the first gain stage in the transmit path.
AI-
18
Inverting input of the first gain stage in the transmit path.
AI+
19
Non-inverting input of the first gain stage in the transmit path.
VAG
20
Mid-Supply analog ground pin, which supplies a 2.5 Volt reference voltage for all-analog signal
processing. This pin should be decoupled to VSS with a 0.01μF to 0.1 μF capacitor. This pin
becomes high impedance when the chip is powered down.
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Publication Release Date: October, 2005
Revision A11
W681513
7. FUNCTIONAL DESCRIPTION
W681513 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC
complies with the specifications of the ITU-T G.712 recommendation. The CODEC also includes a
complete μ-Law and A-Law compander. The μ-Law and A-Law companders are designed to comply
with the specifications of the ITU-T G.711 recommendation.
The block diagram in section 3 shows the main components of the W681513. The chip consists of a
PCM interface, which can process long and short frame sync formats, as well as GCI and IDL formats.
The pre-scaler of the chip provides the internal clock signals and synchronizes the CODEC sample
rate with the external frame sync frequency. The power conditioning block provides the internal
power supply for the digital and the analog section, while the voltage reference block provides a
precision analog ground voltage for the analog signal processing. The main CODEC block diagram
is shown in section 3.
VA
V AG
G
+ -
Receive Path
+
PAO+
PAO PAI
8
+
D/A
μ/A-Contr
Control
ol
Converter
w
-
fC = 3400Hz
Hz
Smoothi
Smoothing
ngFilter
1
RO +
Smoothing
Smoothi
ngFilter
2
Transmit Path
AO
8
++
-
A/D
Converter
μ μ/A- /A
ContrControl
ffC == 200Hz
200
C
Hz Pass
High
High
Filte
Filter
Pas
f C == 3400Hz
3400
Ant
Aliasing
--Aliasi
AntHz
i Filter
ng
AI+
AI -
Ant -Aliasing
-Aliasi
Filter
Figure 7.1 The W681513 Signal Path
7.1. Transmit Path
The A-to-D path of the CODEC contains an analog input amplifier with externally configurable gain
setting (see application examples in section 11). The device has an input operational amplifier whose
output is the input to the encoder section. If the input amplifier is not required for operation it can be
powered down and bypassed. In that case a single ended input signal can be applied to the AO pin or
the AI- pin. The AO pin becomes high input impedance when the input amplifier is powered down. The
input amplifier can be powered down by connecting the AI+ pin to VDD or VSS. The AO pin is selected
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W681513
as an input when AI+ is tied to VDD and the AI- pin is selected as an input when AI+ is tied to VSS (see
Table 7.1).
AI+
Input Amplifier
Input
VDD
Powered Down
AO
1.2 to VDD-1.2
Powered Up
AI+, AI-
VSS
Powered Down
AI-
Table 7.1 Input Amplifier Modes of operation
When the input amplifier is powered down, the input signal at AO or AI- needs to be referenced to the
analog ground voltage VAG.
The output of the input amplifier is fed through a low-pass filter to prevent aliasing at the switched
capacitor 3.4 kHz low pass filter. The 3.4 kHz switched capacitor low pass filter prevents aliasing of
input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low pass filter is
filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed according to the
recommendations in the G.712 ITU-T specification. From the output of the high pass filter the signal is
digitized. The signal is converted into a compressed 8-bit digital representation with either μ-Law or ALaw format. The μ-Law or A-Law format is pin-selectable through the μ/A-Law pin. The compression
format can be selected according to Table 7.2.
μ/A-Law Pin
Format
VSS
A-Law
VDD
μ-Law
Table 7.2.
Pin-selectable Compression Format
The digital 8-bit μ-Law or A-Law samples are fed to the PCM interface for serial transmission at the
sample rate supplied by the external frame sync FST.
7.2. Receive Path
The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and
converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed
through the pin-selectable μ-Law or A-Law expander and converted to analog samples. The mode of
expansion is selected by the μ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a
low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification.
A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is
buffered to provide the receive output signal RO+. The RO+ output can be externally connected to the
PAI pin to provide a differential output with high driving capability at the PAO+ and PAO- pins. By
using external resistors (see section 11 for examples), various gain settings of this output amplifier
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Publication Release Date: October, 2005
Revision A11
W681513
can be achieved. If the transmit power amplifier is not in use, it can be powered down by connecting
PAI to VDD.
7.3. POWER MANAGEMENT
7.3.1. Analog and Digital Supply
The power supply for the analog and digital parts of the W681513 must be 5V +/- 10%. This supply
voltage is connected to the VDD pin. The VDD pin needs to be decoupled to ground through a 0.1 μF
ceramic capacitor.
7.3.2. Analog Ground Reference Voltage Output
The analog ground reference voltage is available for external reference at the VAG pin. This voltage
needs to be decoupled to VSS through a 0.01 μF ceramic capacitor.
7.4. PCM INTERFACE
The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received
through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of
operation of the interface are shown in Table 7.3.
BCLKR
FSR
Interface Mode
2.000 MHz
8 kHz
Long or Short Frame Sync
VSS
VSS
ISDN GCI with active channel B1
VSS
VDD
ISDN GCI with active channel B2
VDD
VSS
ISDN IDL with active channel B1
VDD
VDD
ISDN IDL with active channel B2
Table 7.3 PCM Interface mode selections
7.4.1. Long Frame Sync
The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the
BCLKR or BCLKT pin to a 2.000 MHz clock and connecting the FSR or FST pin to the 8 kHz frame
sync. The device synchronizes the data word for the PCM interface and the CODEC sample rate on
the positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when the FST pin is
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W681513
held HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. The length of the Frame
Sync pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125
μsec. During data transmission in the Long Frame Sync mode, the transmit data pin PCMT will
become low impedance when the Frame Sync signal FST is HIGH or when the 8 bit data word is
being transmitted. The transmit data pin PCMT will become high impedance when the Frame Sync
signal FST becomes LOW while the data is transmitted or when half of the LSB is transmitted. The
internal decision logic will determine whether the next frame sync is a long or short frame sync, based
on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for
two frame sync cycles after every power down state. More detailed timing information can be found in
the interface timing section.
7.4.2. Short Frame Sync
The W681513 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is
HIGH for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge
of the bit-clock, the W681513 starts clocking out the data on the PCMT pin, which will also change
from high to low impedance state. The data transmit pin PCMT will go back to the high impedance
state halfway through the LSB. The Short Frame Sync operation of the W681513 is based on an 8-bit
data word. When receiving data on the PCMR pin, the data is clocked in on the first falling edge after
the falling edge that coincides with the Frame Sync signal. The internal decision logic will determine
whether the next frame sync is a long or short frame sync, based on the previous frame sync pulse.
To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every
power down state. More detailed timing information can be found in the interface timing section.
7.4.3. General Circuit Interface (GCI)
The GCI interface mode is selected when the BCLKR pin is connected to VSS for two or more frame
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface
consists of 4 pins: FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects
channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data
clock DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK.
The data rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted
consecutively. Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is
transmitted on the second 16 clock cycles of DCL. For more timing information, see the timing section.
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Publication Release Date: October, 2005
Revision A11
W681513
7.4.4. Interchip Digital Link (IDL)
The IDL interface mode is selected when the BCLKR pin is connected to VDD for two or more frame
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface
consists of 4 pins: IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR
pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the
first positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK
cycle long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after
the IDL SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK
after the IDL SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the
IDL CLK after the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when
not used for data transmission and also in the time slot of the unused channel. For more timing
information, see the timing section.
7.4.5. System Timing
The system can work at 2000 kHz master clock rate only. The system clock is supplied through the
master clock input MCLK and can be derived from the bit-clock if desired. An internal pre-scaler is
used to generate a fixed 256 kHz and 8 kHz sample clock for the internal CODEC. If the Frame Sync
is LOW for the entire frame sync period while the MCLK and BCLK pin clock signals are still present,
the W681513 will enter the low power standby mode. Another way to power down is to set the PUI pin
to low. When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the
Frame Sync pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will
become low impedance.
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W681513
8. TIMING DIAGRAMS
TFTRHM
TFTRSM
TMCKL
TMCKH
TRISE
TFALL
MCLK
TMCK
TFS
TFSL
FST
TFTRH
BCLKT
0
TFTRS
1
TFTFH
2
3
TFDTD
TBCKH
4
5
6
7
TBDTD
PCMT
D7
D6
8
THID
D5
D4
D3
D2
TBCKL
0
1
TBCK
THID
D1 D0
MSB
LSB
TFS
TFSL
FSR
TFRRH
BCLKR
0
TFRRS
1
TFRFH
2
3
TBCKH
4
5
6
7
8
TBCKL
0
1
TBCK
PCMR
D7
MSB
TDRS
D6
D5
D4
D3
D2
D1 D0
LSB
TDRH
Figure 8.1 Long Frame Sync PCM Timing
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Publication Release Date: October, 2005
Revision A11
W681513
SYMBOL
DESCRIPTION
1/TFS
FST, FSR Frequency
1
MIN
TYP
MAX
UNIT
---
8
---
kHz
TFSL
FST / FSR Minimum LOW Width
TBCK
sec
1/TBCK
BCLKT, BCLKR Frequency
2000
---
2000
kHz
TBCKH
BCLKT, BCLKR HIGH Pulse Width
50
---
---
ns
TBCKL
BCLKT, BCLKR LOW Pulse Width
50
---
---
ns
TFTRH
BCLKT 0 Falling Edge to FST Rising
Edge Hold Time
20
---
---
ns
TFTRS
FST Rising Edge to BCLKT 1 Falling
edge Setup Time
80
---
---
ns
TFTFH
BCLKT 2 Falling Edge to FST Falling
Edge Hold Time
50
---
---
ns
TFDTD
FST Rising Edge to Valid PCMT Delay
Time
---
---
60
ns
TBDTD
BCLKT Rising Edge to Valid PCMT
Delay Time
---
---
60
ns
THID
Delay Time from the Later of FST
Falling Edge, or
10
---
60
ns
BCLKT 8 Falling Edge to PCMT Output
High Impedance
TFRRH
BCLKR 0 Falling Edge to FSR Rising
Edge Hold Time
20
---
---
ns
TFRRS
FSR Rising Edge to BCLKR 1 Falling
edge Setup Time
80
---
---
ns
TFRFH
BCLKR 2 Falling Edge to FSR Falling
Edge Hold Time
50
---
---
ns
TDRS
Valid PCMR to BCLKR Falling Edge
Setup Time
0
---
---
ns
TDRH
PCMR Hold Time from BCLKR Falling
Edge
50
---
---
ns
Table 8.1 Long Frame Sync PCM Timing Parameters
1
TFSL must be at least ≥ TBCK
- 14 -
W681513
TFTRHM
TFTRSM
TMCKL
TMCKH
TRISE
TFALL
MCLK
TMCK
TFS
TFTFH
TFTFS
FST
TFTRS
TFTRH
BCLKT
-1
0
TBCKH
1
2
3
TBDTD
PCMT
D7
4
5
6
7
0
8
TBDTD
D6
D5
TBCKL
TBCK
THID
D4
D3
D2
1
D1 D0
MSB
LSB
TFS
TFRFH
TFRFS
FSR
TFRRS
TFRRH
BCLKR
-1
0
TBCKH
1
2
3
4
5
6
7
TBCKL
0
8
1
TBCK
PCMR
D7
MSB
TDRS
D6
D5
D4
D3
D2
D1 D0
LSB
TDRH
Figure 8.2 Short Frame Sync PCM Timing
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Publication Release Date: October, 2005
Revision A11
W681513
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
1/TFS
FST, FSR Frequency
---
8
---
kHz
1/TBCK
BCLKT, BCLKR Frequency
2000
---
2000
kHz
TBCKH
BCLKT, BCLKR HIGH Pulse Width
50
---
---
ns
TBCKL
BCLKT, BCLKR LOW Pulse Width
50
---
---
ns
TFTRH
BCLKT –1 Falling Edge to FST Rising Edge Hold
Time
20
---
---
ns
TFTRS
FST Rising Edge to BCLKT 0 Falling edge Setup
Time
80
---
---
ns
TFTFH
BCLKT 0 Falling Edge to FST Falling Edge Hold Time
50
---
---
ns
TFTFS
FST Falling Edge to BCLKT 1 Falling Edge Setup
Time
50
---
---
ns
TBDTD
BCLKT Rising Edge to Valid PCMT Delay Time
10
---
60
ns
THID
Delay Time from BCLKT 8 Falling Edge to PCMT
Output High Impedance
10
---
60
ns
TFRRH
BCLKR –1 Falling Edge to FSR Rising Edge Hold
Time
20
---
---
ns
TFRRS
FSR Rising Edge to BCLKR 0 Falling edge Setup
Time
80
---
---
ns
TFRFH
BCLKR 0 Falling Edge to FSR Falling Edge Hold Time
50
---
---
ns
TFRFS
FSR Falling Edge to BCLKR 1 Falling Edge Setup
Time
50
---
---
ns
TDRS
Valid PCMR to BCLKR Falling Edge Setup Time
0
---
---
ns
TDRH
PCMR Hold Time from BCLKR Falling Edge
50
---
---
ns
Table 8.2 Short Frame Sync PCM Timing Parameters
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W681513
TFS
FST
TFSFH
TFSRS
TFSRH
BCLKT
-1
0
1
TBCKH
2
3
4
5
TBDTD
PCMT
6
8
9
THID
TBDTD
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
TDRS
PCMR
7
10
11 12
LSB
15 16
17
18
TBCK
THID
TBDTD
D7 D6 D5 D4 D3 D2
D1 D0
LSB
MSB
TDRS
D7 D6 D5 D4 D3 D2 D1 D0
14
TBDTD
TDRH
MSB
13
TBCKL
TDRH
D7 D6 D5 D4 D3 D2
MSB
BCH = 0
B1 Channel
D1 D0
LSB
BCH = 1
B2 Channel
Figure 8.3 IDL PCM Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
1/TFS
FST Frequency
---
8
---
kHz
1/TBCK
BCLKT Frequency
2000
---
2000
kHz
TBCKH
BCLKT HIGH Pulse Width
50
---
---
ns
TBCKL
BCLKT LOW Pulse Width
50
---
---
ns
TFSRH
BCLKT –1 Falling Edge to FST Rising Edge
Hold Time
20
---
---
ns
TFSRS
FST Rising Edge to BCLKT 0 Falling edge
Setup Time
60
---
---
ns
TFSFH
BCLKT 0 Falling Edge to FST Falling Edge
Hold Time
20
---
---
ns
TBDTD
BCLKT Rising Edge to Valid PCMT Delay
Time
10
---
60
ns
THID
Delay Time from the BCLKT 8 Falling Edge
(B1 channel) or BCLKT 18 Falling Edge (B2
Channel) to PCMT Output High Impedance
10
---
50
ns
TDRS
Valid PCMR to BCLKT Falling Edge Setup
Time
20
---
---
ns
TDRH
PCMR Hold Time from BCLKT Falling Edge
75
---
---
ns
Table 8.3 IDL PCM Timing Parameters
- 17 -
Publication Release Date: October, 2005
Revision A11
W681513
TFS
FST
TFSFH
TFSRS
TFSRH
TBCKH
TBCKL
BCLKT
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
TFDTD
PCMT
TBDTD
TBDTD
D7 D6 D5 D4 D3 D2 D1 D0
TDRS
D7 D6 D5 D4 D3 D2
D1 D0
LSB
TDRS
TDRH
TDRH
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2
MSB
THID
TBDTD TBCK
LSB MSB
MSB
PCMR
THID
D1 D0
LSB MSB
BCH = 0
B1 Channel
LSB
BCH = 1
B2 Channel
Figure 8.4 GCI PCM Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
1/TFST
FST Frequency
---
8
---
kHz
1/TBCK
BCLKT Frequency
2000
---
2000
kHz
TBCKH
BCLKT HIGH Pulse Width
50
---
---
ns
TBCKL
BCLKT LOW Pulse Width
50
---
---
ns
TFSRH
BCLKT 0 Falling Edge to FST Rising Edge Hold Time
20
---
---
ns
TFSRS
FST Rising Edge to BCLKT 1 Falling edge Setup Time
60
---
---
ns
TFSFH
BCLKT 1 Falling Edge to FST Falling Edge Hold Time
20
---
---
ns
TFDTD
FST Rising Edge to Valid PCMT Delay Time
---
---
60
ns
TBDTD
BCLKT Rising Edge to Valid PCMT Delay Time
---
---
60
ns
THID
Delay Time from the BCLKT 16 Falling Edge (B1
channel) or BCLKT 32 Falling Edge (B2 Channel) to
PCMT Output High Impedance
10
---
50
ns
TDRS
Valid PCMR to BCLKT Rising Edge Setup Time
20
---
---
ns
TDRH
PCMR Hold Time from BCLKT Rising Edge
---
---
60
ns
Table 8.4 GCI PCM Timing Parameters
- 18 -
W681513
SYMBOL
DESCRIPTION
1/TMCK
Master Clock Frequency
TMCKH
TMCK
/
MCLK Duty
Operation
TYP
MIN
Cycle
--for
256
kHz
HIGH
2000
45%
MAX
UNIT
---
kHz
55%
TMCKH
Minimum Pulse Width
MCLK(512 kHz or Higher)
for
50
---
---
ns
TMCKL
Minimum Pulse Width LOW for MCLK
(512 kHz or Higher)
50
---
---
ns
TFTRHM
MCLK falling Edge to FST Rising Edge
Hold Time
50
---
---
ns
TFTRSM
FST Rising Edge to MCLK Falling edge
Setup Time
50
---
---
ns
TRISE
Rise Time for All Digital Signals
---
---
50
ns
TFALL
Fall Time for
---
---
50
ns
All Digital Signals
Table 8.5 General PCM Timing Parameters
- 19 -
Publication Release Date: October, 2005
Revision A11
W681513
9. ABSOLUTE MAXIMUM RATINGS
9.1. ABSOLUTE MAXIMUM RATINGS
Condition
Value
0
Junction temperature
150 C
Storage temperature range
-650C to +1500C
Voltage Applied to any pin
(VSS - 0.3V) to (VDD + 0.3V)
Voltage applied to any pin (Input current limited to +/-20 mA)
(VSS – 1.0V) to (VDD + 1.0V)
VDD - VSS
-0.5V to +6V
1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability. Functional operation is not implied at these conditions.
9.2. OPERATING CONDITIONS
Condition
Value
Industrial operating temperature
-400C to +850C
Supply voltage (VDD)
+4.5V to +5.5V
Ground voltage (VSS)
0V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely
affect the life and reliability of the device.
- 20 -
W681513
10. ELECTRICAL CHARACTERISTICS
10.1. GENERAL PARAMETERS
Conditions
Min (2)
Typ (1)
Max (2)
Units
0.6
V
Symbol
Parameters
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
VOL
PCMT Output LOW Voltage
IOL = 3 mA
VOH
PCMT Output HIGH Voltage
IOL = -3 mA
IDD
VDD Current (Operating) - ADC + DAC
No Load
6
8
ISB
VDD Current (Standby)
FST & FSR =Vss ;
PUI=VDD
10
100
Ipd
VDD Current (Power Down)
PUI= Vss
0.1
10
μA
IIL
Input Leakage Current
VSS
