A
User Guide
SU60-SIPT Development Kit (DVK-SU60-SIPT)
Version 1.0
DVK-SU60-SIPT
User Guide
REVISION HISTORY
Version
1.0
Date
29 July 2017
Notes
Initial Release
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/wireless
Approver
Jay White
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DVK-SU60-SIPT
User Guide
CONTENTS
1
Overview.............................................................................................................................................................4
Introduction ................................................................................................................................................4
Package Contents .......................................................................................................................................4
2
SU60-SIPT Development Kit – Main Development Board ..................................................................................4
Key Features ...............................................................................................................................................5
Understanding the Development Board ....................................................................................................6
3
Functional Blocks ................................................................................................................................................7
Pin Definitions ............................................................................................................................................7
3.1.1
SDIO-Pin Header .................................................................................................................................7
3.1.2
PCIe Golden Finger .............................................................................................................................8
Power Supply ..............................................................................................................................................9
Host Configuration .................................................................................................................................. 10
Tact Switch............................................................................................................................................... 10
3.4.1
PDn (SW9) ........................................................................................................................................ 11
3.4.2
PMU_EN (SW8) ................................................................................................................................ 11
4-wire UART Serial Interface ................................................................................................................... 11
3.5.1
UART Mapping ................................................................................................................................. 12
3.5.2
UART Interface Driven by USB ......................................................................................................... 12
3.5.3
UART Interface Driven by External Source ...................................................................................... 13
32.768KHz Oscillator................................................................................................................................ 13
PCM ......................................................................................................................................................... 14
LTE Coexistence ....................................................................................................................................... 14
GPIOs ....................................................................................................................................................... 15
LED Indicator ........................................................................................................................................... 15
U.FL Connector ........................................................................................................................................ 16
4
Additional Documentation .............................................................................................................................. 16
Embedded Wireless Solutions Support Center:
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www.lairdtech.com/wireless
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DVK-SU60-SIPT
User Guide
1 OVERVIEW
The Laird SU60-SIPT development kit provides a platform for rapid wireless connectivity prototyping, providing
multiple options for the development of Wi-Fi and Bluetooth applications.
This guide applies to Rev. 01 of the development PCB and relates to DVK-SU60-SIPT-B0 on the PCB itself. The
complete functionality of the development kit hardware requires the use of Laird SU60-SIPT FW version xx.xx.xx
or greater.
Part Number: DVK-SU60-SIPT
Applicable to the following Wi-Fi part number: SU60-SIPT (Dual-band 802.11ac Wi-Fi + Bluetooth v4.2 combo SiP
Introduction
The Laird SU60-SIPT development kit is designed to support the rapid development of applications and software
for the SU60-SIPT of Wi-Fi + Bluetooth modules featuring Laird’s innovative event-driven programming language
– xxxxxx. More information regarding this product series including additional documentation is available from
the product page of the Laird website.
Package Contents
All kits contain the following:
Development board
Power options
IDC cable x
SDIO extension cable
Web link card
The development board has the required SU60-SIPT module installed onto it and
exposes all the various hardware interfaces available.
USB cable – Type A to micro B. The cable also provides serial communications via
the FTDI USB – RS232 converter chip on the development board
DC barrel plug with clips for connection to external power supply
Supplied to allow a simple connection to the ? x ? way pin headers into J6, J7, and J8.
The IDC cables are 2.54 mm pitch.
Supplied to allow a simple connection to the SDIO socket.
Provides links to additional information including the 60-series user guide,
schematics, quick start guides, and firmware release notes.
2 SU60-SIPT DEVELOPMENT KIT – MAIN DEVELOPMENT BOARD
This section describes the SU60-SIPT development board hardware. The SU60-SIPT development board is
delivered with the SU60-SIPT module but no onboard firmware and applications.
The SU60-SIPT development board is a universal development tool to highlight the capabilities of the SU60-SIPT
module. The development kit is supplied in a default configuration which should be suitable for multiple
experimentation options. It also offers multiple pin headers that help to create different configurations for
SU60-SIPT module. This allows you to test different operating scenarios.
The development board allows the SU60-SIPT module to physically connect to a SDIO host via the supplied SDIO
extension cable and USB host via USB cable for development purposes. The development board also provides
USB-to-Virtual COM port conversion through a FTDI chip – part number FT232R. Any Windows PC (XP or later)
and Linux PC (Ubuntu xx.xx or Fedora xx.xx) should auto-install the necessary drivers; if your PC cannot locate
the drivers, you can download them from http://www.ftdichip.com/Drivers/VCP.htm
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/wireless
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DVK-SU60-SIPT
User Guide
Key Features
The SU60-SIPT development board contains the following features:
SU60-SIPT module installed on-board
Power supply options for powering development board from:
– USB
– External DC supply
– SDIO interface
– PCIe interface
Regulated 3.3 V for powering the SU60-SIPT module. Optional regulated 1.8 V for powering the VCCIO for FTDI
chip
USB to UART bridge (FTDI chip)
USB interface for Wi-Fi or Bluetooth
PCIe interface for Wi-Fi
Module UART can be interfaced to:
– USB (PC) using the USB-UART bridge
– External UART source (using IO break-out connector when development board powered from DC jack
or SDIO interface)
Current measuring options:
– Pin header (Ammeter)
IO break-out (2.54 mm pitch headers) connectors interface for plugging-in external modules and accessing all
interfaces of the SU60-SIPT module [UART, LTE coexistence, PCM, GPIO, JTAG].
Two buttons and LEDs for user interaction
Seven slide switches for DC source, IO level, and host config
External 32 KHz oscillator for the sleep clock
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DVK-SU60-SIPT
User Guide
Understanding the Development Board
CON1 CON3
J22
J15
FTDI-FT232R
J17
J18
J16
USB2
USB to UART
J7
J6
SW9
J8
SW8
J11
J3
J10
J9
SW1
Slide SW
J2
J1
J12
SU60SIPTModul
e
J5
LED1
J13
32KHz OSC
SW7
SW6
SW5
SW4
SW2
SW3
LED2
J14
LED3
USB1
USB 2.0
J20
J4
SDIO
CN1
DC Jack
mPCIe
Figure 1: Development board
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DVK-SU60-SIPT
User Guide
3 FUNCTIONAL BLOCKS
The development board is formed from the following major functional blocks:
Pin Definitions
3.1.1 SDIO-Pin Header
Figure 2: DVK-SU60-SIPT SDIO pin header
Table 1: SDIO pin definitions
Pin
#
Name
Type
1
2
3
4
5
6
GND
SDIO DATA2
GND
SDIO DATA3
GND
SDIO CMD
I/O, PU
I/O, PU
I/O
Voltage
Ref.
1.8V
1.8V
1.8V
7
8
9
10
11
12
GND
GND
SDIO_3V3
SDIO_3V3
GND
SDIO CLK
Power
Power
I, PU
1.8V
13
14
GND
GND
-
-
15
16
GND
SDIO DATA0
I/O, PU
17
18
GND
SDIO DATA1
I/O, PU
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Description
If Not Used
Ground
SDIO 4-bit Mode DATA line Bit[2]
Ground
SDIO 4-bit Mode DATA line Bit[3]
Ground
SDIO 4-bit Mode Command/Response
GND
N/C
GND
N/C
GND
N/C
Ground
Ground
3.3V module power supply
3.3V module power supply
Ground
SDIO 4-bit Mode Clock Input
GND
GND
GND
N/C
Ground
Ground
GND
GND
1.8V
Ground
SDIO 4-bit Mode DATA line Bit[0]
GND
N/C
1.8V
Ground
SDIO 4-bit Mode DATA line Bit[1]
GND
N/C
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User Guide
3.1.2 PCIe Golden Finger
Table 2: PCIe pin definitions
Pin
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Name
Type
PEWAKE0#
PCIE_3V3
GND
CLKREQ0#
GND
REFCLKn0
REFCLKp0
GND
GND
-
I/O
Power
I/O
I
I
-
Voltage
Ref.
3.3V
3.3V
1.8V
1.8V
-
20
W_DISABLE1#
I, PU
3.3V
21
GND
-
-
22
PERST0#
I, PD
3.3V
23
24
25
26
27
28
29
30
31
32
33
34
35
PETn0
PCIE_3V3
PETp0
GND
GND
GND
PERn0
PERp0
GND
GND
O
Power
O
I
I
-
1.8V
1.8V
1.8V
1.8V
-
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Description
If Not Used
PCIe wake signal (input/output) (active low)
3.3V module power supply
Ground
PCIe clock request (input/output) (active low)
Ground
PCIe Differential Clock Input-Negative
PCIe Differential Clock Input-Positive
Ground
Ground
PCIe host indication to disable the WLAN
function of the device (input) (active low)
Ground
PCIe host indication to reset the device
(input) (active low)
PCIe Transmit Data-Negative
3.3V module power supply
PCIe Transmit Data-Positive
Ground
Ground
Ground
PCIe Receive Data-Negative
PCIe Receive Data-Positive
Ground
Ground
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N/C
GND
GND
GND
N/C
N/C
GND
GND
N/C
GND
N/C
N/C
N/C
GND
GND
GND
N/C
N/C
GND
GND
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Pin
#
36
37
38
39
40
41
42
43
Name
Type
USB_DGND
USB_D+
PCIE_3V3
GND
PCIE_3V3
GND
I/O
I/O
Power
Power
-
Voltage
Ref.
3.3V
3.3V
-
44
LED1#
O, PU
3.3V
45
-
-
-
46
LED2#
O, PU
3.3V
47
48
49
50
51
52
GND
PCIE_3V3
Power
-
Description
If Not Used
USB Differential Data-Negative
Ground
USB Differential Data-Positive
3.3V module power supply
Ground
3.3V module power supply
Ground
LED indicator for WLAN with 10mA drive
capability
LED indicator for BT with 10mA drive
capability.
Ground
3.3V module power supply
N/C
GND
N/C
GND
GND
N/C
N/C
GND
-
Power Supply
12V
DC Jack
CN1
DC/DC
12V→5V
5V
5V
DC/DC
5V→3.3V
SW1
5V
USB Connector
USB1 / USB2
3.3V
PCIe Interface
5V
SDIO Interface
Pin Header
J3
Pin Header
J20
Pin Header
J5
3.3V
3.3V
SU60-SIPT
Module
3.3V
Figure 3: DVK-SU60-SIPT power supply
The development board can be powered from DC 12V supply (into DC jack connector CN1), USB (type micro-B)
connector (USB1 and USB2), or the host interface (PCIe or SDIO interface). The power source fed into DC jack is
regulated down to 5V with an on-board regulator and wire to SW1.
The 5V from the USB or the DC jack is regulated down to 3.3V with an on-board regulator on the development
board. Switch SW1 selects between the regulated 5V and USB. The voltage from host interface (PCIe or SDIO
interface) is not regulated but is fed directly to SU60-SIPT module supply pin.
The default position of SW2 is to select regulated 5V.
The development board has a 1.8 V regulator for the VCCIO of FTDI-Chip.
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DC/DC
5V→3.3V
3.3V
PCIe Interface
SDIO Interface
VIO
Pin Header
J3
Pin Header
J20
Pin Header
J5
J1
REG_VIO
LDO
3.3V→1.8V
SU60-SIPT
1.8V
SW2
SW4
VIO_SD
J2
REG_VIO_SD
SW3
Figure 4: DVK-SU60-2230C 1.8V power supply
On the development board, the power domain:
3V3 supplies the SU60-SIPT module only
The header connectors (J3, J20, J5) can be used to measure the current of power domain 3V3
REG_1V8 supplies the FTDI chip IO, VIO and VIO_SD
Host Configuration
The development board have three slide switches (SW5, SW6, SW7) for bootstrap configuration. To view its
location, refer to Table 3.
Table 3: Bootstrap configuration
Strap Value
SW7, SW6, SW5
CON[0], CON[1], CON[2]
000
001
010
011
101
WLAN
BT
SDIO
SDIO
PCIe
PCIe
UART
SDIO
USB 2.0
UART
USB 2.0
USB 2.0
Tact Switch
The development board have three tact switches (SW8, SW9) for optional. To view its location, refer to Figure 1.
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3.4.1 PDn (SW9)
3V3
J9
J10
3V3
SW9
PDn
1V8
GND
GND
GND
GND
Figure 5: DVK-SU60-2230C PDn power supply
Full Power-Down (Input) (Active Low)
0 – Full power-down mode
1 – Normal mode
PDn can accept an input either 1.8V or 3.3V
.
PDn may be driven by the host
PDn must be high for normal operation
There is an internal pull-up resistor on this pin.
3.4.2 PMU_EN (SW8)
3V3
GND
GND
J11
SW8
PMU_EN
GND
GND
GPIO21
PCIE_PERSTn
Figure 6: DVK-SU60-2230C PMU_EN power supply
Enable input for internal PMU (Input) (Active Low).
0 – Disable the input for internal PMU.
1 – Normal mode
PMU_EN can accept an input of 3.3V.
PMU_EN may be driven by the host
PMU_EN must be high for normal operation
There is an internal pull-up resister on this pin.
Note: PDn and PMU_EN are also wired to TP1 and TP2 for optional. To view its location, refer to Figure 1.
4-wire UART Serial Interface
The development board provides access to the SU60-SIPT module 4-wire UART interface (TX, RX, CTS, RTS)
either through USB (via U7 FTDI USB-UART convertor chip) or through a breakout header connector J15, J16,
J17, and J18. Refer to Figure 1.
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Note:
SU60-SIPT module provides 4-wire UART interface on the HW.
For 3.3V VIO, VIH is from 2.31V to 3.7V; VIL is from -0.4V to 0.99V.
For 1.8V VIO, VIH is from 1.26V to 2.2V; VIL is from -0.4V to 0.54V.
3.5.1 UART Mapping
UART connection on the SU60-SIPT module and FTDI IC are shown in table below. Refer to Figure 1 to see how
the SU60-SIPT module UART is mapped to the breakout header connector (J15, J16, J17 and J18).
Table 4: UART mapping
SU60-SIPT Default function
FTDI IC UART
UART_RXD (output)
UART_TXD (input)
UART_CTSn (output)
UART_RTSn (input)
TXD
RXD
RTS
CTS
3.5.2 UART Interface Driven by USB
USB Connector – The development kit provides a USB Type micro-B connector (USB2) which allows connection
to any USB host device. The connector optionally supplies power to the development kit and the USB
signals are connected to a USB to serial convertor device (FT232R).
USB to UART – The development kit is fitted with a (U6) FTDI FT232R USB to UART converter which provides
USB-to-Virtual COM port on any Windows PC (XP or later). Upon connection, Windows auto-installs the
required drivers. For more details and driver downloads, visit
http://www.ftdichip.com/Products/FT232R.htm.
UART interface driven by USB FTDI chip – In normal operation, the SU60-SIPT module UART interface is driven
by the FTDI FT232R USB to UART converter.
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DVK-SU60-SIPT
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3.5.3 UART Interface Driven by External Source
UART interface driven by external UART source – The SU60-SIPT module UART interface (TX, RX, CTS, RTS) is
presented at a 2.54 mm (0.1”) pitch headers (J15, J16, J17, and J18). To allow the SU60-SIPT UART interface
to be driven from the breakout header connector (J15, J16, J17, and J18):
– The development board must be powered from DC jack (CON5) and switch SW1 must be in position
DC JACK 5V.
J15
UART_RTSn
J16
UART_CTSn
SU60-SIPT
FT232R
Module
J17
UART_RXD
J18
UART_TXD
External
Source
Figure 6: USB to UART Interface and Header to UART interface
32.768KHz Oscillator
The development kit is fitted with a (U5) 32.768KHz oscillator which provides sleep clock to SU60-SIPT module.
Fit a jumper on J14 to disable the sleep clock, if necessary.
Figure 7: Pin Header J14
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PCM
The development kit provides the PCM signal on J7.
The pin descriptions of J20 for PCM signal are shown in below table.
Table 5: PCM signal pins
J20
Description
Pin 1
Pin 2
GND
PCM_IN
Pin 3
Pin 4
PCM_OUT
PCM_BCLK
Pin 5
Pin 6
PCM_SYNC
GND
Note:
For 3.3V VIO, VIH is from 2.31V to 3.7V; VIL is from -0.4V to 0.99V.
For 1.8V VIO, VIH is from 1.26V to 2.2V; VIL is from -0.4V to 0.54V.
LTE Coexistence
The development kit provides the LTE coexistence and JTAG signal on J6.
The pin descriptions of J6 are shown in below table.
Table 6: LTE coexistence pins
J21
Description
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
GND
LTE_SOUT
LTE_SIN
JTAG_TMS
JTAG_TCK
GND
Note:
For 3.3V VIO, VIH is from 2.31V to 3.7V; VIL is from -0.4V to 0.99V.
For 1.8V VIO, VIH is from 1.26V to 2.2V; VIL is from -0.4V to 0.54V
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GPIOs
The development kit provides GPIO signal wire to J8.
Table 7: GPIO pins
J8
Description
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
GPIO0
GPIO2
GPIO3
GPIO21
GPIO22
GND
Note:
For 3.3V VIO, VIH is from 2.31V to 3.7V; VIL is from -0.4V to 0.99V.
For 1.8V VIO, VIH is from 1.26V to 2.2V; VIL is from -0.4V to 0.54V
LED Indicator
Table 8: LED pins
LEDs
LED1
Description
WLAN status (Active Low)
LED2
LED3
BT status (Active Low)
3.3V Module Power
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U.FL Connector
The development kit provides U.FL connectors for RF measurement.
Table 9: U.FL connectors
U.FL
Description
CON3
CON1
ANT0 (Wi-Fi)
ANT1 (Wi-Fi + BT)
4 ADDITIONAL DOCUMENTATION
Laird offers a variety of documentation and ancillary information to support our customers through the initial
evaluation process and ultimately into mass production. Additional documentation includes:
DVK-SU60-SIPT – User Manual
DVK-SU60-SIPT - Schematics
SU60-SIPT Module – User Manual – Hardware Datasheet and Integration Guide
For any additional questions or queries, or to receive local technical support for this Development Kit or 60
series modules, please contact wirelessinfo@lairdtech.com
Embedded Wireless Solutions Support Center:
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www.lairdtech.com/wireless
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